ZY2105 5A No-Bus P O L Da ta She e t
8V to 14V Input • 0.5V to 5.5V Output
ZD-01967 Rev. B1.4, 11-Oct-2011 www.power-one.com Page 1 of 14
Member of the Family
Applications
• Low voltage, high density systems with
Interm ediate Bus Ar c hitec tur es (IBA)
• Point-of-load regulators for high performance DSP,
FPGA, AS IC , and microprocessor applications
• Industrial computing, servers, and storage
• Broadban d, net work ing, opt ic al, and wireles s
communications systems
• Active memory bus terminators
Benefits
• Integrates digital power conversion with intelligent
power management
• Eliminates the need for external power
management components and communication bus
• Completely programmable via pin strapping and
one external resistor
• One part that covers all applications
• Reduces board space, system cost and
complexity, and time to market
Features
• RoHS lead free and lead-solder-exempt products are
available
• Wide input voltage range: 8V–14V
• High continuous output current: 5A
• Wide programmable output voltage range: 0.5V–5.5V
• Output voltage margining
• Overcurrent and overtemperature protections
• Overvoltage and under volt age pr otec ti ons, and Pow er
Good signal tracking the output voltage setpoint
• Tracking during turn-on and turn-off with guaranteed
slew rates
• Sequenced and cascaded modes of operation
• Single-wire line for frequency synchronization
between multiple POLs
• Programmable feedback loop compensation
• Enable control
• Flexible fault management and propagation
• Start-up into the load pre-biased up to 100%
• Current sink capability
• Industry standard size through-hole single-in-line
package: 1.2”x0.26”
• Low height of 0.84”
• Wide operating temperature range: 0 to 70ºC
• UL 60950-1/CS A 22.2 No. 60950-1-07 Second
Edition, IEC 60950-1: 2005, and EN 60950-1:2006
Description
Power-One’s point-of-load converters are recomm ended for use with regulated bus converters in an Intermediate
Bus Arc hitecture (IBA) . The ZY2105 is an int elligent, f ully programm able step-down p oint-of-load DC-DC module
integrating digital power conversion and power management. The ZY2105 completely eliminates the need for
external components for sequencing, tracking, protection, monitoring, and reporting. Performance parameters of
the ZY2105 are programmable by pin strapping and an external resistor and can be changed by the user at any
time during product development and service without a need for a communication bus.
Reference Documents
No-BusTM POL Converters. Application Note
Z-One® POL Converters. Eutectic Solder Process Application Note
Z-One® POL Converters. Lead-Free Process Application Note
ZY2105 5A No-Bus P O L Da ta She e t
8V to 14V Input • 0.5V to 5.5V Output
ZD-01967 Rev. B1.4, 11-Oct-2011 www.power-one.com Page 2 of 14
1. Orderin g Information
ZY 21 05 y – zz
Product
family:
Z-One
Module
Series:
No-Bus
POL
Converter
Output
Current:
5A
RoHS compliance:
No suffix - RoHS compliant with Pb solder
exemption1
G - RoHS compliant for all six substances
Dash
Packaging Option2:
R1 – 48 pcs Tray
Q1 – 1 pc sample for
evaluation only
______________________________________
1 The solder exemption ref ers to all the rest rict ed materials except l ead in solder. These material s are Cadmi um (Cd), Hexavalent chrom ium
(Cr6+), Mercury (Hg), P ol ybromi nated biphenyl s (PBB), Polybrominated diphenylethers (P B DE), and Lead (Pb) used anywhere except in
solder.
2 Packaging opt i on is used only for ordering and not included in the part number printed on the POL converter label.
Example: ZY2105G-R3: A 48-piece tray of RoHS compliant POL converters. Each POL converter is labeled
ZY2105G.
2. A b solute Maximum Ratings
Stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect long-
term reliability, and cause permanent damage to the POL converter.
Parameter Conditions/Description Min Max Units
Operating Temperature Controller Case Temperature -40 105 °C
Input Voltage 250ms Transient 15 VDC
3. Environmen tal and Mechanical Specifica tions
Parameter Conditions/Description Min Nom Max Units
Ambient Temperature Range 0 70 °C
Storage Temperature (Ts) -55 125 °C
Weight 6 grams
Operating Vibration
(sinusoidal)
Frequency Range
Magnitude
Sweep Rate
Repetitions in each axis (Min-Max-Min Sweep)
5
0.5
1
2
500
Hz
G
oct/min
sweeps
Non-Operating Shock
(half sine)
Acceleration
Duration
Number of shocks in each axis
50
11
10 G
ms
MTBF Calculated Per Telcordia Technologies SR-332 TBD MHrs
Peak Reflow Temperature ZY2105 220 °C
Peak Reflow Temperature ZY2105G 245 260 °C
Lead Plating ZY2105 and ZY2105G 100% Matte Tin
Moisture Sensitivity Level JEDEC J-STD-020C 3
ZY2105 5A No-Bus P O L Da ta She e t
8V to 14V Input • 0.5V to 5.5V Output
ZD-01967 Rev. B1.4, 11-Oct-2011 www.power-one.com Page 3 of 14
4. Electrical Specifications
Specificat ions appl y at the input voltag e from 8V to 14V, o utput load f rom 0 to 5A, ambient temperature fr om 0°C
to 70°C, output capacitance consisting of 3x22µF ceramics and a 47µF tantalum, and the CCA=0 unless otherwise
noted.
4.1 Input Specifications
Parameter Conditions/Description Min Nom Max Units
Input voltage (VIN) 8 14 VDC
Undervoltage Lockout Threshold Ramping Up
Ramping Down 7.2
6.8 VDC
VDC
Input Current VIN=12V, POL is OFF 19 mADC
Maximum Input Current VIN=8V, VOUT=5.5V 3.7 ADC
4.2 Output Specifications
Parameter Conditions/Description Min Nom Max Units
Output Current (IOUT) VIN MIN to VIN MAX -51 5 ADC
Output Voltage Range (VOUT) Programmable with a resist or between
TRIM and MARGIN pins
Default (no resistor)
0.5
0.5
5.5
VDC
VDC
Output Voltage Setpoint
Accuracy2VIN=12V, IOUT=0.5*IOUT MAX, room
temperature ±1.5% or 20mV whichever is
greater %VOUT
Line Regulation2 VIN MIN to VIN MAX ±0.5 %VOUT
Load Regulation2 0 to IOUT MAX ±0.5 %VOUT
Dynamic Regulation
Peak Deviation
Settling Time
50% – 100% – 50% load step,
Slew rate 2.5A/µs,
to 10% of peak deviation
100
60
mV
µs
Output Voltage Peak-to-Peak
Ripple and Noise
BW=20MHz
Full Load
VIN=12V, VOUT≤1.0V
VIN=12V, VOUT=2.5V
VIN=12V, VOUT=5.0V 15
20
25 mV
mV
mV
Efficiency
VIN=12V
Full Load
Room temperature
VOUT=0.5V
VOUT=0.75V
VOUT=1.0V
VOUT=1.2V
VOUT=1.8V
VOUT=2.5V
VOUT=3.3V
VOUT=5.0V
63.2
71.5
76.8
79.8
84.8
87.9
90.0
92.4
%
%
%
%
%
%
%
%
Temperature Coefficient VIN=12V, IOUT=0.5*IOUT MAX, VOUT=5V 60 ppm/°C
Switching Frequency 450 500 550 kHz
1 At the negative output current (bus terminator mode) efficiency of the ZY2105 degrades resulting in increased internal power dissipation.
Therefore maximum allowable negative current under specific conditions is 20% lower than the current determined from the derating curves
shown in paragraph 5.5
2 Digital PW M has an inherent quantization uncert ai nt y of ±6.25mV that is not included in the specifi ed static regulati on parameters.
ZY2105 5A No-Bus P O L Da ta She e t
8V to 14V Input • 0.5V to 5.5V Output
ZD-01967 Rev. B1.4, 11-Oct-2011 www.power-one.com Page 4 of 14
4.3 Protection Specifications
Parameter Conditions/Description Min Nom Max Units
Output Overcurrent Protection
Type Non-Latching, 130ms period
Threshold 155 %IOUT
Threshold Accuracy -25 25 %IOCP.SET
Output Overvoltage Protection
Type Latching
Threshold Follows the output voltage setpoint 1301 %VO.SET
Threshold Accuracy Measured at VO.SET=2.5V -2 2 %VOVP.SET
Delay From instant when threshold is exceeded until
the turn-off co mm and is gener ated 6 μs
Output Undervoltage Protection
Type Non-Latching, 130ms period
Threshold Follows the output voltage setpoint 75 %VO.SET
Threshold Accuracy Measured at VO.SET=2.5V -2 2 %VUVP.SET
Delay From instant when threshold is exceeded until
the turn-off co mm and is gener ated 6 μs
Overtemperature Protection
Type Non-Latching, 130ms period
Turn Off Threshold Temperature is increasing 120 °C
Turn On Threshold Temperature is decreasing after module was
shut down by OTP
110 °C
Threshold Accuracy -5 5 °C
Delay From instant when threshold is exceeded until
the turn-off co mm and is gener ated 6 μs
Power Good Signal (PGOOD pin)
Logic
V
OUT
is inside the PG window and stable
VOUT is outside of the PG window or ramping
up/down
High
Low
N/A
Lower Threshold Follows the output voltage setpoint 90 %VO.SET
Upper Threshold Follows the output voltage setpoint 110 %VO.SET
Delay From instant when threshold is exceeded until
status of PG pin changes 6 μs
Threshold Accuracy Measured at VO.SET=2.5V -2 2 %VO.SET
___________________
1 Minimum OVP threshold is 1. 0V
ZY2105 5A No-Bus P O L Da ta She e t
8V to 14V Input • 0.5V to 5.5V Output
ZD-01967 Rev. B1.4, 11-Oct-2011 www.power-one.com Page 5 of 14
4.4 Feature Specifications
Parameter Conditions/Description Min Nom Max Units
Tracking
Rising Slew Rate Proportional to SYNC frequency 0.1 V/ms
Falling Slew Rate Proportional to SYNC frequency -0.5 V/ms
Enable (EN pin)
EN Pin Polarity Positive (enables the output when EN pin is
open or pulled high)
EN High Threshold 2.3 VDC
EN Low Threshold 1.0 VDC
Open Circuit Voltage 3.3 VDC
Turn-On Delay From EN pin changin g state to VOUT
starting to ramp up 0 ms
Turn-Off Delay From EN pin changing state to VOUT
reaching 0V 11 ms
Feedback Loop Compensation (CCA pin)
CCA pin is open Recommended COUT/ESR range,
combinatio n of cerami c + tantalum 50/5 +
220/40 100/5 +
470/40 400/5 +
2000/20 µF/mΩ
µF/mΩ
CCA pin is connected to GND Recommended COUT/ESR range, ceramic 100/5 220/5 400/5 µF/mΩ
ZY2105 5A No-Bus P O L Da ta She e t
8V to 14V Input • 0.5V to 5.5V Output
ZD-01967 Rev. B1.4, 11-Oct-2011 www.power-one.com Page 6 of 14
4.5 Signal Specifications
Parameter Conditions/Description Min Nom Max Units
VDD Internal supply voltage 3.15 3.3 3.45 V
SYNC Line
ViL_s LOW level input voltage -0.5 0.3 x VDD V
ViH_s HIGH level input voltage
0.75 x
VDD
VDD + 0.5 V
Vhyst_s Hysteresis of input Schmitt trigger
0.25 x
VDD
0.45 x
VDD
V
IoL_s LO W level sink current V(SYNC)=0.5V 14 60 mA
Ipu_s Pull-up current source V(SYNC)=0V 300 1000 μA
Tr_s Maximum allowed rise time 10/90%VDD 300 ns
Cnode_s Added node capacitan ce 5 10 pF
Freq_s Clock frequency of external SYNC line 475 525 kHz
Tsynq Sync pulse duration 22 28 % of clo ck
cycle
T0 Data=0 pulse duration 72 78 % of clock
cycle
Inputs: CCA, EN, IM
Iup_x Pull-up current source V(X)=0 25 110 μA
ViL_x LOW level input voltage -0.5 0.3 x VDD V
ViH_x HIGH level input voltage 0.7 x VDD VDD+0.5 V
Vhyst_x Hysteresis of input Schmitt trigger 0.1 x VDD 0.3 x VDD V
RdnL_x
External pull down resista nce
pin forced low
10 kΩ
Power Good and OK Inputs/Outputs
Iup_PG Pull-up current source V(PG)=0 25 110 μA
Iup_OK Pull-up current source V(OK)=0 175 725 μA
ViL_x LOW level input voltage -0.5 0.3 x VDD V
ViH_x HIGH level input voltage 0.7 x VDD VDD+0.5 V
Vhyst_x Hysteresis of input Schmitt trigger 0.1 x VDD 0.3 x VDD V
IoL_x LOW level sink current at 0.5V 4 20 mA
ZY2105 5A No-Bus P O L Da ta She e t
8V to 14V Input • 0.5V to 5.5V Output
ZD-01967 Rev. B1.4, 11-Oct-2011 www.power-one.com Page 7 of 14
5. Typical Performance Characteristics
5.1 Efficiency Curves
55
60
65
70
75
80
85
90
95
0 1 2 3 4 5
Output Current, A
Efficiency, %
Vo=5.0V Vo=3.3V Vo=2.5V
Vo=1.8V Vo=1.2V
Figure 1. Efficiency vs. Load. Vin=9.6V
55
60
65
70
75
80
85
90
95
0 1 2 3 4 5
Output Current, A
Efficiency, %
Vo=5V Vo=3.3V Vo=2.5V
Vo=1.8V Vo=1.2V
Figure 2. Efficiency vs. Load. Vin=12V
60
65
70
75
80
85
90
95
0.5 11.5 22.5 33.5 44.5 5
Output Voltage, V
Efficiency, %
Vin=12V Vin=9.6V
Figure 3. Efficiency vs. Output Voltage, Iout=5A
75
80
85
90
95
8 9 10 11 12 13 14
Input Vol tage, V
Efficiency, %
Vo=1.2V Vo=2.5V Vo=5V
Figure 4. Efficiency vs. Input Voltage. Iout=5A
ZY2105 5A No-Bus P O L Da ta She e t
8V to 14V Input • 0.5V to 5.5V Output
ZD-01967 Rev. B1.4, 11-Oct-2011 www.power-one.com Page 8 of 14
5.2 Turn-On Characteristics
Figure 5. Tracking Turn-On.
Vin=12V, Ch1 – V1, C h2 – V2, Ch3 – V3
5.3 Turn-Off Characteri stics
Figure 6. Tracking Turn-Off
Vin=12V, Ch1 – V1, C h2 – V2, Ch3 – V3
5.4 Transient Respon se
The pictures below show the deviation of the output
voltage i n respons e to the 50%-100%-50% step load
at 2.5A/μs. In all tests the POL converter had a tot al
of 110μF ceramic and tantalum capacitors connected
across the output pins. The speed of the transient
response was varied by selecting different CCA
settings.
Figure 7. Vin=12V, Vout=5V. CCA=0
Figure 8. Vin=12V, Vout=5V. CCA=1
ZY2105 5A No-Bus P O L Da ta She e t
8V to 14V Input • 0.5V to 5.5V Output
ZD-01967 Rev. B1.4, 11-Oct-2011 www.power-one.com Page 10 of 14
6. Typical Application
POL2
22uF
TRIM
MARGIN
IM
CCA
EN
SYNC OK
PGOOD
4.7uF
POL3
22uF
TRIM
MARGIN
IM
CCA
EN
SYNC OK
PGOOD
4.7uF
POL1
22uF
47uF
VIN
VOUT
GND
TRIM
MARGIN
IM
CCA
EN
SYNC OK
PGOOD
4.7uF
22uF
IBV
Vo1 Vo2
Vo3
ENABLE
VIN
VIN
VOUT
PGND
VOUT
GND
22uF 22uF
47uF 22uF 22uF 22uF
47uF 22uF 22uF 22uF
Figure 12. Complete Schematic of Application with Three Independent Outputs. Intermediate Bus Voltage is from 8V to 14V.
In this application three POL converters are configured to deliver three independent output voltages. Output
voltages are programmed with the resistors connected between TRIM and MARGIN pins of individual converters.
POL1 is configured as a master (IM pin is grounded) and all other POL converters are synchronized to the
switching frequency of POL1.
All converters are controlled by the common ENABLE signal. Turn-on and turn-off processes of the system are
illustrated by pictures in Figure 5 and Figure 6.
ZY2105 5A No-Bus P O L Da ta She e t
8V to 14V Input • 0.5V to 5.5V Output
ZD-01967 Rev. B1.4, 11-Oct-2011 www.power-one.com Page 11 of 14
7. Pin Assignments and Descri p tion
Pin
Name Pin
Number Pin
Type Buffer
Type Pin Description Notes
OK 8 I/O PU Fault Status Connect to OK pin of other Z- POLs. Leave
open, if not used
SYNC 9 I/O PU Frequency Synchronization
Line Connect to SYNC pin of other Z-POLs or to an
external clock generator
PGOOD 6 I/O PU Power Good
IM 10 I PU Master Mode Tie to GND to make the POL the clock master or
leave open to synchronize to external clock
CCA 2 I PU Compensation Coefficient
Address Tie to PGND for 0 or leave open for 1
MARGIN 3 A Output Voltage Margining To program the output voltage, connect a
resistor between MARGIN and TRIM
EN 5 I PU Enable POL is ON when the pin is high or floating. POL
is OFF when the pin is low or connected to GND
TRIM 4 A Output Voltage Trim To program the output voltage, connect a
resistor between MARGIN and TRIM
VOUT 1 P Output Voltage
GND 7 P Power Ground
VIN 11 P Input Voltage
Legend: I=input, O=output, I/O=input/out put, P=power, A= anal og, PU=i nternal pul l -up
ZY2105 5A No-Bus P O L Da ta She e t
8V to 14V Input • 0.5V to 5.5V Output
ZD-01967 Rev. B1.4, 11-Oct-2011 www.power-one.com Page 12 of 14
8. Pin and Feature Description
8.1 OK, Fault Status
The open drain input/output with the internal pull-up
resistor. The POL convert er pulls its OK p in lo w, if a
fault occurs. Pulling lo w the OK input by an exter nal
circuitry turns off the POL converter.
8.2 SYNC, Frequency Synchronization Line
The bidir ectional input/ outp ut wit h the i nternal pull-up
resistor. If the POL converter is configured as a
master, the SYNC line propagates clock to other
POL converters. If the POL converter is configured
as a slave, the internal clock recovery circuit
synchronizes to the clock of the SYN C line.
8.3 IM, Interleave Mode
The input with the internal pull-up resistor. Pulling
the IM pin low configures a POL converter as a
master.
8.4 PG, Power Good
The open drain input/output with the internal pull-up
resistor. T he pin is pu lled lo w by the PO L convert er,
if the output volt age is outside of the window defined
by the Power Good High and Low thresholds.
Note: See the No-Bus Application Note for recommendations on
PG deglitching.
8.5 CCA, Compensation Coefficient Address
The input with internal pull-up to s elect one of 2 sets
of digital filter coefficients optimized for different
characteristics of output capacitance.
8.6 MARGIN, Output Voltage Margining
The output of the 2V internal voltage reference that
is used to program the output voltage of the POL
converter.
8.7 EN, En ab le
The input with the internal pull-up res istor. The POL
converter is turned off, when the pin is pulled low
8.8 TRIM, Output Voltage Trim
The input of the TRIM comparator for the output
voltage programming.
The output voltage can be programmed by a single
resistor connected between MARGIN and TRIM
pins.
9. A p p lication Infor mation
9.1 Output Voltage Programming
Resistance of the t rim res istor is determined f r om the
equation below:
,
)5.5(20
OUT
OUT
TRIM VV
R−×
= kΩ
where VOUT is the desired output voltage in Volts.
If the RTRIM is open or the TRIM pin is shorted to
PGND, the VOUT=0.5V.
9.2 Output Voltage Margining
Margining can be implemented by changing the
resistance between the REF and TRIM pins.
Figure 13. Margining Configuration
In the schematic shown in Figure 13, the nominal
output voltage is set with the trim resistor RTRIM
calculated from the equation in the paragraph 9.1.
Resistors RUP and RDOWN are added to margin the
output voltage up and down respectively and
determined from the equations below.
∆
∆−×
×
+
×
=%%5
20
20 VVR
R
R
RTRIM
TRIM
TRIM
UP
, kΩ
( )
∆−
∆
×+= %100 %
20 V
V
RR
TRIMDOWN
, kΩ
MARGIN
TRIM
POL
GND
R
DOWN
R
TRIM
Margining
Down Switch
(normally
closed)
Margining
Up Switch
(normally
open)
R
UP
ZY2105 5A No-Bus P O L Da ta She e t
8V to 14V Input • 0.5V to 5.5V Output
ZD-01967 Rev. B1.4, 11-Oct-2011 www.power-one.com Page 13 of 14
where RTRIM is the value of the trim resistor in kΩ and
ΔV% is the absolute value of desired margining
expressed in percents of the nominal output voltage.
During normal operation the resistors are removed
from the circuit by the switches. The “Margining
Down” s witch is normally closed s horting the resis tor
RDOWN while the “Margining Up” switch is normally
open disconnecting the resistor RUP.
An alter nat ive c onf ig urat ion of the margining c irc u it is
shown in Figure 14. In the configuration both
switches are normally open that may be
advantageous in some implementations.
Figure 14. Alternative Margining Configuration
RUP and RDOWN for this configuration are determined
from the following equations:
∆
∆−×
×
+
×
=%%5
20
20 VVR
R
R
RTRIM
TRIM
TRIM
UP
, kΩ
∆
∆
−
×
+
×
=%%100
20
20 VV
R
R
RTRIM
TRIM
DOWN
, kΩ
Caution: Noise inject ed into the TRIM node may affect accuracy
of the output voltage and stability of the POL
converter. A lways minim ize the PCB trace l ength from
the TRIM pin to external components to avoid noise
pickup.
Refer to No-BusTM POL Converters. Application
Note on www.power-one.com for more application
information on this and other product features.
MARGIN
TRIM
POL
GND
R
TRIM
R
DOWN
Margining
Down Switch
(normally
open)
Margining
Up Switch
(normally
open)
R
UP
ZY2105 5A No-Bus P O L Da ta She e t
8V to 14V Input • 0.5V to 5.5V Output
ZD-01967 Rev. B1.4, 11-Oct-2011 www.power-one.com Page 14 of 14
10. Mechanical Drawings
All Dimension s are in m m
Tolerances: XX.X: ±0.1 XX.XX: ±0.05
Figure 15. Me chanical Draw in g
Figure 16. Recommended Footprint – Top View
Notes:
1. NUCLEAR AND MEDICAL APPLICATIONS - Power-One products are not designed, intended for use in, or authorized for use as critical
components in life support systems, equipm ent us ed in hazardous environm ents , or nuclear c ontrol sys t ems without the express written
consent of the respective divisi onal presi dent of Power-One, I nc.
2. TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on
the date manufactured. Specifications are subject to change without notice.
