© Semiconductor Components Industries, LLC, 2015
July, 2019 Rev. P3
1Publication Order Number:
NVMFD5C650NL/D
NVMFD5C650NL
MOSFET – Power, Dual
N-Channel
60 V, 4.2 mW, 111 A
Features
Small Footprint (5x6 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low QG and Capacitance to Minimize Driver Losses
NVMFD5C650NLWF Wettable Flank Option for Enhanced Optical
Inspection
AECQ101 Qualified and PPAP Capable
These Devices are PbFree and are RoHS Compliant
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter Symbol Value Unit
DraintoSource Voltage VDSS 60 V
GatetoSource Voltage VGS ±20 V
Continuous Drain
Current RJC
(Notes 1, 2, 3) Steady
State
TC = 25°CID111 A
TC = 100°C 88
Power Dissipation
RJC (Notes 1, 2)
TC = 25°CPD125 W
TC = 100°C 62
Continuous Drain
Current RJA
(Notes 1, 2, 3) Steady
State
TA = 25°CID21 A
TA = 100°C 15
Power Dissipation
RJA (Notes 1 & 2)
TA = 25°CPD3.5 W
TA = 100°C 1.8
Pulsed Drain Current TA = 25°C, tp = 10 sIDM 502 A
Operating Junction and Storage Temperature TJ, Tstg 55 to
+ 175
°C
Source Current (Body Diode) IS91 A
Single Pulse DraintoSource Avalanche
Energy (TJ = 25°C, IL(pk) = 6 A)
EAS 186 mJ
Lead Temperature for Soldering Purposes
(1/8 from case for 10 s)
TL260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter Symbol Value Unit
JunctiontoCase Steady State RJC 1.37 °C/W
JunctiontoAmbient Steady State (Note 2) RJA 46.9
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surfacemounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
MARKING
DIAGRAM
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A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
V(BR)DSS RDS(ON) MAX ID MAX
60 V 4.2 m @ 10 V
111 A
5.8 m @ 4.5 V
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
D1
D1
D2
D2
S1
G1
S2
G2
Dual NChannel
D1
S1
G1
XXXXXX
AYWZZ
D2
D1
D2
S2
G2
D2
D1
DFN8 5x6
(SO8FL)
CASE 506BT
1
NVMFD5C650NL
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2
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
DraintoSource Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 A60 V
DraintoSource Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
27.1 mV/°C
Zero Gate Voltage Drain Current IDSS VGS = 0 V,
VDS = 60 V
TJ = 25 °C 10
A
TJ = 125°C 100
GatetoSource Leakage Current IGSS VDS = 0 V, VGS = 20 V 100 nA
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 98 A1.2 2.2 V
Negative Threshold Temperature Coefficient VGS(TH)/TJ5.0 mV/°C
DraintoSource On Resistance RDS(on) VGS = 10 V ID = 20 A 3.5 4.2
m
VGS = 4.5 V ID = 20 A 4.6 5.8
Forward Transconductance gFS VDS = 15 V, ID = 50 A 120 S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance CISS
VGS = 0 V, f = 1 MHz, VDS = 25 V
2546
pF
Output Capacitance COSS 1258
Reverse Transfer Capacitance CRSS 17
Total Gate Charge QG(TOT) VGS = 4.5 V, VDS = 48 V; ID = 50 A 16
nC
Total Gate Charge QG(TOT) VGS = 10 V, VDS = 48 V; ID = 50 A 37
Threshold Gate Charge QG(TH)
VGS = 4.5 V, VDS = 48 V; ID = 50 A
4.3
GatetoSource Charge QGS 8.3
GatetoDrain Charge QGD 3.1
Plateau Voltage VGP 3.3 V
SWITCHING CHARACTERISTICS (Note 5)
TurnOn Delay Time td(ON)
VGS = 4.5 V, VDS = 48 V,
ID = 5 A, RG = 1.0
13
ns
Rise Time tr24
TurnOff Delay Time td(OFF) 37
Fall Time tf13
DRAINSOURCE DIODE CHARACTERISTICS
Forward Diode Voltage VSD VGS = 0 V,
IS = 20 A
TJ = 25°C 0.9 1.2
V
TJ = 125°C 0.8
Reverse Recovery Time tRR
VGS = 0 V, dIS/dt = 50 A/s,
IS = 50 A
44
ns
Charge Time ta22
Discharge Time tb22
Reverse Recovery Charge QRR 35 nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 s, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
NVMFD5C650NL
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3
TYPICAL CHARACTERISTICS
Figure 1. OnRegion Characteristics Figure 2. Transfer Characteristics
VDS, DRAINTOSOURCE VOLTAGE (V) VGS, GATETOSOURCE VOLTAGE (V)
1.51.00.50
0
20
100
140
2.52.01.00
0
20
40
60
100
140
Figure 3. OnResistance vs. GatetoSource
Voltage
Figure 4. OnResistance vs. Drain Current and
Gate Voltage
VGS, GATETOSOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
1098765
4
8
7030 4010
3
4
8
Figure 5. OnResistance Variation with
Temperature
Figure 6. DraintoSource Leakage Current
vs. Voltage
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAINTOSOURCE VOLTAGE (V)
12510075502502550
1.0
1.2
1.4
1.6
2.0
5535255
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
RDS(on), DRAINTOSOURCE RESISTANCE (m)
RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)
IDSS, LEAKAGE (nA)
10 to 4.5 V
3.6 V
3.4 V
3.2 V
VGS = 2.6 V
VDS = 10 V
TJ = 125°CTJ = 55°C
TJ = 25°C
7
10
ID = 20 A
TJ = 25°C
60 90
2
6
TJ = 25°C
VGS = 4.5 V
VGS = 10 V
ID = 20 A
VGS = 10 V
TJ = 125°C
TJ = 175°C
TJ = 25°C
15 45
10
100
1K
10K
RDS(on), DRAINTOSOURCE RESISTANCE (m)
120
43
175
1.8
2.52.0 3.00.5
0.8
0.6
150
80
100
5
7
TJ = 85°C
40
120
1.5 3.5
5
TJ = 150°C
1
100K
60
6
9
20
80
4.0
3.0 V
2.8 V
50 80
NVMFD5C650NL
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4
TYPICAL CHARACTERISTICS
Figure 7. Capacitance Variation Figure 8. GatetoSource vs. Total Charge
VDS, DRAINTOSOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)
30 4020 60100
1
100
10K
2520151050
0
4
9
10
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
RG, GATE RESISTANCE ()VSD, SOURCETODRAIN VOLTAGE (V)
0.4 0.60.3
0.1
10
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
VDS, DRAINTOSOURCE VOLTAGE (V)
10001010.1
0.1
1
10
1000
C, CAPACITANCE (pF)
VGS, GATETOSOURCE VOLTAGE (V)
t, TIME (ns)
IS, SOURCE CURRENT (A)
ID, DRAIN CURRENT (A)
TJ = 25°C
VGS = 0 V
f = 1 MHz
Ciss
Coss
Crss 2
5
6
VDS = 48 V
ID = 50 A
TJ = 25°C
0.5 0.9
VGS = 0 V
TC = 25°C
VGS 10 V
Single Pulse
RDS(on) Limit
Thermal Limit
Package Limit
10 s
10 ms
Qgd
100
1K
0.5 ms
1 ms
Figure 12. Maximum Drain Current vs. Time in
Avalanche
TIME IN AVALANCHE (s)
0.00001
0.1
10
100
IPEAK (A)
TJ(initial) = 25°C
TJ(initial) = 100°C
0.0001 0.001 0.01
100
50
1
3
7
8
Qgs
TJ = 25°CTJ = 125°C TJ = 55°C
10
0.7 0.8
1
403530
1
VGS = 4.5 V
VDS = 48 V
ID = 50 A td(off)
td(on)
tf
tr
10
100
1K
1 10 100
1
NVMFD5C650NL
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5
TYPICAL CHARACTERISTICS
Figure 13. Thermal Response
PULSE TIME (sec)
0.010.001 100.0001 0.10.00001 10.000001
0.1
1
10
100
R(t) (°C/W)
100 1000
50% Duty Cycle
Single Pulse
20%
10%
5%
2%
1%
0.01
DEVICE ORDERING INFORMATION
Device Marking Package Shipping
NVMFD5C650NLT1G 5C650L DFN8
(PbFree)
1500 / Tape & Reel
NVMFD5C650NLWFT1G 650LWF DFN8
(PbFree, Wettable Flanks)
1500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
M3.25
h−−−
3.50
−−−
DFN8 5x6, 1.27P Dual Flag (SO8FLDual)
CASE 506BT
ISSUE E
DATE 26 FEB 2013
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
XXXXXX= Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
1234
56
TOP VIEW
SIDE VIEW
BOTTOM VIEW
D1
E1
h
D
E
B
A
0.20 C
0.20 C
2X
2X
DIM MIN
MILLIMETERS
A0.90
A1 −−−
b0.33
c0.20
D5.15 BSC
D1 4.70
D2 3.90
E6.15 BSC
E1 5.70
E2 3.90
e1.27 BSC
G0.45
K0.51
L0.48
A
0.10 C
0.10 C
14
8
e
8X
D2
b1 E2
b
A0.10 B
C
0.05 C
L
DETAIL A
A1
c
4X
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer
to device data sheet for actual part
marking.
1
XXXXXX
AYWZZ
1
5
MAX
−−−
−−−
0.42
−−−
4.90
4.10
5.90
4.15
0.55
−−−
0.61
M
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
1.27
0.75
1.40
3.70
4.56
8X
N1.80 2.00
78
N
PITCH
6.59
4.84
1.00
DIMENSION: MILLIMETERS
PIN ONE
IDENTIFIER
NOTE 7
NOTE 4 CSEATING
PLANE
DETAIL A NOTE 6
4X
K
NOTE 3
2.30
4X
0.70
5.55
4X
0.56
2X
D3 1.50 1.70
b1 0.33 0.42
ÉÉ
ÉÉ
4X
D3
G
4X
DETAIL B
DETAIL B
ALTERNATE
CONSTRUCTION
2.08
2X
K1 0.56 −−−
K1
3.75
12
_
MAX
1.10
0.05
0.51
0.33
5.10
4.30
6.10
4.40
0.65
−−−
0.71
2.20
1.90
0.51
−−−
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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DFN8 5X6, 1.27P DUAL FLAG (SO8FLDUAL)
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