M48T18-150PC1F - STMicroelectronics

1/27December 2005

M48T08

M48T 08 Y, M48 T1 8

5V, 64 Kbit (8 Kb x8) TIMEKEEPER® SRAM

Rev 7.0

FEATURES SUMMARY

■INTEGRAT ED ULTRA LOW PO WER SRAM,

REAL TIME CLOCK, PO WER-FAIL

CONTR OL CIRCUIT, AND BATTERY

■BYTEWI D E™ RAM-LIKE CLOC K ACC ESS

■BCD CO DED YEAR, MONTH, DAY, DAT E,

H OURS, MINUTES, and SECONDS

■TYPICAL CLOCK ACCURA CY OF ±1

MINUTE A MONTH, AT 25°C

■AUTOMATIC POWER-FAIL CHIP

DESELECT AND WRI TE PROTECTION

■WRITE PRO TECT VOLTAGES

(VPFD = Power-fail Deselect Voltage):

– M48T08: VCC = 4.75 to 5.5V

4.5V ≤ VPFD ≤ 4.75V

– M48T18/T08Y: VCC = 4.5 to 5.5V

4.2V ≤ VPFD ≤ 4.5V

■SOFT WARE CONTRO LLED CLOCK

CALIBRATION FOR HIGH ACCURACY

APPLICATIONS

■SELF-CONTAINED BAT TERY AND

CRYSTA L IN THE CAPHAT™ DIP

PACKAGE

■PACKAGING INCL UDES A 28-LEAD SOIC

AND SNAPHAT® TO P (to be ordered

separately)

■SOIC PACKAGE PROVIDES DIRECT

CONNECTION FOR A SNAP HAT TOP

WHICH CO NTAIN S THE BATTERY AND

CRYSTAL

■PIN AND FUNCTION COMPATIBLE WITH

D S1643 and JEDEC STA NDARD 8K x8

SRAMs

■RoHS COMPLIANCE

Lead-free components are com pliant with the

RoHS Di recti ve.

Figure 1. 28-pin PCDIP, CAPHAT™ Packag e

Figu re 2. 28- pi n S OI C Package

PCDIP28 (PC)

Battery/Crystal

CAPHAT

SNAPHAT (SH)

Battery/Crystal

SOH28 (MH)

M48T08, M48T08Y, M48T18

2/27

TABLE OF CONTENTS

FEATUR ES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. 28-pin PCDIP, CAPHAT™ Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. 28-pin SOIC Packag e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUM MARY DESCRIPT ION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. Logi c Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signa l Na mes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 4. DIP Connectio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 5. S OIC Connect ions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 7. RE AD Mode AC Wavefo rms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. REA D Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

WRITE M ode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 8. WRI TE Enable Controlle d, WRITE AC Wave form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 9. Chip Enable C ontrolled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4. WRITE Mode AC Characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Re tention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Power-fail Interrupt Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

CLOCK O PERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Reading the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 10.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

VCC Noise And Negative Going Transie nts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12.Supply Voltage Protect ion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

MAXIMU M RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 6. Absolute Maximum Rati ngs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

DC AND AC PARAM ETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 7. Operating a nd AC Measurement Cond itions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9

Figure 14.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3/27

M48T08, M48T08Y, M48T18

Table 10. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 11. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

PACKAGE MECHANICAL INFORMATIO N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 15.PCDIP28 – 28-pin Plastic DI P , battery CAPHAT, Pack age Outline . . . . . . . . . . . . . . . . 21

Table 12. PCDI P28 – 28-pin Plastic DIP, bat tery CAPH AT, Package Mecha nical Data. . . . . . . . . 21

Figure 16. SOH28 – 28-lead Plastic Small Outline, 4-socket bat tery SNAPHA T, Package Outline. 22

Table 13. S OH28 – 28-lead Plastic SO, 4-socket battery SNAPHAT, Packag e Mech. Data . . . . . 22

Figure 17.SH – 4-pin SNAPHA T Housing for 48mAh Ba ttery & Crystal, Package Outline . . . . . . . 23

Table 14. SH – 4-pin SNAPH AT Housing for 48mAh Ba ttery & Crystal, P ack age M ech. Data . . . . 23

Figure 18.SH – 4-pin SNAPHA T Housing for 120mAh B attery & Crystal, P ack age Ou tline . . . . . . 24

Table 15. SH – 4-pin SNAPH AT Housing for 120mAh B attery & Crystal, P ackage M ec h. Data . . . 24

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 16. Orde ring Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 17. SNAPHAT Batte ry Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

REVISION HISTO RY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 18. Document Revi sion History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

M48T08, M48T08Y, M48T18

4/27

S UM MARY DESCRIPTION

The M48T08/18/08Y TIMEKEEPER® RAM is an

8K x 8 non-volatile static RAM and real time clock

which is pin and functional compatible with the

DS1643. The monolithic chip is available in two

special packages to provide a highly integrated

battery back ed-up memory and real time clock so-

lution.

The M48T08/18/08Y is a non-v olatile pin and func-

tion equivalent to any JEDEC standard 8K x 8

SRAM. It also easily fits into many ROM, EPROM,

and EEPROM sockets, providing the non-volatility

of PROMs without any requirement for special

WRITE timing or limitations on the number of

WRITEs that can be performed.

The 28-pin, 600mil DIP CAPHAT™ houses the

M48T08/18/08Y silicon with a quartz crystal and a

long- life lit hium button cell in a single package.

The 28-pin, 330mil SOIC provides sockets with

gold plated contacts at both ends for direct con-

nection to a separate SNAPHAT® housing con-

taining the battery and cry stal. The unique d esign

allows the SNAPHAT battery package to be

mounted on top of the SOIC package after the

completion of the surface mount process. Inser-

tion of the SNAPHAT housing after reflow pre-

vents pote ntial b attery and crystal dam age due to

the high temperatures required for device surface-

mounting. The SNA PHAT housing is k ey ed to pre-

vent reverse insertion.

The SOIC and battery/crystal packages are

shipped separately in plastic anti-static tubes or in

Tape & Reel form. F or t he 2 8 le ad S OIC , t he bat-

tery/crystal package (e.g., SNAPHAT) part num-

ber is “M4T28-BR12SH” or “M4T32-BR12SH”

(see Table 17., page 25 ).

Figure 3. Logic Diagram Tabl e 1. Signal Names

AI01020

A0-A12

DQ0-DQ7

VCC

M48T08

M48T08Y

M48T18

VSS

E1 INT

A0-A12 Address Inputs

DQ0-DQ7 Data Inputs / Outputs

INT Power Fail Interrupt (Open Drain)

E1 Chip Enable 1

E2 Chip Enable 2

GOutput Enable

WWRITE Enable

VCC Supply Voltage

VSS Ground

5/27

M48T08, M48T08Y, M48T18

Figu re 4. DIP C on ne ctions Figu r e 5. S OI C Co nn e ct io ns

Figu re 6. Blo ck Diagram

DQ0

A10

DQ7

A11

DQ5DQ1

DQ2 DQ3VSS DQ4

DQ6

A12

INT VCC

AI01182

M48T08

M48T18

14 16

AI01021B

DQ0

A10

DQ7

A11

DQ5DQ1

DQ2 DQ3VSS DQ4

DQ6

A12

INT VCC

M48T08Y

AI01333

LITHIUM

CELL

OSCILLATOR AND

CLOCK CHAIN

VPFD

INTVCC VSS

32,768 Hz

CRYSTAL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

8 x 8 BiPORT

SRAM ARRAY

8184 x 8

SRAM ARRAY

A0-A12

DQ0-DQ7

POWER

M48T08, M48T08Y, M48T18

6/27

OPERATION MODES

As Figure 6., page 5 shows, the static memory ar-

ray and the quartz-controlled clock osc illator of the

M48T08/18/08Y are integrated on one silicon chip.

The two circuits are interconnected at the upper

eight memory locations to provide user accessible

BYTEWIDE™ clock information in the bytes with

addresses 1FF8h-1FFFh.

The clock locations contain t he year, month, date,

day, hour, minute, and second in 24 hour BCD for-

mat. Corrections f or 28, 29 (leap yea r - valid unt il

2100), 30, and 31 day months are made automat-

ically. Byte 1FF8h is the clock control regis ter. This

byte controls user access to the c lock inform ation

and also stores the clock calibration setting.

The eight clock bytes are not the actual clock

counters themselves; they are memory locations

consisting of BiPORT™ READ/WRITE memory

cells. The M48T08/18/08Y includes a clock control

circuit which updates the clock bytes with current

information once per second. The information can

be accessed by the user in the same manner as

any ot her location in t he stati c memory array.

The M48T08/18/08Y also has its own Power-fail

Detect circuit. The control circuitry constantly mon-

itors the single 5V supply for an out of tolerance

condition. When VCC is out of tolerance, the circuit

write protects the SRAM, providing a high degree

of data sec urity i n the m idst of unpredictable sys-

tem operation brought on by low VCC. As VCC falls

below the Battery Back-up Switchover Voltage

(VSO), the control circuitry connects the battery

which maintains data and cl ock operati on until val-

id power re turns.

Table 2. Operating Modes

No te: X = VIH or VIL; VSO = B atte ry Back-u p Sw i tch over Vo l tag e.

1. See Table 11., page 20 for details.

Mode VCC E1 E2 G W DQ0-DQ7 Power

Deselect

4.75 to 5.5V

4.5 to 5.5V

VIH X X X High Z Standby

Deselect X VIL X X High Z Standby

WRITE VIL VIH XVIL DIN Active

READ VIL VIH VIL VIH DOUT Active

READ VIL VIH VIH VIH High Z Active

Deselect VSO to VPFD(min)(1) X X X X High Z CMOS Standby

Deselect ≤ VSO(1) X X X X High Z Battery Back-up Mode

7/27

M48T08, M48T08Y, M48T18

READ Mode

The M4 8T08/18/08Y i s in the RE AD M ode when-

ever W (WRITE Enable) is hig h, E 1 (Chip Enable

1) is low, and E 2 (Chip Enable 2) is hi gh. The de-

vice architecture allows ripple-through access of

data from eight of 65,536 locations in the static

storage array. Thus, the unique address specif ied

by the 13 address inputs defines w hich one of the

8,192 bytes of data is to be accessed. Va lid data

will be available at the Data I/O pins within address

access time (tAVQV) after the last address input

signal is stable, providing that the E1, E2, and G

access ti mes are a lso satisfied. If the E 1, E2 and

G access times are not met, valid data will be

available af ter the latter of the Chip Enable Access

tim e s (tE1LQV or tE2HQV) or Output Ena ble Access

tim e (tGLQV).

The state of the eight three-state Da ta I/O si gnals

is controlled by E1, E2 and G. If the outputs are ac-

tivated before tAVQV, the dat a lines will be driven to

an indeterminate state until tAVQV. If the address

inputs are changed whil e E1, E2 and G remain ac-

tive, output data will remai n valid for Output Data

Hold time (tAXQX) but will go indeterminate until the

next address access.

Figure 7. READ Mode AC Waveforms

No te: W RITE Enable (W) = Hig h.

AI00962

tAVAV

tAVQV tAXQX

tE1LQV

tE1LQX

tE1HQZ

tGLQV

tGLQX

tGHQZ

VALID

A0-A12

DQ0-DQ7

tE2HQV

tE2HQX

VALID

tE2LQZ

M48T08, M48T08Y, M48T18

8/27

Table 3. READ M ode AC Characteristics

Note: 1. Val i d fo r Ambien t Operat in g T em pera t ure: TA = 0 to 70 ° C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (ex cept whe re noted) .

Symbol Parameter(1)

M48T08/M48T18/T08Y

Unit–100/–10 (T08Y) –150/–15 (T08Y)

MinMaxMinMax

tAVAV READ Cycle Time 100 150 ns

tAVQV Address Valid to Output Valid 100 150 ns

tE1LQV Chip Enable 1 Low to Output Valid 100 150 ns

tE2HQV Chip Enable 2 High to Output Valid 100 150 ns

tGLQV Output Enable Low to Output Valid 50 75 ns

tE1LQX Chip Enable 1 Low to Output Transition 10 10 ns

tE2HQX Chip Enable 2 High to Output Transition 10 10 ns

tGLQX Output Enable Low to Output Transition 5 5 ns

tE1HQZ Chip Enable 1 High to Output Hi-Z 50 75 ns

tE2LQZ Chip Enable 2 Low to Output Hi-Z 50 75 ns

tGHQZ Output Enable High to Output Hi-Z 40 60 ns

tAXQX Address Transition to Output Transition 5 5 ns

9/27

M48T08, M48T08Y, M48T18

WRITE Mod e

The M48T08/18/ 08Y is in the WRITE Mode when-

ever W, E1, and E2 are active. The start of a

WRITE is ref erenced from the latter occurring fal l -

ing edge of W or E1, or the rising edge of E2. A

WRITE is terminated by the earlier rising edge of

W or E1, or the f alling edge of E2. The addres ses

must be held valid throughout the cycle. E1 or W

must return high or E2 low for a minimum of tE1HAX

or tE2LAX from Chi p Enable or tWHAX from WRITE

Enable prior to the initiation of another READ or

WRITE Cycle. Data-in must be valid tDVWH prior to

the end of WRITE and remain valid for tWHDX af-

terward. G should be kept high during WRITE Cy-

cles to avoid bus contention; however, if the output

bus has been activated by a low on E1 and G and

a high on E2, a low o n W will disable the outp uts

tWLQZ after W fa lls .

Figure 8. WRITE Enable Controlled, WRITE AC Wavefo rm

AI00963

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A12

DQ0-DQ7

VALID

tAVWH

tAVE1L

tAVE2H

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

M48T08, M48T08Y, M48T18

10/27

Figu re 9 . Chip Enable Controlled, WRITE AC Wav eforms

AI00964B

tAVAV

tE1HAX

tDVE1H

tDVE2L

A0-A12

DQ0-DQ7

VALID

tAVE1H

tAVE1L

tAVWL

tAVE2L

tE1LE1H

tE2LAX

tAVE2H tE2HE2L

tE1HDX

tE2LDX

DATA INPUT

11/27

M48T08, M48T08Y, M48T18

Table 4. WRITE Mo de AC Characteristics

Note: 1. Val i d fo r Ambien t Operat in g T em pera t ure: TA = 0 to 70 ° C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (ex cept whe re noted) .

Symbol Parameter(1)

M48T08/M48T18/T08Y

Unit–100/–10 (T08Y) –150/–15 (T08Y)

MinMaxMinMax

tAVAV WRITE Cycle Time 100 150 ns

tAVWL Address Valid to WRITE Enable Low 0 0 ns

tAVE1L Address Valid to Chip Enable 1 Low 0 0 ns

tAVE2H Address Valid to Chip Enable 2 High 0 0 ns

tWLWH WRITE Enable Pulse Width 80 100 ns

tE1LE1H Chip Enable 1 Low to Chip Enable 1 High 80 130 ns

tE2HE2L Chip Enable 2 High to Chip Enable 2 Low 80 130 ns

tWHAX WRITE Enable High to Address Transition 10 10 ns

tE1HAX Chip Enable 1 High to Address Transition 10 10 ns

tE2LAX Chip Enable 2 Low to Address Transition 10 10 ns

tDVWH Input Valid to WRITE Enable High 50 70 ns

tDVE1H Input Valid to Chip Enable 1 High 50 70 ns

tDVE2L Input Valid to Chip Enable 2 Low 50 70 ns

tWHDX WRITE Enable High to Input Transition 5 5 ns

tE1HDX Chip Enable 1 High to Input Transition 5 5 ns

tE2LDX Chip Enable 2 Low to Input Transition 5 5 ns

tWLQZ WRITE Enable Low to Output Hi-Z 50 70 ns

tAVWH Address Valid to WRITE Enable High 80 130 ns

tAVE1H Address Valid to Chip Enable 1 High 80 130 ns

tAVE2L Address Valid to Chip Enable 2 Low 80 130 ns

tWHQX WRITE Enable High to Output Transition 10 10 ns

M48T08, M48T08Y, M48T18

12/27

Data Retention Mode

With valid VCC applied, the M 48T08/18/08Y oper-

ates as a convention al BY TEWIDE™ st atic RA M.

Should t he suppl y volt age decay, the RAM wil l au-

tomatically power-fail de se lect, write protecting it-

self when VCC falls within the VPFD (max), VPFD

(min) window. All outputs become high imped-

ance, and all inputs are treated as “Don't care.”

Note: A power failure during a WRITE cycle may

corrupt data at the currently addressed location,

but does not jeopardize the rest of t he RAM's con-

tent. At voltages below VPFD (min), the user can be

assured the memory will be in a write protected

state, provided t he VCC fall time i s not less than tF.

The M48T08/18/08Y may respond to transient

noise spikes on VCC that reach into the deselect

window during the time the device is sampling

VCC. Therefore, decoupling of the power supply

lines is re comm ended.

When VCC drops below VSO, the control circuit

switches power to the internal battery which pre-

serves data and powers the clock. The internal

button cell will maintain data in the M48T08/18/

08Y for an accumulated period of at least 10 years

when VCC is less than VSO.

Note: Requires use of M4T32-BR12SH

SNAPHAT® t op when using the SOH28 pack age.

As system power returns and VCC rises above

VSO, the battery is disconnected and the power

supply is switched to external VCC.

Write protecti on cont inues until VCC reaches VPFD

(min) plus trec (min ). E1 should be kept high or E2

low a s VCC rises past VPFD (m in) to prevent i nad-

ver tent WRITE cyc les prior t o syst em stabilization.

Normal RAM operation can resume trec after VCC

exceeds VPFD (max).

For more information on Battery Storage Li fe refer

to the A pp lication Note AN101 2.

Power-fail Interrupt Pin

The M48T08/18/08Y continuously monitors VCC.

When VCC falls to the power-fail detect trip point,

an interrupt is immediate ly generated. An internal

clock provides a delay of between 10µs and 40µs

before automatically deselecting the M48T08/18/

08Y. The INT pin is an open drain output and re-

quires an external pull up r esistor, even if t he inter-

rupt output function is not being us ed .

13/27

M48T08, M48T08Y, M48T18

CL OCK OP ERATIONS

Reading the Clock

Updates to the TIMEKEEPER® registers should

be halted before clock data is read to prevent

reading data in transition. The BiPORT™ TIME-

KEEPER cell s i n the RAM a r r ay are o n ly dat a r eg -

isters and not the actual clock counters, so

updating the registers can be halted without dis-

turbing the clock i tself.

Updating is halted when a '1' is written to the

READ Bit, the seventh bit in the control register.

As long as a '1' rem ains in that po si tion, updating

is halted. After a halt is issued, the registers reflect

the count; that is, the day, dat e, and the time that

were current at the moment the halt command was

issued.

All of the TIMEKEEPER registe rs are up dated si-

multaneously. A halt will not interrupt an update in

progress. Updating is within a second af ter the bit

is re se t to a '0.'

S etti ng the C l ock

The eighth bit of the cont rol register is the WRI TE

Bit. Setting the WRITE Bit to a '1,' like the READ

Bit, halts updates to the TIMEKEEPER registers.

The user can then load them with the correct day,

date, and ti me data in 24 hour BCD format (on Ta-

ble 5.). Resetting the WRITE Bit to a '0' then trans-

fers t he v alues of all time registers (1FF9h-1FFFh )

to the actual TIMEKEEPER counters and allows

normal operation to resume. The FT Bit and the

bits marked as '0' in T able 5. must be written to '0'

to allow for normal TIMEKEEPER and RAM oper-

ation.

See the Application Note AN923, “TIMEKEEPER®

Rolling Into the 21st Century” for information on

Century Rollover.

Table 5. Register Map

Keys: S = SIGN Bit

FT = FREQUENCY TEST Bit (Set to '0' for normal clock operation)

R = READ Bit

W = WRI T E Bi t

ST = STOP Bit

0 = Must be set to '0'

Address Data Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

1FFFh 10 Years Year Year 00-99

1FFEh 0 0 0 10 M Month Month 01-12

1FFDh 0 0 10 Date Date Date 01-31

1FFCh 0 FT 0 0 0 Day Day 01-07

1FFBh 0 0 10 Hours Hours Hours 00-23

1FFAh 0 10 Minutes Minutes Minutes 00-59

1FF9h ST 10 Seconds Seconds Secon ds 00-59

1FF8h W R S Calibration Control

M48T08, M48T08Y, M48T18

14/27

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the

device is going to spend a significant amount of

time on the shelf, the oscillator can be turned off to

minimize current drain on the battery. The ST OP

Bit (ST) is the MSB of the seconds register. Setting

it to a '1' stops the os cillator. Th e M4 8T08/ 18/08Y

(in the PCDIP28 package) is shipped from STMi-

croelectronics with the STOP Bit set to a '1.' When

reset to a '0,' the M48T08/18/08Y oscillator starts

within one second.

Note: To guarantee oscillator start-up after initial

power-up, first write the STOP B it (ST) to '1,' then

re set to '0. '

Ca libr a tin g t h e C lock

The M48T08/18/08Y is driven by a quartz-con-

trolled oscillator with a nominal frequency of

32,768 Hz. A typical M48T08/18/08Y is accurate

within 1 minute per mont h at 25°C without cal i bra-

tion. The devices are tested not to exceed ± 35

ppm (parts per million) oscillator frequency error at

25°C, which equates to about ±1.53 minutes per

month. With the calibration bits properly set, the

accuracy of each M48T08/18/08Y improves to

better than +1/–2 ppm at 25°C.

The oscillation rate of any crystal changes with

temperature. Figure 10., page 15 shows the fre-

quency error that can be expected at vari ous tem-

peratures. Most clock chips compensate for

crystal frequency a nd tem perature shift error with

cumbersome “trim” capacitors. The M48T08/18/

08Y design, however, employs periodic counter

correction. The calibr ation circuit adds or subtract s

counts from the oscillator divider circuit at the di-

vide by 256 stage, as shown in Figure

11., page 15. The number of times pulses are

blanked (subtracted, negative calibration) or split

(added, positive calibration) depends upon the

value loaded into the five-bit Calibration Byte

found in the Control Register. Adding counts

speeds the clock up, sub tracting counts slows the

clock down.

The Calibration Byte occupies the five lower order

bits in the Control register. This by te can be set t o

represent any value between 0 and 31 in binary

form. The sixt h bi t is the Sign Bit; '1' indicates pos-

itive calibration, '0' indicates negative calibration.

Calibration occurs within a 64 minute cycle. The

fi rst 62 minutes i n the cycle may, o nce per minut e,

have one second either shortened by 128 or

lengthene d by 256 oscillato r cycles. If a binary '1'

is l oaded into the register, only the first 2 minutes

in the 64 minute cycle will be modified ; if a binary

6 is loaded, the first 12 will be affected, and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 osc illator cycles for

every 125,829,120 actual oscillator cycles; that is

+4.068 or –2.034 ppm of adjustment per calibra-

tion step i n t he cal ibration register. Assum ing that

the oscillator is in fact running at exactly 32,768Hz ,

each of the 31 increments in the Calibration Byte

would represent +10.7 or –5.35 seconds per

month which c orresponds to a total range of +5.5

or –2.75 minutes per month.

Two methods are available for ascertaining how

much calibration a given M48T08/1 8/08 Y may re-

quire. The first involves simply setting the clock,

letting it run for a month and comparing it to a

known accurate reference (lik e WWV broadcasts) .

While that may seem crude, it allows the designer

to give the end user the ability to calibrate his clock

as his environment may require, even after the fi-

nal product is packaged in a non-user servi ceable

enclosure. All the d esigner has t o do i s provide a

simple utility that accesses the Calibration Byte.

The second approach is better suited to a m anu-

facturing environment, and involves the use of

standard test equipment. When the Frequency

Test (FT) Bit, the seventh-most significant bit in

the Day Regis ter , is s et to a '1 ,' an d the oscilla tor

is running at 32,768 Hz, the LSB (DQ0) of the Sec-

onds Register will toggle at 512 Hz. Any deviation

from 51 2 Hz in dicat es th e degree and direction of

oscillator frequency shift at the test temperature.

For example, a reading of 512.01024 Hz would in-

dicate a +20 ppm oscillator frequency error, requir-

ing a –10 (WR001010) to be loaded into the

Calibration Byte for correction.

Note: Setting or changing the Calibration Byte

does not affect the Frequency Test output fre-

quency. The device must be selected and ad-

dresses must be stable at Address 1FF9h when

reading the 512 Hz on DQ0.

The LSB of th e S econds Regist er is m onitored by

holding the M48T08/18/08Y in an extended READ

of the Seconds Register, but without having the

READ Bit set. The FT Bit MUST be reset to '0' for

normal clock operations to resume.

For more i nformation on cali bration, see the A ppli-

cation Note AN934, “TIMEKEEPER® Calibra t ion.”

15/27

M48T08, M48T08Y, M48T18

Figure 10. Crys tal Accuracy Acro ss Tem p eratur e

Figu re 11 . Cl ock C al ib r at i on

AI02124

-80

-60

-100

-40

-20

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70

∆F= -0.038 (T - T

)

± 10%

Fppm

= 25 °C

ppm

°C

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

M48T08, M48T08Y, M48T18

16/27

VCC Noise And Negative Go ing Transients

ICC transients, including those produced by output

switching, can produce voltage fluctuations, re-

sulting in spi kes on the VCC bus. These trans ien ts

can be reduced if capaci tors are used to store en-

ergy which stabilizes the VCC bus. The energy

stored in the bypass c apacit ors will be released as

low going spikes are generated or energy will be

absorbed when overshoots occur. A ceramic by-

pass capaci tor value of 0.1µF (as shown in Figure

12.) is recomm ended in order to provide the need-

ed filtering.

In addition to t ransients that are caused by normal

SRAM operation, power cycling can generat e neg-

ative voltage s pikes on VCC that drive it to values

below VSS by as much as one volt. These negative

spikes can cause data corruption in the SRAM

while in battery backup mode. To protect from

these voltage spikes, it is recommended to con-

nect a schottky diode from VCC to VSS (cathode

connected to VCC, ano de to VSS). Schottky diode

1N5817 is recommended for through hole and

MBRS120T3 is recommended for surface mount.

Figure 12. Supply Voltage Protection

AI02169

VCC

0.1µF DEVICE

VCC

VSS

17/27

M48T08, M48T08Y, M48T18

MAXI MUM RAT IN G

Stressing the device above t he rating l isted in t he

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Oper ating sections of this specification is

not impl ied. Exposure to Absol ute Max imum Ra t-

ing conditions for extended periods may affect de-

vice reliability. Refer also to the

STMicroelectronics S URE P rogram and other rel-

evant quality documents.

Table 6. Absolute Maximum Ratings

Note: 1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not t o exceed 150°C for longer

th an 30 seconds).

2. For SO packag e, s tandard (SnPb) lead fini sh: Re flow at peak temperatu re of 225° C (tota l thermal budget not t o excee d 180°C fo r

betw een 90 t o 150 sec o nds) .

3. For SO package, Lead-fr ee (Pb-f ree) lead fini sh: Refl ow at peak tem perature of 260°C (t ot al thermal budget not to exceed 245°C

for greater than 30 seconds).

CAUTION: N egative undershoots be l ow –0.3V are not allowed on any pin while in the Batt ery B ack- up mode.

CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPH AT so ckets.

Symbol Parameter Value Unit

TAAmbient Operating Temperature 0 to 70 °C

TSTG S torage Te mperat ure (VCC Off, Oscillator Off) –40 to 85 °C

TSLD(1,2,3) Lead Solder Temperature for 10 seconds 260 °C

VIO Input or Output Voltages –0.3 to 7 V

VCC Supply Voltage –0.3 to 7 V

IOOutput Current 20 mA

PDPower Dissipation 1 W

M48T08, M48T08Y, M48T18

18/27

DC AND AC PARAM ETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Characteristic tables are

derived from tests pe rf ormed unde r t he Measure-

ment Condition s listed in the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 7. Operating and AC Measurem en t Conditions

Note: Output Hi -Z is defi ned as the point where dat a i s no longer driv en.

Fi gure 13. AC Testi ng Load Cir cuit

Table 8. Capacitance

Note: 1. Effective c apacitance me asured with power supply at 5V; s ampled only, not 100% tested.

2. At 25° C, f = 1MHz.

3. Outputs deselected .

Parameter M48T08 M48T18/T08Y Unit

Supply Voltage (VCC)4.75 to 5.5 4.5 to 5.5 V

Ambient Operating Temperature (TA)0 to 70 0 to 70 °C

Load Capacitance (CL)100 100 pF

Input Rise and Fall Times ≤ 5 ≤ 5ns

Input Pulse Voltages 0 to 3 0 to 3 V

Input and Output Timing Ref. Voltages 1.5 1.5 V

AI01019

OUT

CL = 100pF

CL includes JIG capacitance

1.8kΩ

DEVICE

UNDER

TEST

1kΩ

Symbol Parameter(1,2) Min Max Unit

CIN Input Capacitance 10 pF

CIO(3) Input / Output Capacitance 10 pF

19/27

M48T08, M48T08Y, M48T18

Table 9. DC Characteristics

Note: 1. Val i d fo r Ambien t Operat in g T em pera t ure: TA = 0 to 70 ° C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (ex cept whe re noted) .

2. Outputs deselected .

3. Mea su re d with Cont rol Bits se t as fo ll ows: R = '1'; W, ST, FT = ' 0 .'

4. The INT pin is Open Drain.

Symbol Parameter Test Condition(1) M48T08/M48T18/T08Y Unit

Min Max

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO(2) Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC Supply Current Outputs open 80 mA

ICC1(3) Supply Current (Standby) TTL E1 = VIH, E2 = VIL 3mA

ICC2(3) Supply Current (Standby) CMOS E1 = VCC – 0.2V,

E2 = VSS + 0.2V 3mA

VIL Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2.2 VCC + 0.3 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

Output Low Voltage (INT)(4) IOL = 0.5mA 0.4 V

VOH Output High Voltage IOH = –1mA 2.4 V

M48T08, M48T08Y, M48T18

20/27

Figure 14. Power Down /U p Mode AC Waveform s

Note : Inp uts may or may n ot b e rec ogni zed at this time . Caut ion sho uld be tak en to ke ep E1 hi gh or E2 low as V CC rises past VPFD (min).

Some syste ms may perform ina dvertent WRITE cycles after VCC rises above VPFD (min ) but befo re normal system oper ations begin.

Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running.

Table 10. Power Down/U p AC Characteri stics

Note: 1. Val i d fo r Ambien t Operat in g T em pera t ure: TA = 0 to 70 ° C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (ex cept whe re noted) .

2. VPFD (max) to VPFD (min) fall time of les s than t F may result in deselection/wri te protection not occurring until 200µs after VCC p a ss-

es VPFD (mi n).

3. VPFD (min) to VSS fall time of less than tFB may c ause corruption of RAM data.

Table 11. Power Down/U p Trip Points DC Characteristic s

Note: 1. All voltages referen ced to VSS.

2. Vali d for Ambient Operating Tem perature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (ex cept where noted) .

3. At 55°C, VCC = 0V; tDR = 8.5 years (typ) at 70°C. Requires use of M4T32-BR12SH SNAPHAT® t op when using the SOH28 package.

Symbol Parameter(1) Min Max Unit

tPD E1 or W at VIH or E2 at VIL before Po wer Down 0µs

tF(2) VPFD (max) to VPFD (min) VCC Fall Time 300 µs

tFB(3) VPFD (min) to VSS VCC Fall Time 10 µs

tRVPFD (min) to VPFD (max) VCC Rise Time 0µs

tRB VSS to VPFD (min) VCC Rise Time 1µs

trec E1 or W at VIH or E2 at VIL before Power Up 1ms

tPFX INT Low to Auto Deselect 10 40 µs

tPFH VPFD (max) to INT High 120 µs

Symbol Parameter(1,2) Min Typ Max Unit

VPFD Power-fail Dese lect Voltage M48T08 4.5 4.6 4.75 V

M48T18/T08Y 4.2 4.3 4.5 V

VSO Battery Back-up Switchover Voltage 3.0 V

tDR Expected Data Retention Time 10(3) YEARS

AI00566

VCC

INPUTS

INT

(PER CONTROL INPUT)

OUTPUTS

DON'T CARE

HIGH-Z

tFB

tPFX

tPFH

trec

tPD tRB

tDR

VALID VALID

NOTE

(PER CONTROL INPUT)

RECOGNIZEDRECOGNIZED

VPFD (max)

VPFD (min)

VSO

21/27

M48T08, M48T08Y, M48T18

P ACKAGE MECHANICAL INFO RMATION

Figure 15. PCDIP28 – 28-pi n Plastic DIP, battery CAPHAT, Package Outline

No te : D rawing is not to scale.

Table 12. PCDIP28 – 28-pin Plastic DIP , battery CAPHAT, Package Me chanica l Data

Symb mm inches

Typ Min Max Typ Min Max

A 8.89 9.65 0.350 0.380

A1 0.38 0.76 0.015 0.030

A2 8.38 8.89 0.330 0.350

B 0.38 0.53 0.015 0.021

B1 1.14 1.78 0.045 0.070

C 0.20 0.31 0.008 0.012

D 39.37 39.88 1.550 1.570

E 17.83 18.34 0.702 0.722

e1 2.29 2.79 0.090 0.110

e3 29.72 36.32 1.170 1.430

eA 15.24 16.00 0.600 0.630

L 3.05 3.81 0.120 0.150

N28 28

PCDIP

B1 B e1

M48T08, M48T08Y, M48T18

22/27

Figure 16. SO H28 – 28-le ad Plas tic S m all Outlin e, 4 -socket battery SNAP HAT, Package Outline

No te : D rawing is not to scale.

Table 13. SOH28 – 28-lead Plastic SO, 4-socket battery SNAPHAT, Package Mech. Data

Symb mm inches

Typ Min Max Typ Min Max

A 3.05 0.120

A1 0.05 0.36 0.002 0.014

A2 2.34 2.69 0.092 0.106

B 0.36 0.51 0.014 0.020

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e1.27– –0.050– –

eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

α0° 8° 0° 8°

N 28 28

CP 0.10 0.004

SOH-A

LA1 α

23/27

M48T08, M48T08Y, M48T18

Figure 17. SH – 4-pin SNA PH AT Ho using for 4 8m Ah Batt ery & Crystal, Package Ou tline

No te : D rawing is not to scale.

Tabl e 14. SH – 4- pi n S N APH AT Housing for 48mAh Batte ry & Crystal, Pack age Me ch. Da t a

Symb mm inches

Typ Min Max Typ Min Max

A 9.78 0.385

A1 6.73 7.24 0.265 0.285

A2 6.48 6.99 0.255 0.275

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 14.22 14.99 0.560 0.590

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

SHTK-A

A1 A

M48T08, M48T08Y, M48T18

24/27

Figure 18. SH – 4-pin SNAPHAT Housin g for 120mAh Battery & Crystal, Package Outline

No te : D rawing is not to scale.

Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal , Package Mech. Data

Symb mm inches

Typ Min Max Typ Min Max

A 10.54 0.415

A1 8.00 8.51 0.315 .0335

A2 7.24 8.00 0.285 0.315

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 17.27 18.03 0.680 .0710

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

SHTK-A

A1 A

25/27

M48T08, M48T08Y, M48T18

PART NUMBERING

Table 16. Ordering Information Scheme

Note: 1. The M48T08 /1 8 part is offered with the PCDIP28 (e.g., CA P HAT™) package only.

2. The SOIC pac kage (S OH28) requires the SNA P HAT® ba tt ery/crystal p ackage which is ordered separate l y under t he part number

“M4 T XX- BR12S H” in pl as tic tube o r “M4T XX- BR12S HTR” in T a pe & Reel fo rm (s ee Table 17.). The M48T08Y part is offered in the

SOH28 (SNA P HAT) package o nl y.

Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell bat-

tery.

For other options, or for more information on any aspec t of t his device, pl ease contact the ST Sales Of fice

nearest you.

Table 17. SNAPHAT Battery Table

Example: M48T 18 –100 PC 1 E

Device Type

M48T

Supply Voltage and Write Protect Voltage

08(1) = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V

18/08Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V

Speed

–100 = 100ns

–150 = 150ns

–10 = 100ns (M48T08Y)

Package

PC(1) = PCDIP28

MH(2) = SOH28

Temperature Range

1 = 0 to 70°C

Shipping Method

For SOH28:

blank = Tubes (Not for New Design - Use E)

E = ECOPACK Package, Tubes

F = ECOPACK Package, Tape & Reel

TR = Tape & Reel (Not for New Design - Use F)

For PCDIP28:

blank = ECOPACK Package, Tubes

Part Number Descript ion Package

M4T28-BR12SH Lithium Battery (48mAh) SNAPHAT SH

M4T32-BR12SH Lithium Battery (120mAh) SNAPHAT SH

M48T08, M48T08Y, M48T18

26/27

REVISION HISTORY

Table 18. Document Revi sion History

Date Version Revision Details

December 1999 1.0 First Issue

07-Feb-00 2.0 From Preliminary Data to Data Sheet; Battery Low Flag paragraph changed; 100ns

speed class identifier changed (Tables 3, 4)

11-Jul-00 2.1 tFB changed (Table 10); Watchdog Timer paragraph changed

16-Jul-01 3.0 Reformatted; SNAPHAT battery table added (Table 17); added temp./voltage info. to

tables (Tables 8, 9, 3, 4, 10, 11)

01-Aug-01 3.1 Reference to App. Note corrected in “Calibrating the Clock” section

21-Dec-01 3.2 Changes to text in document to reflect addition of M48T08Y option

06-Mar-02 3.3 Fix Ordering Information table and add to footnote (Table 16)

20-May-02 3.4 Modify reflow time and temperature footnotes (Table 6)

29-Aug-02 3.5 tDR specification temperature updated (Table 11)

28-Mar-03 4.0 v2.2 template applied; updated test conditions (Table 10)

10-Dec-03 5.0 Reformatted

30-Mar-04 6.0 Reformatted; Lead-free (Pb-free) information package update (Table 6, 16)

13-Dec-05 7.0 Updated template, Lead-free information, removed footnote (Table 9, 16)

27/27

M48T08, M48T08Y, M48T18

Information fur nished is believed to b e accurate and relia ble. However, STMicroelectronics a ssumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for us e as c ri t i cal com ponents in lif e support devices or syste m s without express written approv al of STMi croelect ronics.

The ST l ogo i s a regist ered tra dem ark of STMi croelectron ics.

All other names are th e property of their respec tive owners

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