NJU26060-05A Digital Signal Processor with PWM Modulator for Correction of Sound General Description The NJU26060-05A is a high performance 24-bit digital signal processor included sampling rate converter (SRC), PWM modulators. The NJU26060-05A provides Stereo Expander II, Elevation, 256Tap FIR filter, 8band IIR filter, Dynamic Bass Boost, two systems Limiter, and Dynamic Range Compression. The NJU26060-05A is suitable for TV, mini component, CD radio-cassette, speakers system and other audio products. Package NJU26060V-05A Features - Hardware 24bit Fixed-point Digital Signal Processing Clock Frequency : 24.576MHz, Embedded PLL Circuit Sampling rate converter (SRC) : Fs=8kHz to 192kHz 48kHz PWM modulator : 4ch Outputs (2 stereos) Digital interface transmitter (DIT) : 1 port Digital Audio Interface : 3 Input ports / 2 Output ports (switch over from PWM output) Digital Audio Format : I2S 24bit, Left-justified, Right-justified, BCK : 32/64fs Master / Slave Mode - Sampling Rate Converter: Slave mode - DSP: Master Mode Host Interface : I2C Bus ( Fast-mode/400kbps) Power Supply : VDD = 3.3V Input terminal: : 5V Input tolerant Package : SSOP44 (Pb-Free) - Software HPF Input Signal Detect Input Trim Stereo Expander Elevation 256Taps FIR Filter 8Band IIR Filter (78Band PEQ + Shelf Filter) Master Volume DBB Xover (HPF/LPF) DRC SDO0 DRC Mixer SDO1 Cch : C/SW Mixer Delay Output Trimmer / Inverter Limiter BEEP * The detail hardware specification of the NJU26060-05A is described in the "NJU26060 Series Hardware Specification". Ver.2014.02.04 -1- NJU26060-05A DSP Block Diagram 24Bit Fixed-point DSP Core BCKO LRO SDI0 SDI1 Serial Audio Interface (Master) PWM Modulator 0 Over Sampling Digital Filter Delta-Sigma Modulator PWM Generator OUTLP0 Over Sampling Digital Filter Delta-Sigma Modulator PWM Generator OUTRP0 OUTLN0 OUTRN0 SDI2 PWMEN0 PWM_MUTEb SDI Select PWM_DISb PWM_ERRb BCKO LRO 512fs PWM Modulator 1 PROGRAM CONTROL Sampling Rate Convertor (Slave) 24Bit x 24Bit MULTIPLIER Over Sampling Digital Filter Delta-Sigma Modulator OUTLN1 BCKI SDO0 ALU LRI OUTLP1 PWM Generator Over Sampling Digital Filter SCL Delta-Sigma Modulator OUTRP1 PWM Generator OUTRN1 I2C INTERFACE ADDRESS GENERATION UNIT SDO1 SDA PWMEN1 RESETb BCKO LRO MCKO S/PDIF Transmitter 2048fs TIMING GENERATOR / PLL 256fs SDO OFF 512fs CLKOUT GPO GPIO INTERFACE CLK WDC PROC FIRMWARE OTP PROGRAM RAM 1.8V DATA RAM0 VREGO LDO DATA RAM1 Fig 1. NJU26060-05A Hardware Block Diagram Function Block Diagram SDI0 HPF Input Signal Detect Input Trim Stereo Expander Elevation 256Taps FIR Filter 8Band IIR Filter Master Volume DBB SDI1 SDI2 BEEP SDO0 (L/R) HPF out LPF DRC DRC DRC Mixer C/SW Mixer Delay Output Trimmer -96dB ~ +24dB / Inverter HPF Limiter SDO1 (C/SW or SW) Limiter LPF out Fig 2. NJU26060-05A Block Diagram -2- Ver.2014.02.04 NJU26060-05A Pin Configuration RESETb 1 44 BCKO PWM_MUTEb 2 43 LRO PWM_DISb SDA 3 42 MCKO 4 41 SDO SCL 5 40 TEST3 LRI 6 39 BCKI 7 38 SDI0 8 37 GPO WDC PROC SDI1 9 36 TEST2 SDI2 10 35 CLK REGDISb 11 34 CLKOUT VDD 12 33 VDD VSS 13 32 VSS VREGO 14 31 VREGO VDDPLL 15 30 TEST1 VSSPLL PWMEN1 16 17 29 28 PWM_ERRb PWMEN0 OUTRN1 18 27 OUTRN0 OUTRP1 19 26 OUTRP0 OUTLN1 20 25 OUTLN0 OUTLP1 21 24 OUTLP0 VSSPWM 22 23 VDDPWM NJU26060-05A Fig 3. NJU26060-05A Pin Configuration Ver.2014.02.04 -3- NJU26060-05A Pin Description Table 1. Pin No. Symbol I/O 1 RESETb I Reset 2 PWM_MUTEb I+ PWM Block Mute request input 3 PWM_DISb I+ PWM Block Standby request input 4 SDA OD 5 SCL I I2C clock (connect to VSS when this is not used) 6 LRI I- LR Clock Input for Fs conversion side 7 BCKI I- Bit Clock Input for Fs conversion side SDI0 I- Audio Data Input 0 SDI1 I- Audio Data Input 1 SDI2 I- Audio Data Input 2 REGDISb I Built-in Power Supply Enable (connect to VDD) VDD P Power Supply +3.3V GND 8 9 10 11 12 13 Description (RESETb="Low" : DSP Reset) I2C serial data I/O (connect to VSS with 3.3kohm when this is not used) VSS G 14 VREGO PI Built-in Power Supply Bypass (connect capacitors 10uF and 0.01uF) 15 VDDPLL PA PLL Power Supply +1.8V (connect to VREGO) 16 VSSPLL GA PLL Power Supply GND 17 PWMEN1 O 18 OUTRN1 OP PWM1 R- output / Audio Data output 1 (setting Firmware) 19 OUTRP1 OP PWM1 R+ output 20 OUTLN1 OP PWM1 L- output / Audio Data output 0 (setting Firmware) 21 OUTLP1 OP PWM1 L+ output 22 VSSPWM GP PWM Power Supply GND 23 VDDPWM PP PWM Power Supply +3.3V (decoupling capacitor is required to stable power supply) 24 OUTLP0 OP PWM0 L+ output 25 OUTLN0 OP PWM0 L- output 26 OUTRP0 OP PWM0 R+ output 27 OUTRN0 OP PWM0 R- output PWMEN0 O PWM0 enable output (PWMEN0='1': enable) PWM_ERRb I+ PWM block stop request input (PWM_ERRb='0': PWM stop) TEST1 I for Test (connected to VSS) VREGO PI Built-in Power Supply Bypass (connect capacitors 10uF and 0.01uF) GND 28 29 30 31 32 Note : Pin Description PWM1 enable output (PWMEN1='1': enable) VSS G 33 VDD P Power Supply +3.3V 34 CLKOUT O OSC Output 35 CLK I OSC Clock Input 36 TEST2 I- for Test (connected to VSS) 37 PROC I+ PROC terminal 38 WDC O+ Watch dog clock terminal 39 GPO OD Signal detection terminal 40 TEST3 I- for Test (connected to VSS) 41 SDO O OFF / DIT output 0 / GPO(same function as pin#39) (selected by command) 42 MCKO O Master Clock Output for A/D, D/A 43 LRO O LR clock Output 44 BCKO O Bit clock Output I I+ OD I/O OP : Input O: Output : Input (Pull-up) I -: Input (Pull-down) : Bi-directional (Open Drain) This pin requires a pull-up resistance. : Bi-directional PI: Built-in Power Supply Bypass : PWM output(supply for VDDPWM) NOTICE: Does not keep the terminal without the pull-up resistance or the pull-down resistance open. The functions of SDIO0 to SDIO2, SDO, OUTxxx depend on the IC specifications. -4- Ver.2014.02.04 NJU26060-05A Audio Clock Three kinds of clocks are needed for digital audio data transfer. (1) LR clock (LRI, LRO) is needed by serial-data transmission. It is the same as the sampling frequency of a digital audio signal. (2) Bit clock (BCKI, BCKO) is needed by serial-data transmission. It becomes the multiple of LR clock. (3) Master clock (MCKO) needed by A/D, D/A converter, etc. It becomes the multiple of LR clock. It is not related to serial audio data transmission. The NJU26060-05A support serial data format that includes 32(32fs) or 64(64fs) BCK clocks. The NJU26060-05A supplies the clock necessary for digital audio data transmission to an external device as a master device by each terminal of MCKO, BCKO, and LRO. On the other hand, the sampling rate converter that works as a slave device takes digital audio data with the clock input to BCKI and the terminal LRI, and converts the sampling frequency into the clock system composed of MCKO/BCKO/LRO. After internal reset ends as a master clock, the terminal MCKO sets the buffer output or 2 dividing frequency the output of the input clock to the terminal CLK. The stop is also possible according to the command of the firmware. The NJU26060-05A is used by 512 times the internal operation sampling frequency (It is 24.576MHz in the sampling frequency 48kHz). In that case, NJU26060-05A can output 64 times, 32 times the bit clock to of the LR clock one time the sampling frequency and of each, and 512 times and 256 times the master clock as a mastering device. Table 5 shows the relation of each clock. The NJU26060 series support two clock frequencies (24.576kHz ,or 22.572kHz) as hardware specifications. However NJU26060-05A acceptable one clock frequency (24.576kHz), cause of the software on NJU26060-05A supports one clock frequency (24.576kHz). Table 2. Supply Clock for CLK pin Frequency and BCKO,LRO,MCKO Clock Frequency Clock Signal Multiple Frequency 24.576MHz(for pin#35) LRO BCKO(32Fs) BCKO(64Fs)* MCKO(256Fs)* MCKO(512Fs) 1Fs 32Fs 64Fs 256Fs 512Fs 48kHz 1.536MHz 3.072MHz 12.288MHz 24.576MHz * default for starting up Serial Audio Data Input/Output Audio interface of the NJU26060-05A includes three data input ports: SDI0, SDI1 and SDI2 (Table 3), and three data output ports: SDO0, SDO1 and SDO2 (Table 4). Table 3. Pin No. 8 9 10 Serial Audio Input Pin Description Symbol Description SDI0 Audio Data Input 0 SDI1 Audio Data Input 1 SDI2 Audio Data Input 2 Table 4. Serial Audio Output Pin Description Pin No. Symbol Description 20 OUTLN1 Audio Data Output 0 (L/R) 18 OUTRN1 Audio Data Output 1 (C/SW) 41 SDO OFF Pin#20, 18 can be change the function to PWM1 output. Pin#41 can be change the function to DIT (output 0) or GPO output (the function is same as Pin#39). Refer to table1. Ver.2014.02.04 -5- NJU26060-05A I2C bus Interface I2C bus interface transfers data to the SDA pin and clocks data to the SCL pin. SDA pin is a bi-directional open drain and requires a pull-up resister. The slave address is set up as Table 5. When the initialization is finished (After reset NJU26060-05A), NJU26060-05A can be communicated with Host. However until finished the initialization, the Host can't be get any correct responses. Note : The serial host interface supports "Standard-Mode (100kbps)" and "Fast-Mode (400kbps)" I2C bus data transfer. Table 5. bit7 0 bit6 0 Serial Host Interface Pin Description bit5 1 Fixed value bit4 1 R/W bit3 1 bit2 0 bit1 0 bit0 R/W Data format Start bit R/W bit Slave Address 7bit ACK *: On "R/W bit", "0"="W", "1"="R". General-purpose in/out pin The NJU26060 Series has general-purpose in/out pin. On NJU26060-05A, these terminals operate as below functions (Table 6). Table 6. Pin No. 40 39 -6- General-purpose in/out pin and pin disposal Symbol TEST3 (Pull-down I) GPO (O) 38 WDC (O) 37 PROC (I) Description Terminal for a test. Connect to VSS Signal detection terminal. Default is Hi-Z. Connect to VDD with pull-up resistor. It outputs Low If it detects no signal. Output of the watchdog clock. This terminal is toggled between "Low" and "High" in the audio processing. Thus, this terminal notifies the correct operating to another devices. If monitored by watchdog IC, microcontroller, and so on, abnormal condition can be detected. The rate of WDC is 100msec (10Hz). . PROC terminal, H: However reset the NJU26060-05A, signal processing is not started. To start signal processing, start command is required. L: After reset the NJU26060-05A, signal processing is started (default setting: master volume is muted). Ver.2014.02.04 NJU26060-05A Command Table Table 7. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Command table Function Set Task System State Smooth Control Config Master Volume Control Command Volume Control Command Input Trim Command Input Select Command Elevation Gain Command Time Alignment Command IIR Filter Fo Command IIR Filter Q Command IIR Filter Gain Command IIR Filter Mode Command IIR Filter Smooth Command FIR Bypass Trim Command FIR New Coeff Send Lch Command FIR New Coeff Send Rch Command FIR Coeff Update Command Expander Gain Command Expander Low Boost Command DBB LPF Fc Command DBB Attack Time / Release Time Command DBB Level Command DBB Effect Command DBB Treble Boost Level Command DRC Mode Select Command DRC Ratio And Attack Time / Release Time DRC Threshole Level Set Up Command Xover Fc Command Xover Order Command Ch Output Invert Command DRC Mixer Command Subsonic Filter Fc Command Limiter Threshold Command Input Signal Detect Command Beep Start Command PWM0 Set Command PWM1 Set Command Expander Mode Command Version Number Request Command Revision Number Request Command DSP Software Reset Command Start Command (Boot With Mute) Start Command (Boot With Unmute) Nop Command Notes : In respect to detail command information, request New Japan Radio Co., Ltd. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver.2014.02.04 -7- Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: NJR: NJU26060-05A