MCP6C02 Zero-Drift, 65V High-Side Current Sense Amplifier Features General Description * Single Amplifier: MCP6C02 * Bidirectional or Unidirectional * Input (Common-mode) Voltages: - +3.0V to +65V, specified - +2.8V to +68V, operating - -0.3V to +70V, survival * Power Supply: - 2.0V to 5.5V - Single or Dual (Split) Supplies * High DC Precision: - VOS: 1.65 V (typical) - CMRR: 154 dB (typical) - PSRR: 138 dB (typical) - Gain Error: 0.1% (typical) * Preset Gains: 20, 50 and 100 V/V * POR Protection: - HV POR for VIP - VSS - LV POR for VDD - VSS * Bandwidth: 500 kHz (typical) * Supply Currents: - IDD: 490 A (typical) - IBP: 170 A (typical) * Enhanced EMI Protection: - EMIRR: 118 dB at 2.4 GHz (typical) * Specified Temperature Ranges: - -40C to +125C (E-Temp part) - -40C to +150C (H-Temp part) The Microchip Technology Inc. MCP6C02 high-side current sense amplifier is offered with preset gains of 20, 50 and 100 V/V. The Common-mode input range (VIP) is +3V to +65V. The Differential-mode input range supports unidirectional and (VDM = VIP - VIM) bidirectional applications. The power supply can be set between 2.0V and 5.5V. Parts in the SOT-23 package are specified over -40C to +125C (E-Temp), while parts in the 3x3 VDFN package are specified over -40C to +150C (H-Temp). The Zero-Drift architecture supports very low input errors, which allow a design to use shunt resistors of lower value (and lower power dissipation). Package Types (Top View) MCP6C02 SOT-23 VOUT 1 VSS 2 VIP 3 6 VDD VIP 1 5 VREF VSS 2 4 VIM NC 3 NC 4 8 VIM EP 9 7 VREF 6 VDD 5 VOUT * Includes Exposed Thermal Pad (EP); see Table 3-1. Typical Application Circuit +5V 2.2 F 10 nF Typical Applications * Automotive (see Product Identification System) - AEC-Q100 Qualified, Grade 0 (VDFN package) - AEC-Q100 Qualified, Grade 1 (SOT-23 package) * Motor Control * Analog Level Shifter * Industrial Computing * Battery Monitor/Tester MCP6C02 3x3 VDFN * 100 nF VBAT +36V RSH 2.2 m U1 MCP6C02-100 VOUT 20 k IL < 20A VL Related Products * MCP6C04-020 * MCP6C04-050 * MCP6C04-100 2018-2019 Microchip Technology Inc. DS20006129B-page 1 MCP6C02 Functional Diagram Gain Options VDD VIP GM1 VIM I1 VOUT RM3 RF VFG I2 RG GM2 VREF VSS TABLE 1: Table 1 shows key specifications that differentiate between the three different differential gain (GDM) options. See Section 1.0 "Electrical Characteristics", Section 6.0 "Packaging Information" and the Product Identification System for further information on the GDM options available. KEY DIFFERENTIATING SPECIFICATIONS GDM (V/V) Nom. VOS ( V) Max. TC1 ( nV/C) Max. CMRR (dB) Min. PSRR (dB) Min. VDMH (V) Min. BW (kHz) Typ. Eni (Vp-p) Typ. eni (nV/Hz) MCP6C02-020 20 16 90 132 109 0.265 500 1.54 74 MCP6C02-050 50 14 70 138 115 0.106 0.95 46 MCP6C02-100 100 12 65 116 0.053 0.92 44 Part No. Note 1: 2: 3: 4: 390 Typ. VOS and TC1 limits are by design and characterization only. TC1 covers the Extended Temperature Range (-40C to +125C) and the High Temperature Range (-40C to +150C). CMRR is at VDD = 5.5V. Eni is at f = 0.1 Hz to 10 Hz. eni is at f < 500 Hz. DS20006129B-page 2 2018-2019 Microchip Technology Inc. MCP6C02 Figure 1, Figure 2 and Figure 3 show input offset voltage versus temperature for the three gain options (GDM = 20, 50 and 100 V/V). The MCP6C02's CMRR supports applications in noisy environments. Figure 4 shows how CMRR is high, even for frequencies near 100 kHz. 100 6 90 4 CMRR (dB) Input Offset Voltage; VOS (V) 8 2 0 -2 -4 GDM = 20 VDD = 5.5V 28 Samples -6 -25 0 25 50 75 100 Ambient Temperature; TA (C) 125 70 60 50 -8 -50 80 150 FIGURE 1: Input Offset Voltage vs. Temperature, GDM = 20 V/V. 40 10k 1.E+04 FIGURE 4: GDM = 100 GDM = 50 GDM = 20 100k 1.E+05 Frequency; f (Hz) 1M 1.E+06 CMRR vs. Frequency. Input Offset Voltage; VOS (V) 8 6 4 2 0 -2 -4 GDM = 50 VDD = 5.5V 28 Samples -6 -8 -50 -25 0 25 50 75 100 Ambient Temperature; TA (C) 125 150 FIGURE 2: Input Offset Voltage vs. Temperature, GDM = 50 V/V. Input Offset Voltage; VOS (V) 8 6 4 2 0 -2 -4 GDM = 100 VDD = 5.5V 27 Samples -6 -8 -50 -25 0 25 50 75 100 Ambient Temperature; TA (C) 125 150 FIGURE 3: Input Offset Voltage vs. Temperature, GDM = 100 V/V. 2018-2019 Microchip Technology Inc. DS20006129B-page 3 MCP6C02 NOTES: DS20006129B-page 4 2018-2019 Microchip Technology Inc. MCP6C02 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings VDD - VSS .................................................................................................................................................. -0.3V to +5.5V Current at Input Pins (Note 1) .................................................................................................................................2 mA Analog Inputs (VIP and VIM) (Note 1) .......................................................................................................... -0.3V to +70V All Other Inputs and Outputs.....................................................................................................VSS - 0.3V to VDD + 0.3V Input Difference Voltage (VDM) (Note 1)................................................................................................................... 1.2V Output Short-Circuit Current ........................................................................................................................... Continuous Current at Output and Supply Pins ....................................................................................................................... 30 mA Storage Temperature ..............................................................................................................................-65C to +150C Maximum Junction Temperature (Note 2) ............................................................................................................. +155C ESD protection (HBM, CDM, MM) ....................................................................................................... 2 kV, 2 kV, 300V Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. Note 1: These voltage and current ratings are physically independent; each required condition must be enforced by the user (see Section 5.1.1 "Input Voltage Limits" and Section 5.1.2 "Input Current Limits"). 2: The Absolute Maximum Junction Temperature is not intended for continuous use. 1.2 Voltage and Temperature Ranges The various voltage and temperature ranges are listed in Table 1-1. TABLE 1-1: VOLTAGE AND TEMPERATURE RANGES Parameter Units GDM (V/V) Comment VDD (Note 2) V All VDD (LV POR on) Range Type Sym. Spec. Oper. Abs. Min./Max. Min. VDDL 2.0 1.7 -0.3 VPLHVPLH 0.1 Typ. -- -- LV POR Hysteresis -- VIP (Note 2) V All Typ. -- 2.0 to 5.5 -- -- Max. VDDH 5.5 5.5 5.5 Min. VIPL 3.0 2.8 -0.3 VIP (HV POR on) VIPLD 2.8 2.6 HV POR Hysteresis VIPLH 0.2 Typ. 0.2 Typ. -- Typ. -- 34 -- -- Max. VIPH 65 68 70 VIP (HV POR on) -- Note 1: 2: 3: 4: 5: All of this table's limits are set by design and characterization. The HV POR is triggered by VIP, with hysteresis. The LV POR is triggered by VDD, with hysteresis. VDM = VIP - VIM. VIM is in its range when both VIP and VDM are in their ranges. Allowing the ambient temperature (TA) to exceed the Maximum Ambient Temperature limit (TAH) may cause parameters to exceed their specified limits. See Section 1.1 "Absolute Maximum Ratings " for the Absolute Maximum Junction Temperature and Storage Temperature limits. VOL and VOH are at RL = 1 k 2018-2019 Microchip Technology Inc. DS20006129B-page 5 MCP6C02 TABLE 1-1: VOLTAGE AND TEMPERATURE RANGES (CONTINUED) Parameter Units GDM (V/V) Comment VREF V All -- VOUT (Note 5) VDM V V All 20 -- -- Range Type Sym. Min. VRL Typ. -- Max. VRH Min. VOL All 5: 0 0 -0.3 VDD/4 -- -- VDD - 1.25 VDD - 1.15 VDD + 0.3 0.06 Max 0 -0.3 Typ. -- VDD/2 -- -- VOH VDD - 0.13 Min VDD VDD + 0.3 Min. VDML -3/GDM -4.25/GDM -1.2 Typ. -- 0 -- -- Max. VDMH 5.3/GDM 5.5/GDM +1.2 E-Temp and H-Temp Parts Min. TAL -40 -40 -40 Typ. -- 25 -- -- E-Temp Parts Max. TAH +125 +150 +155 +150 +155 H-Temp Parts Note 1: 2: 3: 4: Abs. Min./Max. -4.05/GDM All C Oper. Max. 50, 100 TA Spec. All of this table's limits are set by design and characterization. The HV POR is triggered by VIP, with hysteresis. The LV POR is triggered by VDD, with hysteresis. VDM = VIP - VIM. VIM is in its range when both VIP and VDM are in their ranges. Allowing the ambient temperature (TA) to exceed the Maximum Ambient Temperature limit (TAH) may cause parameters to exceed their specified limits. See Section 1.1 "Absolute Maximum Ratings " for the Absolute Maximum Junction Temperature and Storage Temperature limits. VOL and VOH are at RL = 1 k DS20006129B-page 6 2018-2019 Microchip Technology Inc. MCP6C02 1.3 Specifications TABLE 1-2: DC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2 and RL = 10 k to VL; see Figure 1-9 and Figure 1-10. Parameter Sym. Min. Typ. Max. Units V Gain Conditions Input Offset (VIP = VIM) (Note 1) Input Offset Voltage VOS Drift, Linear Temp. Co. VOS TC1 VOS Drift, Quadratic Temp. Co. TC2 VOS Drift, Exponential Temp. Co. TCX -16 1.9 +16 -14 1.65 +14 -12 1.5 +12 -90 10 +90 8 +70 50 -65 7 +65 100 -- 60 -- pV/C2 95 VOS -- 1.8 100 -- V Power Supply Rejection Ratio PSRR -- 20 50 0.10 100 -- V 1.9 20 50 0.09 TC1 20 0.31 0.18 TA = -40C to +125C, for E-Temp parts (Note 2, Note 3) 50 0.11 TC1 Aging 20 -70 -- Note 2 100 nV/C 105 VOS Aging 20 50 108 hr at +150C (changes measured at +25C) 100 -- nV/C 20 1.1 50 1.0 100 109 134 115 138 -- dB 50 20 116 140 100 VDD = 2.0V to 5.5V Input Current and Impedance (VIP and VIM) VIP's Input Bias Current IBP 120 170 215 A VIM's Input Bias Current IBM -- 0.2 -- nA VDD = 2.0V to 5.5V VDD = 5.5V IBM2 3 VDD = 5.5V, VDM = VDML IBM3 -2 VDD = 5.5V, VDM = VDMH Capacitance at VIP CVIP Capacitance at VIM CVIM 11 Capacitance across VDM CVDM 12 Note 1: 2: 3: 4: All -- 40 -- pF The VIP input is treated as the Common-mode input (e.g., for CMRR). VDM = (VIP - VIM). Set by design and characterization. VOS is screened in production (see Appendix B: "Offset Test Screens"). See the discussion in Section 1.6.2, Input Offset Related Errors. See Section 1.6, Explanation of DC Error Specifications. 2018-2019 Microchip Technology Inc. DS20006129B-page 7 MCP6C02 TABLE 1-2: DC ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2 and RL = 10 k to VL; see Figure 1-9 and Figure 1-10. Parameter Sym. Min. Typ. Max. Units Gain Conditions -- 2.4 3.0 V All VIPLD 2.15 2.8 VIP VIPLH 0.2 -- VIPLH = VIPL - VIPLD Input Common-Mode Voltage (VIP) VIP's Voltage Range Low VIPL VIP's Voltage Range High VIPH 65 -- -- Common-Mode Rejection Ratio CMRR 132 159 -- 138 163 Common-Mode Nonlinearity (Note 4) INLCM -- 0.006 dB 20 50 165 VIP VDD = 2.0V to 5.5V, VIP = 3V to 65V 100 -- ppm All VDD = 5.5V, VIP = 3V to 65V V All See Section 5.1.6, Setting the Voltage at VREF Reference Voltage (VREF) Reference Voltage Range (Note 2) Gain Resistance VRL -- -- 0 VRH VDD -1.25 -- -- RF + RG -- 175 -- k 185 240 VREF Input Capacitance CREF -- 11 20 50 100 -- pF All V/V 20 Differential Input (VDM) (Note 1) Differential Gain 20 GDM MCP6C02-020 50 50 MCP6C02-050 100 100 MCP6C02-100 20 VDD = 5.5V, VREF = 4.1V, VL = 0V Differential Input (VDM) - Continued (Note 1) Differential Input Voltage Range Differential Gain Error Note 1: 2: 3: 4: VDML -3/GDM -- -- V -4.05/GDM 50, 100 VDMH -- gE -- 0.1 -- -1.6 0.1 +1.6 -- 0.1 -- 5.3/GDM All % VDD = 5.5V, VREF = 0V, VL = VDD VDD = 2.0V, VREF = 0.5V, GDMVDM = -0.4V to 1.4V VDD = 5.5V, VREF = 2.75V, GDMVDM = -2.65V to 2.65V VDD = 5.5V, VREF = 0V, GDMVDM = 0.2V to 5.3V 0.1 20 VDD = 5.5V, VREF = 4.25V, GDMVDM = -3V to 1.15V 0.1 50, 100 VDD = 5.5V, VREF = 4.25V, GDMVDM = -4V to 1.15V The VIP input is treated as the Common-mode input (e.g., for CMRR). VDM = (VIP - VIM). Set by design and characterization. VOS is screened in production (see Appendix B: "Offset Test Screens"). See the discussion in Section 1.6.2, Input Offset Related Errors. See Section 1.6, Explanation of DC Error Specifications. DS20006129B-page 8 2018-2019 Microchip Technology Inc. MCP6C02 TABLE 1-2: DC ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2 and RL = 10 k to VL; see Figure 1-9 and Figure 1-10. Parameter Differential Gain Drift Sym. Min. Typ. Max. Units Gain gE/TA -- 5 -- ppm/C All -- 5 -- gE -- 0.15 -- % INLDM -- 50 -- ppm gE Aging Differential Nonlinearity (Note 4) Conditions VDD = 2.0V, VREF = 0.5V, GDMVDM = -0.4V to 1.4V VDD = 5.5V, VREF = 2.75V, GDMVDM = -2.65V to 2.65V 408 hr at +150C, VDD = 5.5V, VREF = 2.75V, GDMVDM = -2.65V to 2.65V, (change measured at +25C) VDD = 2.0V, VREF = 0.5V, GDMVDM = -0.4V to 1.4V 100 VDD = 5.5V, VREF = 2.75V, GDMVDM = -2.65V to 2.65V Output (VOUT) Minimum Output Voltage Swing VOL -- 3 -- mV All 5 VDD = 2.0V, VREF = 0V VDM = -0.5V/GDM VDD = 5.5V, VREF = 0V VDM = -0.5V/GDM 20 60 VDD = 5.5V, VREF = 0V VDM = -0.5V/GDM, RL = 1 k 3 -- VDD = 5.5V, VREF = 0V VDM = -0.5V/GDM, VL = 0V 6 -- Output (VOUT) - Continued Maximum Output Voltage Swing VDD - VOH -- 10 Output Short Circuit Current ISCP -- -- VDD = 2.0V, VREF = 0.75V VDM = 1.75V/GDM 40 130 VDD = 5.5V, VREF = 4.25V VDM = 1.75V/GDM, RL = 1 k 5 -- VDD = 5.5V, VREF = 0V VDM = 1.75V/GDM, VL = VDD +12 -- VDD = 2.0V, VREF = 1V, GDMVDM = 1.0V -12 -20 Note 1: 2: 3: 4: All VDD = 5.5V, VREF = 4.25V VDM = 1.75V/GDM +20 ISCM mV VDD = 5.5V, VREF = 1V, GDMVDM = 1.0V -- VDD = 2.0V, VREF = 1V, GDMVDM = -1.0V VDD = 5.5V, VREF = 1V, GDMVDM = -1.0V The VIP input is treated as the Common-mode input (e.g., for CMRR). VDM = (VIP - VIM). Set by design and characterization. VOS is screened in production (see Appendix B: "Offset Test Screens"). See the discussion in Section 1.6.2, Input Offset Related Errors. See Section 1.6, Explanation of DC Error Specifications. 2018-2019 Microchip Technology Inc. DS20006129B-page 9 MCP6C02 TABLE 1-2: DC ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2 and RL = 10 k to VL; see Figure 1-9 and Figure 1-10. Parameter Sym. Min. Typ. Max. Units Gain 2.0 -- 5.5 V All -660 -- A 490 725 Conditions Power Supplies (VDD, VSS and VIP) Low Supply Voltage VDD High Supply Voltage VIP Quiescent Current at VSS ISS -- Quiescent Current at VDD IDD 300 Quiescent Current at VIP IBP POR Trip Voltages, Low-Side (VDD) POR Trip Voltages, High-Side (VIP) Note 1: 2: 3: 4: (see VIP spec) IO = 0A (see IBP spec) VPLL 1.05 1.35 -- VPLH -- 1.45 1.7 LV POR turns on (VDD ), VL = 0V, VIP = 3V, VREF = 0V VPHL 1.7 1.95 -- HV POR turns off (VIP ), RL = open, VDD = 5.5V (change in ISS) VPHH -- 2.05 2.6 HV POR turns on (VIP ), RL = open, VDD = 5.5V (change in ISS) V All LV POR turns off (VDD ), VL = 0V, VIP = 3V, VREF = 0V The VIP input is treated as the Common-mode input (e.g., for CMRR). VDM = (VIP - VIM). Set by design and characterization. VOS is screened in production (see Appendix B: "Offset Test Screens"). See the discussion in Section 1.6.2, Input Offset Related Errors. See Section 1.6, Explanation of DC Error Specifications. TABLE 1-3: AC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2, RL = 10 k to VL and CL = 60 pF; see Figure 1-11. Parameter Sym. Min. Typ. Max. Units Gain kHz 20, 50 Conditions AC Response Bandwidth BW -- 500 -- 390 Gain Peaking GPK -- 0 GDMVDM = 0.1Vp-p 100 -- dB All V/s All Step Response VDM Slew Rate SR (Note 1) VDM Step Overshoot OSDM -- 4 -- % Overdrive Recovery, Input Differential Mode tIRDL -- 3 -- s (see tORL Spec) tIRDH Note 1: 2: 3: 4: -- 3 -- GDMVDM Step = VDD - 0.5V GDMVDM Step = 0.1V, tr_in = 0.2 s 20 VDD = 5.5V, VREF = 4V, GDMVDM = -3.5V to -1.25V Step, 90% of VOUT change 50, 100 (Note 2) All VDD = 5.5V, VREF = 0.5V, GDMVDM = +4.5V to +2.25V Step, 90% of VOUT change SR is limited by GBWP; the large signal step response is dominated by the small signal bandwidth. At these gains, we cannot distinguish between overdriving VDM or VOUT. See Figure 2-58 for the noise density over a wider frequency range. Not tested; for design guidance only. DS20006129B-page 10 2018-2019 Microchip Technology Inc. MCP6C02 TABLE 1-3: AC ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2, RL = 10 k to VL and CL = 60 pF; see Figure 1-11. Parameter Overdrive Recovery, Output Sym. tORL Min. Typ. Max. -- 1.5 -- Units Gain s All VDD = 5.5V, VREF = 0V, GDMVDM = -0.5V to +2.75V Step, 90% of VOUT change 1.5 tORH -- 1.5 Conditions VDD = 2.0V, VREF = 0V, GDMVDM = -0.5V to +1V Step, 90% of VOUT change -- VDD = 2.0V, VREF = 0.75V, GDMVDM = +1.75V to +0.25V Step, 90% of VOUT change VDD = 5.5V, VREF = 4.25V, GDMVDM = +1.75V to -1.25V Step, 90% of VOUT change 1.5 Noise Input Noise Voltage Eni -- -- 0.48 -- Vp-p 0.30 50 0.29 100 1.54 -- 20 0.95 eni -- Input Current Noise Density - At VIP inip -- Input Current Noise Density - At VIM inim -- 74 f = 0.01 Hz to 1 Hz f = 0.1 Hz to 10 Hz 50 0.92 Input Noise Voltage Density (Note 3) 20 100 -- nV/Hz 20 f < 500 Hz 46 50 44 100 f < 1 kHz All f = 1 kHz 10 -- pA/Hz 8 -- fA/Hz f = 1 kHz, VDM = 0V 33 f = 1 kHz, VDM = 0.15V EMI Protection EMI Rejection Ratio EMIRR -- 96 -- dB All VIN = 0.1VPK, f = 400 MHz 91 VIN = 0.1VPK, f = 900 MHz 114 VIN = 0.1VPK, f = 1800 MHz 118 VIN = 0.1VPK, f = 2400 MHz 121 VIN = 0.1VPK, f = 6000 MHz Power Up/Down Power On Time (VDD ), VOUT Settles tPON -- 65 -- s All 140 Power Off Time (VDD ), VOUT Settles tPOFF -- 8 VDD = 0V to 5.5V, VL = 0V, 90% of VOUT change -- VDD = 2.0V to 0V, VL = 0V, 90% of VOUT change VDD = 5.5V to 0V, VL = 0V, 90% of VOUT change 5.5 VIP Edge Rate VIP Bypass Capacitor Note 1: 2: 3: 4: VDD = 0V to 2.0V, VL = 0V, 90% of VOUT change VIP/t -25 -- +25 V/s All ESD structure not triggered (Note 4) CVIP -- 10 -- nF All Connects to VIP and GND SR is limited by GBWP; the large signal step response is dominated by the small signal bandwidth. At these gains, we cannot distinguish between overdriving VDM or VOUT. See Figure 2-58 for the noise density over a wider frequency range. Not tested; for design guidance only. 2018-2019 Microchip Technology Inc. DS20006129B-page 11 MCP6C02 TABLE 1-4: TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND and VIP = 34V. Parameters Specified Temperature Range Sym. Min. Typ. Max. Units TA -40 -- +125 C Conditions E-Temp parts (Note 2) +150 H-Temp parts (Note 3) Operating Temperature Range -40 -- +150 Note 1 Storage Temperature Range -60 -- +150 No power -- 191 -- JA Thermal Resistance, 6L-SOT-23 Note 1: 2: 3: 1.4 C/W Operation must not cause TJ to exceed the Absolute Maximum Junction Temperature specification (155C), which is not intended for continuous use. See Section 4.1.5, Temperature Performance for design tips. Automotive Grade 1 parts use the 6L-SOT-23 package. They can operate continuously at TA = +125C, as long as the junction temperature stays below 150C. Automotive Grade 0 parts use the 8L-3x3 VDFN package. They can operate at TA = +150C for a limited time, as long as the junction temperature stays below 155C. Simplified Diagrams 1.4.1 VOLTAGE RANGE DIAGRAMS VREF Range (V) These ranges are constant across temperature. VDD VRH VIP Range (V) -40 VIPL - VSS -40 25 85 TA (C) VRL VIPH - VSS 25 85 FIGURE 1-3: vs. Temperature. 125 150 TA (C) FIGURE 1-1: Common-Mode Input Voltage Range vs. Temperature. 1.4.2 125 150 Reference Voltage Range TIMING DIAGRAMS VDM (1V)/GDM VIP tIRC VDM Range (V) VDMH VOUT TA (C) -40 25 85 FIGURE 1-4: Common-Mode Input Overdrive Recovery Timing Diagram. 125 150 VDML FIGURE 1-2: Differential Input Voltage Range vs. Temperature. VIP 34V VDM tIRD VOUT FIGURE 1-5: Differential-Mode Input Overdrive Recovery Timing Diagram. DS20006129B-page 12 2018-2019 Microchip Technology Inc. MCP6C02 EQUATION 1-1: VIP G DM = DM Gain 34V V OUT = G DM 1 + g E VE + VREF VDM V MEAS = G PA V OUT tOR VOUT FIGURE 1-6: Timing Diagram. Output Overdrive Recovery VPLH + 0.1V VPLL + 0.1V tPOFF VPHH + 0.1V 0V VIP tPHOFF RWR 1 1.5.2 Figure 1-10 is used for testing the differential gain error, nonlinearity and input voltage range (gE, INLDM, VDML and VDMH). We compare VMEAS with the ideal VOUT, then extract the above parameters. VDD High-Z On VIP Figure 1-9 tests the MCP6C02's input offset errors (VOS, 1/CMRR, 1/CMRR2 and 1/PSRR, etc.). RWIP is set very low, so IBP does not affect the result. VOUT is filtered and amplified, before measuring the result. RWR RWIM LPF and Gain VMEAS VOUT CL RL VIM VL FIGURE 1-10: Differential Gain Test Circuit. When measuring differential errors (gE, gE/TA and INLDM), all voltages are held constant, except VDM. U1 (DUT) MCP6C02-xxx RWIP RWIM RWR RL LPF and Gain VMEAS VOUT CL VL FIGURE 1-9: the MCP6C02. MCP6C02-xxx When measuring the differential input range, all of the voltages must be in range except VDM. VDD CVIP U1 (DUT) CVIP VOS TEST CIRCUIT CVDD CVDD RWIP Simplified Test Circuits 1.5.1 DC DIFFERENTIAL GAIN TEST CIRCUIT tPHON FIGURE 1-8: VOUT Power On/Off Timing Diagram, High-Side. VIP RWIM 0.1 High-Z On VPHL + 0.1V 1.5 RWIP 4 m tPON FIGURE 1-7: VOUT Power On/Off Timing Diagram, Low-Side. VOUT EQUATION 1-2: 0V VDD VOUT The resistances at the Device Under Test (DUT) need to be small enough for accuracy (see Figure 1-10). These resistances include wires, traces, vias, etc. Input Offset Test Circuit for When MCP6C02 is in its normal range of operation, the DC output voltages are (VE is the sum of input offset errors and gE is the gain error): 2018-2019 Microchip Technology Inc. For accuracy, the wiring resistances at the DUT need to be very small (see Equation 1-2). 1.5.3 AC GAINS TEST CIRCUIT Figure 1-11 is used for testing the INA's different AC gains. The AC voltages are: * vout is the AC output * vip is the AC Common-mode input, used for CMRR plots * vdm is the AC differential input, used for GDM plots (also for CMRR and PSRR) * vdd and vss are the AC supply inputs, used for PSRR plots (including PSRR+ and PSRR-) DS20006129B-page 13 MCP6C02 EQUATION 1-4: VDD + vdd VIP + vip CVDD VOUT = V REF + G DM 1 + g E V E U1 (DUT) MCP6C02-xxx VOUT + vout VDM + vdm ~ RWR RL CVIP CL The input offset error (VE) is extracted from input offset measurements (see Section 1.5.1 "VOS Test Circuit"): EQUATION 1-5: VL FIGURE 1-11: V OUT - V REF V E = --------------------------------GDM 1 + g E AC Gain Test Circuit. The impedance at VREF (shown here as RWR) needs to have a magnitude less than 1, for gain accuracy in the signal bandwidth. The magnitude needs to be < 50, when f < 1 MHz, to maintain good stability. We usually assume gE = 0, in Equation 1-5, when extracting VE. The result is accurate enough, since gE is so low. 1.6 VE has several terms, which assume a linear response to changes in VDD, VSS, VIP and VREF. Explanation of DC Error Specifications 1.6.1 LINEAR RESPONSE MODEL VOS's dependence on temperature (TA) is quadratic plus exponential (VOS, TC1, TC2 and TCX). The aging specs (VOS and TC1) are not included, for simplicity. When the inputs and the output are in their normal ranges, and the nonlinear errors are negligible, the output voltage (VOUT) is: The exponential factor in Equation 1-6 decreases at colder temperatures (TA). This table gives an indication of this relationship. EQUATION 1-3: TABLE 1-5: EXPONENTIAL TERM TA (C) 2((TA - 150C) (10C)) 65 0.003 VDM is the input voltage. VE is the sum of input offset errors (due to VOS, PSRR, CMRR, CMRR2, TC1, TC2, etc.). gE is the gain error (GDM is the nominal gain). +85 0.011 +105 0.044 +125 0.177 1.6.2 +150 1.000 V OUT = V REF + G DM 1 + g E VDM + V E INPUT OFFSET RELATED ERRORS When VDM = 0V, the linear response model for VOUT becomes: EQUATION 1-6: T A - 150 C 10 C V DD - V SS VIP V REF 2 VE = VOS + ------------------------------------ + ---------------- + ------------------- + T A TC 1 + T A TC 2 + TC X 2 CMRR CMRR2 PSRR Where: PSRR, CMRR and CMRR2 are in units of V/V TA is in units of C VDM = 0 1.6.3 INPUT OFFSET'S COMMON-MODE VOLTAGE NONLINEARITY The input offset error (VE) changes nonlinearly with VIP. Figure 1-12 shows the MCP6C02's VE vs. VIP, as well as a linear fit line (VE_LIN), that goes through the center point (VC, V2) and has the same slope as the end points. DS20006129B-page 14 2018-2019 Microchip Technology Inc. MCP6C02 EQUATION 1-9: VE, VE_LIN (V) V ED = VOUT - V REF + G DM VDM G DM VE_LIN V3 VE Figure 1-13 shows VED vs. VDM, as well as a linear fit line (VED_LIN) based on VDM and gE. The amplifier is in one of the standard condition sets. The linear fit line (VED_LIN) goes through the center point (VC, V2) and has the same slope as the end points. V2 V1 VED, VED_LIN (V) VE VIPL VC VIPH FIGURE 1-12: Input Offset Error vs. Common-Mode Input Voltage. The part is in standard conditions (VOUT = 0, VDM = 0, etc.). VIP sweeps from VIPL to VIPH. The test circuit is in Section 1.5.1, VOS Test Circuit. Calculate VE at each point with Equation 1-5. Based on the measured VE data, we obtain the following linear fit: V E_LIN = V 2 + V IP - V C CMRR Where: VC = VIPL + VIPH 2 1 CMRR = V3 - V 1 VIPH - V IPL The remaining error (VE) is described by the Common-mode Nonlinearity spec: INL CMH = max VE V IPH - VIPL INL CML = min V E V IPH - VIPL Where: 1.6.4 VED V2 V1 VED VD1 VDM (V) VC VD2 Based on the measured VED data, we obtain the following linear fit: EQUATION 1-10: V ED_LIN = V2 + VDM - V C g E Where: VC = VD1 + V D2 2 g E = V 3 - V 1 V D2 - V D1 EQUATION 1-8: = INL CML , V3 FIGURE 1-13: Differential Input Error vs. Differential Input Voltage. EQUATION 1-7: INL CM = INL CMH , VED_LIN VIP (V) INL CMH INL CML otherwise VE = V E - V E_LIN DIFFERENTIAL GAIN ERROR AND NONLINEARITY The differential errors are extracted from differential gain measurements (see Section 1.5.2, DC Differential Gain Test Circuit), based on Equation 1-3. These errors are then split into the differential gain error (gE) and the input nonlinearity error INLDM. The remaining error (VED) is described by the Differential Nonlinearity spec: EQUATION 1-11: INL DMH = max VED V D2 - V D1 INL DML = min VED V D2 - V D1 INL DM = INL DMH , = INL DML , INL DMH INL DML otherwise Where: V ED = V ED - VED_LIN The aging spec gE is not included here, for simplicity. VDM sweeps are not always centered on VDM = 0V; the INLDM spec will interact with the VOS spec. The error VED is calculated by subtracting the ideal output from VOUT, then dividing by the ideal gain GDM. 2018-2019 Microchip Technology Inc. DS20006129B-page 15 MCP6C02 NOTES: DS20006129B-page 16 2018-2019 Microchip Technology Inc. MCP6C02 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2, RL = 10 k to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11. 2.1 DC Precision 35% 50% GDM = 20 TA = +25C 28 Samples Percentage of Occurrences Percentage of Occurrences 40% 30% 25% VDD = 2.0V VDD = 5.5V 20% 15% 10% 5% 0% FIGURE 2-1: GDM = 20. Input Offset Voltage, 25% 20% VDD = 2.0V VDD = 5.5V 15% 10% 5% FIGURE 2-4: Drift, GDM = 20. Linear Input Offset Voltage 45% GDM = 50 TA = +25C 28 Samples Percentage of Occurrences Percentage of Occurrences 30% -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 Input Offset Voltage Drift; TC1 (nV/C) VDD = 2.0V VDD = 5.5V 25% 20% 15% 10% 5% 0% 40% 35% GDM = 50 TA = -40C to +150C 28 Samples VDD = 2.0V VDD = 5.5V 30% 25% 20% 15% 10% 5% 0% -6 -5 -4 -3 -2 -1 0 1 2 3 4 Input Offset Voltage; VOS (V) FIGURE 2-2: GDM = 50. 5 6 Input Offset Voltage, -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 Input Offset Voltage Drift; TC1 (nV/C) FIGURE 2-5: Drift, GDM = 50. Linear Input Offset Voltage 35% 40% GDM = 100 TA = +25C 27 Samples Percentage of Occurrences Percentage of Occurrences 35% 10 12 35% 35% 40% GDM = 20 TA = -40C to +150C 28 Samples 0% -12 -10 -8 -6 -4 -2 0 2 4 6 8 Input Offset Voltage; VOS (V) 30% 45% 30% 25% VDD = 5.5V VDD = 2.0V 20% 15% 10% 5% 30% GDM = 100 TA = -40C to +150C 27 Samples 25% 20% 15% 10% VDD = 5.5V VDD = 2.0V 5% 0% 0% -6 -5 FIGURE 2-3: GDM = 100. -4 -3 -2 -1 0 1 2 3 4 Input Offset Voltage; VOS (V) Input Offset Voltage, 2018-2019 Microchip Technology Inc. 5 6 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 Input Offset Voltage Drift; TC1 (nV/C) FIGURE 2-6: Drift, GDM = 100. Linear Input Offset Voltage DS20006129B-page 17 MCP6C02 Note: Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2, RL = 10 k to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11. 35% GDM = 20 TA = -40C to +150C 28 Samples Percentage of Occurrences Percentage of Occurrences 45% 40% 30% 25% 20% VDD = 5.5V VDD = 2.0V 15% 10% 5% 0% -300 -200 -100 0 100 200 Input Offset Voltage Drift; TC2 (pV/C2) 300 Percentage of Occurrences Percentage of Occurrences GDM = 50 TA = -40C to +150C 28 Samples VDD = 2.0V VDD = 5.5V 30% 25% 20% 15% 10% 5% 0% -120 -80 -40 0 40 80 Input Offset Voltage Drift; TC2 (pV/C2) 6 VDD = 2.0V VDD = 5.5V 0.4 0.8 1.2 1.6 2.0 Input Offset Voltage Drift; TCX (V) 2.4 FIGURE 2-11: Exponential Input Offset Voltage Drift, GDM = 50. 40% GDM = 100 TA = -40C to +150C 27 Samples Percentage of Occurrences Percentage of Occurrences 1 2 3 4 5 Input Offset Voltage Drift; TCX (V) GDM = 50 TA = -40C to +150C 28 Samples 0.0 45% 35% 55% 50% 45% 40% 35% 30% 25% 20% 15% 10% 5% 0% 120 FIGURE 2-8: Quadratic Input Offset Voltage Drift, GDM = 50. 40% GDM = 20 TA = -40C to +150C 28 Samples 0 45% 35% VDD = 2.0V VDD = 5.5V FIGURE 2-10: Exponential Input Offset Voltage Drift, GDM = 20. FIGURE 2-7: Quadratic Input Offset Voltage Drift, GDM = 20. 40% 55% 50% 45% 40% 35% 30% 25% 20% 15% 10% 5% 0% 30% VDD = 5.5V VDD = 2.0V 25% 20% 15% 10% 5% GDM = 100 TA = -40C to +150C 27 Samples 35% 30% 25% 20% 15% VDD = 2.0V VDD = 5.5V 10% 5% 0% 0% -120 -80 -40 0 40 80 Input Offset Voltage Drift; TC2 (pV/C2) FIGURE 2-9: Quadratic Input Offset Voltage Drift, GDM = 100. DS20006129B-page 18 120 0.0 0.2 0.4 0.6 0.8 1.0 Input Offset Voltage Drift; TCX (V) 1.2 FIGURE 2-12: Exponential Input Offset Voltage Drift, GDM = 100. 2018-2019 Microchip Technology Inc. MCP6C02 Note: Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2, RL = 10 k to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11. 8 6 4 2 0 -2 -6 -8 GDM = 20 VIP = 3V Representative Part -10 150C 125C 85C 25C -40C -4 ,QSXW2IIVHW9ROWDJH926 9 Input Offset Voltage; VOS (V) 10 *'0 9'' 9 & & & & & 5HSUHVHQWDWLYH3DUW 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage; VDD (V) FIGURE 2-13: Input Offset Voltage vs. Power Supply Voltage, with GDM = 20. &RPPRQ0RGH,QSXW9ROWDJH9,3 9 FIGURE 2-16: Input Offset Voltage vs. Common-Mode Input Voltage, with GDM = 20. 8 4 2 0 -2 -4 -6 -8 GDM = 50 VIP = 3V 150C 125C 85C 25C -40C Representative Part Input Offset Voltage; VOS (V) Input Offset Voltage; VOS (V) 8 6 4 2 0 -2 -4 -6 0 150C 125C 85C 25C -40C GDM = 100 VIP = 3V Representative Part 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage; VDD (V) FIGURE 2-15: Input Offset Voltage vs. Power Supply Voltage, with GDM = 100. 2018-2019 Microchip Technology Inc. 5 Representative Part 10 15 20 25 30 35 40 45 50 55 60 65 70 Common Mode Input Voltage; V,3 (V) FIGURE 2-17: Input Offset Voltage vs. Common-Mode Input Voltage, with GDM = 50. Input Offset Voltage; VOS (V) Input Offset Voltage; VOS (V) 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 GDM = 50 VDD = 2.0V -8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage; VDD (V) FIGURE 2-14: Input Offset Voltage vs. Power Supply Voltage, with GDM = 50. +150C +125C +85C +25C -40C 6 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 +150C +125C +85C +25C -40C GDM = 100 VDD = 2.0V 0 5 Representative Part 10 15 20 25 30 35 40 45 50 55 60 65 70 Common Mode Input Voltage; V,3 (V) FIGURE 2-18: Input Offset Voltage vs. Common-Mode Input Voltage, with GDM = 100. DS20006129B-page 19 MCP6C02 Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2, RL = 10 k to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11. 10 8 40% Representative Part Percentage of Occurrences Input Offset Voltage; VOS (V) Note: 6 4 2 0 -2 -4 -6 -8 GDM = 20 VDD = 5.5V +150C +125C +85C +25C -40C 35% 30% 25% 15% 10% 5% 0.014 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Reference Voltage; VREF (V) Input Offset Voltage; VOS (V) -40C +25C +85C +125C +150C 4 2 0 -2 -4 -6 -8 GDM = 50 VDD = 5.5V Representative Part 35% 0.026 1/CMRR, with GDM = 20. 30% GDM = 50 TA = +25C VIP = 3V to 65V 28 Samples 25% VDD = 2.0V VDD = 5.5V 20% 15% 10% 5% Representative Part 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Reference Voltage; VREF (V) FIGURE 2-21: Input Offset Voltage vs. Reference Voltage, with GDM = 100. 0.014 0.016 55% 50% 45% 40% 35% 30% 25% 20% 15% 10% 5% 0% 0.018 0.020 0.022 1/CMRR (V/V) 0.024 0.026 1/CMRR, with GDM = 50. FIGURE 2-23: Percentage of Occurrences Input Offset Voltage; VOS (V) +150C +125C +85C +25C -40C DS20006129B-page 20 0.024 0% FIGURE 2-20: Input Offset Voltage vs. Reference Voltage, with GDM = 50. GDM = 100 VDD = 5.5V 0.018 0.020 0.022 1/CMRR (V/V) 40% 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Reference Voltage; VREF (V) 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 0.016 FIGURE 2-22: Percentage of Occurrences FIGURE 2-19: Input Offset Voltage vs. Reference Voltage, with GDM = 20. 8 VDD = 2.0V VDD = 5.5V 20% 0% -10 6 GDM = 20 TA = +25C VIP = 3V to 65V 28 Samples GDM = 100 TA = +25C VIP = 3V to 65V 28 Samples VDD = 5.5V VDD = 2.0V 0.014 0.016 FIGURE 2-24: 0.018 0.020 0.022 1/CMRR (V/V) 0.024 0.026 1/CMRR, with GDM = 100. 2018-2019 Microchip Technology Inc. MCP6C02 Percentage of Occurrences 50% 45% 40% 35% Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2, RL = 10 k to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11. 160 GDM = 20 TA = +25C VDD = 2.0V to 5.5V 28 Samples 150 30% 25% 20% 130 120 15% 10% 100 -0.3 -0.2 -0.1 0.0 0.1 1/PSRR (V/V) FIGURE 2-25: 0.2 0.3 1/PSRR, with GDM = 20. -50 30% 0 25 50 75 100 Ambient Temperature; TA (C) 125 150 125 150 CMRR vs. Ambient 160 GDM = 50 TA = +25C VDD = 2.0V to 5.5V 28 Samples 150 PSRR (dB) 35% -25 FIGURE 2-28: Temperature. 40% Percentage of Occurrences VIP = 3V to 65V 28 Samples 110 5% 0% 25% 20% 15% 140 130 GDM = 100 GDM = 50 GDM = 20 120 10% VDD = 2.0V to 5.5V 28 Samples 110 5% 100 0% -0.12 -0.08 FIGURE 2-26: -0.04 0.00 0.04 1/PSRR (V/V) 0.08 -50 0.12 1/PSRR, with GDM = 50. 20% 15% 10% 5% 0% -0.06 -0.04 FIGURE 2-27: -0.02 0.00 0.02 1/PSRR (V/V) 0.04 0.06 1/PSRR, with GDM = 100. 2018-2019 Microchip Technology Inc. 0 25 50 75 100 Ambient Temperature; TA (C) 50% 45% 40% 35% 30% 25% 20% 15% 10% 5% 0% PSRR vs. Ambient Final Test TA = +25C 294 Samples GDM = 100 GDM = 50 GDM = 20 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 25% Percentage of Occurrences GDM = 100 TA = +25C VDD = 2.0V to 5.5V 27 Samples -25 FIGURE 2-29: Temperature. 30% Percentage of Occurrences GDM = 100 GDM = 50 GDM = 20 140 CMRR (dB) Note: Input Offset Voltage; VOS (V) FIGURE 2-30: Test Results. Input Offset Voltage - Final DS20006129B-page 21 MCP6C02 Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2, RL = 10 k to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11. 18% GDM = 50 GDM = 20 25% 20% 10% 5% 14% 12% 10% 0% 8% 6% 4% 2% -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 -0.3 -0.3 -0.2 -0.2 -0.1 -0.1 0.0 0.1 0.1 0.2 0.2 0.3 0.3 0.4 0.4 0.5 0.5 0.6 0.6 0.7 0.7 0% Gain Error Drift; gE/TA (ppm/C) 1/PSRR (V/V) CMRR - Final Test Results. TA = +25C VDD = 5.5V VREF = 2.75V 294 Samples 70% 60% 50% GDM = 20 40% GDM = 50 GDM = 100 30% 20% 10% 300 280 260 240 220 200 180 160 140 40 20 0% 0 GDM = 100 GDM = 50 GDM = 20 FIGURE 2-32: Percentage of Occurrences Gain Error Temperature 80% Final Test TA = +25C 294 Samples 1/CMRR (V/V) 55% 50% 45% 40% 35% 30% 25% 20% 15% 10% 5% 0% FIGURE 2-34: Drift. Percentage of Occurrences 55% 50% 45% 40% 35% 30% 25% 20% 15% 10% 5% 0% PSRR - Final Test Results. -0.10 -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 Percentage of Occurrences FIGURE 2-31: 120 15% GDM = 100 GDM = 20 VDD = 5.5V TA = -40C to +150C 300 Samples 16% 80 30% Final Test TA = +25C 294 Samples 100 35% Percentage of Occurrences Percentage of Occurrences 40% 60 Note: Differential Gain Non-Linearity; | INLDM | (ppm) FIGURE 2-35: Nonlinearity. Differential Gain TA = +25C VDD = 5.5V VREF = 2.75V 294 Samples GDM = 100 GDM = 20 -0.8 -0.6 -0.4 FIGURE 2-33: DS20006129B-page 22 -0.2 0.0 0.2 0.4 Gain Error; gE (%) 0.6 0.8 Gain Error. 2018-2019 Microchip Technology Inc. MCP6C02 Note: 5 10 15 20 25 30 35 40 45 50 55 60 65 70 Non-Inverting Input Voltage; VIP (V) FIGURE 2-37: VIM Pin Input Bias Current vs. Input Common-Mode Voltage, VDM = VDML. ,QYHUWLQJ,QSXW%LDV&XUUHQW ,%0 $ Q *'09'0 9 9'' 9 *'0 Q & & Q & & & S S ,QYHUWLQJ,QSXW9ROWDJH9,0 9 ,QYHUWLQJ,QSXW9ROWDJH9,0 9 FIGURE 2-38: VIM Pin Input Bias Current vs. Input Common-Mode Voltage, VDM = VDMH. 2018-2019 Microchip Technology Inc. $PELHQW7HPSHUDWXUH7$ & FIGURE 2-40: VIM Pin Input Bias Current vs. Ambient Temperature. 4 VDM = VDML: GDM = 20 GDM = 50 GDM = 100 3 2 1 0 -1 -2 VDM = VDMH: GDM = 100 GDM = 50 GDM = 20 -3 -4 0.30 S 0.25 & & & *'09'0 9 *'09'0 9 Q 0.20 Q Q 0.15 & & 150 *'0 0.10 Q 125 FIGURE 2-39: VIP Pin Input Bias Current vs. Ambient Temperature. Q *'09'0 9 9'' 9 *'0 0 25 50 75 100 Ambient Temperature; TA (C) 0.05 ,QYHUWLQJ,QSXW%LDV&XUUHQW ,%0 $ Q -25 0.00 FIGURE 2-36: VIP Pin Input Bias Current vs. Input Common-Mode Voltage. -50 -0.15 0 Representative Part -0.05 -40C +25C +85C +125C +150C 220 200 180 160 140 120 100 80 60 40 20 0 -0.10 Representative Part ,QYHUWLQJ,QSXW%LDV&XUUHQW ,%0 $ 220 200 180 160 140 120 100 80 60 40 20 0 Non-Inverting Input Bias Current; IBP (A) Other DC Voltages and Currents Inverting Input Current; IBM (nA) Non-Inverting Input Bias Current; IBP (A) 2.2 Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2, RL = 10 k to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11. Differential Input Voltage;VDM (V) FIGURE 2-41: VIM Pin Input Bias Current vs. Differential Input Voltage. DS20006129B-page 23 MCP6C02 Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2, RL = 10 k to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11. 1.E-03 1m 1000 1.E-04 100 1.E-05 10 Output Voltage Range; VOL, VOH (mV) Input Bias Current; -(IBP + IBM) (A) 150C 125C 85C 25C -40C 1.E-06 1 1.E-07 100n 1.E-08 10n 1.E-09 1n -0.30 10 70 9 69 8 68 7 VIPH - VSS 6 67 66 5 65 4 64 3 63 2 62 VIPL - VSS 61 0 Input Common Mode Voltage Range; VIPH (V) Input Common Mode Voltage Range; VIPL (V) 10 VDD - VOH VOL - VSS 0.1 0.00 FIGURE 2-42: Input Bias Current vs. Input Common-Mode Voltage (below VSS). 1 100 1 -0.25 -0.20 -0.15 -0.10 -0.05 Input Common Mode Voltage; VIP (V) 35 30 25 20 15 5 -50 3RZHU6XSSO\&XUUHQW,'' $ 5HIHUHQFH9ROWDJH5DQJH 95/95+ 9 9'' 95+ 95/ 966 $PELHQW7HPSHUDWXUH7$ & FIGURE 2-44: Reference Voltage Range vs. Ambient Temperature. DS20006129B-page 24 -25 0 25 50 75 100 Ambient Temperature; TA (C) 125 150 FIGURE 2-46: Output Voltage Range vs. Ambient Temperature. VDD - VOH VOL - VSS 10 0 FIGURE 2-43: Common-Mode Input Range vs. Ambient Temperature. Output Voltage Range vs. 40 -50 -25 0 25 50 75 100 125 150 Ambient Temperature; TA (C) 10 45 60 1 Output Current Magnitude; | IOUT | (mA) FIGURE 2-45: Output Current. Output Voltage Range; VOL, VOH (mV) Note: ,QFUHDVLQJ9'' & & & & & 3RZHU6XSSO\9ROWDJH9'' 9 FIGURE 2-47: Supply Voltage. Supply Current vs. Power 2018-2019 Microchip Technology Inc. MCP6C02 Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2, RL = 10 k to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11. 50 2.6 6-Lead SOT-23 40 2.5 30 -40C +25C +85C +125C 20 10 HV POR Trip Points; VIPL and VIPLD (V) Short Circuit Current; ISC (mA) Note: 0 +125C +85C +25C -40C -10 -20 -30 -40 2.4 2.3 VIPL VIPLD 2.2 2.1 2.0 1.9 1.8 -50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage; VDD (V) FIGURE 2-48: Output Short Circuit Current vs. Power Supply Voltage for E-Temp Parts. -50 -25 0 25 50 75 100 Ambient Temperature; TA (C) 125 150 FIGURE 2-51: HV POR (for VIP) Trip Points vs. Ambient Temperature. 6KRUW&LUFXLW&XUUHQW,6& P$ i9')1 & & & & & & & & & & 3RZHU6XSSO\9ROWDJH9'' 9 FIGURE 2-49: Output Short Circuit Current vs. Power Supply Voltage for H-Temp Parts. 1.7 LV POR Trip Points; VPLH and VPLL (V) 1.6 1.5 1.4 1.3 VPLH VPLL 1.2 1.1 1.0 0.9 0.8 0.7 -50 -25 0 25 50 75 100 125 Ambient Temperature; TA (C) 150 FIGURE 2-50: LV POR (for VDD) Trip Points vs. Ambient Temperature. 2018-2019 Microchip Technology Inc. DS20006129B-page 25 MCP6C02 Note: Frequency Response 'LIIHUHQWLDO*DLQ*'0 G% ( N &/ S) S) S) S) Q) Q) Q) Q) Q) Q) 1.E+02 100 ( 0 0 Gain vs. Frequency, with 90 120 EMI Rejection; EMIRR (dB) 140 70 60 GDM = 100 GDM = 50 GDM = 20 50 40 10k 1.E+04 100k 1.E+05 Frequency; f (Hz) FIGURE 2-53: 120 110 100 90 80 70 60 50 40 30 20 10 0 1k 1.E+3 1.E+7 10M VIP = 0.1VPK 100 80 60 40 20 0 100M 1.0E+08 1M 1.E+06 CMRR vs. Frequency. 1.E+6 1M Frequency; f (Hz) FIGURE 2-55: Closed-Loop Output Impedance Magnitude vs. Frequency. 100 80 GDM = 20 GDM = 50 GDM = 100 1.E+01 10 1.E+5 100k 1G 1.0E+09 Frequency; f (Hz) FIGURE 2-56: Frequency. 10G 1.0E+10 EMI Rejection Ratio vs. 140 EMI Rejection; EMIRR (dB) CMRR (dB) 1.E+03 1k ( N )UHTXHQF\I+] FIGURE 2-52: Capacitive Load. PSRR (dB) 1.E+04 10k *'0 99 5,62 Closed-Loop Output Impedance Magnitude; mag(ZO_CL) () 2.3 Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2, RL = 10 k to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11. GDM = 100 GDM = 50 GDM = 20 10k 1.E+4 FIGURE 2-54: DS20006129B-page 26 100k 1M 1.E+5 1.E+6 Frequency; f (Hz) PSRR vs. Frequency. 10M 1.E+7 120 100 80 f: 6.0 GHz 4.0 GHz 2.4 GHz 1.8 GHz 0.9 GHz 0.4 GHz 60 40 20 0 0.01 0.1 Input Common Mode Voltage; VIP (VPK) FIGURE 2-57: Signal Strength. 1 EMI Rejection Ratio vs. 2018-2019 Microchip Technology Inc. MCP6C02 Note: Noise and Intermodulation Distortion Input Noise Voltage Density; eni (V/Hz) 300n GDM = 20 GDM = 50 GDM = 100 1.E-7 100n 1.E-8 10n 0.1 1.E-1 1 1.E+0 10 100 1.E+3 1k 1.E+1 1.E+2 Frequency; f (Hz) 10k 1.E+4 NPBW = 1 Hz 0 100k 1.E+5 Input Noise Voltage Density 1.E-4 100 20 40 60 FIGURE 2-61: Time, GDM = 20. Input Noise Voltage vs. NPBW = 10 Hz 1.E-6 1 1.E-7 100n 1.E-8 10n 0.1 1.E-1 1 1.E+0 10 100 1k 1.E+1 1.E+2 1.E+3 Frequency; f (Hz) FIGURE 2-59: Frequency. 10k 1.E+4 100k 1.E+5 Input Noise Voltage vs. NPBW = 1 Hz 0 40 60 80 100 120 140 160 180 200 Time; t (s) Input Noise Voltage vs. GDM = 100 fSAM = 40 SPS GDM = 20 VDD = 5.5V, at DC = 0.1 VPK, at 100 Hz No VDD bypass cap Residual Tone at 100 Hz 1.E-05 f = 2 Hz, f 3201 Hz = 64 Hz, f 3250 Hz 1.E+02 1.E+03 1.E+04 Frequency; f (Hz) 1.E+05 FIGURE 2-60: Intermodulation Distortion vs. Frequency, with VDD Disturbance. 2018-2019 Microchip Technology Inc. Input Noise Voltage; Eni(t) (0.5 V/div) NPBW = 10 Hz 1.E-04 1.E+01 20 FIGURE 2-62: Time, GDM = 50. 1.E-03 1.E-06 1.E+00 80 100 120 140 160 180 200 Time; t (s) GDM = 50 fSAM = 40 SPS GDM = 20 GDM = 50 GDM = 100 1.E-5 10 NPBW = 10 Hz Input Noise Voltage; Eni(t) (0.5 V/div) Integrated Input Noise Voltage (from DC); Eni(0 to f) (VRMS) FIGURE 2-58: vs. Frequency. Output Voltage Tones; VOUT (VPK) GDM = 20 fSAM = 40 SPS Input Noise Voltage; Eni(t) (0.5 V/div) 2.4 Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2, RL = 10 k to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11. NPBW = 1 Hz 0 20 40 60 FIGURE 2-63: Time, GDM = 100. 80 100 120 140 160 180 200 Time; t (s) Input Noise Voltage vs. DS20006129B-page 27 MCP6C02 Note: Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2, RL = 10 k to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11. Time Response VOS GDM = 20 GDM = 50 GDM = 100 NPBW = 10 Hz TA 50 5 40 30 20 5 4 3 0.8 2 0.7 1 GDM = 20 VOS (VOUT - 0.5V)/GDM 0.6 0 0.5 -1 0.4 -2 tSettle tON 0.3 -3 0 Power Supply Voltage; VDD (V) 6 1.1 VDD (V) VOUT (V) 3 2 On Off 10 1 0 0 1 2 3 4 5 6 Time; t (ms) 7 8 9 10 FIGURE 2-67: The MCP6C02 Shows No Phase Reversal vs. Input Common-Mode Overdrive. 1.2 0.9 4 VIP VOUT 0 FIGURE 2-64: Input Offset Voltage vs. Time, with Temperature Change. Output Voltage; VOUT (V) 6 20 40 60 80 100 120 140 160 180 200 Time; t (s) 1.0 7 VDD = 5.0V 60 Output Voltage; VOUT (20 mV/div) 0 70 Output Voltage; VOUT (V) 550 500 450 400 350 300 250 200 150 100 50 0 PCB effects dominate exponential decays. GDM = 20 GDM = 50 GDM = 100 Common Mode Input Voltage; VIP (V) 80 60 40 20 0 -20 -40 -60 -80 -100 -120 -140 Sensor Temperature; TSEN (C) Input Offset Voltage; VOS (V) 2.5 GDM = 100 GDM = 50 GDM = 20 50 100 150 200 250 300 350 400 450 500 Time; t (s) Time; t (2 s/div) FIGURE 2-65: Input Offset Voltage vs. Time, at Power-Up. FIGURE 2-68: Small Signal Step Response to Differential Input Voltage. 3 2 1 VOUT 0 GDMVDM 0 1 2 3 4 5 6 Time; t (ms) -1 7 8 9 10 FIGURE 2-66: The MCP6C02 Shows No Phase Reversal vs. Differential Input Overdrive. DS20006129B-page 28 Output Voltage; VOUT (0.2V/div) 4 GDM = 20 Common Mode Input Voltage; VIP (0.5V/div) Differential Input Voltage; GDMVDM (1V/div) 5 Output Voltage; VOUT (V) 6 VIP GDM = 50 GDM = 100 VOUT 0 1 2 3 4 5 6 Time; t (s) 7 8 9 10 FIGURE 2-69: Small Signal Step Response to Common-Mode Input Voltage. 2018-2019 Microchip Technology Inc. MCP6C02 Note: Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2, RL = 10 k to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11. 0 Rise Time; tr (s) Output Voltage; VOUT (50 mV/div) GDM = 20 RISO = 0 CL = 100 pF CL = 1 nF CL = 10 nF 10 20 30 40 50 60 t (s) 70 80 90 100 FIGURE 2-70: Small Signal Step Response to Differential Input Voltage, with Capacitive Load (CL). GDM = 100 GDM = 50 GDM = 20 1n 100p 1.E-10 1.E-9 Capacitive Load; CL (F) 10n 1.E-8 FIGURE 2-72: Small Signal Step Response Rise Time, with Capacitive Load (CL). 100 70% Settling Time to 1%; tsettle (s) RISO = 0 60% Overshoot 2.0 RISO = 0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 10p 1.E-11 50% 40% 30% 20% GDM = 100 GDM = 50 GDM = 20 10% 0% 10p 1.E-11 1n 100p 1.E-10 1.E-9 Capacitive Load; CL (F) 10n 1.E-8 FIGURE 2-71: Small Signal Step Response Overshoot, with Capacitive Load (CL). 2018-2019 Microchip Technology Inc. RISO = 0 GDM = 100 GDM = 50 GDM = 20 10 10p 1.E-11 1n 100p 1.E-10 1.E-9 Capacitive Load; CL (F) 10n 1.E-8 FIGURE 2-73: Small Signal Step Response Settling Time, with Capacitive Load (CL). DS20006129B-page 29 MCP6C02 NOTES: DS20006129B-page 30 2018-2019 Microchip Technology Inc. MCP6C02 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6C02 SOT-23 1 2 3 4 5 6 -- -- Note 1: 3.1 3x3 VDFN Sym. 5 VOUT Output voltage 2 VSS Negative power supply 1 VIP Noninverting input (at load's RSH) and positive (high-side) power supply 8 VIM Inverting input (at load's RSH) 7 VREF Output reference 6 VDD Positive (low-side) power supply 3,4 NC No connection 9 EP Exposed thermal pad; must be connected to VSS The SOT package is for E-temp and the VDFN package is for H-temp. Noninverting Analog Signal Input (VIP) The noninverting input (VIP) is a high-impedance CMOS input. It is designed to operate over a wide voltage range, with a voltage source to drive it. In this data sheet, it is treated as the Common-mode input voltage. VIP is the high voltage power supply pin, and is normally between VSS + 3V and VSS + 65V. It supplies the current needed to operate the high voltage circuitry. VIP needs a good bypass capacitor (e.g., 10 nF). VIP - VSS triggers the HV POR. The edge rate applied to VIP (VIP/t) needs to be limited, so the ESD diodes do not clamp. VIP is treated as the common mode voltage in this data sheet, due to the inputs' architecture. Since VDM is relatively small, this simplification is accurate; it also simplifies the specifications and applications information. 3.2 Inverting Analog Signal Input (VIM) The inverting input (VIM) is a high-impedance CMOS input, with low input bias current. VIM is designed to operate near the VIP voltage. The difference voltage VDM (or VIP - VIM) is the input signal for this amplifier. 3.3 Description Analog Output Reference Voltage (VREF) 3.4 Analog Output (VOUT) The analog output pin (VOUT) is a low-impedance voltage source. 3.5 Low-Side Power Supplies (VDD, VSS) VDD is normally between VSS + 2.0V and VSS + 5.5V, while the VREF and VOUT pins are usually between VSS and VDD. VDD - VSS triggers the LV POR. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need good bypass capacitors. In split supply configurations, including dual supplies, ground is between VSS and VDD. Both supply pins will need good bypass capacitors. In a single (negative) supply configuration, VDD connects to ground and VSS connects to the supply. VSS will need good bypass capacitors. 3.6 Exposed Pad (EP) The Exposed Thermal Pad (EP) connects internally to the VSS pin; they must be connected to the same potential on the Printed Circuit Board (PCB). This pad can be connected to a PCB ground plane to provide a larger heat sink. This improves the package thermal resistance (JA). The analog output reference voltage is a high-impedance CMOS input. VREF is set to a DC voltage, which shifts VOUT. Its dynamic response helps reject power surges and glitches at the VIP, VDD and VSS pins. 2018-2019 Microchip Technology Inc. DS20006129B-page 31 MCP6C02 NOTES: DS20006129B-page 32 2018-2019 Microchip Technology Inc. MCP6C02 4.0 DEVICE OPERATION This chapter includes additional information on basic operations and major functions. 4.1 EQUATION 4-2: Basic Performance 4.1.1 The input (differential) signal is applied to GM1. Due to its architecture, the MCP6C02's signal inputs are best described by VIP and VDM. The inverting input is then: V IM = V IP - VDM IDEAL PERFORMANCE Figure 4-1 shows the basic circuit; inputs, supplies and output. When the inputs (VIP, VIM, VDD, VSS and VREF) and output (VOUT) are in their specified ranges, and the part is nearly ideal, the output voltage is: The negative feedback loop includes GM2, RM3, RF and RG. These blocks set the DC open-loop gain (AOL) and the nominal differential gain (GDM): EQUATION 4-3: EQUATION 4-1: A OL = G M2 R M3 VOUT V REF + G DM V DM G DM = 1 + R F RG Where: GDM = Differential-Mode Gain VREF = Output Reference Voltage VDM = Differential-Mode Input (VIP - VIM) VDD AOL is very high, so the current into RM3 (I1 + I2) is nearly zero. This makes the differential inputs to GM1 and GM2 equal in magnitude and opposite in polarity. Ideally, this gives: EQUATION 4-4: U1 V FG - VREF = VDM MCP6C02 VIP V OUT = V REF + G DM V DM VOUT VIM For an ideal part, within the operating ranges, changing VIP, VSS or VDD produces no change in VOUT. VREF shifts VOUT as needed in the design. VREF VSS FIGURE 4-1: The different GDM options change GM1, GM2, RF, RG and the internal compensation capacitor. This results in the performance trade-offs highlighted in Table 1. Basic Circuit. For normal operation, keep: * * * * VIP between VIPL and VIPH VDM between VDML and VDMH VREF between VRL and VRH VOUT between 0.1V to VDD - 0.1V, usually - VOL and VOH are hard limits 4.1.3 4.1.3.1 DC PERFORMANCE DC Voltage Errors ANALOG ARCHITECTURE Section 1.6, Explanation of DC Error Specifications covers some DC specifications. The input offset error (with temperature coefficients), gain error and nonlinearities are discussed in detail. Figure 4-2 shows the block diagram for these high-side current sense amplifiers, without any details on offset correction. Plots in Section 2.1, DC Precision and Section 2.2, Other DC Voltages and Currents give useful information. 4.1.2 VDD VIP GM1 VIM I1 VFG I2 GM2 VSS FIGURE 4-2: VOUT RM3 RF In this data sheet, CMRR is based on changes in VIP (i.e., CMRR = VIP/VOS); this is accurate, since VDM is relatively small. This CMRR describes the rejection of errors at the high voltage supply, without any contribution from VDM. RG VREF MCP6C02 Block Diagram. 2018-2019 Microchip Technology Inc. DS20006129B-page 33 MCP6C02 4.1.3.2 DC Current Errors Figure 4-3 shows the resistors and currents that change the DC bias point. The input bias currents (IBP, IBM and IBR), together with a circuit's external input resistances, give an DC error (see Equation 1-2). These parts are compensated to have a stable response. For instance, step response overshoot is low. In this data sheet, the AC CMRR is measured at VIP; this is accurate, since VDM is relatively small. 4.1.5 VDD RWIP RWIM IBP IBM VHV VOUT RF RG RSH FIGURE 4-3: Currents. U1 MCP6C02 The input offset voltage's temperature drift is detailed in Equation 1-6. Other temperature responses are shown in Section 1.3, Specifications and Section 2.0 "Typical Performance Curves". Since there are three power supply pins (VIP, VDD and VSS), and VIP reaches 65V, power and temperature rise calculations are important. The power dissipated is calculated as follows (IOUT is positive when it flows out of the VOUT pin): VSS IL Load IBR RWR DC Bias Resistors and RSH is set by the design requirements, given the load current (IL). For most applications, RSH would be between 100 and 1. EQUATION 4-6: P TOT = PDD + P BP + P OUT Where: IOUT = (VOUT - VL)/RL PDD = (VDD - VSS) IDD PBP = (VIP - VSS) IBP POUT = (VDD - VOUT) IOUT, IOUT 0A = (VSS - VOUT) IOUT, IOUT < 0A The DC input offset error due to the input currents is: VOS_IR = VDM - ILRSH = IBM(RSH + RWIM) - IBPRWIP Since these currents do not correlate, minimize the magnitude of each resistance. IBPRIP will dominate in many designs. RWR modifies the gain error and the DC output offset error (VOUT changes IBR): EQUATION 4-5: V REF = - I BR R WR g E - R WR GDM R F + R G VOUT VREF + V REF + G DM V DM 1 + g E + g E 4.1.4 TEMPERATURE PERFORMANCE AC PERFORMANCE The bandwidth of these parts (fBW) is set internally to either 500 kHz (GDM = 20 or 50) or 390 kHz (GDM = 100). The large signal bandwidth is close to the small signal bandwidth; slew rate (SR) has little effect on VOUT (a benefit of our current-mode architecture). Now we can estimate the junction temperature of the device (see Table 1-4): EQUATION 4-7: T J = T A + PTOT JA 4.1.6 NOISE PERFORMANCE This part is designed to have low input noise voltage density at lower frequencies. The offset correction (Section 4.2.2, Chopping Action) modulates high frequency white noise down to DC; it also modulates low frequency 1/f noise to higher frequencies. The measured input noise voltage density is shown in Figure 2-58. That figure also shows Integrated Input Noise Voltage (Eni, in units of VRMS) between 0 Hz and f (between 0.1 Hz and 100 kHz). The Input Noise Voltage Density (eni) changes with VDM. However, that relationship is a weak one. The bandwidth at the maximum output swing is called the Full Power Bandwidth (fFPBW). It is limited by the Slew Rate (SR) for many amplifiers, but is close to fBW for these parts. This is a benefit of the current-mode architecture these parts have. DS20006129B-page 34 2018-2019 Microchip Technology Inc. MCP6C02 4.2 Overview of Zero-Drift Operation Figure 4-4 shows a diagram of the MCP6C02; It explains how slow voltage errors at the input are reduced in this architecture (much better VOS, TC1 TC2, CMRR, CMRR2, PSRR and 1/f noise). VIP VIM DM Clamps EMI Filters GM1 Chopper Input Switches GA1 Chopper Output Switches GA2 Chopper Output Switches Low-Pass Filter EMI Filter VREF RG RF VFG Low-Pass Filter RM4 VOUT FIGURE 4-4: 4.2.1 GM2 Chopper Input Switches MCP6C02 Block Diagram. BUILDING BLOCKS The Main Amplifiers (GM1 and GM2) are designed for high gain and bandwidth, with a differential topology. The main input pairs (+ and - pins at the top left) are for the higher frequency portion of the input signal. The auxiliary input pairs (+ and - pins at the bottom left) are for the low frequency and high precision portion of the input signal and correct the input offset voltage. Both inputs are added together internally. The Auxiliary Amplifiers (GA1 and GA2), the Chopper Input Switches and the Chopper Output Switches provide a high DC gain to the input signal. DC errors are modulated to higher frequencies and white noise to low frequencies. The internal LV POR (for VDD - VSS) starts the part in a known good state, protecting against power supply brown-outs. The internal HV POR (for VIP - VSS) ensures protection of the low voltage circuitry, as well as proper functioning. 4.2.2 Figure 4-5 shows the amplifier connections for the first phase of the Chopping Clock and Figure 4-6 shows them for the second phase. The slow voltage errors alternate in polarity, making the average error small. VIP VIM The Low-Pass Filter reduces high-frequency content, including harmonics of the Chopping Clock. The Output Buffer (RM4) converts current to voltage, drives the external load at VOUT and creates a negative feedback loop through RF and RG. RF and RG help set the differential gain. The Oscillator runs at fCLK = 50 kHz for the gains of 20 and 50, and at fCLK = 100 kHz for the gain of 100. fCLK is divided by 2, to produce the Chopping Clock rate (25 kHz and 50 kHz, respectively). 2018-2019 Microchip Technology Inc. CHOPPING ACTION GA1 LowPass Filter GA2 LowPass Filter VREF VFG FIGURE 4-5: First Chopping Clock Phase; Simplified Diagram. DS20006129B-page 35 MCP6C02 VIP VIM GA1 LowPass Filter The VIP and VIM input pins have an ESD structure designed to limit VIP - VSS and VDM. The double parallel diode structure that limits ESD damage through VDM also limits VDM in other conditions. VIP VREF HV ESD VFG GA2 LowPass Filter FIGURE 4-6: Second Chopping Clock Phase; Simplified Diagram. 4.2.3 FINAL TEST VS. BENCH These amplifiers will show intermodulation distortion (IMD) products when an AC signal is present. The signal and clock can be decomposed into sine wave tones (Fourier series components). These tones interact with the zero-drift circuitry's nonlinear response to produce IMD tones at sum and difference frequencies. Each of the square wave clock's harmonics has a series of IMD tones centered on it. 4.3 DM ESD FIGURE 4-7: Input Protection for VDM (i.e., for VIM) and VIP - VSS. The VREF, VOUT and VDD pins have ESD structures that limit their voltages above VSS (i.e., limit VREF - VSS, VOUT - VSS and VDD - VSS). VREF VOUT LV ESD VSS LV ESD VSS VDD The bench results will give good guidance on how to design your circuit. The specified limits (for final test) give min/max limits used to screen outliers in production. INTERMODULATION DISTORTION (IMD) HV POR VSS Due to limitations in the final test environment (e.g., equipment accuracies, thermocouple effects crosstalk and test time), final test measurements are not as accurate as bench measurements. For this reason, the input offset voltage related specifications (VOS, TC1, TC2, ..., CMRR and PSRR) are significantly wider than the histograms from bench measurements. 4.2.4 VIM LV ESD LV POR VSS FIGURE 4-8: VOUT and VDD. 4.3.2 Input Protection for VREF, PHASE REVERSAL This part is designed to not exhibit phase inversion when the input signals (VIP, VDM and VREF) exceed their specified ranges (but not their absolute ranges). Protection The MCP6C02 helps the designer provide enough protection against undesired conditions and signals in their environment. 4.3.1 INTERNAL PROTECTION DEVICES All of the ESD structures clamp their inputs when they try to go too far below VSS. Their breakdown voltage is high enough to allow normal operation, but not low enough to protect against slow overvoltage events. Very fast ESD events (that meet the specification) are limited so that damage does not occur. The supply inputs (VIP - VSS and VDD - VSS) are also connected to PORs, so that internal power up sequencing is well controlled. DS20006129B-page 36 2018-2019 Microchip Technology Inc. MCP6C02 5.0 APPLICATIONS This chapter includes design recommendations and typical application circuits. The Common-mode rejection (see Figure 2-16, Figure 2-17, Figure 2-18 and Figure 2-53) supports applications in noisy environments. Our Current-mode architecture gives high CMRR at higher frequencies than was traditional (e.g., 80 dB near 80 kHz, instead of near 60 Hz). The power supply rejection (see Figure 2-54) also has excellent rejection at higher frequencies than traditional. 5.1 Recommended Design Practices Some simple design practices help take advantage of the MCP6C02's performance in high side current sensing applications. 5.1.1 INPUT VOLTAGE LIMITS To prevent damage and/or improper operation of these amplifiers, the circuit must limit the voltages at the VIP and VIM input pins, as well as the differential input voltage VDM (see Section 1.1, Absolute Maximum Ratings ). These requirements are independent of the current limits discussed below. The ESD protection on the VIP and VDM inputs was discussed in Section 4.3.1, Internal Protection Devices. This structure was chosen to protect the input transistors against many (but not all) overvoltage conditions, and to minimize input bias currents (IBP and IBM). To protect the inputs, always drive VIP with a low impedance source and use a shunt resistor (RSH) with low resistance (designed to not fail open). Placing zener diode(s) or a transorb across RSH will also help protect the inputs. 5.1.2 5.1.3 BYPASS CAPACITORS Be sure to specify capacitors that will support your application. Be sure to look at: * Voltage Rating (well above the maximum value for its pins) * Dielectrics (good Temp. Cos. and reasonable Volt. Cos. * Size * Surface Mount vs. Leaded * Cost vs. availability If possible, connect VSS to ground. This will make your design simpler. Bypass VIP to VSS with a local bypass capacitor next to these pins (e.g.,10 nF). If needed, a bulk bypass capacitor can also be added (e.g.,1 F). Bypass VDD to VSS with a local bypass capacitor next to these pins (e.g.,100 nF). A bulk bypass capacitor should also be added close by (e.g.,2.2 F); placing it next to the local bypass capacitor is a good choice. 5.1.4 PROTECTING THE INPUTS Designs using the MCP6C02 will need (common) protection methods in the circuit design. When working on the bench, be careful to use the same protection methods (e.g., do not hot-swap the supply voltages). The following subsections give ideas that might be useful in your design. 5.1.4.1 Protecting the VIP Input Always place a bypass capacitor (CIP in Figure 5-1) from VIP to ground. This helps protect this HV supply input from fast glitches. A 10 nF capacitor is reasonable for many designs. VDD VIP MCP6C02 INPUT CURRENT LIMITS To prevent damage to (or improper operation of) these amplifiers, the circuit must limit the currents into the VIP and VIM input pins (see Section 1.1, Absolute Maximum Ratings ). This requirement is independent of the voltage limits discussed above. One way to ensure the input currents are limited is to always drive VIP with a low impedance source, and to use a shunt resistor (RSH) with low resistance (designed to not fail open). Placing zener diode(s) or a transorb across RSH will also help protect the inputs. U1 VS CIP RSH VIM Load FIGURE 5-1: VOUT VREF VSS Protecting VIP. The VIP/t spec in Table 1-3 gives the maximum edge rate that should be input to the VIP pin. Limit the source (VS in Figure 5-1) to slower edge rates. Limiting the current out of VS, depending on the application, can also help protect VIP. 2018-2019 Microchip Technology Inc. DS20006129B-page 37 MCP6C02 5.1.4.2 Protecting VDM (and VIM) The shunt resistor (RSH in Figure 5-2 keeps VDM in range, as long as the load current is not too high. If extra protection is needed in your design, ideas to consider include: * Limiting VS's output current * Setting VS's output ESR high enough to reduce overshoot - The ESR should be a dynamic resistance, not a physical one * Limit VDM (see Figure 5-2) - Add anti-parallel diodes between VIP and VIM, in case RSH fails open - Add a capacitor between the VIP and VIM pins When VIP and VDM are protected, then VIM is too. VIP C VIP VDD U1 MCP6C02 D1 D2 CSH VOUT RSH VIM FIGURE 5-2: 5.1.4.3 Protecting VDM with Diodes. Protection for Capacitive Loads Limiting the current from VS helps protect the circuit in Figure 5-3. The resistance seen by VS (RVS (VS's ESR) and RCL (CL's ESR)) helps reduce step response overshoot, which provides more protection. Using CSH (see Figure 5-2) will create a voltage divider for fast edges; be careful to limit the resulting VDM. VDD VIP VDD VIP U1 MCP6C02 CIP RSH VIM RVS VS D1 Motor FIGURE 5-4: 5.1.5 VOUT Protection for Motor Loads. SETTING THE VOLTAGES AT VIP AND VIM VIP is tied to a voltage source, to minimize glitches and crosstalk. This part's excellent CMRR versus frequency helps reject Common-mode (i.e., at VIP) noise and glitches. A local pass capacitor to VSS can help, when the design allows it; 10 nF is usually a good choice (see the Typical Application Circuit on Page 1). A shunt resistor (RSH) is connected between VIP and VIM, then to the load (which is grounded). It is selected for the trade-off between accuracy (high RSH) and power dissipation (low RSH). Low power dissipation also leads to reduced size and cost. RSH also helps protect these pins against large glitches; make sure it will never fail open. The bypass capacitor on VIP reduces the risk of high overvoltage events, when the current changes abruptly (such as an inductive load opening). A good layout is necessary to minimize DC and AC errors. Figure 5-5 shows a layout that minimizes input resistances seen by IBN and IBM. The critical paths are between RSH and the pins VIP and VIM (RWIP and RWIM). U1 MCP6C02 CIP RSH VIM RVS VS VOUT CL Pin VIP Pin VIM (trace = RWIP) (trace = RWIM) trace to VHV RCL trace to load RSH FIGURE 5-3: Loads. 5.1.4.4 Protection for Capacitive Protection for Motor Loads Limiting the current and/or edge rates from VS helps protect the circuit in Figure 5-4. The resistance RVS (VS's ESR) might help in some designs. The catch diode (D1) keeps decaying motor currents near ground, which protects the inputs. DS20006129B-page 38 FIGURE 5-5: PCB Layout for RSH (connections to VIP and VIM). For accuracy, the wiring resistances at the device inputs need to be small: 2018-2019 Microchip Technology Inc. MCP6C02 EQUATION 5-1: VDD RWIP 4 m CVDD U1 RWIM 0.1 5.1.6 VIP SETTING THE VOLTAGE AT VREF R C R VIM VREF VDD U2 (ADC) MCP6C02 VOUT MCP3xxx CVIP VIM R C R Use when VREF = VSS = GND FIGURE 5-6: CR Use when VREF 0.1V VREF Bypass Circuit #1. Figure 5-7 uses an IC VREF to generate VREF - VSS, an R-C low-pass filter to reject fast glitches seen at VREF - VSS and an op amp buffer ( 1 MHz) to drive VREF with a low impedance source (see Equation 1-2) (notice only one connection to VSS is shown, for good precision). 2018-2019 Microchip Technology Inc. VREF Bypass Circuit #2. Driving the VREF pin instead with a simple divider and capacitor will cause potential issues. The equivalent resistance needs to be low (see Equation 5-2), so the divider will draw a lot of current. The capacitor will need to be large, to set a reasonable pole, increasing cost and PCB space. We strongly recommend against designs with VSS < VREF < VSS + 0.1V, since AC glitches may become an problem. 5.1.7 CVDD U1 VIP RR FIGURE 5-7: Figure 5-6 shorts VREF and VSS together. The ADC connects its negative input to VREF, so it can reject glitches on VSS and VREF (notice only one connection to VSS is shown, for good precision). CREF CBUF The DC resistance seen at VREF needs to be small. This resistance includes trace resistance, via resistance and output resistance of any driving amplifiers. For good gain error in the signal band, maintain this resistance in that band. The AC impedance seen at VREF needs to support stability at frequencies near the bandwidth. See Section 5.1.8.1, Driving VREF for more information. VDD VDD For designs with VREF VSS + 0.1V, connect VREF and VSS with a relatively large capacitor. Since VREF needs a low impedance source, we recommend the following two design approaches. RWR 1 MCP3xxx CVIP For designs with VREF = VSS, short the VREF and VSS pins together; connect them to ground (or other reference) using one low impedance via (or trace). This minimizes DC and AC errors. EQUATION 5-2: U2 (ADC) MCP6C02 VOUT TEMPERATURE RISE Make sure that TJ does not exceed the Absolute Maximum Junction Temperature spec (see Section 1.1, Absolute Maximum Ratings ). This is a strong concern when TA is high (e.g., above 125C), when IOUT's magnitude is large (e.g., near the short circuit limit) or when VIP is high. Formulas needed for this part of the design are found in Section 4.1.5, Temperature Performance. Figure 2-64 shows that temperature ramp rates need to be limited, for best performance. The decay rates shown there are limited by the PCB and other components. 5.1.8 ENSURING STABILITY A few simple design techniques will help take advantage of these stable parts. Simulations and bench measurements help to verify the solutions (e.g., look at step response overshoot and ringing). DS20006129B-page 39 MCP6C02 Driving VREF 5.1.8.2 Source Impedances The recommended DC source resistances (at VIP, VIM and VREF; see Equation 5-2) will help ensure stability, by keeping R-C time constants very fast. 5.1.8.3 Capacitive Loads Driving large capacitive loads can cause stability problems for voltage amplifiers. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth reduces. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. Lower gains (GDM) exhibit greater sensitivity to capacitive loads. When driving large capacitive loads with these parts (e.g., > 80 pF), a small series resistor at the output (RISO in Figure 5-8) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. VDD VIP MCP6C02 CVIP RISO VOUT CL VIM FIGURE 5-8: Recommended RISO Values for Capacitive Loads. Figure 5-9 shows the typical responses versus CL, when RISO is a short circuit (also see Figure 2-70 to Figure 2-73). Figure 5-10 gives recommended RISO values for different capacitive loads and gains. The x-axis is the load capacitance (CL). After selecting RISO for the circuit, double check the resulting frequency response peaking and step response overshoot on the bench. Modify RISO's value until the response is reasonable. *3. 6ROLG/LQHV %: 'DVKHG/LQHV S ( *'0 *'0 *'0 S S ( Q Q ( ( ( &DSDFLWLYH/RDG&/ ) Q ( FIGURE 5-9: Bandwidth and Gain Peaking vs. Capacitive Load, without RISO. 1.E+04 10k 1.E+03 1k 1.E+02 100 1.E+01 10 10p 1.E-11 GDM = 100 GDM = 50 GDM = 20 100p 1n 10n 1.E-10 1.E-09 1.E-08 Capacitive Load; CL (F) FIGURE 5-10: Capacitive Load. 5.1.9 CVDD U1 5,62 %DQGZLGWK%:N+] When the frequency is near the bandwidth (e.g., between BW/4 and 4 BW), the source's impedance magnitude should be below 50. *DLQ3HDNLQJ*3.G% The voltage source driving the VREF pin must be low impedance (see Equation 1-2), so that the signal gain is constant within the signal bandwidth. Recommended RISO () 5.1.8.1 100n 1.E-07 Recommended RISO vs. NOISE DESIGN As shown in Figure 2-58 and Table 1-3, the input noise voltage density is white (and low) at low frequencies. This supports accurate averages (DC estimates) in applications. 1/f noise is negligible for almost all applications. As a result, the time domain data in Figure 2-61, Figure 2-62 and Figure 2-63 is well behaved. Figure 2-58 also shows a curve of the Integrated Input Noise Voltage (Eni, in units of VRMS) between 0 Hz and f (between 0.1 Hz and 100 kHz). To estimate Eni between the frequencies f1 and f2, simply take the RMS difference (i.e., Eni |f1 to f2 = sqrt(Eni22 - Eni12)). The Input Noise Voltage Density (eni) changes with VDM; however, that it is a weak relationship, so it can be neglected in designs. Figure 5-11 and Figure 5-12 show the device noise as a Signal-to-Noise ratio (SNR), assuming the signal is a full-scale sine wave (at VOUT). The x-axis is the circuit's bandwidth (BW), to make it easy to evaluate a particular design. The input offset voltage is shown as a Signal-to-Offset ratio (SVosR), to indicate where the DC offset dominates the error. DS20006129B-page 40 2018-2019 Microchip Technology Inc. MCP6C02 Setting VSS = GND has the potential to increase rejection of crosstalk and glitches. In any case, a good ground design (e.g., ground plane on a PCB) and appropriate bypass capacitors are needed to realize these benefits. It pays to be sure that your capacitor's voltage rating and dielectric will support your needs over your voltage and temperature ranges. With some dielectrics, it pays to also take aging (changes over time) into account too. 130 VDD = 2.0V Dashed Lines = SVosR Solid Lines = SNR SNR and SVosR (dB) 120 110 100 90 80 70 60 GDM = 20 GDM = 50 GDM = 100 50 1 1.E+0 10 1.E+1 5.2 100 1k 1.E+2 1.E+3 Bandwidth; f (Hz) 10k 1.E+4 100k 1.E+5 FIGURE 5-11: SNR vs. Bandwidth Estimates, VDD = 2.0V. SNR and SVosR (dB) 100 The ADC operates on a different supply; its ground will be different due to I-R drops and glitches. The differential input is tied to VREF, so that its CMRR can reject differences between grounds. 90 80 70 60 GDM = 20 GDM = 50 GDM = 100 50 1 1.E+0 10 1.E+1 100 1k 1.E+2 1.E+3 Bandwidth; f (Hz) 10k 1.E+4 100k 1.E+5 FIGURE 5-12: SNR vs. Bandwidth Estimates, VDD = 5.5V. 5.1.10 MOTOR CURRENT MONITORS Figure 5-13 shows a simplified DC Motor Current Monitor circuit with a regulated voltage supply. The MCP6C02 and its circuit are all connected to the same ground, for better glitch performance. In this case, since IL is non-negative, we choose VREF = VSS. VDD = 5.5V Dashed Lines = SVosR Solid Lines = SNR 110 The following circuits give guidance on using the MCP6C02 within common applications. They leave out details and the design requirements followed. 5.2.1 130 120 Typical Application Circuits UNIDIRECTIONAL APPLICATIONS In unidirectional applications where VREF = VSS, it is important to minimize output headroom (VOL). The lower VOL is, the more accurate the zero scale reading is. To reduce VOL, make IOUT as low as possible. This is done by making RL high and by tying VL to VSS. +5V 10 nF 2.2 F 100 nF +48V RSH 2.2 m BIDIRECTIONAL APPLICATIONS Figure 5-7 shows ways to connect VREF and VSS for best performance. To maximize headroom, reduce VOL and VOH by setting RL high. 5.1.12 SUPPLY PINS As described in Section 3.5 "Low-Side Power Supplies (VDD, VSS)", the ground potential (GND) can be set where needed in your design. The most common design approach has VSS = GND (positive single supply). Other common design approaches have VDD = GND (negative single supply) or VSS < GND < VDD (dual, or split, supplies). 2018-2019 Microchip Technology Inc. MCP6C02-100 VOUT 20 k IL < 20A VREF +5V Figure 5-6 shows how to connect VREF and VSS for best performance. 5.1.11 U1 2.2 F U2 (ADC) R MCP3xxx VOUT 100 nF C VREF R FIGURE 5-13: Motor Current Monitor for Regulated Supply Voltage. H-Bridge motor drive circuits can place their current monitors in several positions. Figure 5-14 shows a few possibilities: * Position A - This uses a unidirectional monitor (MCP6C02 at VA1 and VA2), with current polarity determined by the timing of the switches (SWLT, DS20006129B-page 41 MCP6C02 etc.) * Positions B and C - This uses two unidirectional monitors (on MCP6C02 at VB1 and VB2 and the other at VC1 and VC2), with each one representing one current polarity * Position D - This uses a bidirectional monitor (MCP6C02 at VD1 and VD2), with current polarity determined by the output - The monitor must function at and below ground - The monitor must withstand large switching steps and glitches - We caution that the MCP6C02 should not be used in these conditions. Obviously, choosing different locations for the monitor(s) gives trade-offs in accuracy and complexity. For instance, the monitor at Position D directly measures the motor current, but will have large voltage swings at its VIP pin. The switches are discrete semiconductor switches (i.e., CMOS, Bipolar, IGFET, etc.). VHV 5.2.2 The MCP6C02 can be used to shift analog voltages from a high positive voltage down to a low voltage. Many possibilities exit; Figure 5-15 is just one possible implementation. The input attenuator (R1 and R2) allow a wider range of voltages to be measured. No resistor is placed between V1 and the noninverting input, so that the input current IBP doesn't cause an offset shift. The attenuator resistors' accuracy and values may affect the circuit's gain error and offset. The +2.5V reference level allows bidirectional voltage sensing; it needs to be very low impedance and reject glitches on the supply or ground (see Figure 5-7 for recommendations on this part of the circuit). +5V 2.2 F 10 nF V1 100 nF R1 V2 VOUT R2 100 k U1 VA1 IA ANALOG LEVEL SHIFTER +5V RA 2.2 F VA2 RB U2 VC1 VB1 IB IC SWLT ID VD1 SWLB RD MCP3xxx VOUT R RC VC2 VB2 +2.5V MCP6C02 +2.5V R 100 nF C SWRT VD2 FIGURE 5-15: Analog Level Shifter. SWRB FIGURE 5-14: H-Bridge Motor Current Monitor, With a Few Possible Monitor Locations. DS20006129B-page 42 2018-2019 Microchip Technology Inc. MCP6C02 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 6-Lead SOT-23 Example Part Number Code MCP6C02T-020E/CHY 22 MCP6C02T-050E/CHY 25 MCP6C02T-100E/CHY 21 MCP6C02T-020E/CHYVAO 22 MCP6C02T-050E/CHYVAO 25 MCP6C02T-100E/CHYVAO 21 8-Lead VDFN Example Part Number MCP6C02T-020H/Q8B Legend: XX...X Y YY WW NNN e3 * Note: 2247 Code 220 MCP6C02T-050H/Q8B 250 MCP6C02T-100H/Q8B 2100 MCP6C02T-020H/Q8BVAO 220 MCP6C02T-050H/Q8BVAO 250 MCP6C02T-100H/Q8BVAO 2100 220 1922 256 Device-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2018-2019 Microchip Technology Inc. DS20006129B-page 43 MCP6C02 6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 2X 0.15 C A-B D e1 A D E 2 E1 E E1 2 2X 0.15 C D 2X 0.20 C A-B e 6X b B 0.20 C A-B D TOP VIEW C A A2 SEATING PLANE 6X A1 0.10 C SIDE VIEW R1 L2 R c GAUGE PLANE L (L1) END VIEW Microchip Technology Drawing C04-028C (CH) Sheet 1 of 2 DS20006129B-page 44 2018-2019 Microchip Technology Inc. MCP6C02 6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits N Number of Leads e Pitch Outside lead pitch e1 A Overall Height Molded Package Thickness A2 Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Foot Length L Footprint L1 Seating Plane to Gauge Plane L1 Foot Angle c Lead Thickness Lead Width b MIN 0.90 0.89 0.00 0.30 0 0.08 0.20 MILLIMETERS NOM 6 0.95 BSC 1.90 BSC 1.15 2.80 BSC 1.60 BSC 2.90 BSC 0.45 0.60 REF 0.25 BSC - MAX 1.45 1.30 0.15 0.60 10 0.26 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-028C (CH) Sheet 2 of 2 2018-2019 Microchip Technology Inc. DS20006129B-page 45 MCP6C02 6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging GX Y Z C G G SILK SCREEN X E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch C Contact Pad Spacing X Contact Pad Width (X3) Y Contact Pad Length (X3) G Distance Between Pads Distance Between Pads GX Z Overall Width MIN MILLIMETERS NOM 0.95 BSC 2.80 MAX 0.60 1.10 1.70 0.35 3.90 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2028B (CH) DS20006129B-page 46 2018-2019 Microchip Technology Inc. MCP6C02 8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN] With 2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N (DATUM A) (DATUM B) E NOTE 1 2X 0.10 C 1 2 2X TOP VIEW 0.10 C 0.10 C C A A1 SEATING PLANE 8X (A3) 0.08 C SIDE VIEW 0.10 C A B D2 1 A 2 NOTE 1 0.10 A C A B E2 K N L 8X b e BOTTOM VIEW 0.10 0.05 C A B C Microchip Technology Drawing C04-21358 Rev B Sheet 1 of 2 2018-2019 Microchip Technology Inc. DS20006129B-page 47 MCP6C02 8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN] With 2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging A4 PARTIALLY PLATED E3 SECTION A-A Units Dimension Limits Number of Terminals N e Pitch Overall Height A Standoff A1 Terminal Thickness A3 Overall Length D Exposed Pad Length D2 Overall Width E Exposed Pad Width E2 b Terminal Width Terminal Length L K Terminal-to-Exposed-Pad Wettable Flank Step Cut Depth A4 E3 Wettable Flank Step Cut Width MIN 0.80 0.00 2.30 1.50 0.25 0.35 0.20 0.10 - MILLIMETERS NOM 8 0.65 BSC 0.85 0.03 0.203 REF 3.00 BSC 2.40 3.00 BSC 1.60 0.30 0.40 0.13 - MAX 0.90 0.05 2.50 1.70 0.35 0.45 0.15 0.04 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-21358 Rev B Sheet 2 of 2 DS20006129B-page 48 2018-2019 Microchip Technology Inc. MCP6C02 8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN] With 2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Y2 EV 8 OV C X2 EV CH G1 Y1 1 2 SILK SCREEN X1 G2 E RECOMMENDED LAND PATTERN Units Dimension Limits Contact Pitch E Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 Contact Pad to Center Pad (X8) G1 Contact Pad to Contact Pad (X6) G2 Pin 1 Index Chamfer CH Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.65 BSC MAX 1.70 2.50 3.00 0.35 0.80 0.20 0.20 0.20 0.33 1.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-23358 Rev B 2018-2019 Microchip Technology Inc. DS20006129B-page 49 MCP6C02 NOTES: DS20006129B-page 50 2018-2019 Microchip Technology Inc. MCP6C02 APPENDIX A: REVISION HISTORY Revision B (September 2019) The following is the list of modifications. 1. 2. 3. Added the H-Temp part in an 8 lead 3 x 3 VDFN package. Clarified specifications, timing diagrams and power calculations. Added discussion on circuit protection. Revision A (November 2018) * Initial release of this document. 2018-2019 Microchip Technology Inc. DS20006129B-page 51 MCP6C02 NOTES: 2018-2019 Microchip Technology Inc. DS20006129B-page 52 MCP6C02 APPENDIX B: OFFSET TEST SCREENS Input offset voltage specifications in the DC spec table (Table 1-1) are based on bench measurements (see Section 2.1, DC Precision). These measurements are much more accurate than at test, because: * * * * We use production screens to support the quality of our VOS specification in outgoing products. The screen limits are wider and are used to eliminate fliers; see Table B-1. More compact circuit Parts soldered on the PCB More time spent averaging (reduced noise) Better temperature control - Reduced temperature gradients - Greater accuracy TABLE B-1: OFFSET TEST SCREENS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V, VDM = 0V, VREF = VDD/4, VL = VDD/2 and RL = 10 k to VL; see Figure 1-9 and Figure 1-10. Parameters input Offset Voltage Sym. Min. Max. Units Gain VOS -34 +34 V 20 -24 +24 50 -20 +20 100 2018-2019 Microchip Technology Inc. Conditions Test Screen DS20006129B-page 53 MCP6C02 NOTES: 2018-2019 Microchip Technology Inc. DS20006129B-page 54 MCP6C02 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO. Device -XXX Tape and Reel Option Gain Option X(2) /XXX(2) Temperature Package Range XXX(3) Class a) MCP6C02T-020E/CHY: Tape and Reel, Differential Gain = 20, Extended Temperature, 6LD SOT-23 b) MCP6C02T-050E/CHY: Tape and Reel, Differential Gain = 50, Extended Temperature, 6LD SOT-23 c) MCP6C02T-100E/CHY: Tape and Reel, Differential Gain = 100, Extended Temperature, 6LD SOT-23 Device: MCP6C02: Tape and Reel Option: T Gain Option: 020 050 100 = Differential Gain of 20 V/V = Differential Gain of 50 V/V = Differential Gain of 100 V/V d) MCP6C02T-020H/Q8B: Temperature Range: E H = -40C to +125C(2) (Extended) = -40C to +150C(2) (High) Tape and Reel, Differential Gain = 20, High Temperature, 8LD VDFN e) MCP6C02T-050H/Q8B: Package: CHY Q8B = Plastic Small Outline Transistor (SOT-23(2)), 6-Lead = Very Thin Plastic Dual Flat Outline (3x3 VDFN(2)), 8-Lead Tape and Reel, Differential Gain = 50, High Temperature, 8LD VDFN f) MCP6C02T-100H/Q8B: Tape and Reel, Differential Gain = 100, High Temperature, 8LD VDFN Class: Zero-Drift, 65V High-Side Current Sense Amp Examples: = Tape and Reel(1) (Blank) = Non-Automotive VAO = Automotive g) MCP6C02T-020E/CHYVAO: Automotive, Tape and Reel, Differential Gain = 20, Extended Temperature, 6LD SOT-23 h) MCP6C02T-050E/CHYVAO: Automotive, Tape and Reel, Differential Gain = 50, Extended Temperature, 6LD SOT-23 i) MCP6C02T-100E/CHYVAO: Automotive, Tape and Reel, Differential Gain = 100, Extended Temperature, 6LD SOT-23 j) MCP6C02T-020H/Q8BVAO: Automotive, Tape and Reel, Differential Gain = 20, High Temperature, 8LD VDFN k) MCP6C02T-050H/Q8BVAO: Automotive, Tape and Reel, Differential Gain = 50, High Temperature, 8LD VDFN l) MCP6C02T-100H/Q8BVAO: Automotive, Tape and Reel, Differential Gain = 100, High Temperature, 8LD VDFN Note 1: 2: 3: 2018-2019 Microchip Technology Inc. Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. E-Temp parts are only in the SOT-23 package. HTemp parts are only in the 3x3 VDFN package. Automotive parts are AEC-Q100 qualified. SOT23 packaged parts are Grade 1 and VDFN packaged parts are Grade 0. DS20006129B-page 55 MCP6C02 NOTES: DS20006129B-page 56 2018-2019 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. 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Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2019, Microchip Technology Incorporated, All Rights Reserved. For information regarding Microchip's Quality Management Systems, please visit www.microchip.com/quality. 2018-2019 Microchip Technology Inc. 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