2018-2019 Microchip Technology Inc. DS20006129B-page 1
MCP6C02
Features
• Single Amplifier: MCP6C02
• Bidirectional or Unidirectional
• Input (Common-mode) Voltages:
- +3.0V to +65V, specified
- +2.8V to +68V, operating
- -0.3V to +70V, survival
• Power Supply:
- 2.0V to 5.5V
- Single or Dual (Split) Supplies
• High DC Precision:
-V
OS: ±1.65 μV (typical)
- CMRR: 154 dB (typical)
- PSRR: 138 dB (typical)
- Gain Error: ±0.1% (typical)
• Preset Gains: 20, 50 and 100 V/V
• POR Protection:
- HV POR for VIP –V
SS
- LV POR for VDD –V
SS
• Bandwidth: 500 kHz (typical)
• Supply Currents:
-I
DD: 490 μA (typical)
-I
BP: 170 μA (typical)
• Enhanced EMI Protection:
- EMIRR: 118 dB at 2.4 GHz (typical)
• Specified Temperature Ranges:
- -40°C to +125°C (E-Temp part)
- -40°C to +150°C (H-Temp part)
Typical Applications
• Automotive (see Product Identification System)
- AEC-Q100 Qualified, Grade 0
(VDFN package)
- AEC-Q100 Qualified, Grade 1
(SOT-23 package)
• Motor Control
• Analog Level Shifter
• Industrial Computing
• Battery Monitor/Tester
Related Products
• MCP6C04-020
• MCP6C04-050
• MCP6C04-100
General Description
The Microchip Technology Inc. MCP6C02 high-side
current sense amplifier is offered with preset gains of
20, 50 and 100 V/V. The Common-mode input range
(VIP) is +3V to +65V. The Differential-mode input range
(VDM =V
IP –V
IM) supports unidirectional and
bidirectional applications.
The power supply can be set between 2.0V and 5.5V.
Parts in the SOT-23 package are specified over -40°C
to +125°C (E-Temp), while parts in the 3×3 VDFN
package are specified over -40°C to +150°C (H-Temp).
The Zero-Drift architecture supports very low input
errors, which allow a design to use shunt resistors of
lower value (and lower power dissipation).
Package Types (Top View)
Typical Application Circuit
MCP6C02
SOT-23
VIP
VSS
VIM
1
2
3
6
4
VDD
VOUT
5VREF
NC
VSS
NC
VREF
VDD
1
2
3
4
8
7
6
5VOUT
VIM
VIP
MCP6C02
3×3 VDFN *
EP
9
* Includes Exposed Thermal Pad (EP); see
Ta b l e 3 - 1 .
VBAT
+36V VOUT
2.2 µF
U1
MCP6C02-100
100 nF
+5V
RSH
VL
IL<20A
20 kΩ
2.2 mΩ
10 nF
Zero-Drift, 65V High-Side Current Sense Amplifier
MCP6C02
DS20006129B-page 2 2018-2019 Microchip Technology Inc.
Functional Diagram Gain Options
Table 1 shows key specifications that differentiate
between the three different differential gain (GDM)
options. See Section 1.0 “Electrical Characteris-
tics”, Section 6.0 “Packaging Information” and the
Product Identification System for further information
on the GDM options available.
RF
VFG
VOUT
VREF
RM3
GM2
I2
RG
VDD
VSS
GM1 I1
VIP
VIM
TABLE 1: KEY DIFFERENTIATING SPECIFICATIONS
Part No.
GDM
(V/V)
Nom.
VOS
(± μV)
Max.
TC1
(± nV/°C)
Max.
CMRR
(dB)
Min.
PSRR
(dB)
Min.
VDMH
(V)
Min.
BW
(kHz)
Typ.
Eni
(μVp-p)
Typ.
eni
(nV/√Hz)
Typ.
MCP6C02-020 20 16 90 132 109 0.265 500 1.54 74
MCP6C02-050 50 14 70 138 115 0.106 0.95 46
MCP6C02-100 100 12 65 116 0.053 390 0.92 44
Note 1: VOS and TC1 limits are by design and characterization only.
2: TC1 covers the Extended Temperature Range (-40°C to +125°C) and the High Temperature Range (-40°C
to +150°C).
3: CMRR is at VDD =5.5V.
4: Eni is at f=0.1Hzto10Hz. e
ni is at f < 500 Hz.
2018-2019 Microchip Technology Inc. DS20006129B-page 3
MCP6C02
Figure 1, Figure 2 and Figure 3 show input offset
voltage versus temperature for the three gain options
(GDM = 20, 50 and 100 V/V).
FIGURE 1: Input Offset Voltage vs.
Temperature, GDM =20V/V.
FIGURE 2: Input Offset Voltage vs.
Temperature, GDM =50V/V.
FIGURE 3: Input Offset Voltage vs.
Temperature, GDM = 100 V/V.
The MCP6C02's CMRR supports applications in noisy
environments. Figure 4 shows how CMRR is high,
even for frequencies near 100 kHz.
FIGURE 4: CMRR vs. Frequency.
-8
-6
-4
-2
0
2
4
6
8
-50 -25 0 25 50 75 100 125
150
Input Offset Voltage; VOS
(μV)
Ambient Temperature; TA(°C)
GDM = 20
VDD = 5.5V
28 Samples
-8
-6
-4
-2
0
2
4
6
8
-50 -25 0 25 50 75 100 125
150
Input Offset Voltage; VOS
(μV)
Ambient Temperature; TA(°C)
GDM = 50
VDD = 5.5V
28 Samples
-8
-6
-4
-2
0
2
4
6
8
-50 -25 0 25 50 75 100 125
150
Input Offset Voltage; VOS
(μV)
Ambient Temperature; TA(°C)
GDM = 100
VDD = 5.5V
27 Samples
40
50
60
70
80
90
100
1.E+04 1.E+05
1.E+06
CMRR (dB)
Frequency; f (Hz)
G
DM
= 100
GDM
= 50
GDM
= 20
10k
1M
100k
MCP6C02
DS20006129B-page 4 2018-2019 Microchip Technology Inc.
NOTES:
2018-2019 Microchip Technology Inc. DS20006129B-page 5
MCP6C02
1.0 ELECTRICAL CHARACTERISTICS
1.1 Absolute Maximum Ratings †
VDD –V
SS .................................................................................................................................................. -0.3V to +5.5V
Current at Input Pins (Note 1) .................................................................................................................................±2 mA
Analog Inputs (VIP and VIM) (Note 1) .......................................................................................................... -0.3V to +70V
All Other Inputs and Outputs.....................................................................................................VSS – 0.3V to VDD +0.3V
Input Difference Voltage (VDM) (Note 1)...................................................................................................................±1.2V
Output Short-Circuit Current ........................................................................................................................... Continuous
Current at Output and Supply Pins .......................................................................................................................±30 mA
Storage Temperature ..............................................................................................................................-65°C to +150°C
Maximum Junction Temperature (Note 2) ............................................................................................................. +155°C
ESD protection (HBM, CDM, MM) ....................................................................................................... ≥2 kV, 2 kV, 300V
Note 1: These voltage and current ratings are physically independent; each required condition must be enforced by
the user (see Section 5.1.1 “Input Voltage Limits” and Section 5.1.2 “Input Current Limits”).
2: The Absolute Maximum Junction Temperature is not intended for continuous use.
1.2 Voltage and Temperature Ranges
The various voltage and temperature ranges are listed in Table 1-1.
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1: VOLTAGE AND TEMPERATURE RANGES
Parameter Units GDM (V/V) Comment
Range
Type Sym. Spec. Oper. Abs. Min./Max.
VDD
(Note 2)
VAll V
DD ↑
(LV POR on)
Min. VDDL 2.0 1.7 -0.3
LV POR
Hysteresis
VPLH-
VPLH
0.1 Typ. — —
— Typ. — 2.0 to 5.5 — —
Max. VDDH 5.5 5.5 5.5
VIP
(Note 2)
VAll V
IP ↑
(HV POR on)
Min. VIPL 3.0 2.8 -0.3
VIP ↓
(HV POR on)
VIPLD 2.8 2.6
HV POR
Hysteresis
VIPLH 0.2 Typ. 0.2 Typ. —
—Typ.— 34 — —
Max. VIPH 65 68 70
Note 1: All of this table’s limits are set by design and characterization.
2: The HV POR is triggered by VIP
, with hysteresis. The LV POR is triggered by VDD, with hysteresis.
3: VDM =V
IP –V
IM. VIM is in its range when both VIP and VDM are in their ranges.
4: Allowing the ambient temperature (TA) to exceed the Maximum Ambient Temperature limit (TAH) may
cause parameters to exceed their specified limits. See Section 1.1 “Absolute Maximum Ratings †” for
the Absolute Maximum Junction Temperature and Storage Temperature limits.
5: VOL and VOH are at RL=1k
MCP6C02
DS20006129B-page 6 2018-2019 Microchip Technology Inc.
VREF VAll —Min.V
RL 00 -0.3
Typ. — VDD/4 — —
Max. VRH VDD –1.25 V
DD –1.15 V
DD +0.3
VOUT
(Note 5)
VAll —Min.V
OL 0.06 Max 0 -0.3
Typ. — VDD/2 — —
Max. VOH VDD –0.13
Min
VDD VDD +0.3
VDM V20 —Min.V
DML -3/GDM -4.25/GDM -1.2
50, 100 -4.05/GDM
All Typ. — 0 — —
Max. VDMH 5.3/GDM 5.5/GDM +1.2
TA°C All E-Temp and
H-Temp Parts
Min. TAL -40 -40 -40
Typ. — 25 — —
E-Temp Parts Max. TAH +125 +150 +155
H-Temp Parts +150 +155
TABLE 1-1: VOLTAGE AND TEMPERATURE RANGES (CONTINUED)
Parameter Units GDM (V/V) Comment
Range
Type Sym. Spec. Oper. Abs. Min./Max.
Note 1: All of this table’s limits are set by design and characterization.
2: The HV POR is triggered by VIP
, with hysteresis. The LV POR is triggered by VDD, with hysteresis.
3: VDM =V
IP –V
IM. VIM is in its range when both VIP and VDM are in their ranges.
4: Allowing the ambient temperature (TA) to exceed the Maximum Ambient Temperature limit (TAH) may
cause parameters to exceed their specified limits. See Section 1.1 “Absolute Maximum Ratings †” for
the Absolute Maximum Junction Temperature and Storage Temperature limits.
5: VOL and VOH are at RL=1k
2018-2019 Microchip Technology Inc. DS20006129B-page 7
MCP6C02
1.3 Specifications
TABLE 1-2: DC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V,
VDM =0V, V
REF =V
DD/4, VL=V
DD/2 and RL=10kΩ to VL; see Figure 1-9 and Figure 1-10.
Parameter Sym. Min. Typ. Max. Units Gain Conditions
Input Offset (VIP = VIM) (Note 1)
Input Offset Voltage VOS -16 ±1.9 +16 μV20Note 2
-14 ±1.65 +14 50
-12 ±1.5 +12 100
VOS Drift,
Linear Temp. Co.
TC1-90 ±10 +90 nV/°C 20 TA= -40°C to +125°C,
for E-Temp parts
(Note 2, Note 3)
-70 ±8 +70 50
-65 ±7 +65 100
VOS Drift,
Quadratic Temp. Co.
TC2—±60—pV/°C
220
±95 50
±105 100
VOS Drift,
Exponential Temp. Co.
TCX—1.8—μV20
0.31 50
0.10 100
VOS Aging ∆VOS —±0.18— μV 20 108 hr at +150°C
(changes measured at +25°C)
±0.11 50
±0.09 100
TC1 Aging ∆TC1— ±1.9 — nV/°C 20
±1.1 50
±1.0 100
Power Supply Rejection
Ratio
PSRR 109 134 — dB 20 VDD =2.0Vto5.5V
115 138 50
116 140 100
Input Current and Impedance (VIP and VIM)
VIP's Input Bias Current IBP 120 170 215 μAAllV
DD =2.0Vto5.5V
VIM's Input Bias Current IBM — ±0.2 — nA VDD =5.5V
IBM2 3V
DD =5.5V, V
DM =V
DML
IBM3 -2 VDD =5.5V, V
DM =V
DMH
Capacitance at VIP CVIP —40—pF
Capacitance at VIM CVIM 11
Capacitance across VDM CVDM 12
Note 1: The VIP input is treated as the Common-mode input (e.g., for CMRR). VDM =(V
IP –V
IM).
2: Set by design and characterization. VOS is screened in production (see Appendix B: “Offset Test Screens”).
3: See the discussion in Section 1.6.2, Input Offset Related Errors.
4: See Section 1.6, Explanation of DC Error Specifications.
MCP6C02
DS20006129B-page 8 2018-2019 Microchip Technology Inc.
Input Common-Mode Voltage (VIP)
VIP’s Voltage Range Low VIPL —2.43.0VAllV
IP ↑
VIPLD 2.15 2.8 VIP ↓
VIPLH 0.2 — VIPLH =V
IPL –V
IPLD
VIP’s Voltage Range High VIPH 65 — —
Common-Mode Rejection
Ratio
CMRR 132 159 — dB 20 VDD = 2.0V to 5.5V,
VIP = 3V to 65V
138 163 50
165 100
Common-Mode
Nonlinearity (Note 4)
INLCM — ±0.006 — ppm All VDD =5.5V, V
IP = 3V to 65V
Reference Voltage (VREF)
Reference Voltage
Range (Note 2)
VRL ——0 VAllSee Section 5.1.6, Setting
the Voltage at VREF
VRH VDD –1.25 — —
Gain Resistance RF+R
G—175—kΩ20
185 50
240 100
VREF Input Capacitance CREF —11—pFAll
Differential Input (VDM) (Note 1)
Differential Gain GDM 20 V/V 20 MCP6C02-020
50 50 MCP6C02-050
100 100 MCP6C02-100
Differential Input (VDM) – Continued (Note 1)
Differential Input Voltage
Range
VDML -3/GDM —— V20V
DD =5.5V, V
REF =4.1V,
VL=0V
-4.05/GDM 50,
100
VDMH — 5.3/GDM All VDD =5.5V, V
REF =0V,
VL=V
DD
Differential Gain Error gE—±0.1— % V
DD =2.0V, V
REF =0.5V,
GDMVDM = -0.4V to 1.4V
-1.6 ±0.1 +1.6 VDD =5.5V, V
REF = 2.75V,
GDMVDM = -2.65V to 2.65V
—±0.1— V
DD =5.5V, V
REF =0V,
GDMVDM = 0.2V to 5.3V
±0.1 20 VDD =5.5V, V
REF = 4.25V,
GDMVDM = -3V to 1.15V
±0.1 50,
100
VDD =5.5V, V
REF = 4.25V,
GDMVDM = -4V to 1.15V
TABLE 1-2: DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V,
VDM =0V, V
REF =V
DD/4, VL=V
DD/2 and RL=10kΩ to VL; see Figure 1-9 and Figure 1-10.
Parameter Sym. Min. Typ. Max. Units Gain Conditions
Note 1: The VIP input is treated as the Common-mode input (e.g., for CMRR). VDM =(V
IP –V
IM).
2: Set by design and characterization. VOS is screened in production (see Appendix B: “Offset Test Screens”).
3: See the discussion in Section 1.6.2, Input Offset Related Errors.
4: See Section 1.6, Explanation of DC Error Specifications.
2018-2019 Microchip Technology Inc. DS20006129B-page 9
MCP6C02
Differential Gain Drift ∆gE/∆TA— ±5 — ppm/°C All VDD =2.0V, V
REF =0.5V,
GDMVDM = -0.4V to 1.4V
—±5— V
DD =5.5V, V
REF =2.75V,
GDMVDM = -2.65V to 2.65V
gE Aging ∆gE— ±0.15 — % 408 hr at +150°C,
VDD =5.5V, V
REF =2.75V,
GDMVDM = -2.65V to 2.65V,
(change measured at +25°C)
Differential Nonlinearity
(Note 4)
INLDM —±50—ppm V
DD =2.0V, V
REF =0.5V,
GDMVDM = -0.4V to 1.4V
±100 VDD =5.5V, V
REF =2.75V,
GDMVDM = -2.65V to 2.65V
Output (VOUT)
Minimum Output
Voltage Swing
VOL —3—mVAllV
DD =2.0V, V
REF = 0V
VDM =-0.5V/G
DM
5V
DD =5.5V, V
REF = 0V
VDM =-0.5V/G
DM
20 60 VDD =5.5V, V
REF = 0V
VDM =-0.5V/G
DM, RL=1kΩ
3— V
DD =5.5V, V
REF = 0V
VDM =-0.5V/G
DM, VL=0V
Output (VOUT)–Continued
Maximum Output
Voltage Swing
VDD –
VOH
—6—mVAllV
DD =2.0V, V
REF = 0.75V
VDM = 1.75V/GDM
10 VDD =5.5V, V
REF = 4.25V
VDM = 1.75V/GDM
40 130 VDD =5.5V, V
REF = 4.25V
VDM = 1.75V/GDM, RL=1kΩ
5— V
DD =5.5V, V
REF = 0V
VDM = 1.75V/GDM, VL=V
DD
Output Short Circuit
Current
ISCP —+12— V
DD =2.0V, V
REF =1V,
GDMVDM =1.0V
+20 VDD =5.5V, V
REF =1V,
GDMVDM =1.0V
ISCM —-12— V
DD =2.0V, V
REF =1V,
GDMVDM = -1.0V
-20 VDD =5.5V, V
REF =1V,
GDMVDM = -1.0V
TABLE 1-2: DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V,
VDM =0V, V
REF =V
DD/4, VL=V
DD/2 and RL=10kΩ to VL; see Figure 1-9 and Figure 1-10.
Parameter Sym. Min. Typ. Max. Units Gain Conditions
Note 1: The VIP input is treated as the Common-mode input (e.g., for CMRR). VDM =(V
IP –V
IM).
2: Set by design and characterization. VOS is screened in production (see Appendix B: “Offset Test Screens”).
3: See the discussion in Section 1.6.2, Input Offset Related Errors.
4: See Section 1.6, Explanation of DC Error Specifications.
MCP6C02
DS20006129B-page 10 2018-2019 Microchip Technology Inc.
Power Supplies (VDD, VSS and VIP)
Low Supply Voltage VDD 2.0 — 5.5 V All
High Supply Voltage VIP (see VIP spec)
Quiescent Current at VSS ISS —-660—μAI
O=0A
Quiescent Current at VDD IDD 300 490 725
Quiescent Current at VIP IBP (see IBP spec)
POR Trip Voltages,
Low-Side (VDD)
VPLL 1.05 1.35 — V All LV POR turns off (VDD ↓),
VL=0V, V
IP =3V, V
REF =0V
VPLH — 1.45 1.7 LV POR turns on (VDD ↑),
VL=0V, V
IP =3V, V
REF =0V
POR Trip Voltages,
High-Side (VIP)
VPHL 1.7 1.95 — HV POR turns off (VIP ↓),
RL= open, VDD =5.5V
(change in ISS)
VPHH — 2.05 2.6 HV POR turns on (VIP ↑),
RL= open, VDD =5.5V
(change in ISS)
TABLE 1-2: DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V,
VDM =0V, V
REF =V
DD/4, VL=V
DD/2 and RL=10kΩ to VL; see Figure 1-9 and Figure 1-10.
Parameter Sym. Min. Typ. Max. Units Gain Conditions
Note 1: The VIP input is treated as the Common-mode input (e.g., for CMRR). VDM =(V
IP –V
IM).
2: Set by design and characterization. VOS is screened in production (see Appendix B: “Offset Test Screens”).
3: See the discussion in Section 1.6.2, Input Offset Related Errors.
4: See Section 1.6, Explanation of DC Error Specifications.
TABLE 1-3: AC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V,
VDM =0V, V
REF =V
DD/4, VL=V
DD/2, RL=10kΩ to VL and CL=60pF; see Figure 1-11.
Parameter Sym. Min. Typ. Max. Units Gain Conditions
AC Response
Bandwidth BW — 500 — kHz 20, 50 GDMVDM =0.1V
p-p
390 100
Gain Peaking GPK — 0 — dB All
Step Response
VDM Slew Rate SR (Note 1)V/μsAllG
DMVDM Step = VDD –0.5V
VDM Step Overshoot OSDM —4 — % G
DMVDM Step = 0.1V, tr_in =0.2μs
Overdrive Recovery,
Input Differential Mode
tIRDL —3 — μs20V
DD = 5.5V, VREF =4V,
GDMVDM = -3.5V to -1.25V Step,
90% of VOUT change
(see tORL Spec) 50, 100 (Note 2)
tIRDH —3 — AllV
DD = 5.5V, VREF =0.5V,
GDMVDM = +4.5V to +2.25V Step,
90% of VOUT change
Note 1: SR is limited by GBWP; the large signal step response is dominated by the small signal bandwidth.
2: At these gains, we cannot distinguish between overdriving VDM or VOUT
.
3: See Figure 2-58 for the noise density over a wider frequency range.
4: Not tested; for design guidance only.
2018-2019 Microchip Technology Inc. DS20006129B-page 11
MCP6C02
Overdrive Recovery,
Output
tORL —1.5 — μsAllV
DD = 2.0V, VREF =0V,
GDMVDM = -0.5V to +1V Step,
90% of VOUT change
1.5 VDD = 5.5V, VREF =0V,
GDMVDM = -0.5V to +2.75V Step,
90% of VOUT change
tORH —1.5 — V
DD = 2.0V, VREF =0.75V,
GDMVDM = +1.75V to +0.25V Step,
90% of VOUT change
1.5 VDD = 5.5V, VREF =4.25V,
GDMVDM = +1.75V to -1.25V Step,
90% of VOUT change
Noise
Input Noise Voltage Eni —0.48 — μVp-p 20 f = 0.01 Hz to 1 Hz
0.30 50
0.29 100
— 1.54 — 20 f=0.1Hzto10Hz
0.95 50
0.92 100
Input Noise Voltage
Density (Note 3)
eni —74 —nV/√Hz 20 f < 500 Hz
46 50
44 100 f < 1 kHz
Input Current Noise
Density – At VIP
inip —10 —pA/√Hz All f = 1 kHz
Input Current Noise
Density – At VIM
inim —8 —fA/√Hz f=1kHz, V
DM =0V
33 f = 1 kHz, VDM =0.15V
EMI Protection
EMI Rejection Ratio EMIRR — 96 — dB All VIN =0.1V
PK, f = 400 MHz
91 VIN =0.1V
PK, f = 900 MHz
114 VIN =0.1V
PK, f = 1800 MHz
118 VIN =0.1V
PK, f = 2400 MHz
121 VIN =0.1V
PK, f = 6000 MHz
Power Up/Down
Power On Time (VDD ↑),
VOUT Settles
tPON —65 — μsAllV
DD = 0V to 2.0V, VL=0V,
90% of VOUT change
140 VDD = 0V to 5.5V, VL=0V,
90% of VOUT change
Power Off Time (VDD ↓),
VOUT Settles
tPOFF —8 — V
DD = 2.0V to 0V, VL=0V,
90% of VOUT change
5.5 VDD = 5.5V to 0V, VL=0V,
90% of VOUT change
VIP Edge Rate ∆VIP/∆t -25 — +25 V/μs All ESD structure not triggered (Note 4)
VIP Bypass Capacitor CVIP — 10 — nF All Connects to VIP and GND
TABLE 1-3: AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V,
VDM =0V, V
REF =V
DD/4, VL=V
DD/2, RL=10kΩ to VL and CL=60pF; see Figure 1-11.
Parameter Sym. Min. Typ. Max. Units Gain Conditions
Note 1: SR is limited by GBWP; the large signal step response is dominated by the small signal bandwidth.
2: At these gains, we cannot distinguish between overdriving VDM or VOUT
.
3: See Figure 2-58 for the noise density over a wider frequency range.
4: Not tested; for design guidance only.
MCP6C02
DS20006129B-page 12 2018-2019 Microchip Technology Inc.
1.4 Simplified Diagrams
1.4.1 VOLTAGE RANGE DIAGRAMS
These ranges are constant across temperature.
FIGURE 1-1: Common-Mode Input
Voltage Range vs. Temperature.
FIGURE 1-2: Differential Input Voltage
Range vs. Temperature.
FIGURE 1-3: Reference Voltage Range
vs. Temperature.
1.4.2 TIMING DIAGRAMS
FIGURE 1-4: Common-Mode Input
Overdrive Recovery Timing Diagram.
FIGURE 1-5: Differential-Mode Input
Overdrive Recovery Timing Diagram.
TABLE 1-4: TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = 2.0V to 5.5V, VSS = GND and VIP =34V.
Parameters Sym. Min. Typ. Max. Units Conditions
Specified Temperature Range TA-40 — +125 °C E-Temp parts (Note 2)
+150 H-Temp parts (Note 3)
Operating Temperature Range -40 — +150 Note 1
Storage Temperature Range -60 — +150 No power
Thermal Resistance, 6L-SOT-23 JA — 191 — °C/W
Note 1: Operation must not cause TJ to exceed the Absolute Maximum Junction Temperature specification (155°C), which is
not intended for continuous use. See Section 4.1.5, Temperature Performance for design tips.
2: Automotive Grade 1 parts use the 6L-SOT-23 package. They can operate continuously at TA = +125°C, as long as the
junction temperature stays below 150°C.
3: Automotive Grade 0 parts use the 8L-3×3 VDFN package. They can operate at TA = +150°C for a limited time, as long
as the junction temperature stays below 155°C.
VIPH –V
SS
VIP Range (V)
TA(°C)
-40 25 85 125 150
VIPL –V
SS
VDML
VDM Range (V)
TA(°C)
-40 25 85 125 150
VDMH
VRH
VREF Range (V)
TA(°C)
-40 25 85 125 150
VRL
VDD
VOUT
tIRC
VDM
VIP
±(1V)/GDM
VOUT
tIRD
VIP
VDM
34V
2018-2019 Microchip Technology Inc. DS20006129B-page 13
MCP6C02
FIGURE 1-6: Output Overdrive Recovery
Timing Diagram.
FIGURE 1-7: VOUT Power On/Off Timing
Diagram, Low-Side.
FIGURE 1-8: VOUT Power On/Off Timing
Diagram, High-Side.
1.5 Simplified Test Circuits
1.5.1 VOS TEST CIRCUIT
Figure 1-9 tests the MCP6C02’s input offset errors
(VOS, 1/CMRR, 1/CMRR2 and 1/PSRR, etc.). RWIP is
set very low, so IBP does not affect the result. VOUT is
filtered and amplified, before measuring the result.
FIGURE 1-9: Input Offset Test Circuit for
the MCP6C02.
When MCP6C02 is in its normal range of operation, the
DC output voltages are (VE is the sum of input offset
errors and gE is the gain error):
EQUATION 1-1:
The resistances at the Device Under Test (DUT) need
to be small enough for accuracy (see Figure 1-10).
These resistances include wires, traces, vias, etc.
EQUATION 1-2:
1.5.2 DC DIFFERENTIAL GAIN TEST
CIRCUIT
Figure 1-10 is used for testing the differential gain error,
nonlinearity and input voltage range (gE, INLDM, VDML
and VDMH). We compare VMEAS with the ideal VOUT
,
then extract the above parameters.
FIGURE 1-10: Differential Gain Test Circuit.
When measuring the differential input range, all of the
voltages must be in range except VDM.
When measuring differential errors (gE, ∆gE/∆TA and
INLDM), all voltages are held constant, except VDM.
For accuracy, the wiring resistances at the DUT need to
be very small (see Equation 1-2).
1.5.3 AC GAINS TEST CIRCUIT
Figure 1-11 is used for testing the INA’s different AC
gains. The AC voltages are:
•v
out is the AC output
•v
ip is the AC Common-mode input, used for
CMRR plots
•v
dm is the AC differential input, used for GDM plots
(also for CMRR and PSRR)
•v
dd and vss are the AC supply inputs, used for
PSRR plots (including PSRR+ and PSRR-)
VOUT
tOR
VIP
VDM
34V
VPLH +0.1V
0V
High-Z
VOUT
VDD tPOFF tPON
On
VPLL +0.1V
VPHH +0.1V
0V
High-Z
VOUT
VIP tPHOFF tPHON
On
VPHL +0.1V
VDD
U1 (DUT)
MCP6C02-xxx
RWR RL
VL
VMEAS
VIP
CVIP CL
CVDD
RWIM
RWIP
VOUT
LPF
and
Gain
GDM =
VOUT GDM 1gE
+VEVREF
+=
VMEAS GPAVOUT
=
DM Gain
RWIP ≤4mΩ
RWIM ≤0.1Ω
RWR ≤1Ω
VDD
U1 (DUT)
MCP6C02-xxx
RWR RL
VL
VMEAS
VIP
CVIP
CL
CVDD
RWIM
RWIP
VOUT
LPF
and
Gain
VIM
MCP6C02
DS20006129B-page 14 2018-2019 Microchip Technology Inc.
FIGURE 1-11: AC Gain Test Circuit.
The impedance at VREF (shown here as RWR) needs to
have a magnitude less than 1Ω, for gain accuracy in the
signal bandwidth. The magnitude needs to be < 50Ω,
when f < 1 MHz, to maintain good stability.
1.6 Explanation of DC Error
Specifications
1.6.1 LINEAR RESPONSE MODEL
When the inputs and the output are in their normal
ranges, and the nonlinear errors are negligible, the out-
put voltage (VOUT) is:
EQUATION 1-3:
VDM is the input voltage. VE is the sum of input offset
errors (due to VOS, PSRR, CMRR, CMRR2, TC1, TC2,
etc.). gE is the gain error (GDM is the nominal gain).
1.6.2 INPUT OFFSET RELATED ERRORS
When VDM = 0V, the linear response model for VOUT
becomes:
EQUATION 1-4:
The input offset error (VE) is extracted from input offset
measurements (see Section 1.5.1 “VOS Test
Circuit”):
EQUATION 1-5:
We usually assume gE=0, in Equation 1-5, when
extracting VE. The result is accurate enough, since gE
is so low.
VE has several terms, which assume a linear response
to changes in VDD, VSS, VIP and VREF
.
VOS’s dependence on temperature (TA) is quadratic
plus exponential (VOS, TC1, TC2 and TCX). The aging
specs (∆VOS and ∆TC1) are not included, for simplicity.
The exponential factor in Equation 1-6 decreases at
colder temperatures (TA). This table gives an indication
of this relationship.
EQUATION 1-6:
1.6.3 INPUT OFFSET’S COMMON-MODE
VOLTAGE NONLINEARITY
The input offset error (VE) changes nonlinearly with VIP
.
Figure 1-12 shows the MCP6C02’s VE vs. VIP
, as well
as a linear fit line (VE_LIN), that goes through the center
point (VC, V2) and has the same slope as the end
points.
VDD +v
dd
U1 (DUT)
MCP6C02-xxx
RWR RL
VL
VOUT +v
out
~
VIP +v
ip
VDM +v
dm
CVIP
CL
CVDD
VOUT VREF GDM 1g
E
+VDM VE
++=
TABLE 1-5: EXPONENTIAL TERM
TA (°C) 2((TA–150°C) ⁄ (10°C))
≤65 ≤0.003
+85 0.011
+105 0.044
+125 0.177
+150 1.000
VOUT VREF GDM 1g
E
+VE
+=
VE
VOUT VREF
–
GDM 1g
E
+
---------------------------------=
Where:
PSRR, CMRR and CMRR2 are in units of V/V
∆TA is in units of °C
VDM =0
VEVOS
VDD
VSS
–
PSRR
------------------------------------
VIP
CMRR
----------------
VREF
CMRR2
-------------------
TATC1
TA
2TC2TCX 2
TA150
C–10
C

++++++=
2018-2019 Microchip Technology Inc. DS20006129B-page 15
MCP6C02
FIGURE 1-12: Input Offset Error vs.
Common-Mode Input Voltage.
The part is in standard conditions (∆VOUT =0, V
DM =0,
etc.). VIP sweeps from VIPL to VIPH. The test circuit is in
Section 1.5.1, VOS Test Circuit. Calculate VE at each
point with Equation 1-5.
Based on the measured VE data, we obtain the
following linear fit:
EQUATION 1-7:
The remaining error (∆VE) is described by the
Common-mode Nonlinearity spec:
EQUATION 1-8:
1.6.4 DIFFERENTIAL GAIN ERROR AND
NONLINEARITY
The differential errors are extracted from differential
gain measurements (see Section 1.5.2, DC
Differential Gain Test Circuit), based on
Equation 1-3. These errors are then split into the
differential gain error (gE) and the input nonlinearity
error INLDM.
The error VED is calculated by subtracting the ideal
output from VOUT
, then dividing by the ideal gain GDM.
EQUATION 1-9:
Figure 1-13 shows VED vs. VDM, as well as a linear fit
line (VED_LIN) based on VDM and gE. The amplifier is in
one of the standard condition sets. The linear fit line
(VED_LIN) goes through the center point (VC, V2) and
has the same slope as the end points.
FIGURE 1-13: Differential Input Error vs.
Differential Input Voltage.
Based on the measured VED data, we obtain the
following linear fit:
EQUATION 1-10:
The remaining error (∆VED) is described by the
Differential Nonlinearity spec:
EQUATION 1-11:
The aging spec ∆gE is not included here, for simplicity.
VDM sweeps are not always centered on VDM =0V; the
INLDM spec will interact with the VOS spec.
V1
V3
VE,V
E_LIN (V)
VIP (V)
VIPL VIPH
VC
V2
VE_LIN
VE
∆VE
Where:
VE_LIN V2VIP VC
–CMRR
+=
VCVIPL VIPH
+2
=
1CMRR
V3V1
–VIPH VIPL
–
=
Where:
VEVEVE_LIN
–=
INLCMH max
VE
VIPH VIPL
–
=
INLCML min
VE
VIPH VIPL
–
=
INLCM INLCMH, INLCMH INLCML
=
INLCML, otherwise=
VED VOUT VREF GDM VDM
+–GDM
=
V1
V3
VED, VED_LIN (V)
VDM (V)
VD1 VD2
VC
V2
VED_LIN
VED
∆VED
Where:
VED_LIN V2VDM VC
–gE
+=
gEV3V1
–VD2 VD1
–
=
VCVD1 VD2
+2
=
Where:
VED VED VED_LIN
–=
INLDMH max
VED
VD2 VD1
–
=
INLDML min
VED
VD2 VD1
–
=
INLDM INLDMH, INLDMH INLDML
=
INLDML, otherwise=
MCP6C02
DS20006129B-page 16 2018-2019 Microchip Technology Inc.
NOTES:
2018-2019 Microchip Technology Inc. DS20006129B-page 17
MCP6C02
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA=+25°C, V
DD = 2.0V to 5.5V, VSS = GND, VIP =34V, V
DM =0V,
VREF =V
DD/4, VL=V
DD/2, RL=10kΩ to VL and CL=60pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
2.1 DC Precision
FIGURE 2-1: Input Offset Voltage,
GDM =20.
FIGURE 2-2: Input Offset Voltage,
GDM =50.
FIGURE 2-3: Input Offset Voltage,
GDM =100.
FIGURE 2-4: Linear Input Offset Voltage
Drift, GDM =20.
FIGURE 2-5: Linear Input Offset Voltage
Drift, GDM =50.
FIGURE 2-6: Linear Input Offset Voltage
Drift, GDM = 100.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
5%
10%
15%
20%
25%
30%
35%
40%
-12 -10 -8 -6 -4 -2 0 2 4 6 8 10
12
Percentage of Occurrences
Input Offset Voltage; VOS (μV)
GDM = 20
TA= +25°C
28 Samples
VDD = 2.0V VDD = 5.5V
0%
5%
10%
15%
20%
25%
30%
35%
-6 -5 -4 -3 -2 -1 0 1 2 3 4 5
6
Percentage of Occurrences
Input Offset Voltage; VOS (μV)
GDM = 50
TA= +25°C
28 Samples
VDD = 2.0V
VDD = 5.5V
0%
5%
10%
15%
20%
25%
30%
35%
40%
-6 -5 -4 -3 -2 -1 0 1 2 3 4 5
6
Percentage of Occurrences
Input Offset Voltage; VOS (μV)
GDM = 100
TA= +25°C
27 Samples
VDD = 5.5V
VDD = 2.0V
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
-60 -50 -40 -30 -20 -10 0 10 20 30 40 50
60
Percentage of Occurrences
Input Offset Voltage Drift; TC1(nV/°C)
GDM = 20
TA= -40°C to +150°C
28 Samples
VDD = 2.0V
VDD = 5.5V
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
-30 -25 -20 -15 -10 -5 0 5 10 15 20 25
30
Percentage of Occurrences
Input Offset Voltage Drift; TC1(nV/°C)
GDM = 50
TA= -40°C to +150°C
28 Samples
VDD = 2.0V
VDD = 5.5V
0%
5%
10%
15%
20%
25%
30%
35%
-30 -25 -20 -15 -10 -5 0 5 10 15 20 25
30
Percentage of Occurrences
Input Offset Voltage Drift; TC1(nV/°C)
GDM = 100
TA= -40°C to +150°C
27 Samples
VDD = 5.5V
VDD = 2.0V
MCP6C02
DS20006129B-page 18 2018-2019 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = 2.0V to 5.5V, VSS = GND, VIP =34V, V
DM =0V,
VREF =V
DD/4, VL=V
DD/2, RL=10kΩ to VL and CL=60pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
FIGURE 2-7: Quadratic Input Offset
Voltage Drift, GDM = 20.
FIGURE 2-8: Quadratic Input Offset
Voltage Drift, GDM = 50.
FIGURE 2-9: Quadratic Input Offset
Voltage Drift, GDM = 100.
FIGURE 2-10: Exponential Input Offset
Voltage Drift, GDM = 20.
FIGURE 2-11: Exponential Input Offset
Voltage Drift, GDM = 50.
FIGURE 2-12: Exponential Input Offset
Voltage Drift, GDM = 100.
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
-300 -200 -100 0 100 200
300
Percentage of Occurrences
Input Offset Voltage Drift; TC2(pV/°C2)
VDD = 5.5V
VDD = 2.0V
GDM = 20
TA= -40°C to +150°C
28 Samples
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
55%
0123456
Percentage of Occurrences
Input Offset Voltage Drift; TCX(μV)
VDD = 2.0V
VDD = 5.5V
GDM = 20
TA= -40°C to +150°C
28 Samples
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
55%
0.0 0.4 0.8 1.2 1.6 2.0
2.4
Percentage of Occurrences
Input Offset Voltage Drift; TCX(μV)
GDM = 50
TA= -40°C to +150°C
28 Samples
VDD = 2.0V
VDD = 5.5V
0%
5%
10%
15%
20%
25%
30%
35%
40%
0.0 0.2 0.4 0.6 0.8 1.0
1.2
Percentage of Occurrences
Input Offset Voltage Drift; TCX(μV)
GDM = 100
TA= -40°C to +150°C
27 Samples
VDD = 2.0V
VDD = 5.5V
2018-2019 Microchip Technology Inc. DS20006129B-page 19
MCP6C02
Note: Unless otherwise indicated, TA=+25°C, V
DD = 2.0V to 5.5V, VSS = GND, VIP =34V, V
DM =0V,
VREF =V
DD/4, VL=V
DD/2, RL=10kΩ to VL and CL=60pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
FIGURE 2-13: Input Offset Voltage vs.
Power Supply Voltage, with GDM = 20.
FIGURE 2-14: Input Offset Voltage vs.
Power Supply Voltage, with GDM = 50.
FIGURE 2-15: Input Offset Voltage vs.
Power Supply Voltage, with GDM = 100.
FIGURE 2-16: Input Offset Voltage vs.
Common-Mode Input Voltage, with GDM =20.
FIGURE 2-17: Input Offset Voltage vs.
Common-Mode Input Voltage, with GDM =50.
FIGURE 2-18: Input Offset Voltage vs.
Common-Mode Input Voltage, with GDM = 100.
-10
-8
-6
-4
-2
0
2
4
6
8
10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
5.5
Input Offset Voltage; V
OS
(μV)
Power Supply Voltage; V
DD
(V)
GDM = 20
VIP = 3V Representative Part
150°C
125°C
85°C
25°C
-40°C
-8
-6
-4
-2
0
2
4
6
8
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
5.5
Input Offset Voltage; V
OS
(μV)
Power Supply Voltage; VDD (V)
GDM = 50
VIP = 3V Representative Part
150°C
125°C
85°C
25°C
-40°C
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
5.5
Input Offset Voltage; V
OS
(μV)
Power Supply Voltage; V
DD
(V)
GDM = 100
VIP = 3V Representative Part
150°C
125°C
85°C
25°C
-40°C
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-8
-6
-4
-2
0
2
4
6
8
0 5 10 15 20 25 30 35 40 45 50 55 60 65
70
Input Offset Voltage; VOS (μV)
Common Mode Input Voltage; V,3 (V)
+150°C
+125°C
+85°C
+25°C
-40°C
GDM = 50
VDD = 2.0V Representative Part
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
0 5 10 15 20 25 30 35 40 45 50 55 60 65
70
Input Offset Voltage; VOS (μV)
Common Mode Input Voltage; V,3 (V)
+150°C
+125°C
+85°C
+25°C
-40°C
GDM = 100
VDD = 2.0V Representative Part
MCP6C02
DS20006129B-page 20 2018-2019 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = 2.0V to 5.5V, VSS = GND, VIP =34V, V
DM =0V,
VREF =V
DD/4, VL=V
DD/2, RL=10kΩ to VL and CL=60pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
FIGURE 2-19: Input Offset Voltage vs.
Reference Voltage, with GDM =20.
FIGURE 2-20: Input Offset Voltage vs.
Reference Voltage, with GDM =50.
FIGURE 2-21: Input Offset Voltage vs.
Reference Voltage, with GDM = 100.
FIGURE 2-22: 1/CMRR, with GDM =20.
FIGURE 2-23: 1/CMRR, with GDM =50.
FIGURE 2-24: 1/CMRR, with GDM =100.
-10
-8
-6
-4
-2
0
2
4
6
8
10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
5.5
Input Offset Voltage; VOS (μV)
Output Reference Voltage; VREF (V)
G
DM
= 20
V
DD
= 5.5V
Representative Part
+150°C
+125°C
+85°C
+25°C
-40°C
-40°C
C
C
C
+150°C
+150°C
+125
+85
+25
-40
0%
5%
10%
15%
20%
25%
30%
35%
40%
0.014 0.016 0.018 0.020 0.022 0.024
0.026
Percentage of Occurrences
1/CMRR (μV/V)
GDM = 20
TA= +25°C
VIP = 3V to 65V
28 Samples
VDD = 2.0V
VDD = 5.5V
0%
5%
10%
15%
20%
25%
30%
35%
40%
0.014 0.016 0.018 0.020 0.022 0.024
0.026
Percentage of Occurrences
1/CMRR (μV/V)
GDM = 50
TA= +25°C
VIP = 3V to 65V
28 Samples
VDD = 2.0V
VDD = 5.5V
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
55%
0.014 0.016 0.018 0.020 0.022 0.024
0.026
Percentage of Occurrences
1/CMRR (μV/V)
GDM = 100
TA= +25°C
VIP = 3V to 65V
28 Samples
VDD = 5.5V
VDD = 2.0V
2018-2019 Microchip Technology Inc. DS20006129B-page 21
MCP6C02
Note: Unless otherwise indicated, TA=+25°C, V
DD = 2.0V to 5.5V, VSS = GND, VIP =34V, V
DM =0V,
VREF =V
DD/4, VL=V
DD/2, RL=10kΩ to VL and CL=60pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
FIGURE 2-25: 1/PSRR, with GDM = 20.
FIGURE 2-26: 1/PSRR, with GDM = 50.
FIGURE 2-27: 1/PSRR, with GDM = 100.
FIGURE 2-28: CMRR vs. Ambient
Temperature.
FIGURE 2-29: PSRR vs. Ambient
Temperature.
FIGURE 2-30: Input Offset Voltage - Final
Test Results.
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
-0.3 -0.2 -0.1 0.0 0.1 0.2
0.3
Percentage of Occurrences
1/PSRR (μV/V)
GDM = 20
TA= +25°C
VDD = 2.0V to 5.5V
28 Samples
0%
5%
10%
15%
20%
25%
30%
35%
40%
-0.12 -0.08 -0.04 0.00 0.04 0.08
0.12
Percentage of Occurrences
1/PSRR (μV/V)
GDM = 50
TA= +25°C
VDD = 2.0V to 5.5V
28 Samples
0%
5%
10%
15%
20%
25%
30%
-0.06 -0.04 -0.02 0.00 0.02 0.04
0.06
Percentage of Occurrences
1/PSRR (μV/V)
GDM = 100
TA= +25°C
VDD = 2.0V to 5.5V
27 Samples
100
110
120
130
140
150
160
-50 -25 0 25 50 75 100 125
150
CMRR (dB)
Ambient Temperature; TA(°C)
VIP = 3V to 65V
28 Samples
GDM = 100
GDM = 50
GDM = 20
100
110
120
130
140
150
160
-50 -25 0 25 50 75 100 125
150
PSRR (dB)
Ambient Temperature; TA(°C)
VDD = 2.0V to 5.5V
28 Samples
GDM = 100
GDM = 50
GDM = 20
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
16
18
20
Percentage of Occurrences
Input Offset Voltage; VOS (μV)
Final Test
TA= +25°C
294 Samples
GDM = 50
GDM = 20
GDM = 100
MCP6C02
DS20006129B-page 22 2018-2019 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = 2.0V to 5.5V, VSS = GND, VIP =34V, V
DM =0V,
VREF =V
DD/4, VL=V
DD/2, RL=10kΩ to VL and CL=60pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
FIGURE 2-31: PSRR - Final Test Results.
FIGURE 2-32: CMRR - Final Test Results.
FIGURE 2-33: Gain Error.
FIGURE 2-34: Gain Error Temperature
Drift.
FIGURE 2-35: Differential Gain
Nonlinearity.
0%
5%
10%
15%
20%
25%
30%
35%
40%
-0.3
-0.3
-0.2
-0.2
-0.1
-0.1
0.0
0.1
0.1
0.2
0.2
0.3
0.3
0.4
0.4
0.5
0.5
0.6
0.6
0.7
0.7
Percentage of Occurrences
1/PSRR (μV/V)
Final Test
TA= +25°C
294 Samples GDM = 50
GDM = 20
GDM = 100
G
= 100
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
16
18
20
Percentage of Occurrences
Gain Error Drift; ΔgE/ΔTA(ppm/°C)
G
DM
= 20
VDD = 5.5V
TA= -40°C to +150°C
300 Samples
0%
10%
20%
30%
40%
50%
60%
70%
80%
0
20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
Percentage of Occurrences
Differential Gain Non-Linearity; | INLDM | (ppm)
TA= +25°C
VDD = 5.5V
VREF = 2.75V
294 Samples
GDM = 20
GDM = 50
GDM = 100
2018-2019 Microchip Technology Inc. DS20006129B-page 23
MCP6C02
Note: Unless otherwise indicated, TA=+25°C, V
DD = 2.0V to 5.5V, VSS = GND, VIP =34V, V
DM =0V,
VREF =V
DD/4, VL=V
DD/2, RL=10kΩ to VL and CL=60pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
2.2 Other DC Voltages and Currents
FIGURE 2-36: VIP Pin Input Bias Current
vs. Input Common-Mode Voltage.
FIGURE 2-37: VIM Pin Input Bias Current
vs. Input Common-Mode Voltage, VDM =V
DML.
FIGURE 2-38: VIM Pin Input Bias Current
vs. Input Common-Mode Voltage, VDM =V
DMH.
FIGURE 2-39: VIP Pin Input Bias Current
vs. Ambient Temperature.
FIGURE 2-40: VIM Pin Input Bias Current
vs. Ambient Temperature.
FIGURE 2-41: VIM Pin Input Bias Current
vs. Differential Input Voltage.
0
20
40
60
80
100
120
140
160
180
200
220
0 5 10 15 20 25 30 35 40 45 50 55 60 65
70
Non-Inverting Input Bias
Current; IBP (μA)
Non-Inverting Input Voltage; VIP (V)
-40°C
+25°C
+85°C
+125°C
+150°C
Representative Part
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150
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Current; IBP (μA)
Ambient Temperature; TA(°C)
Representative Part
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0.00
0.05
0.10
0.15
0.20
0.25
0.30
Inverting Input Current; I
BM
(nA)
Differential Input Voltage;VDM (V)
VDM = VDML:
GDM = 20
GDM = 50
GDM = 100
V
DM
= V
DMH
:
GDM
= 100
GDM
= 50
GDM = 20
MCP6C02
DS20006129B-page 24 2018-2019 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = 2.0V to 5.5V, VSS = GND, VIP =34V, V
DM =0V,
VREF =V
DD/4, VL=V
DD/2, RL=10kΩ to VL and CL=60pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
FIGURE 2-42: Input Bias Current vs. Input
Common-Mode Voltage (below VSS).
FIGURE 2-43: Common-Mode Input Range
vs. Ambient Temperature.
FIGURE 2-44: Reference Voltage Range
vs. Ambient Temperature.
FIGURE 2-45: Output Voltage Range vs.
Output Current.
FIGURE 2-46: Output Voltage Range vs.
Ambient Temperature.
FIGURE 2-47: Supply Current vs. Power
Supply Voltage.
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-0.30 -0.25 -0.20 -0.15 -0.10 -0.05
0.00
Input Bias Current; -(I
BP
+ I
BM
)
(A)
Input Common Mode Voltage; VIP (V)
1m
100μ
10μ
1μ
100n
10n
1n
150°C
125°C
85°C
25°C
-40°C
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1000
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10
Output Voltage Range;
VOL, VOH (mV)
Output Current Magnitude; | IOUT | (mA)
VDD –V
OH
VOL –V
SS
0
5
10
15
20
25
30
35
40
45
-50 -25 0 25 50 75 100 125
150
Output Voltage Range;
VOL, VOH (mV)
Ambient Temperature; TA(°C)
VDD –V
OH
VOL –V
SS
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2018-2019 Microchip Technology Inc. DS20006129B-page 25
MCP6C02
Note: Unless otherwise indicated, TA=+25°C, V
DD = 2.0V to 5.5V, VSS = GND, VIP =34V, V
DM =0V,
VREF =V
DD/4, VL=V
DD/2, RL=10kΩ to VL and CL=60pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
FIGURE 2-48: Output Short Circuit Current
vs. Power Supply Voltage for E-Temp Parts.
FIGURE 2-49: Output Short Circuit Current
vs. Power Supply Voltage for H-Temp Parts.
FIGURE 2-50: LV POR (for VDD) Trip
Points vs. Ambient Temperature.
FIGURE 2-51: HV POR (for VIP) Trip Points
vs. Ambient Temperature.
-50
-40
-30
-20
-10
0
10
20
30
40
50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
5.5
Short Circuit Current; ISC
(mA)
Power Supply Voltage; VDD (V)
6-Lead SOT-23
-40°C
+25°C
+85°C
+125°C
+125°C
+85°C
+25°C
-40°C
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1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
-50 -25 0 25 50 75 100 125
150
LV POR Trip Points;
VPLH and VPLL (V)
Ambient Temperature; TA(°C)
VPLH
VPLL
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
-50 -25 0 25 50 75 100 125
150
HV POR Trip Points;
VIPL and VIPLD (V)
Ambient Temperature; TA(°C)
VIPL
VIPLD
MCP6C02
DS20006129B-page 26 2018-2019 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = 2.0V to 5.5V, VSS = GND, VIP =34V, V
DM =0V,
VREF =V
DD/4, VL=V
DD/2, RL=10kΩ to VL and CL=60pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
2.3 Frequency Response
FIGURE 2-52: Gain vs. Frequency, with
Capacitive Load.
FIGURE 2-53: CMRR vs. Frequency.
FIGURE 2-54: PSRR vs. Frequency.
FIGURE 2-55: Closed-Loop Output
Impedance Magnitude vs. Frequency.
FIGURE 2-56: EMI Rejection Ratio vs.
Frequency.
FIGURE 2-57: EMI Rejection Ratio vs.
Signal Strength.
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10k
1.E+01
1.E+02
1.E+03
1.E+04
1.E+5 1.E+6
1.E+7
Closed-Loop Output Impedance
Magnitude; mag(ZO_CL) (Ω)
Frequency; f (Hz)
100k 1M
10M
10
100
1k
10k
GDM = 20
GDM = 50
GDM = 100
0
20
40
60
80
100
120
140
1.0E+08 1.0E+09
1.0E+10
EMI Rejection; EMIRR (dB)
Frequency; f (Hz)
100M
1G
10G
VIP= 0.1VPK
0
20
40
60
80
100
120
140
0.01 0.1 1
EMI Rejection; EMIRR (dB)
Input Common Mode Voltage; VIP (VPK)
f:
6.0 GHz
4.0 GHz
2.4 GHz
1.8 GHz
0.9 GHz
0.4 GHz
2018-2019 Microchip Technology Inc. DS20006129B-page 27
MCP6C02
Note: Unless otherwise indicated, TA=+25°C, V
DD = 2.0V to 5.5V, VSS = GND, VIP =34V, V
DM =0V,
VREF =V
DD/4, VL=V
DD/2, RL=10kΩ to VL and CL=60pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
2.4 Noise and Intermodulation Distortion
FIGURE 2-58: Input Noise Voltage Density
vs. Frequency.
FIGURE 2-59: Input Noise Voltage vs.
Frequency.
FIGURE 2-60: Intermodulation Distortion
vs. Frequency, with VDD Disturbance.
FIGURE 2-61: Input Noise Voltage vs.
Time, GDM = 20.
FIGURE 2-62: Input Noise Voltage vs.
Time, GDM = 50.
FIGURE 2-63: Input Noise Voltage vs.
Time, GDM = 100.
1.E-8
1.E-7
1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4
1.E+5
Input Noise Voltage Density;
eni (V/√Hz)
Frequency; f (Hz)
0.1 1 10 100 1k 10k
100k
10n
100n
300n
GDM = 20
GDM = 50
GDM = 100
1.E-8
1.E-7
1.E-6
1.E-5
1.E-4
1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4
1.E+5
Integrated Input Noise Voltage
(from DC); Eni(0 to f) (VRMS
)
Frequency; f (Hz)
0.1
10n
100n
1μ
10μ
100μ
1 10 100 1k 10k
100k
GDM = 20
GDM = 50
GDM = 100
1.E-06
1.E-05
1.E-04
1.E-03
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04
1.E+05
Output Voltage Tones; VOUT (VPK
)
Frequency; f (Hz)
Δf = 2 Hz, f ≤ 3201 Hz
= 64 Hz, f ≥ 3250 Hz
GDM = 20
VDD = 5.5V, at DC
= 0.1 VPK, at 100 Hz
No VDD bypass cap
Residual Tone
at 100 Hz
0 20406080100120140160180
200
Input Noise Voltage;
Eni(t) (0.5 μV/div)
Time; t (s)
G
DM
= 20
f
SAM = 40 SPS NPBW = 10 Hz
NPBW = 1 Hz
0 20 40 60 80 100 120 140 160 180
200
Input Noise Voltage;
Eni(t) (0.5 μV/div)
Time; t (s)
G
DM
= 50
f
SAM = 40 SPS
NPBW = 10 Hz
NPBW = 1 Hz
0 20 40 60 80 100 120 140 160 180
200
Input Noise Voltage;
Eni(t) (0.5 μV/div)
Time; t (s)
G
DM
= 100
f
SAM = 40 SPS
NPBW = 10 Hz
NPBW = 1 Hz
MCP6C02
DS20006129B-page 28 2018-2019 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = 2.0V to 5.5V, VSS = GND, VIP =34V, V
DM =0V,
VREF =V
DD/4, VL=V
DD/2, RL=10kΩ to VL and CL=60pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
2.5 Time Response
FIGURE 2-64: Input Offset Voltage vs.
Time, with Temperature Change.
FIGURE 2-65: Input Offset Voltage vs.
Time, at Power-Up.
FIGURE 2-66: The MCP6C02 Shows No
Phase Reversal vs. Differential Input Overdrive.
FIGURE 2-67: The MCP6C02 Shows No
Phase Reversal vs. Input Common-Mode
Overdrive.
FIGURE 2-68: Small Signal Step Response
to Differential Input Voltage.
FIGURE 2-69: Small Signal Step Response
to Common-Mode Input Voltage.
0
50
100
150
200
250
300
350
400
450
500
550
-140
-120
-100
-80
-60
-40
-20
0
20
40
60
80
0 20 40 60 80 100 120 140 160 180 200
Sensor Temperature; TSEN (°C)
Input Offset Voltage; V
OS
(μV)
Time; t (s)
PCB effects
dominate
exponential
decays.
NPBW = 10 Hz
GDM = 20
GDM = 50
GDM = 100
GDM = 20
GDM = 50
GDM = 100
VOS
TA
V
(V)
V
-1
0
1
2
3
4
5
6
012345678910
Output Voltage; VOUT (V)
Differential Input Voltage;
GDMVDM (1V/div)
Time; t (ms)
GDMVDM
VOUT
0
1
2
3
4
5
6
7
0
10
20
30
40
50
60
70
012345678910
Output Voltage; VOUT (V)
Common Mode Input Voltage;
VIP (V)
Time; t (ms)
VDD = 5.0V
VIP
VOUT
On
Off
Output Voltage; V
OUT
(20 mV/div)
Time; t (2 μs/div)
G
DM
= 100
GDM
= 50
GDM
= 20
0123456789
10
Output Voltage; VOUT (0.2V/div)
Common Mode Input Voltage;
VIP (0.5V/div)
Time; t (μs)
VIP
GDM = 50
GDM = 100
VOUT
GDM = 20
2018-2019 Microchip Technology Inc. DS20006129B-page 29
MCP6C02
Note: Unless otherwise indicated, TA=+25°C, V
DD = 2.0V to 5.5V, VSS = GND, VIP =34V, V
DM =0V,
VREF =V
DD/4, VL=V
DD/2, RL=10kΩ to VL and CL=60pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
FIGURE 2-70: Small Signal Step Response
to Differential Input Voltage, with Capacitive
Load (CL).
FIGURE 2-71: Small Signal Step Response
Overshoot, with Capacitive Load (CL).
FIGURE 2-72: Small Signal Step Response
Rise Time, with Capacitive Load (CL).
FIGURE 2-73: Small Signal Step Response
Settling Time, with Capacitive Load (CL).
0 102030405060708090
100
Output Voltage; V
OUT
(50
mV/div)
t (μs)
G
DM
= 20
R
ISO = 0Ω
CL= 100 pF
CL= 1 nF
CL= 10 nF
0%
10%
20%
30%
40%
50%
60%
70%
1.E-11 1.E-10 1.E-9
1.E-8
Overshoot
Capacitive Load; CL(F)
RISO = 0Ω
GDM = 100
GDM = 50
GDM = 20
10p 100p 1n
10n
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
1.E-11 1.E-10 1.E-9
1.E-8
Rise Time; t
r
(μs)
Capacitive Load; CL(F)
RISO = 0Ω
G
DM
= 100
GDM
= 50
GDM
= 20
10p 100p 1n
10n
10
100
1.E-11 1.E-10 1.E-9
1.E-8
Settling Time to 1%; t
settle
(μs)
Capacitive Load; CL(F)
RISO = 0Ω
GDM = 100
GDM = 50
GDM = 20
10p 100p 1n
10n
MCP6C02
DS20006129B-page 30 2018-2019 Microchip Technology Inc.
NOTES:
2018-2019 Microchip Technology Inc. DS20006129B-page 31
MCP6C02
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Tab l e 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Noninverting Analog Signal Input
(VIP)
The noninverting input (VIP) is a high-impedance
CMOS input. It is designed to operate over a wide
voltage range, with a voltage source to drive it. In this
data sheet, it is treated as the Common-mode input
voltage.
VIP is the high voltage power supply pin, and is
normally between VSS + 3V and VSS + 65V. It supplies
the current needed to operate the high voltage circuitry.
VIP needs a good bypass capacitor (e.g., 10 nF). VIP –
VSS triggers the HV POR.
The edge rate applied to VIP (∆VIP/∆t) needs to be
limited, so the ESD diodes do not clamp.
VIP is treated as the common mode voltage in this data
sheet, due to the inputs' architecture. Since VDM is
relatively small, this simplification is accurate; it also
simplifies the specifications and applications
information.
3.2 Inverting Analog Signal Input (VIM)
The inverting input (VIM) is a high-impedance CMOS
input, with low input bias current. VIM is designed to
operate near the VIP voltage. The difference voltage
VDM (or VIP –V
IM) is the input signal for this amplifier.
3.3 Analog Output Reference Voltage
(VREF)
The analog output reference voltage is a
high-impedance CMOS input. VREF is set to a DC
voltage, which shifts VOUT
. Its dynamic response helps
reject power surges and glitches at the VIP
, VDD and
VSS pins.
3.4 Analog Output (VOUT)
The analog output pin (VOUT) is a low-impedance
voltage source.
3.5 Low-Side Power Supplies
(VDD, VSS)
VDD is normally between VSS + 2.0V and VSS +5.5V,
while the VREF and VOUT pins are usually between VSS
and VDD. VDD –V
SS triggers the LV POR.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need good bypass capacitors.
In split supply configurations, including dual supplies,
ground is between VSS and VDD. Both supply pins will
need good bypass capacitors.
In a single (negative) supply configuration, VDD
connects to ground and VSS connects to the supply.
VSS will need good bypass capacitors.
3.6 Exposed Pad (EP)
The Exposed Thermal Pad (EP) connects internally to
the VSS pin; they must be connected to the same
potential on the Printed Circuit Board (PCB).
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (JA).
MCP6C02 Sym. Description
SOT-23 3×3 VDFN
15V
OUT Output voltage
22V
SS Negative power supply
31V
IP Noninverting input (at load’s RSH) and positive (high-side) power supply
48V
IM Inverting input (at load’s RSH)
57V
REF Output reference
66V
DD Positive (low-side) power supply
— 3,4 NC No connection
— 9 EP Exposed thermal pad; must be connected to VSS
Note 1: The SOT package is for E-temp and the VDFN package is for H-temp.
MCP6C02
DS20006129B-page 32 2018-2019 Microchip Technology Inc.
NOTES:
2018-2019 Microchip Technology Inc. DS20006129B-page 33
MCP6C02
4.0 DEVICE OPERATION
This chapter includes additional information on basic
operations and major functions.
4.1 Basic Performance
4.1.1 IDEAL PERFORMANCE
Figure 4-1 shows the basic circuit; inputs, supplies and
output. When the inputs (VIP
, VIM, VDD, VSS and VREF)
and output (VOUT) are in their specified ranges, and the
part is nearly ideal, the output voltage is:
EQUATION 4-1:
FIGURE 4-1: Basic Circuit.
For normal operation, keep:
•V
IP between VIPL and VIPH
•V
DM between VDML and VDMH
•V
REF between VRL and VRH
•V
OUT between 0.1V to VDD – 0.1V, usually
-V
OL and VOH are hard limits
4.1.2 ANALOG ARCHITECTURE
Figure 4-2 shows the block diagram for these high-side
current sense amplifiers, without any details on offset
correction.
FIGURE 4-2: MCP6C02 Block Diagram.
The input (differential) signal is applied to GM1. Due to
its architecture, the MCP6C02’s signal inputs are best
described by VIP and VDM. The inverting input is then:
EQUATION 4-2:
The negative feedback loop includes GM2, RM3, RF and
RG
. These blocks set the DC open-loop gain (AOL) and
the nominal differential gain (GDM):
EQUATION 4-3:
AOL is very high, so the current into RM3 (I1+I
2) is
nearly zero. This makes the differential inputs to GM1
and GM2 equal in magnitude and opposite in polarity.
Ideally, this gives:
EQUATION 4-4:
For an ideal part, within the operating ranges, changing
VIP
, VSS or VDD produces no change in VOUT
. VREF
shifts VOUT as needed in the design.
The different GDM options change GM1, GM2, RF
, RG
and the internal compensation capacitor. This results in
the performance trade-offs highlighted in Ta b l e 1 .
4.1.3 DC PERFORMANCE
4.1.3.1 DC Voltage Errors
Section 1.6, Explanation of DC Error Specifications
covers some DC specifications. The input offset error
(with temperature coefficients), gain error and
nonlinearities are discussed in detail.
Plots in Section 2.1, DC Precision and Section 2.2,
Other DC Voltages and Currents give useful
information.
In this data sheet, CMRR is based on changes in VIP
(i.e., CMRR = ∆VIP/∆VOS); this is accurate, since VDM
is relatively small. This CMRR describes the rejection
of errors at the high voltage supply, without any
contribution from VDM.
VOUT VREF GDMVDM
+
Where:
GDM = Differential-Mode Gain
VREF = Output Reference Voltage
VDM = Differential-Mode Input (VIP –V
IM)
VDD U1
MCP6C02
VOUT
VSS
VIP
VIM
VREF
RF
VFG
VOUT
VREF
RM3
GM2
I2
RG
VDD
VSS
GM1 I1
VIP
VIM
VIM VIP VDM
–=
AOL GM2RM3
=
GDM 1R
FRG
+=
VFG VREF
–VDM
=
VOUT VREF GDMVDM
+=
MCP6C02
DS20006129B-page 34 2018-2019 Microchip Technology Inc.
4.1.3.2 DC Current Errors
Figure 4-3 shows the resistors and currents that
change the DC bias point. The input bias currents (IBP
,
IBM and IBR), together with a circuit’s external input
resistances, give an DC error (see Equation 1-2).
FIGURE 4-3: DC Bias Resistors and
Currents.
RSH is set by the design requirements, given the load
current (IL). For most applications, RSH would be
between 100 µΩ and 1Ω.
The DC input offset error due to the input currents is:
VOS_IR =V
DM –I
LRSH
=I
BM(RSH +R
WIM)–I
BPRWIP
Since these currents do not correlate, minimize the
magnitude of each resistance. IBPRIP will dominate in
many designs.
RWR modifies the gain error and the DC output offset
error (VOUT changes IBR):
EQUATION 4-5:
4.1.4 AC PERFORMANCE
The bandwidth of these parts (fBW) is set internally to
either 500 kHz (GDM = 20 or 50) or 390 kHz
(GDM =100).
The large signal bandwidth is close to the small signal
bandwidth; slew rate (SR) has little effect on VOUT (a
benefit of our current-mode architecture).
The bandwidth at the maximum output swing is called
the Full Power Bandwidth (fFPBW). It is limited by the
Slew Rate (SR) for many amplifiers, but is close to fBW
for these parts. This is a benefit of the current-mode
architecture these parts have.
These parts are compensated to have a stable
response. For instance, step response overshoot is
low.
In this data sheet, the AC CMRR is measured at VIP;
this is accurate, since VDM is relatively small.
4.1.5 TEMPERATURE PERFORMANCE
The input offset voltage’s temperature drift is detailed in
Equation 1-6. Other temperature responses are shown
in Section 1.3, Specifications and Section 2.0
“Typical Performance Curves”.
Since there are three power supply pins (VIP
, VDD and
VSS), and VIP reaches 65V, power and temperature rise
calculations are important.
The power dissipated is calculated as follows (IOUT is
positive when it flows out of the VOUT pin):
EQUATION 4-6:
Now we can estimate the junction temperature of the
device (see Ta b l e 1 - 4 ):
EQUATION 4-7:
4.1.6 NOISE PERFORMANCE
This part is designed to have low input noise voltage
density at lower frequencies. The offset correction
(Section 4.2.2, Chopping Action) modulates high
frequency white noise down to DC; it also modulates
low frequency 1/f noise to higher frequencies.
The measured input noise voltage density is shown in
Figure 2-58. That figure also shows Integrated Input
Noise Voltage (Eni, in units of VRMS) between 0 Hz and
f (between 0.1 Hz and 100 kHz).
The Input Noise Voltage Density (eni) changes with
VDM. However, that relationship is a weak one.
IBR
VDD
VSS
U1
MCP6C02
VOUT
RWR
RG
RF
VHV
IL
Load
RSH
IBM
IBP
RWIM
RWIP
VREF IBRRWR
–=
gERWRGDM
–RFRG
+
VOUT VREF
VREF
+GDMVDM 1g
E
gE
+++
PTOT PDD PBP POUT
++=
Where:
IOUT =(V
OUT – VL)/RL
PDD =(V
DD – VSS) IDD
PBP =(V
IP – VSS) IBP
POUT =(V
DD – VOUT) IOUT
, IOUT ≥0A
=(V
SS – VOUT) IOUT
, IOUT <0A
TJTAPTOT
JA
+=
2018-2019 Microchip Technology Inc. DS20006129B-page 35
MCP6C02
4.2 Overview of Zero-Drift Operation
Figure 4-4 shows a diagram of the MCP6C02; It explains how slow voltage errors at the input are reduced in this
architecture (much better VOS, TC1 TC2, CMRR, CMRR2, PSRR and 1/f noise).
FIGURE 4-4: MCP6C02 Block Diagram.
4.2.1 BUILDING BLOCKS
The Main Amplifiers (GM1 and GM2) are designed for
high gain and bandwidth, with a differential topology.
The main input pairs (+ and - pins at the top left) are for
the higher frequency portion of the input signal. The
auxiliary input pairs (+ and - pins at the bottom left) are
for the low frequency and high precision portion of the
input signal and correct the input offset voltage. Both
inputs are added together internally.
The Auxiliary Amplifiers (GA1 and GA2), the Chopper
Input Switches and the Chopper Output Switches
provide a high DC gain to the input signal. DC errors
are modulated to higher frequencies and white noise to
low frequencies.
The Low-Pass Filter reduces high-frequency content,
including harmonics of the Chopping Clock.
The Output Buffer (RM4) converts current to voltage,
drives the external load at VOUT and creates a negative
feedback loop through RF and RG
. RF and RG help set
the differential gain.
The Oscillator runs at fCLK = 50 kHz for the gains of 20
and 50, and at fCLK = 100 kHz for the gain of 100. fCLK
is divided by 2, to produce the Chopping Clock rate
(25 kHz and 50 kHz, respectively).
The internal LV POR (for VDD –V
SS) starts the part in a
known good state, protecting against power supply
brown-outs. The internal HV POR (for VIP –V
SS)
ensures protection of the low voltage circuitry, as well
as proper functioning.
4.2.2 CHOPPING ACTION
Figure 4-5 shows the amplifier connections for the first
phase of the Chopping Clock and Figure 4-6 shows
them for the second phase. The slow voltage errors
alternate in polarity, making the average error small.
FIGURE 4-5: First Chopping Clock Phase;
Simplified Diagram.
VIP
VIM
GM1
GA1
Chopper
Input
Switches
Chopper
Output
Switches
Low-Pass
Filter
RM4
VOUT
VREF
GM2
GA2
Chopper
Input
Switches
Chopper
Output
Switches
Low-Pass
Filter
RG
RF
EMI
Filters
DM
Clamps
EMI
Filter
VFG
VIP
VIM
GA1
Low-
Pass
Filter
VREF
VFG
GA2
Low-
Pass
Filter
MCP6C02
DS20006129B-page 36 2018-2019 Microchip Technology Inc.
FIGURE 4-6: Second Chopping Clock
Phase; Simplified Diagram.
4.2.3 FINAL TEST VS. BENCH
Due to limitations in the final test environment
(e.g., equipment accuracies, thermocouple effects
crosstalk and test time), final test measurements are
not as accurate as bench measurements. For this
reason, the input offset voltage related specifications
(VOS, TC1, TC2, ..., CMRR and PSRR) are significantly
wider than the histograms from bench measurements.
The bench results will give good guidance on how to
design your circuit. The specified limits (for final test)
give min/max limits used to screen outliers in
production.
4.2.4 INTERMODULATION DISTORTION
(IMD)
These amplifiers will show intermodulation distortion
(IMD) products when an AC signal is present.
The signal and clock can be decomposed into sine
wave tones (Fourier series components). These tones
interact with the zero-drift circuitry’s nonlinear response
to produce IMD tones at sum and difference
frequencies. Each of the square wave clock’s
harmonics has a series of IMD tones centered on it.
4.3 Protection
The MCP6C02 helps the designer provide enough
protection against undesired conditions and signals in
their environment.
4.3.1 INTERNAL PROTECTION DEVICES
All of the ESD structures clamp their inputs when they
try to go too far below VSS. Their breakdown voltage is
high enough to allow normal operation, but not low
enough to protect against slow overvoltage events.
Very fast ESD events (that meet the specification) are
limited so that damage does not occur.
The supply inputs (VIP –V
SS and VDD –V
SS) are also
connected to PORs, so that internal power up
sequencing is well controlled.
The VIP and VIM input pins have an ESD structure
designed to limit VIP –V
SS and VDM. The double
parallel diode structure that limits ESD damage through
VDM also limits VDM in other conditions.
FIGURE 4-7: Input Protection for VDM
(i.e., for VIM) and VIP –V
SS.
The VREF
, VOUT and VDD pins have ESD structures that
limit their voltages above VSS (i.e., limit VREF –V
SS,
VOUT –V
SS and VDD –V
SS).
FIGURE 4-8: Input Protection for VREF
,
VOUT and VDD.
4.3.2 PHASE REVERSAL
This part is designed to not exhibit phase inversion
when the input signals (VIP
, VDM and VREF) exceed
their specified ranges (but not their absolute ranges).
VIP
VIM
GA1
Low-
Pass
Filter
VREF
VFG
GA2
Low-
Pass
Filter
VIM
VIP
HV
ESD
HV
POR DM ESD
VSS
VREF
LV
ESD
VDD
LV
ESD
LV
POR
VOUT
LV
ESD
VSS
VSS
VSS
2018-2019 Microchip Technology Inc. DS20006129B-page 37
MCP6C02
5.0 APPLICATIONS
This chapter includes design recommendations and
typical application circuits.
The Common-mode rejection (see Figure 2-16,
Figure 2-17, Figure 2-18 and Figure 2-53) supports
applications in noisy environments. Our Current-mode
architecture gives high CMRR at higher frequencies
than was traditional (e.g., 80 dB near 80 kHz, instead
of near 60 Hz).
The power supply rejection (see Figure 2-54) also has
excellent rejection at higher frequencies than
traditional.
5.1 Recommended Design Practices
Some simple design practices help take advantage of
the MCP6C02's performance in high side current
sensing applications.
5.1.1 INPUT VOLTAGE LIMITS
To prevent damage and/or improper operation of these
amplifiers, the circuit must limit the voltages at the VIP
and VIM input pins, as well as the differential input
voltage VDM (see Section 1.1, Absolute Maximum
Ratings †). These requirements are independent of
the current limits discussed below.
The ESD protection on the VIP and VDM inputs was
discussed in Section 4.3.1, Internal Protection
Devices. This structure was chosen to protect the input
transistors against many (but not all) overvoltage
conditions, and to minimize input bias currents (IBP and
IBM).
To protect the inputs, always drive VIP with a low
impedance source and use a shunt resistor (RSH) with
low resistance (designed to not fail open). Placing
zener diode(s) or a transorb across RSH will also help
protect the inputs.
5.1.2 INPUT CURRENT LIMITS
To prevent damage to (or improper operation of) these
amplifiers, the circuit must limit the currents into the VIP
and VIM input pins (see Section 1.1, Absolute
Maximum Ratings †). This requirement is
independent of the voltage limits discussed above.
One way to ensure the input currents are limited is to
always drive VIP with a low impedance source, and to
use a shunt resistor (RSH) with low resistance
(designed to not fail open). Placing zener diode(s) or a
transorb across RSH will also help protect the inputs.
5.1.3 BYPASS CAPACITORS
Be sure to specify capacitors that will support your
application. Be sure to look at:
• Voltage Rating (well above the maximum value for
its pins)
• Dielectrics (good Temp. Cos. and reasonable Volt.
Cos.
•Size
• Surface Mount vs. Leaded
• Cost vs. availability
If possible, connect VSS to ground. This will make your
design simpler.
Bypass VIP to VSS with a local bypass capacitor next to
these pins (e.g.,10 nF). If needed, a bulk bypass
capacitor can also be added (e.g.,1 µF).
Bypass VDD to VSS with a local bypass capacitor next
to these pins (e.g.,100 nF). A bulk bypass capacitor
should also be added close by (e.g.,2.2 µF); placing it
next to the local bypass capacitor is a good choice.
5.1.4 PROTECTING THE INPUTS
Designs using the MCP6C02 will need (common)
protection methods in the circuit design. When working
on the bench, be careful to use the same protection
methods (e.g., do not hot-swap the supply voltages).
The following subsections give ideas that might be
useful in your design.
5.1.4.1 Protecting the VIP Input
Always place a bypass capacitor (CIP in Figure 5-1)
from VIP to ground. This helps protect this HV supply
input from fast glitches. A 10 nF capacitor is
reasonable for many designs.
FIGURE 5-1: Protecting VIP
.
The ∆VIP/∆t spec in Ta b l e 1 - 3 gives the maximum edge
rate that should be input to the VIP pin. Limit the source
(VS in Figure 5-1) to slower edge rates.
Limiting the current out of VS, depending on the
application, can also help protect VIP
.
VDD U1
MCP6C02
VSS
VIM
VOUT
VREF
CIP
VIP
VSRSH
Load
MCP6C02
DS20006129B-page 38 2018-2019 Microchip Technology Inc.
5.1.4.2 Protecting VDM (and VIM)
The shunt resistor (RSH in Figure 5-2 keeps VDM in
range, as long as the load current is not too high. If
extra protection is needed in your design, ideas to
consider include:
• Limiting VS's output current
• Setting VS's output ESR high enough to reduce
overshoot
- The ESR should be a dynamic resistance,
not a physical one
• Limit VDM (see Figure 5-2)
- Add anti-parallel diodes between VIP and
VIM, in case RSH fails open
- Add a capacitor between the VIP and VIM
pins
When VIP and VDM are protected, then VIM is too.
FIGURE 5-2: Protecting VDM with Diodes.
5.1.4.3 Protection for Capacitive Loads
Limiting the current from VS helps protect the circuit in
Figure 5-3. The resistance seen by VS (RVS (VS's ESR)
and RCL (CL's ESR)) helps reduce step response over-
shoot, which provides more protection. Using CSH (see
Figure 5-2) will create a voltage divider for fast edges;
be careful to limit the resulting VDM.
FIGURE 5-3: Protection for Capacitive
Loads.
5.1.4.4 Protection for Motor Loads
Limiting the current and/or edge rates from VS helps
protect the circuit in Figure 5-4. The resistance RVS
(VS's ESR) might help in some designs. The catch
diode (D1) keeps decaying motor currents near ground,
which protects the inputs.
FIGURE 5-4: Protection for Motor Loads.
5.1.5 SETTING THE VOLTAGES AT VIP
AND VIM
VIP is tied to a voltage source, to minimize glitches and
crosstalk. This part’s excellent CMRR versus
frequency helps reject Common-mode (i.e., at VIP)
noise and glitches. A local pass capacitor to VSS can
help, when the design allows it; 10 nF is usually a good
choice (see the Typical Application Circuit on Page 1).
A shunt resistor (RSH) is connected between VIP and
VIM, then to the load (which is grounded). It is selected
for the trade-off between accuracy (high RSH) and
power dissipation (low RSH). Low power dissipation
also leads to reduced size and cost. RSH also helps
protect these pins against large glitches; make sure it
will never fail open.
The bypass capacitor on VIP reduces the risk of high
overvoltage events, when the current changes abruptly
(such as an inductive load opening).
A good layout is necessary to minimize DC and AC
errors. Figure 5-5 shows a layout that minimizes input
resistances seen by IBN and IBM. The critical paths are
between RSH and the pins VIP and VIM (RWIP and
RWIM).
FIGURE 5-5: PCB Layout for RSH
(connections to VIP and VIM).
For accuracy, the wiring resistances at the device
inputs need to be small:
VDD U1
MCP6C02
VIM
VOUT
RSH
VIP
D2
D1CSH
CVIP
VDD U1
MCP6C02
VIM
VOUT
CIP
VIP
VS
RSH
CL
RCL
RVS
VDD U1
MCP6C02
VIM
VOUT
CIP
VIP
VS
RSH
Motor
RVS
D1
Pin VIM
(trace = RWIM)
Pin VIP
tracetoV
HV
RSH
tracetoload
(trace = RWIP)
2018-2019 Microchip Technology Inc. DS20006129B-page 39
MCP6C02
EQUATION 5-1:
5.1.6 SETTING THE VOLTAGE AT VREF
For designs with VREF =V
SS, short the VREF and VSS
pins together; connect them to ground (or other
reference) using one low impedance via (or trace). This
minimizes DC and AC errors.
For designs with VREF ≥VSS + 0.1V, connect VREF and
VSS with a relatively large capacitor. Since VREF needs
a low impedance source, we recommend the following
two design approaches.
The DC resistance seen at VREF needs to be small.
This resistance includes trace resistance, via
resistance and output resistance of any driving
amplifiers. For good gain error in the signal band,
maintain this resistance in that band.
EQUATION 5-2:
The AC impedance seen at VREF needs to support
stability at frequencies near the bandwidth. See
Section 5.1.8.1, Driving VREF for more information.
Figure 5-6 shorts VREF and VSS together. The ADC
connects its negative input to VREF
, so it can reject
glitches on VSS and VREF (notice only one connection
to VSS is shown, for good precision).
FIGURE 5-6: VREF Bypass Circuit #1.
Figure 5-7 uses an IC VREF to generate VREF –V
SS,
an R-C low-pass filter to reject fast glitches seen at
VREF –V
SS and an op amp buffer (≥1MHz) to drive
VREF with a low impedance source (see Equation 1-2)
(notice only one connection to VSS is shown, for good
precision).
FIGURE 5-7: VREF Bypass Circuit #2.
Driving the VREF pin instead with a simple divider and
capacitor will cause potential issues. The equivalent
resistance needs to be low (see Equation 5-2), so the
divider will draw a lot of current. The capacitor will need
to be large, to set a reasonable pole, increasing cost
and PCB space.
We strongly recommend against designs with
VSS <V
REF <V
SS + 0.1V, since AC glitches may
become an problem.
5.1.7 TEMPERATURE RISE
Make sure that TJ does not exceed the Absolute
Maximum Junction Temperature spec (see
Section 1.1, Absolute Maximum Ratings †). This is a
strong concern when TA is high (e.g., above 125°C),
when IOUT’s magnitude is large (e.g., near the short
circuit limit) or when VIP is high.
Formulas needed for this part of the design are found
in Section 4.1.5, Temperature Performance.
Figure 2-64 shows that temperature ramp rates need to
be limited, for best performance. The decay rates
shown there are limited by the PCB and other
components.
5.1.8 ENSURING STABILITY
A few simple design techniques will help take
advantage of these stable parts. Simulations and
bench measurements help to verify the solutions (e.g.,
look at step response overshoot and ringing).
RWIP ≤4mΩ
RWIM ≤0.1Ω
RWR ≤1Ω
U1
MCP6C02
V
IM
Use when V
REF
=V
SS
=GND
V
OUT
U2 (ADC)
MCP3xxx
R
RC
C
VIP
V
DD
C
VDD
V
IP
U1
MCP6C02
VIM
Use when VREF ≥0.1V
VOUT
U2 (ADC)
MCP3xxx
R
RC
CVIP
VDD
CVDD
VIP
RR
CR
VREF
VDD
CREF
VDD
CBUF
MCP6C02
DS20006129B-page 40 2018-2019 Microchip Technology Inc.
5.1.8.1 Driving VREF
The voltage source driving the VREF pin must be low
impedance (see Equation 1-2), so that the signal gain
is constant within the signal bandwidth.
When the frequency is near the bandwidth (e.g.,
between BW/4 and 4 BW), the source’s impedance
magnitude should be below 50Ω.
5.1.8.2 Source Impedances
The recommended DC source resistances (at VIP
, VIM
and VREF; see Equation 5-2) will help ensure stability,
by keeping R-C time constants very fast.
5.1.8.3 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage amplifiers. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth
reduces. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. Lower gains (GDM) exhibit greater sensitivity
to capacitive loads.
When driving large capacitive loads with these parts
(e.g., > 80 pF), a small series resistor at the output
(RISO in Figure 5-8) improves the feedback loop’s
phase margin (stability) by making the output load
resistive at higher frequencies. The bandwidth will be
generally lower than the bandwidth with no capacitive
load.
FIGURE 5-8: Recommended RISO Values
for Capacitive Loads.
Figure 5-9 shows the typical responses versus CL,
when RISO is a short circuit (also see Figure 2-70 to
Figure 2-73).
Figure 5-10 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
load capacitance (CL).
After selecting RISO for the circuit, double check the
resulting frequency response peaking and step
response overshoot on the bench. Modify RISO’s value
until the response is reasonable.
FIGURE 5-9: Bandwidth and Gain
Peaking vs. Capacitive Load, without RISO.
FIGURE 5-10: Recommended RISO vs.
Capacitive Load.
5.1.9 NOISE DESIGN
As shown in Figure 2-58 and Tabl e 1 -3 , the input noise
voltage density is white (and low) at low frequencies.
This supports accurate averages (DC estimates) in
applications.
1/f noise is negligible for almost all applications. As a
result, the time domain data in Figure 2-61, Figure 2-62
and Figure 2-63 is well behaved.
Figure 2-58 also shows a curve of the Integrated Input
Noise Voltage (Eni, in units of VRMS) between 0 Hz and
f (between 0.1 Hz and 100 kHz). To estimate Eni
between the frequencies f1 and f2, simply take the RMS
difference (i.e., Eni |f1 to f2 =sqrt(Eni22–E
ni12)).
The Input Noise Voltage Density (eni) changes with
VDM; however, that it is a weak relationship, so it can be
neglected in designs.
Figure 5-11 and Figure 5-12 show the device noise as
a Signal-to-Noise ratio (SNR), assuming the signal is a
full-scale sine wave (at VOUT). The x-axis is the circuit’s
bandwidth (BW), to make it easy to evaluate a
particular design.
The input offset voltage is shown as a Signal-to-Offset
ratio (SVosR), to indicate where the DC offset
dominates the error.
U1
MCP6C02
VIM
VOUT
RISO
CL
CVIP
VDD
CVDD
VIP








( ( ( ( ( (
%DQGZLGWK%:N+]
*DLQ3HDNLQJ*3.G%
&DSDFLWLYH/RDG&/)
5,62 
*'0 
*'0 
*'0 
*3.± 6ROLG/LQHV
%:± 'DVKHG/LQHV
QQQSSS
1.E+01
1.E+02
1.E+03
1.E+04
1.E-11 1.E-10 1.E-09 1.E-08
1.E-07
Recommended R
ISO
(Ω)
Capacitive Load; CL(F)
10p
100p 1n 10n
100n
GDM = 100
GDM = 50
GDM = 20
10k
1k
100
10
2018-2019 Microchip Technology Inc. DS20006129B-page 41
MCP6C02
FIGURE 5-11: SNR vs. Bandwidth
Estimates, VDD =2.0V.
FIGURE 5-12: SNR vs. Bandwidth
Estimates, VDD =5.5V.
5.1.10 UNIDIRECTIONAL APPLICATIONS
In unidirectional applications where VREF =V
SS, it is
important to minimize output headroom (VOL). The
lower VOL is, the more accurate the zero scale reading
is.
To reduce VOL, make IOUT as low as possible. This is
done by making RL high and by tying VL to VSS.
Figure 5-6 shows how to connect VREF and VSS for
best performance.
5.1.11 BIDIRECTIONAL APPLICATIONS
Figure 5-7 shows ways to connect VREF and VSS for
best performance.
To maximize headroom, reduce VOL and VOH by
setting RL high.
5.1.12 SUPPLY PINS
As described in Section 3.5 “Low-Side Power
Supplies (VDD, VSS)”, the ground potential (GND)
can be set where needed in your design. The most
common design approach has VSS = GND (positive
single supply). Other common design approaches
have VDD = GND (negative single supply) or
VSS <GND<V
DD (dual, or split, supplies).
Setting VSS = GND has the potential to increase
rejection of crosstalk and glitches. In any case, a good
ground design (e.g., ground plane on a PCB) and
appropriate bypass capacitors are needed to realize
these benefits. It pays to be sure that your capacitor's
voltage rating and dielectric will support your needs
over your voltage and temperature ranges. With some
dielectrics, it pays to also take aging (changes over
time) into account too.
5.2 Typical Application Circuits
The following circuits give guidance on using the
MCP6C02 within common applications. They leave out
details and the design requirements followed.
5.2.1 MOTOR CURRENT MONITORS
Figure 5-13 shows a simplified DC Motor Current
Monitor circuit with a regulated voltage supply. The
MCP6C02 and its circuit are all connected to the same
ground, for better glitch performance. In this case,
since IL is non-negative, we choose VREF =V
SS.
The ADC operates on a different supply; its ground will
be different due to I-R drops and glitches. The
differential input is tied to VREF
, so that its CMRR can
reject differences between grounds.
FIGURE 5-13: Motor Current Monitor for
Regulated Supply Voltage.
H-Bridge motor drive circuits can place their current
monitors in several positions. Figure 5-14 shows a few
possibilities:
• Position A – This uses a unidirectional monitor
(MCP6C02 at VA1 and VA2), with current polarity
determined by the timing of the switches (SWLT,
50
60
70
80
90
100
110
120
130
1.E+0 1.E+1 1.E+2 1.E+3 1.E+4
1.E+5
SNR and SVosR (dB)
Bandwidth; f (Hz)
G
DM
= 20
G
DM = 50
G
DM
= 100
VDD = 2.0V
Dashed Lines = SVosR
Solid Lines = SNR
1 10 100 1k 10k
100k
50
60
70
80
90
100
110
120
130
1.E+0 1.E+1 1.E+2 1.E+3 1.E+4
1.E+5
SNR and SVosR (dB)
Bandwidth; f (Hz)
G
DM
= 20
G
DM = 50
GDM = 100
VDD = 5.5V
Dashed Lines = SVosR
Solid Lines = SNR
1 10 100 1k 10k
100k
2.2 µF
U1
MCP6C02-100
100 nF
+5V
RSH
IL<20A
20 kΩ
2.2 mΩ
+48V
U2 (ADC)
MCP3xxx
2.2 µF
100 nF
+5V
R
R
C
VOUT
VOUT
VREF
10 nF
VREF
MCP6C02
DS20006129B-page 42 2018-2019 Microchip Technology Inc.
etc.)
• Positions B and C – This uses two unidirectional
monitors (on MCP6C02 at VB1 and VB2 and the
other at VC1 and VC2), with each one representing
one current polarity
• Position D – This uses a bidirectional monitor
(MCP6C02 at VD1 and VD2), with current polarity
determined by the output
- The monitor must function at and below
ground
- The monitor must withstand large switching
steps and glitches
- We caution that the MCP6C02 should not be
used in these conditions.
Obviously, choosing different locations for the
monitor(s) gives trade-offs in accuracy and complexity.
For instance, the monitor at Position D directly
measures the motor current, but will have large voltage
swings at its VIP pin.
The switches are discrete semiconductor switches
(i.e., CMOS, Bipolar, IGFET, etc.).
FIGURE 5-14: H-Bridge Motor Current
Monitor, With a Few Possible Monitor Locations.
5.2.2 ANALOG LEVEL SHIFTER
The MCP6C02 can be used to shift analog voltages
from a high positive voltage down to a low voltage.
Many possibilities exit; Figure 5-15 is just one possible
implementation.
The input attenuator (R1 and R2) allow a wider range of
voltages to be measured. No resistor is placed
between V1 and the noninverting input, so that the input
current IBP doesn’t cause an offset shift. The attenuator
resistors' accuracy and values may affect the circuit's
gain error and offset.
The +2.5V reference level allows bidirectional voltage
sensing; it needs to be very low impedance and reject
glitches on the supply or ground (see Figure 5-7 for
recommendations on this part of the circuit).
FIGURE 5-15: Analog Level Shifter.
RD
VD1 VD2
SWRT
SWRB
SWLT
SWLB
RC
VC2
VC1
RB
VB2
VB1
RA
VA2
VA1
IBIC
IA
ID
VHV
2.2 µF
U1
MCP6C02
100 nF
+5V
R1
100 kΩ
V1
U2
MCP3xxx
2.2 µF
100 nF
+5V
R
RC
V2
R2
VOUT
+2.5V
VOUT
+2.5V
10 nF
2018-2019 Microchip Technology Inc. DS20006129B-page 43
MCP6C02
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
Legend: XX...X Device-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available charac-
ters for customer-specific information.
3
e
3
e
6-Lead SOT-23 Example
Part Number Code
MCP6C02T-020E/CHY 22
MCP6C02T-050E/CHY 25
MCP6C02T-100E/CHY 21
MCP6C02T-020E/CHYVAO 22
MCP6C02T-050E/CHYVAO 25
MCP6C02T-100E/CHYVAO 21
2247
Part Number Code
MCP6C02T-020H/Q8B 220
MCP6C02T-050H/Q8B 250
MCP6C02T-100H/Q8B 2100
MCP6C02T-020H/Q8BVAO 220
MCP6C02T-050H/Q8BVAO 250
MCP6C02T-100H/Q8BVAO 2100
8-Lead VDFN Example
220
1922
256
MCP6C02
DS20006129B-page 44 2018-2019 Microchip Technology Inc.
B
A
0.15 C A-B
0.15 C D
0.20 C A-B D
2X
TOP VIEW
SIDE VIEW
END VIEW
0.10 C
Microchip Technology Drawing C04-028C (CH) Sheet 1 of 2
2X
6X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]
D
EE1
e
e1
6X b
E
2
E1
2
D
AA2
A1
L2
Ĭ
L
(L1)
R
R1
c
0.20 C A-B
2X
C
SEATING PLANE
GAUGE PLANE
2018-2019 Microchip Technology Inc. DS20006129B-page 45
MCP6C02
Microchip Technology Drawing C04-028C (CH) Sheet 2 of 2
6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
protrusions shall not exceed 0.25mm per side.
1.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2.
Notes:
REF: Reference Dimension, usually without tolerance, for information purposes only.
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
Dimensioning and tolerancing per ASME Y14.5M
Foot Angle
Number of Leads
Pitch
Outside lead pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
Footprint
Lead Thickness
Lead Width
L1
φ
b
c
Dimension Limits
E
E1
D
L
e1
A
A2
A1
Units
N
e
0°
0.08
0.20 -
-
-
10°
0.26
0.51
MILLIMETERS
0.95 BSC
1.90 BSC
0.30
0.90
0.89
0.00
0.60 REF
2.90 BSC
0.45
2.80 BSC
1.60 BSC
1.15
-
-
MIN
6
NOM
1.45
1.30
0.15
0.60
MAX
Seating Plane to Gauge Plane L1 0.25 BSC
MCP6C02
DS20006129B-page 46 2018-2019 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
Microchip Technology Drawing No. C04-2028B (CH)
6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Dimension Limits
Contact Pad Length (X3)
Overall Width
Distance Between Pads
Contact Pad Width (X3)
Contact Pitch
Contact Pad Spacing
3.90
1.10
G
Z
Y
1.70
0.60
MAXMIN
C
X
E
Units
NOM
0.95 BSC
2.80
MILLIMETERS
Distance Between Pads GX 0.35
E
X
GX
Y
GC
Z
SILK SCREEN
G
2018-2019 Microchip Technology Inc. DS20006129B-page 47
MCP6C02
B
A
0.10 C
0.10 C
0.10 C A B
0.05 C
(DATUM B)
(DATUM A)
C
SEATING
PLANE
12
N
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.10 C A B
0.10 C A B
0.10 C
0.08 C
Microchip Technology Drawing C04-21358 Rev B Sheet 1 of 2
2X
8X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN]
With 2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks
D
E
NOTE 1
(A3)
AA1
12
N
D2
E2
NOTE 1
L
K
e
8X b
A
A
MCP6C02
DS20006129B-page 48 2018-2019 Microchip Technology Inc.
Microchip Technology Drawing C04-21358 Rev B Sheet 2 of 2
Number of Terminals
Overall Height
Terminal Width
Overall Width
Terminal Length
Exposed Pad Width
Terminal Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
b
E2
A3
e
L
E
N
0.65 BSC
0.203 REF
1.50
0.35
0.25
0.80
0.00
0.30
0.40
1.60
0.85
0.03
3.00 BSC
MILLIMETERS
MIN NOM
8
1.70
0.45
0.35
0.90
0.05
MAX
K-0.20 -
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated
Dimensioning and tolerancing per ASME Y14.5M
Terminal-to-Exposed-Pad
8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
With 2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks
Overall Length
Exposed Pad Length
D
D2 2.30
3.00 BSC
2.40 2.50
A4
E3
SECTION A–A
PARTIALLY
PLATED
Wettable Flank Step Cut Depth A4 0.10 0.13 0.15
E3 --0.04Wettable Flank Step Cut Width
2018-2019 Microchip Technology Inc. DS20006129B-page 49
MCP6C02
RECOMMENDED LAND PATTERN
Dimension Limits
Units
Optional Center Pad Width
Optional Center Pad Length
Contact Pitch
Y2
X2
2.50
1.70
MILLIMETERS
0.65 BSC
MIN
E
MAX
Contact Pad Length (X8)
Contact Pad Width (X8)
Y1
X1
0.80
0.35
Microchip Technology Drawing C04-23358 Rev B
NOM
8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN]
12
8
CContact Pad Spacing 3.00
Contact Pad to Center Pad (X8) G1 0.20
Thermal Via Diameter V
Thermal Via Pitch EV
0.33
1.20
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M
For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
1.
2.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
With 2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks
C
E
X1
Y1
Y2
EV
ØV
G1
SILK SCREEN
EVX2
Pin 1 Index Chamfer CH 0.20
Contact Pad to Contact Pad (X6) G2 0.20
G2
CH
MCP6C02
DS20006129B-page 50 2018-2019 Microchip Technology Inc.
NOTES:
2018-2019 Microchip Technology Inc. DS20006129B-page 51
MCP6C02
APPENDIX A: REVISION HISTORY
Revision B (September 2019)
The following is the list of modifications.
1. Added the H-Temp part in an 8 lead 3 × 3 VDFN
package.
2. Clarified specifications, timing diagrams and
power calculations.
3. Added discussion on circuit protection.
Revision A (November 2018)
• Initial release of this document.
2018-2019 Microchip Technology Inc. DS20006129B-page 52
MCP6C02
NOTES:
2018-2019 Microchip Technology Inc. DS20006129B-page 53
MCP6C02
APPENDIX B: OFFSET TEST
SCREENS
Input offset voltage specifications in the DC spec table
(Ta b l e 1 - 1 ) are based on bench measurements (see
Section 2.1, DC Precision). These measurements are
much more accurate than at test, because:
• More compact circuit
• Parts soldered on the PCB
• More time spent averaging (reduced noise)
• Better temperature control
- Reduced temperature gradients
- Greater accuracy
We use production screens to support the quality of our
VOS specification in outgoing products. The screen
limits are wider and are used to eliminate fliers; see
Table B-1.
TABLE B-1: OFFSET TEST SCREENS
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 34V,
VDM =0V, V
REF =V
DD/4, VL=V
DD/2 and RL=10 k to VL; see Figure 1-9 and Figure 1-10.
Parameters Sym. Min. Max. Units Gain Conditions
input Offset Voltage VOS -34 +34 μV20Test Screen
-24 +24 50
-20 +20 100
2018-2019 Microchip Technology Inc. DS20006129B-page 54
MCP6C02
NOTES:
2018-2019 Microchip Technology Inc. DS20006129B-page 55
MCP6C02
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X(2) /XXX(2)
Package
Temperature
Range
Device
Examples:
a) MCP6C02T-020E/CHY: Tape and Reel,
Differential Gain = 20,
Extended Temperature,
6LD SOT-23
b) MCP6C02T-050E/CHY: Tape and Reel,
Differential Gain = 50,
Extended Temperature,
6LD SOT-23
c) MCP6C02T-100E/CHY: Tape and Reel,
Differential Gain = 100,
Extended Temperature,
6LD SOT-23
d) MCP6C02T-020H/Q8B: Tape and Reel,
Differential Gain = 20,
High Temperature,
8LD VDFN
e) MCP6C02T-050H/Q8B: Tape and Reel,
Differential Gain = 50,
High Temperature,
8LD VDFN
f) MCP6C02T-100H/Q8B: Tape and Reel,
Differential Gain = 100,
High Temperature,
8LD VDFN
g) MCP6C02T-020E/CHYVAO: Automotive,
Tape and Reel,
Differential Gain = 20,
Extended Temperature,
6LD SOT-23
h) MCP6C02T-050E/CHYVAO: Automotive,
Tape and Reel,
Differential Gain = 50,
Extended Temperature,
6LD SOT-23
i) MCP6C02T-100E/CHYVAO: Automotive,
Tape and Reel,
Differential Gain = 100,
Extended Temperature,
6LD SOT-23
j) MCP6C02T-020H/Q8BVAO: Automotive,
Tape and Reel,
Differential Gain = 20,
High Temperature,
8LD VDFN
k) MCP6C02T-050H/Q8BVAO: Automotive,
Tape and Reel,
Differential Gain = 50,
High Temperature,
8LD VDFN
l) MCP6C02T-100H/Q8BVAO: Automotive,
Tape and Reel,
Differential Gain = 100,
High Temperature,
8LD VDFN
Note 1: Tape and Reel identifier only appears in the
catalog part number description. This identifier is
used for ordering purposes and is not printed on
the device package. Check with your Microchip
Sales Office for package availability with the Tape
and Reel option.
2: E-Temp parts are only in the SOT-23 package. H-
Temp parts are only in the 3×3 VDFN package.
3: Automotive parts are AEC-Q100 qualified. SOT-
23 packaged parts are Grade 1 and VDFN
packaged parts are Grade 0.
[X](1)
Tape and Reel
Option
-XXX
Gain Option
XXX(3)
Class
Device: MCP6C02: Zero-Drift, 65V High-Side Current Sense Amp
Tape and Re el
Option:
T = Tape and Reel(1)
Gain Option: 020 = Differential Gain of 20 V/V
050 = Differential Gain of 50 V/V
100 = Differential Gain of 100 V/V
Temperature
Range:
E= -40C to +125C(2) (Extended)
H= -40C to +150C(2) (High)
Package: CHY = Plastic Small Outline Transistor (SOT-23(2)), 6-Lead
Q8B = Very Thin Plastic Dual Flat Outline (3x3 VDFN(2)),
8-Lead
Class: (Blank) = Non-Automotive
VAO = Au tom ot iv e
MCP6C02
DS20006129B-page 56 2018-2019 Microchip Technology Inc.
NOTES:
2018-2019 Microchip Technology Inc. DS20006129B-page 57
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-4984-3
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
DS20006129B-page 58 2018-2019 Microchip Technology Inc.
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05/14/19