Z9972AA - Cypress Semiconductor Corp.

Z9972

Low Voltage Clock Distribution Buffer/Driver

Preliminary

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.0 4/20/2000

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 1 of 10

http://www.imicorp.com

Product Features

• Output Frequency up to 125MHz

• Supports PowerPCTM, and PentiumTM Processors

• 12 Clock Outputs: Frequency Configurable

• Configurable Output Disable

• Two Reference Clock Inputs for Dynamic Toggling

• Oscillator or Crystal Reference Input

• +/- 100 ps Cycle-to-Cycle Jitter

• Glitch-free Output Clocks Transitioning

• 3.3V Power Supply

• Pin Compatible with MPC972

• 52-Pin TQFP Package

Block Diagram

Frequency Table *

VCO_SEL FB_SEL2 FB_SEL1 FB_SEL0 FVCO

00008x

000112x

001016x

001120x

010016x

010124x

011032x

011140x

10004x

10016x

10108x

101110x

11008x

110112x

111016x

111120x

Table 1

* x = the reference input frequency, 200MHz < FVCO <

480MHz.

Pin Configuration

VSS

MR#/OE

SCLK

SDATA

FB_SEL2

PLL_EN

REF_SEL

TCLK_SEL

TCLK0

TCLK1

XIN

XOUT

VDD

FB_SEL1

SYNC

VSS

QC0

VDDC

QC1

SELC0

SELC1

QC2

VDDC

QC3

VSS

INV_CLK

SELB1

SELB0

SELA1

SELA0

QA3

VDDC

QA2

VSS

QA1

VDDC

QA0

VSS

VCO_SEL

VSS

QB0

VDDC

QB1

VSS

QB2

VDDC

QB3

FB_IN

VSS

FB_OUT

VDDC

FB_SEL0

14 15 16 17 18 19 20 21 22 23 24 25 26

52 51 50 49 48 47 46 45 44 43 42 41 40

Z9972

REF_SEL

Phase

Detector VCO

LPF

Sync

Frz

DQQA0

Sync

Frz

Sync

Frz

Sync

Frz

Sync

Frz

Sync

Frz

Power-On

Reset

Output Disable

Circuitry

Data Generator

/4, /6, /8, /12

/4, /6, /8, /10

/2, /4, /6, /8

/4, /6, /8, /10

Sync Pulse

XIN

XOUT

TCLK0

TCLK1

TCLK_SEL

FB_IN

FB_SEL2

MR#/OE

SELA(0,1) 2

SELB(0,1) 2

SELC(0,1) 2

FB_SEL(0,1) 2

SCLK

SDATA

INV_CLK

QA1

QA2

QA3

QB0

QB1

QB2

QB3

QC0

QC1

QC2

QC3

FB_OUT

SYNC

VCO_SEL

PLL_EN

Z9972

Low Voltage Clock Distribution Buffer/Driver

Preliminary

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.0 4/20/2000

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 2 of 10

http://www.imicorp.com

Pin Description

PIN NAME PWR I/O TYPE Description

11 XIN I Oscillator Input. Connect to a crystal.

12 XOUT O Oscillator Output. Connect to a crystal.

9TCLK0 I PU External Reference/Test Clock Input.

10 TCLK1 I PU External Reference/Test Clock Input.

44, 46, 48, 50 QA(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections.

32, 34, 36, 38 QB(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections.

16, 18, 21, 23 QC(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections.

29 FB_OUT VDDC O Feedback Clock Output. Connect to FB_IN for normal operation. The

divider ratio for this output is set by FB_SEL(0:2). See Frequency

Table. A bypass delay capacitor at this output will control Input

Reference/ Output Banks phase relationships.

25 SYNC VDDC O Synchronous Pulse Output. This output is used for system

synchronization. The rising edge of the output pulse is in sync with

both the rising edges of QA (0:3) and QC(0:3) output clocks

regardless of the divider ratios selected.

42, 43 SELA(1,0) IPU

Frequency Select Inputs. These inputs select the divider ratio at

QA(0:3) outputs. See Table 2

40, 41 SELB(1,0) IPU

Frequency Select Inputs. These inputs select the divider ratio at

QB(0:3) outputs. See Table 2

19, 20 SELC(1,0) IPU

Frequency Select Inputs. These inputs select the divider ratio at

QC(0:3) outputs. See Table 2

5, 26, 27 FB_SEL(2:0) IPU

Feedback Select Inputs. These inputs select the divide ratio at

FB_OUT output. See Table 1

52 VCO_SEL IPU

VCO Divider Select Input. W hen set low, the VCO output is divided

by 2. When set high, the divider is bypassed. See Table 1

31 FB_IN I PU Feedback Clock Input. Connect to FB_OUT for accessing the PLL.

6PLL_EN IPU

PLL Enable Input. When asserted high, PLL is enabled. And when

low, PLL is bypassed.

7REF_SEL IPU

Reference Select Input. When high, the crystal oscillator is selected.

And when low, TCLK (0,1) is the reference clock.

8TCLK_SEL IPU

TCLK Select Input. When low, TCLK0 is selected and when high

TCLK1 is selected.

2MR#/OE IPU

Master Reset/Output Enable Input. When asserted low, resets all of

the internal flip-flops and also disables all of the outputs. When pulled

high, releases the internal flip-flops from reset and enables all of the

outputs.

14 INV_CLK IPU

Inverted Clock Input. When set high, QC(2,3) outputs are inverted.

When set low, the inverter is bypassed.

3SCLK I PU Serial Clock Input. Clocks data at SDATA into the internal register.

4SDATA IPU

Serial Data Input. Input data is clocked to the internal register to

enable/disable individual outputs. This provides flexibility in power

management.

17, 22, 28,

33,37, 45, 49 VDDC 3.3V Power Supply for Output Clock Buffers.

13 VDD 3.3V Supply for PLL

1, 15, 24, 30,

35, 39, 47, 51 VSS Common Ground

A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass

capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of

the traces.

Z9972

Low Voltage Clock Distribution Buffer/Driver

Preliminary

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.0 4/20/2000

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 3 of 10

http://www.imicorp.com

Maximum Ratings

Input Voltage Relative to VSS: VSS-0.3V

Input Voltage Relative to VDD: VDD+0.3V

Storage Temperature: -65°C to + 150°C

Operating Temperature: 0°C to +70°C

Maximum Power Supply: 5.5V

This device contains circuitry to protect the inputs

against damage due to high static voltages or electric

field; however, precautions should be taken to avoid

application of any voltage higher than the maximum

rated voltages to this circuit. For proper operation, Vin

and Vout should be constrained to the range:

VSS<(Vin or Vout)<VDD

Unused inputs must always be tied to an appropriate

logic voltage level (either VSS or VDD).

DC Parameters

Characteristic Symbol Min Typ Max Units Conditions

Input Low Voltage VIL VSS - 0.8 V

Input High Voltage VIH 2.0 - VDD V

Input Low Current ( @ VIL = VSS) IIL - -120 µA

Input High Current ( @ VIH = VDD) IIH 10 µA

Output Low Voltage VOL 0.5 V IOL = 20mA, Note 1

Output High Voltage VOH 2.4 V IOH = -20mA, Note 1

Dynamic Supply Current IDDC - 190 215 mA All VDDC and VDD

PLL Supply Current IDD 15 20 mA VDD only

Input Pin Capacitance Cin - - 4 pF

VDD = VDDC =3.3V + 5%, TA = 0°C to +70°C

Note 1: Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.

Note 2: Inputs have pull-up resistors which affect input current.

Z9972

Low Voltage Clock Distribution Buffer/Driver

Preliminary

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.0 4/20/2000

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 4 of 10

http://www.imicorp.com

AC Parameters1

SYMBOL PARAMETER MIN TYP MAX UNITS CONDITIONS

Tr / Tf TCLK Input Rise / Fall 3.0 ns

Fref Reference Input Frequency Note 2 Note 2 MHz

Fxtal Crystal Oscillator Frequency 10 25 MHz See Table 3 for

details

FrefDC Reference Input Duty Cycle 25 75 %

Fvco PLL VCO Lock Range 200 480 MHz

Tlock Maximum PLL lock Time 10 ms

Tr / Tf Output Clocks Rise / Fall Time30.15 1.2 ns 0.8V to 2.0V

- 125 MHz Q (÷2)

120 Q (÷4)

80 Q (÷6)

Fout Maximum Output Frequency

60 Q (÷8)

FoutDC Output Duty Cycle3TCYCLE/2 –

750 TCYCLE/2 +

750 ps

tpZL,

tpZH Output Enable Time3

(all outputs) 210ns

tpLZ,

tpHZ Output Disable Time3

(all outputs) 28ns

TCCJ Cycle to Cycle Jitter3

(peak to peak) +/- 100 ps

TSKEW Any Output to Any Output

Skew3,4 550 ps

TCLK0 -270 130 530Tpd Propagation Delay4,5

TCLK1 -330 70 470 ps QFB =(÷8)

VDD = VDDC = 3.3V +/- 5%, TA = 0°C to +70°C

Note 1: Parameters are guaranteed by design and characterization. Not 100% tested in production.

Note 2: Maximum and minimum input reference is limited by VCO lock range.

Note 3: Outputs loaded with 30pF each.

Note 4: 50Ω transmission line terminated into VDDC/2.

Note 5: Tpd is specified for a 50MHz input reference. Tpd does not include jitter.

Z9972

Low Voltage Clock Distribution Buffer/Driver

Preliminary

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.0 4/20/2000

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 5 of 10

http://www.imicorp.com

Description

The Z9972 has an integrated PLL that provides low skew and low jitter clock outputs for high performance

microprocessors. Three independent banks of four outputs as well as an independent PLL feedback output, FB_OUT,

provide exceptional f lexibility for possible output c onfigurations . T he PLL is ensur ed stable operation given that the VCO

is configured to run between 200 MHz to 480 MHz. This allows a wide range of output frequencies up to125MHz.

The phase detector compares the input reference clock to the external feedback input. For normal operation, the

external f eedback input, FB_IN, is connec ted to the feedbac k output, FB_OUT . T he inter nal VCO is running at m ultiples

of the input reference clock set by FB_SEL(0:2) and VCO_SEL select inputs, refer to Frequency Table. The VCO

frequency is then divided down to provide the required output frequencies. These dividers are set by SELA(0,1),

SELB(0,1), SELC(0,1) select inputs, see table 2 below. For situations were the VCO needs to run at relatively low

frequencies and hence might not be stable, assert VCO_SEL low to divide the VCO frequency by 2. This will maintain

the desired output relationships, but will provide an enhanced PLL lock range.

The Z9972 is also capable of providing inverted output clocks. W hen INV_CLK is asserted high, QC2 and QC3 output

clock s are inver ted. Thes e clock s could be used as feedbac k outputs to the Z9972 or a second PLL devic e to generate

early or late clocks for a specific design. This inversion does not affect the output to output skew.

SELA1 SELA0 QA SELB1 SELB0 QB SELC1 SELC0 QC

12 11

10 11

Table 2

Glitch-Free Output Frequency Transitions

Customarily w hen output buffers have their internal counter’s changed “on the fly’ their output clock periods will:

A. Contain short or “runt” clock periods. These are clock cycles in which the cycle(s) are shorter in period than either

the old or new frequency that is being transitioned to.

B. Contain stretched clock periods. These are clock cycles in which the cycle(s) are longer in period than either the old

or new frequency that is being transitioned to.

This device specifically includes logic to guarantee that runt and stretched clock pulses do not occur if the device logic

levels of any or all of the following pins changed “on the fly” while it is operating: SELA, SELB, SELC, and VCO_SEL.

Z9972

Low Voltage Clock Distribution Buffer/Driver

Preliminary

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.0 4/20/2000

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 6 of 10

http://www.imicorp.com

SYNC Output

In situations were output frequency relationships are not integer multiples of each other the SYNC output provides a

signal for system synchronization. The Z9972 monitors the relationship between the QA and the QC output clocks. It

provides a low going pulse, one period in duration, one period prior to the coincident rising edges of the QA and QC

outputs. The duration and the placement of the pulse depend on the higher of the QA and QC output frequencies. The

following timing diagram illustrates various waveform s for the SYNC output. Note that the SYNC output is defined f or all

possible combinations of the QA and Q C outputs even though under s ome relations hips the lower f requenc y clock c ould

be used as a synchronizing signal.

SYNC

VCO

1:1 Mode

2:1 Mode

3:1 Mode

3:2 Mode

4:1 Mode

4:3 Mode

6:1 Mode

Z9972

Low Voltage Clock Distribution Buffer/Driver

Preliminary

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.0 4/20/2000

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 7 of 10

http://www.imicorp.com

Pow e r Management

The individual output enable / freeze control of the Z9972 allows the user to implement unique power management

schemes into the design. The outputs are stopped in the logic ‘0’ state when the freeze control bits are activated. The

serial input register contains one programm able freeze enable bit for 12 of the 14 output clock s. T he QC0 and FB_OUT

outputs can not be frozen with the serial port, this avoids any potential lock up situation should an error occur in the

loading of the serial data. An output is frozen when a logic ‘0’ is programmed and enabled when a logic ‘1’ is written. The

enabling and freezing of individual outputs is done in such a manner as to eliminate the possibility of partial “runt” clocks.

The serial input register is programmed through the SDATA input by writing a logic ‘0’ start bit followed by 12 NRZ freeze

enable bits. The period of each SDATA bit equals the period of the fr ee running SCLK s ignal. T he SDATA is s ampled on

the rising edge of SCLK.

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11

D0-D3 are the control bits for QA0-QA3, respectively

D4-D7 are the control bits for QB0-QB3, respectively

D8-D10 are the control bits for QC1-QC3, respectively

D11 is the control bit for SYNC

Start

Bit

Suggested Oscillator Crystal Parameters

Characteristic Symbol Min Typ Max Units Conditions

Frequency

Tolerance TC- - +/-100 PPM Note 1

Frequency

Temperature

Stability

TS- - +/- 100 PPM (TA -10 to +60C) Note 1

Aging TA- - 5 PPM/Yr (first 3 y ears @ 25C) Note 1

Load Capacitance CL- 20 - pF The crystal’s rated load. Note 1

Effective Series

Resistance (ESR) RESR - 40 80 Ohms Note 2

Note1: For best perf orm ance and ac curate f requenc ies f rom this devic e, It is r ecom m ended but not m andatory that the

chosen cry stal meets or exceeds these specifications

Note 2: Larger values may cause this device to exhibit oscillator startup problems

Table 3

Z9972

Low Voltage Clock Distribution Buffer/Driver

Preliminary

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.0 4/20/2000

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 8 of 10

http://www.imicorp.com

Package Drawing and Dimensions (52 TQFP)

Z9972

Low Voltage Clock Distribution Buffer/Driver

Preliminary

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.0 4/20/2000

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 9 of 10

http://www.imicorp.com

Package Drawing and Dimensions (Cont.) 52 Pin TQFP Dimensions

INCHES MILLIMETERS

SYMBOL MIN NOM MAX MIN NOM MAX

A - - 0.047 - - 1.20

A1 0.002 0.004 0.006 0.05 0.10 0.15

A2 0.037 0.039 0.041 0.95 1.00 1.05

e 0.026 BSC 0.65 BSC

D 0.472 BSC 12.00 BSC

D1 0.394 BS C 10.00 BSC

E 0. 472 BSC 12.00 BSC

E1 0.394 BSC 10.00 BSC

L 0.018 0.024 0.030 0.45 0.60 0.75

b 0.009 0.013 0.015 0.22 0.32 0.38

b1 0.009 0.012 0.013 0.22 0.30 0.33

ccc - - 0.004 - - 0.10

ddd - - 0.005 - - 0.13

Notes:

1. All dimensioning and tolerancing conform to ANSI

Y14.5-1982.

2. Datum Plane located at mold parting line

and coincident with lead. Where lead exits plastic

body at bottom of parting line.

3. Datums and to be determined at

centerline between leads where leads exit plastic

body at datum plane.

4. To be determined at seating plane

5. Dimensions D1 and E1 do not include mold

protrusion. Allowable mold protrusion is 0.254mm

on D1 and E1 dimensions.

6. “N” is the total number of terminals (in this case 52).

7. These dimensions to be determined at Datum

Plane

8. The top of package is smaller than the bottom of

package by 0.15mm.

9. A dimension “b” does not include Dambar

protrusion. Allowable Dambar protrusion shall be

0.08mm total in excess of the “b” dimension at

maximum material condition. Dambar cannot be

located on the lower radius or the foot.

10. Controlling dimension: millimeter.

11. Maximum allowable die thickness to be assembled

in this package family is 0.30mm.

12. This outline conforms to Jedec publication 95

registration MS026, variations ACB, ACC, ACD and

ACE.

13. A1 is defined as the distance from the seating plane

to the lowest point of the package body.

Z9972

Low Voltage Clock Distribution Buffer/Driver

Preliminary

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.0 4/20/2000

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 10 of 10

http://www.imicorp.com

Ordering Information

Part Number Package Type Production Flow

Z9972AA 52 TQFP Commercial, 0°C to +70°C

Note: The ordering part number is formed by a combination of device number, device revision, package style, and

screening as shown below.

Marking: Example: IMI

Z9972

Date Code, Lot #

Z9972AA

Package

A = TQFP

Revision

IMI Device Number