DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 1
© Copyright 2000–2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
Features
•One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of
Xilinx®FPGA devices
•Simple interface to the FPGA
•Cascadable for storing longer or multiple bitstreams
•Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
•Low-power CMOS floating-gate process
•3.3V supply voltage
•Guaranteed 20 year life data retention
•Available in compact plastic packages: VQ44, PC44,
PC20, VO8, and SO20(1)
•Programming support by leading programmer
manufacturers
•Design support using the ISE® Foundation™ and
ISE WebPACK™ software
•Dual configuration modes for the XC17V16 and
XC17V08(1) devices
♦Serial slow/fast configuration (up to 20 Mb/s)
♦Parallel (up to 160 Mb/s at 20 MHz)
Description
Xilinx introduces the high-density XC17V00 family of
configuration PROMs which provide an easy-to-use, cost-
effective method for storing large Xilinx FPGA configuration
bitstreams. Initial devices in the 3.3V family are available in
16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities. See Figure 1
and Figure 2 for simplified block diagrams of the XC17V00
family.
The XC17V00 PROM can configure a Xilinx FPGA using
the FPGA serial configuration mode interface. When the
FPGA is in Master Serial mode, it generates a configuration
clock that drives the PROM. A short access time after the
rising clock edge, data appears on the PROM DATA output
pin that is connected to the FPGA DIN pin. The FPGA
generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
The XC17V08(1) and XC17V16 PROM can optionally
configure a Xilinx FPGA using the FPGA Parallel
(SelectMAP) configuration mode interface. When the FPGA
is in Master SelectMAP mode, the FPGA generates the
configuration clock that drives the PROM.
When the FPGA is in Slave SelectMAP mode, an external,
free-running oscillator generates the configuration clock
that drives the PROM and the FPGA. After the rising
configuration clock (CCLK) edge, data is available on the
PROMs DATA (D0-D7) pins. The data is clocked into the
FPGA on the following rising edge of the CCLK (Figure 3).
Multiple PROMs can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx ISE Foundation or
ISE WebPACK software compiles the FPGA design file into
a standard Hex format, which is then transferred to most
commercial PROM programmers.
0
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 08 Product Specification
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1. Specific part number and package combinations have been discontinued. Refer to XCN07010. Discontinued part number and package combinations
remain in this data sheet for reference.
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 2
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X-Ref Target - Figure 1
Figure 1: Simplified Block Diagram for XC17V04, XC17V02(1), and XC17V01
(does not show programming circuit)
X-Ref Target - Figure 2
Figure 2: Simplified Block Diagram for XC17V16 and XC17V08(1)
(does not show programming circuit)
EPROM
Cell
Matrix
Address Counter
CE
DATA
OE
Output
CLK
VCC VPP GND
DS073_01_072600
TC
OE
RESET/
OE/
RESET
or
CEO
EPROM
Cell
Matrix
Address Counter
CE
D0 Data
(Serial or Parallel Mode)
OE
8
Output
CLK
BUSY
VCC VPP GND
DS073_02_031506
TC
OE
RESET/
OE/
RESET
or
D[1:7]
(SelectMAP Interface)
CEO
77
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 3
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Pin Description
DATA[0:7]
The array data value corresponding to the internal address
counter location is output on enabled DATA[0-7] output
pin(s) when CE is active, OE is active, and the internal
address counter has not incremented beyond its Terminal
Count (TC) value. Otherwise, all data pins are in a high
impedance state when CE is inactive, OE is inactive, or the
internal address counter has incremented beyond its
Terminal Count (TC) value.
The XC17V01, XC17V02, and XC17V04 have only the
single DATA output pin for connection to the FPGA serial
configuration data input pin.
The XC17V08 and XC17V16 have the D[0-7] output pins.
During device programming, the XC17V08 and XC17V16
must be programmed for use in either serial output mode or
parallel output mode. For XC17V08 and XC17V16 devices
programmed to serial output mode, only the D0 pin is
enabled for data output to the Virtex® series FPGA serial
configuration data input pin. In serial mode, the D[1-7]
output pins remain in high impedance state and may be
unconnected. For XC17V08 and XC17V16 devices
programmed to parallel output mode, all D[0-7] output pins
are enabled for byte-wide data output to the FPGA
SelectMAP configuration data input pins.
The DATA/D0 pin is a bidirectional I/O during device
programming.
CLK
Each rising edge on the CLK input increments the internal
address counter, when CE is active, OE is active, the
internal address counter has not incremented past its
Terminal Count (TC) value, and BUSY is Low.
Note: The BUSY condition applies to only the XC17V08 and
XC17V16.
RESET/OE
The polarity of this input pin is programmable as either
RESET/OE or OE/RESET. The polarity is set at the time of
device programming. The device default is active-High
RESET, but compatibility with Xilinx FPGAs requires the
polarity to be programmed with an active-Low RESET.
When RESET is active, the address counter is held at “0”,
and puts the DATA output in a high-impedance state.
CE
When High, this pin holds the internal address counter in
reset, puts the DATA output in a high-impedance state, and
forces the device into low-ICC standby mode.
CEO
Chip Enable Output is connected to the CE input of the next
PROM in the daisy chain. This output is Low when the CE
and OE inputs are both active AND the internal address
counter has been incremented beyond its Terminal Count
(TC) value. CEO returns to High when OE goes inactive or
CE goes High.
BUSY (XC17V16 and XC17V08 Only)
Asserting the BUSY input High prevents rising edges on
CLK from incrementing the internal address counter and
maintains current data on the data pins.
Note: If the BUSY pin is floating, then the programmable option
to internally tie BUSY to an internal pull-down resistor must be set
during device programming.
VPP
Programming voltage. No overshoot above the specified
maximum voltage is permitted on this pin. For normal read
operation, this pin must be connected to VCC. Failure to do
so may lead to unpredictable, temperature-dependent
operation and severe problems in circuit debugging.
Caution! Do not leave VPP floating!
VCC and GND
Positive supply and ground pins.
PROM Pinouts for XC17V16 and XC17V08
Pins not listed in Ta bl e 1 are “no connect.”
Table 1: Pinouts for XC17V16 and XC17V08(1)
Pin Name 44-pin VQFP (VQ44) 44-pin PLCC (PC44)
BUSY 24 30
D0 40 2
D1 29 35
D2 42 4
D3 27 33
D4 9 15
D5 25 31
D6 14 20
D7 19 25
CLK 43 5
RESET/OE
(OE/RESET)13 19
CE 15 21
GND 6, 18, 28, 37, 41 3, 12, 24, 34, 43
CEO 21 27
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 4
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Capacity
Pinout Diagrams for XC17V16 and XC17V08
PROM Pinouts for XC17V04, XC17V02, and
XC17V01
Pins not listed in Ta bl e 3 are “no connect.”
VPP 35 41
VCC 8, 16, 17, 26, 36, 38 14, 22, 23, 32, 42, 44
Notes:
1. Specific part number and package combinations have been
discontinued. Refer to XCN07010.
Table 2: Device Capacities
Devices Configuration Bits
XC17V16 16,777,216
XC17V08(1) 8,388,608
Notes:
1. Specific part number and package combinations have been
discontinued. Refer to XCN07010.
Table 1: Pinouts for XC17V16 and XC17V08(1)(Cont’d)
Pin Name 44-pin VQFP (VQ44) 44-pin PLCC (PC44)
1
2
3
4
5
6
7
8
9
10
11
VQ44
Top View
NC
NC
NC
NC
D1
GND
D3
VCC
D5
BUSY
NC
NC
OE/RESET
D6
CE
VCC
VCC
GND
D7
NC
CEO
NC
NC
NC
NC
NC
NC
GND
NC
VCC
D4
NC
NC
NC
CLK
D2
GND
DATA(D0)
NC
VCC
GND
VCC
VPP
NC
DS073_12_101502
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
Table 3: Pinouts for XC17V04, XC17V02, and XC17V01
Pin Name
8-pin
VOIC
(V08)
(1)
20-pin
SOIC
(SO20)
(1,3)
20-pin
PLCC
(PC20)
(1,2)
44-pin
VQFP
(VQ44)
(2)
44-pin
PLCC
(PC44)
(2)
DATA 1 1 1 40 2
CLK 2 3 3 43 5
RESET/OE
(OE/RESET)38 81319
CE 4 10 10 15 21
GND 5 11 11 18, 41 24, 3
CEO 6 13 13 21 27
VPP 718 183541
VCC 820 203844
Notes:
1. XC17V01 available in these packages.
2. XC17V02 and XC17V04 available in these packages.
3. Specific part number and package combinations have been
discontinued. Refer to XCN07010.
6
5
4
3
2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
7
8
9
10
11
12
13
14
15
16
17
PC44
Top View
NC
NC
NC
NC
D1
GND
D3
VCC
D5
BUSY
NC
NC
OE/RESET
D6
CE
VCC
VCC
GND
D7
NC
CEO
NC
NC
NC
NC
NC
NC
GND
NC
VCC
D4
NC
NC
NC
CLK
D2
GND
DATA(D0)
NC
VCC
GND
VCC
VPP
NC
DS073_13_101502
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 5
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Capacity
Pinout Diagrams for XC17V04, XC17V02(1),
and XC17V01
Table 4: Device Capacities
Devices Configuration Bits
XC17V04 4,194,304
XC17V02(1) 2,097,152
XC17V01 1,679,360
Notes:
1. Specific part number and package combinations have been
discontinued. Refer to XCN07010.
1
2
3
4
5
6
7
8
9
10
11
VQ44
Top View
(See Note 2)
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
OE/RESET
NC
CE
NC
NC
GND
NC
NC
CEO
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
CLK
NC
GND
DATA(D0)
NC
VCC
NC
NC
VPP
NC
DS073_07_100702
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
6
5
4
3
2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
7
8
9
10
11
12
13
14
15
16
17
PC44
Top View
(See Note 2)
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
OE/RESET
NC
CE
NC
NC
GND
NC
NC
CEO
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
CLK
NC
GND
DATA(D0)
NC
VCC
NC
NC
VPP
NC
DS073_08_100702
VO8
Top View
(See Note 1)
DS073_09_110102
1
2
3
4
8
7
6
5
VCC
VPP
CEO
GND
DATA(D0)
CLK
OE/RESET
CE
DS073_10_082108
SO20
Top
View
(See
Notes 1, 3)
VCC
NC
VPP
NC
NC
NC
NC
CEO
NC
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DATA(D0)
NC
CLK
NC
NC
NC
NC
OE/RESET
NC
CE
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 6
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Notes:
1. XC1701 is available in these packages.
2. XC1702 and XC1704 are available in these packages.
3. Specific part number and package combinations have been
discontinued. Refer to XCN07010.
Xilinx FPGAs and Compatible PROMs
Table 5: Xilinx FPGAs and Compatible PROMs
Device Configuration
Bits PROM
XC2V40 360,096 XC17V01
XC2V80 635,296 XC17V01
XC2V250 1,697,184 XC17V02(1)
XC17V04
XC2V500 2,761,888 XC17V04
XC2V1000 4,082,592 XC17V04
XC2V1500 5,659,296 XC17V08(1)
XC17V16
XC2V2000 7,492,000 XC17V08(1)
XC17V16
XC2V3000 10,494,368 XC17V16
XC2V4000 15,659,936 XC17V16
XC2V6000 21,849, 504 XC17V16+XC17V08(1)
2 of XC17V16
XC2V8000 29,063,072 2 of XC17V16
XCV50 559,200 XC17V01
XCV100 781,216 XC17V01
XCV150 1,040,096 XC17V01
XCV200 1,335,840 XC17V01
XCV300 1,751,808 XC17V02(1)
XC17V04
XCV400 2,546,048 XC17V04
PC20
Top View
(See Notes 1, 2, 3)
DS073_11_062508
3
2
1
20
19
18
17
16
15
14
9
10
11
12
13
4
5
6
7
8
CLK
NC
DATA(D0)
VCC
NC
VPP
NC
NC
NC
NC
NC
CE
GND
NC
CEO
NC
NC
NC
NC
OE/RESET
XCV600 3,607,968 XC17V04
XCV800 4,715,616 XC17V08(1)
XC17V16
XCV1000 6,127,744 XC17V08(1)
XC17V16
XCV50E 630,048 XC17V01
XCV100E 863,840 XC17V01
XCV200E 1,442,016 XC17V01
XCV300E 1,875,648 XC17V02(1)
XC17V04
XCV400E 2,693,440 XC17V04
XCV405E 3,430,400 XC17V04
XCV600E 3,961,632 XC17V04
XCV812E 6,519,648 XC17V08(1)
XC17V16
XCV1000E 6,587,520 XC17V08(1)
XC17V16
XCV1600E 8,308,992 XC17V08(1)
XC17V16
XCV2000E 10,159,648 XC17V16
XCV2600E 12,922,336 XC17V16
XCV3200E 16,283,712 XC17V16
XC3S50 439,264 XC17V01
XC3S200 1,047,616 XC17V01
XC3S400 1,699,136 XC17V02(1)
XC17V04
XC3S1000 3,223,488 XC17V04
XC3S1500 5,214,784 XC17V08(1)
XC17V16
XC3S2000 7,673,024 XC17V08(1)
XC17V16
XC3S4000 11,316,864 XC17V16
XC3S5000 13,271,936 XC17V16
Notes:
1. Specific part number and package combinations have been
discontinued. Refer to XCN07010. For some devices, the
original PROM recommendation is shown along with the
replacement PROM.
Table 5: Xilinx FPGAs and Compatible PROMs (Cont’d)
Device Configuration
Bits PROM
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 7
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Controlling PROMs
Connecting the FPGA device with the PROM.
•The DATA output(s) of the PROM(s) drives the
configuration data input(s) of the lead FPGA device.
•The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).
•The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
•The RESET/OE input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a VCC glitch.
•The PROM CE input is best connected to the FPGA
DONE pin(s) and a pullup resistor. CE can also be
permanently tied Low, but this keeps the DATA output
active and causes an unnecessary supply current of
15 mA maximum.
•SelectMAP mode is similar to Slave Serial mode. The
DATA is clocked out of the PROM one byte per CCLK
instead of one bit per CCLK cycle. See FPGA data
sheets for special configuration requirements.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the three FPGA mode pins. In Master Serial
mode, the FPGA automatically loads the configuration
program from an external memory. The Xilinx PROMs have
been designed for compatibility with the Master Serial
mode.
Upon power-up or reconfiguration, an FPGA enters the
Master Serial mode whenever all three of the FPGA mode-
select pins are Low (M0=0, M1=0, M2=0). Data is read from
the PROM sequentially on a single data line.
Synchronization is provided by the rising edge of the
temporary signal CCLK, which is generated during
configuration.
Master Serial Mode provides a simple configuration
interface. Only one serial data line, two control lines, and
one clock line are required to configure an FPGA. Data from
the PROM is read sequentially, accessed via the internal
address and bit counters which are incremented on every
valid rising edge of CCLK.
If the user-programmable, dual-function DIN pin on the
FPGA is used only for configuration, it must still be held at a
defined level during normal operation. The Xilinx FPGA
families take care of this automatically with an on-chip
default pull-up/down resistor or keeper circuit.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories,
cascaded PROMs provide additional memory. After the last
bit from the first PROM is read, the next clock signal to the
PROM asserts its CEO output Low and disables its DATA
line. The second PROM recognizes the Low level on its CE
input and enables its DATA output. See Figure 3.
After configuration is complete, the address counters of all
cascaded PROMs are reset if the FPGA PROGRAM pin
goes Low, assuming the PROM reset polarity option has
been inverted.
Standby Mode
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high impedance
state regardless of the state of the OE input.
Programming
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
Selecting Reset Polarity and
Configuration Modes
The OE/RESET input polarity is programmable on all
XC17V00 PROMs. In addition, the XC17V08 and XC17V16
can accommodate either serial or parallel configuration
mode. The reset polarity and configuration mode are
selectable through the programmer software. For
compatibility with Xilinx FPGAs, the OE/RESET polarity
must be programmed with RESET active-Low.
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 8
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Table 6: Truth Table for XC17V00 Control Inputs
Control Inputs Internal Address Outputs
RESET(1) CE DATA CEO ICC
Inactive Low If address < TC(2): increment
If address > TC(2): don’t change
Active
High-Z
High
Low
Active
Reduced
Active Low Held reset High-Z High Active
Inactive High Not changing High-Z High Standby
Active High Held reset High-Z High Standby
Notes:
1. The XC17V00 RESET input has programmable polarity
2. TC = terminal count, highest address value.
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 9
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Notes:
1. Specific part number and package combinations have been discontinued. Refer to XCN07010.
X-Ref Target - Figure 3
Figure 3: (a) Master Serial Mode (b) SelectMAP Mode
(dotted lines indicate optional connection)
PROGRAM
DIN
CCLK
INIT
DONE
First
PROM
DATA
CEO
BUSYBUSY
CLK
CE
OPTIONAL
Slave FPGAs
with identical
configurations
FPGA
(Low Resets the Address Pointer)
V
CC
Vpp
OPTIONAL
Daisy-chained
FPGAs with
different
configurations
OE/RESET
DOUT
Modes
(1)
BUSYBUSY
SelectMAP Mode, XC17V16 and XC17V08
(1)
only.
4.7K
4.7K
V
CC
V
CC
V
CC
Vpp
V
CC
V
CC
V
CC
(2)
Master Serial Mode
DS073_03_102708
(1) For Mode pin connections, refer to the appropriate FPGA data sheet or user guide.
(2) For specific DONE resistor recommendations, refer to the appropriate FPGA data sheet or user guide.
Cascaded
PROM
DATA
CLK
CE
OE/RESET
PROGRAM
BUSY
CS
WRITE
INIT
D[0:7]
CCLK
DONE
CLK
D[0:7]
CE
OE/RESET
First
PROM Second
PROM
Modes
(3)
3.3V
External
Osc
(4)
CEO
4.7K
(2)
VCC
VCC Vpp
VCC
1K
I/O
(1)
8
I/O
(1)
1K
(1) CS and WRITE must be pulled down to be used as I/O. One option is shown.
(2) For specific DONE resistor recommendations, refer to the appropriate FPGA data sheet or user guide.
(3) For Mode pin connections, refer to the appropriate FPGA data sheet or user guide.
(4) External oscillator required for FPGA slave SelectMAP modes.
CLK
D[0:7]
CE
OE/RESET
CEO
VCC
VCC Vpp
FPGA
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 10
R
Absolute Maximum Ratings(1)
Operating Conditions (3V Supply)
DC Characteristics Over Operating Condition
Symbol Description Conditions Units
VCC Supply voltage relative to GND –0.5 to +7.0 V
VPP Supply voltage relative to GND –0.5 to +12.5 V
VIN Input voltage relative to GND –0.5 to VCC +0.5 V
VTS Voltage applied to High-Z output –0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) –65 to +150 °C
TJJunction temperature +125 °C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Symbol Description Min Max Units
VCC(1) Supply voltage relative to GND (TA = 0°C to +70°C) Commercial 3.0 3.6 V
Supply voltage relative to GND (TA = –40°C to +85°C) Industrial 3.0 3.6 V
TVCC(2) VCC rise time from 0V to nominal voltage 1.0 50 ms
Notes:
1. During normal read operation VPP must be connected to VCC.
2. At power up, the device requires the VCC power supply to monotonically rise from 0V to nominal voltage within the specified VCC rise time. If
the power supply cannot meet this requirement, then the device may not power-on-reset properly.
Symbol Description Min Max Units
VIH High-level input voltage 2 VCC V
VIL Low-level input voltage 0 0.8 V
VOH High-level output voltage (IOH = –3 mA) 2.4 – V
VOL Low-level output voltage (IOL = +3 mA) – 0.4 V
ICCA Supply current, active mode (at maximum frequency)
(XC17V16 and XC17V08(1) only) – 100 mA
ICCA Supply current, active mode (at maximum frequency)
(XC17V04, XC17V02(1), and XC17V01(1) only) –15mA
ICCS Supply current, standby mode – 1 mA
ILInput or output leakage current –10 10 μA
CIN Input capacitance (VIN = GND, f = 1.0 MHz) – 15 pF
COUT Output capacitance (VIN = GND, f = 1.0 MHz) – 15 pF
Notes:
1. Specific part number and package combinations have been discontinued. Refer to XCN07010.
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 11
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AC Characteristics over Operating Condition for XC17V04, XC17V02, and
XC17V01
X-Ref Target - Figure 4
Symbol Description Min Max Units
TOE OE to data delay – 30 ns
TCE CE to data delay – 45 ns
TCAC CLK to data delay – 45 ns
TDF CE or OE to data float delay(2,3) –50ns
TOH Data hold from CE, OE, or CLK(3) 0–ns
TCYC Clock periods 67 – ns
TLC CLK Low time(3) 25 – ns
THC CLK High time(3) 25 – ns
TSCE CE setup time to CLK (to guarantee proper counting) 25 – ns
THCE CE hold time to CLK (to guarantee proper counting) 0 – ns
THOE OE hold time (guarantees counters are reset) 25 – ns
TCEH CE High time (guarantees counters are reset) 20 – ns
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
5. If TCEH High, 2 μs, TCE = 2 μs.
6. If THOE High, 2 μs, TOE = 2 μs.
RESET/OE
CE
CLK
DATA
TCE
TOE
TLC
TSCE TSCE THCE
THOE
TCAC TOH TDF
TOH
THC
DS073_04_14102005
TCYC
TCEH
Notes:
1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high
RESET polarity. Timing specifications are identical for both polarity settings.
2 The diagram shows timing relationships. The diagram is not reflective of actual FPGA signal sequences. See the appropriate
FPGA data sheet or user guide for actual configuration signal sequences.
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 12
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AC Characteristics over Operating Condition for XC17V16 and XC17V08
X-Ref Target - Figure 5
Symbol Description Min Max Units
TOE OE to data delay – 15 ns
TCE CE to data delay – 20 ns
TCAC CLK to data delay(2) –20ns
TDF CE or OE to data float delay(3,4) –35ns
TOH Data hold from CE, OE, or CLK(4) 0–ns
TCYC Clock periods 50 – ns
TLC CLK Low time(4) 25 – ns
THC CLK High time(4) 25 – ns
TSCE CE setup time to CLK (to guarantee proper counting) 25 – ns
THCE CE hold time to CLK (to guarantee proper counting) 0 – ns
THOE OE hold time (guarantees counters are reset) 25 – ns
TSBUSY BUSY setup time 5 – ns
THBUSY BUSY hold time 5 – ns
TCEH CE High time (guarantees counters are reset) 20 – ns
Notes:
1. AC test load = 50 pF.
2. When BUSY = 0.
3. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
4. Guaranteed by design, not tested.
5. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
6. If TCEH High, 2 μs, TCE = 2 μs.
7. If THOE High, 2 μs, TOE = 2 μs.
RESET/OE
(1)
CE
CLK
BUSY
(2)
DATA
TCE
TOE
TLC
TSCE TSCE THCE
THOE
TCAC
TSBUSY THBUSY
TOH TDF
TOH
THC
DS073_05_031606
TCYC
TCEH
Note:
1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high RESET polarity.
Timing specifications are identical for both polarity settings.
2. If BUSY is inactive (Low) during a rising CLK edge, then new DATA appears at time T
CAC
after the rising CLK edge. If BUSY is active (High)
during a rising CLK edge, then there is no corresponding change to DATA.
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 13
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AC Characteristics over Operating Condition When Cascading
Ordering Information
X-Ref Target - Figure 6
Symbol Description Min Max Units
TCDF CLK to data float delay(2,3) –50ns
TOCK CLK to CEO delay(3) –30ns
TOCE CE to CEO delay(3) –35ns
TOOE RESET/OE to CEO delay(3) –30ns
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
CLK
DATA
CE
CEO
First Bit
Last Bit
TCDF
DS026_07_102005
RESET/OE
TOCK TOOE
TOCE
Notes:
1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high
RESET polarity. Timing specifications are identical for both polarity settings.
2 The diagram shows timing of the First Bit and Last Bit for one PROM with respect to signals involved in a cascaded situation.
The diagram does not show timing of data as one PROM transfers control to the next PROM. The shown timing information must
be applied appropriately to each PROM in a cascaded situation to understand the timing of data during the transfer of control
from one PROM to the next.
XC17V16 PC44 C
Operating Range/Processing
C = Commercial (TA = 0° to +70°C)
I = Industrial (TA = –40° to +85°C)
Package Type
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier
VO8 = 8-pin Plastic Small Outline Thin Package
PC20 = 20-pin Plastic Leaded Chip Carrier
Device Number
XC17V16
XC17V04
XC17V01
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 14
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Valid Ordering Combinations
Marking Information
Due to the small size of the commercial serial PROM packages, the complete ordering part number cannot be marked on
the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows:
XC17V16VQ44C XC17V04PC20C XC17V01VO8C
XC17V16PC44C XC17V04PC44C
XC17V16VQ44I XC17V04VQ44C
XC17V16PC44I XC17V04PC20I
XC17V04PC44I
XC17V04VQ44I
XC17V16 PC44 C
Operating Range/Processing
C=Commercial (T
A = 0° to +70°C)
I = Industrial (TA = –40° to +85°C)
Package Type
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier
VO8 = 8-pin Plastic Small Outline Thin Package
PC20 = 20-pin Plastic Leaded Chip Carrier
SO20 = 20-pin Plastic Small Outline Package(1)
Device Number
XC17V16
XC17V08(1)
XC17V04
XC17V02(1)
XC17V01
Notes:
1. Specific part number and package combinations have been discontinued. Refer to XCN07010.
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 15
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Revision History
The following table shows the revision history for this document.
.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Date Version Revision
07/26/00 1.0 Initial Xilinx release.
10/09/00 1.1 Updated 20-pin PLCC Pinouts.
11/16/00 1.2 Updated pinouts for XC17V16 and XC17V08, ICCA DC Characteristic from standby to active mode; CIN
and COUT from 10 pF to 15 pF, added ICCS for XC17V16 and XC17V08 at 500 μA.
02/20/01 1.3 Added note to pinouts for “no connect,” updated Figure 3.
04/04/01 1.4 Added XC2V products to Compatible PROM table, updated Figure 3, updated text for Virtex-II FPGAs.
10/09/01 1.5 Corrected bitstream length for SCV405E, added power-on supply requirements and note for power-on
reset, updated configuration bits for Virtex-II devices, removed CF from Figure 3, and updated FPGA list.
02/27/02 1.6 Added Virtex-II Pro™ FPGAs to the , page 6.
06/14/02 1.7 Made additions and changes to Xilinx FPGAs and Compatible PROMs, page 6.
07/29/02 1.8 Added Virtex-II Pro FPGAs to , page 6.
11/05/02 1.9 Added pinout diagrams, changed , page 6, and added footnotes to AC Characteristics over Operating
Condition for XC17V04, XC17V02, and XC17V01, page 11 and AC Characteristics over Operating
Condition for XC17V16 and XC17V08, page 12.
04/10/03 1.10 Added Spartan-3 FPGAs to Truth Table for XC17V00 Control Inputs, page 8.
06/07/07 1.11 •Figure 2, page 2 updated to show correct three-state control on output data buses.
•Corrected XC3S50 bitstream size in Xilinx FPGAs and Compatible PROMs, page 6.
•Added section Selecting Reset Polarity and Configuration Modes, page 7.
•Removed maximum soldering temperature (TSOL) from "Absolute Maximum Ratings(1)," page 10.
Refer to Xilinx Device Package User Guide for package soldering guidelines.
•Added notes to timing diagram under AC Characteristics over Operating Condition for XC17V04,
XC17V02, and XC17V01, page 11 for clarification.
•Added notes and updated timing diagram AC Characteristics over Operating Condition for XC17V16
and XC17V08, page 12 for clarification.
•Reversed polarity of RESET/OE signal in timing diagram under , page 13 for consistency and added
notes for clarification.
11/13/08 1.12 •Added support for discontinued device and package combinations per XCN07010.
•Added TJ to "Absolute Maximum Ratings(1)," page 10.
•Updated Figure 3.
