1. General description
The 74HC573-Q100; 74HCT573-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard no. 7A.
The 74HC573-Q100; 74HCT573-Q100 has octal D-type transparent latches featuring
separate D-type inputs for each latch and 3-state true outputs for bus-oriented
applications. A latch enable (LE) inpu t and an output ena ble (OE) input are common to all
latches.
When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the latches are
transparent, i.e. a latch output changes state each time its corresponding D input
changes.
When LE is LOW the latches store the information that was present at the D-inputs a
set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents
of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the OE input does not affect the state of the
latches.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Input levels:
For 74HC573-Q100: CMOS level
For 74HCT573-Q100: TTL level
Inputs and outputs on opposite sides of package allo win g ea sy inter fa ce with
microprocessors
Useful as input or output port for microprocessors and microcomputers
3-state non-inverting outputs for bus-oriented applications
Common 3-state output enable input
Multiple package options
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
Rev. 3 — 5 March 2013 Product data sheet
74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 5 March 2013 2 of 20
NXP Semiconductors 74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature
range Name Description Version
74HC573D-Q100 40 C to +125 C SO20 plastic small outline package; 20 leads;
body width 7.5 mm SOT163-1
74HCT573D-Q100
74HC573DB-Q100 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm SOT339-1
74HCT573DB-Q100
74HC573PW-Q100 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm SOT360-1
74HCT573PW-Q100
74HC573BQ-Q100 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5 4.5 0.85 mm
SOT764-1
74HCT573BQ-Q100
Fig 1. Functional di agram
mna809
3-STATE
OUTPUTS
LATCH
1 to 8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7 12
13
14
15
16
17
18
19
D0
D1
D2
D3
D4
D5
D6
D7
LE
OE
9
11
1
8
7
6
5
4
3
2
74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 5 March 2013 3 of 20
NXP Semiconductors 74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
Fig 2. Logic diag ram
001aae075
Q4
D4
DQ
Q3
D3
DQ
Q2
D2
DQ
Q1
D1
D
LE
Q
Q0
D0
D
LATCH
1LATCH
2LATCH
3LATCH
4LATCH
5
Q
LE
OE
LE LE LE LE
Q5
D5
DQ
LATCH
6
LE
Q6
D6
DQ
LATCH
7
LE
Q7
D7
DQ
LATCH
8
LE
Fig 3. Logic symbol Fig 4. IEC logic symbol
mna807
D0
D1
D2
D3
D4
D5
D6
D7 LE
OE Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
11
12
13
14
15
16
17
18
19
9
8
7
6
5
4
3
2
mna808
12
13
14
15
16
17
18
11 C1
1EN1
1D 19
9
8
7
6
5
4
3
2
74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 5 March 2013 4 of 20
NXP Semiconductors 74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration SO20, SSOP20 and
TSSOP20 Fig 6. Pin configuration DHVQFN20
DDD











2
(
9&&
'
4
'
4
'
4
'
4
'
4
'
4
'
4
'
4
*1' /(
+&4
+&74
DDD
7UDQVSDUHQWWRSYLHZ
4
'
'
4
' 4
' 4
' 4
' 4
' 4
'
*1'
4
*1'
/(
2(
9&&











WHUPLQDO
LQGH[DUHD
+&4
+&74
Table 2. Pin description
Symbol Pin Description
OE 1 3-state output enable input (active LOW)
D[0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input
GND 10 ground (0 V)
LE 11 latch enable input (active HIGH)
Q[0:7] 19, 18, 17, 16, 15, 14, 13, 12 3-state latch output
VCC 20 supply voltage
74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 5 March 2013 5 of 20
NXP Semiconductors 74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
6. Functional description
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
7. Limiting values
[1] For SO20: Ptot derates linearly with 8 mW/K above 70 C.
For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN20 package: Ptot derates linearly with 4.5 mW/K above 60 C.
Table 3. Function table[1]
Operating mode Control Input Internal
latches Output
OE LE Dn Qn
Enable and read register (transparent
mode) LHLLL
HHH
Latch and read register L L l L L
hHH
Latch register and disable outputs H L l L Z
hHZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5 V - 20 mA
IOK output clamping current VO<0.5 V or VO>V
CC +0.5V - 20 mA
IOoutput current VO = 0.5 V to (VCC +0.5V) - 35 mA
ICC supply current - +70 mA
IGND ground current - 70 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation [1] - 500 mW
74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 5 March 2013 6 of 20
NXP Semiconductors 74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC573-Q100 74HCT573-Q100 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0- V
CC V
VOoutput voltage 0 - VCC 0- V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V--83---ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC573-Q100
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL
IO=20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO=20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO=20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO=6.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO=7.8 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI=V
IH or VIL
IO=20A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO=20A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO=20A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 6.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO= 7.8 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND;
VCC =6.0V --0.1 - 1.0 - 1.0 A
IOZ OFF-state
output current VI=V
IH or VIL;
VO=V
CC or GND;
VCC =6.0V
--0.5 - 5.0 - 10.0 A
74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 5 March 2013 7 of 20
NXP Semiconductors 74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
ICC supply current VI=V
CC or GND; IO=0A;
VCC =6.0V - - 8.0 - 80 - 160 A
CIinput
capacitance -3.5- pF
74HCT573-Q100
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO=20 A 4.4 4.5 - 4.4 - 4.4 - V
IO=6 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO=20A - 0 0.1 - 0.1 - 0.1 V
IO= 6.0 mA - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND;
VCC =5.5V --0.1 - 1.0 - 1.0 A
IOZ OFF-state
output current VI=V
IH or VIL; VCC =5.5V;
VO=V
CC or GND per input
pin; other inputs at VCC or
GND; IO=0A
--0.5 - 5.0 - 10 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =5.5V - - 8.0 - 80 - 160 A
ICC additional
supply current VI=V
CC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO=0A
per input pin; Dn inputs - 35 126 - 158 - 172 A
per input pin; LE input - 65 234 - 293 - 319 A
per input pin; OE input - 125 450 - 563 - 613 A
CIinput
capacitance -3.5- pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 5 March 2013 8 of 20
NXP Semiconductors 74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
10. Dynamic characteristics
Table 7. Dynam ic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
For type 74HC573-Q100
tpd propagation
delay Dn to Qn; see Figure 7 [1]
VCC = 2.0 V - 47 150 - 190 - 225 ns
VCC = 4.5 V - 17 30 - 38 - 45 ns
VCC =5V; C
L=15pF - 14 - - - - - ns
VCC = 6.0 V - 14 26 - 33 - 38 ns
tpd propagation
delay LE to Qn; see Figure 8 [1]
VCC = 2.0 V - 50 150 - 190 - 225 ns
VCC = 4.5 V - 18 30 - 38 - 45 ns
VCC =5V; C
L=15pF - 15 - - - - - ns
VCC = 6.0 V - 14 26 - 33 - 38 ns
ten enable time OE to Qn; see Figure 9 [2]
VCC = 2.0 V - 44 140 - 175 - 210 ns
VCC = 4.5 V - 16 28 - 35 - 42 ns
VCC = 6.0 V - 13 24 - 30 - 36 ns
tdis disable time OE to Qn; see Figure 9 [3]
VCC = 2.0 V - 55 150 - 190 - 225 ns
VCC = 4.5 V - 20 30 - 38 - 45 ns
VCC = 6.0 V - 16 26 - 33 - 38 ns
tttransition
time Qn; see Figure 7 [4]
VCC = 2.0 V - 14 60 - 75 - 90 ns
VCC = 4.5 V - 5 12 - 15 - 18 ns
VCC = 6.0 V - 4 10 - 13 - 15 ns
tWpulse width LE HIGH; see Figure 8
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
VCC = 6.0 V 14 4 - 17 - 20 - ns
tsu set-up time Dn to LE; see Figure 10
VCC = 2.0 V 50 11 - 65 - 75 - ns
VCC = 4.5 V 10 4 - 13 - 15 - ns
VCC = 6.0 V 9 3 - 11 - 13 - ns
thhold time Dn to LE; see Figure 10
VCC = 2.0 V 5 3 - 5 - 5 - ns
VCC = 4.5 V 5 1 - 5 - 5 - ns
VCC = 6.0 V 5 1 - 5 - 5 - ns
CPD power
dissipation
capacitance
CL=50pF;f=1 MHz;
VI=GNDtoV
CC
[5] -26- - - - -pF
74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 5 March 2013 9 of 20
NXP Semiconductors 74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
[1] tpd is the same as tPLH and tPHL.
[2] ten is the same as tPZH and tPZL.
[3] tdis is the same as tPLZ and tPHZ.
[4] tt is the same as tTHL and tTLH.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi = input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
For type 74HCT573-Q100
tpd propagation
delay Dn to Qn; see Figure 7 [1]
VCC = 4.5 V - 20 35 - 44 - 53 ns
VCC =5V; C
L=15pF - 17 - - - - - ns
tpd propagation
delay LE to Qn; see Figure 8 [1]
VCC = 4.5 V - 18 35 - 44 - 53 ns
VCC =5V; C
L=15pF - 15 - - - - - ns
ten enable time OE to Qn; see Figure 9 [2]
VCC = 4.5 V - 17 30 - 38 - 45 ns
tdis disable time OE to Qn; see Figure 9 [3]
VCC = 4.5 V - 18 30 - 38 - 45 ns
tttransition
time Qn; see Figure 7 [4]
VCC = 4.5 V - 5 12 - 15 - 18 ns
tWpulse width LE HIGH; see Figure 8
VCC = 4.5 V 16 5 - 20 - 24 - ns
tsu set-up time Dn to LE; see Figure 10
VCC = 4.5 V 13 7 - 16 - 20 - ns
thhold time Dn to LE; see Figure 10
VCC = 4.5 V 9 4 - 11 - 15 - ns
CPD power
dissipation
capacitance
CL=50pF;f=1 MHz;
VI=GNDtoV
CC
[5] -26- - - - -pF
Table 7. Dynam ic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 5 March 2013 10 of 20
NXP Semiconductors 74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
11. Waveforms
Measurement points are given in Table 8.
Fig 7. Prop a ga tio n de la y da ta input (Dn) to output (Qn) and outpu t transiti on time
001aae082
Dn input
Qn output
VM
tPLH tPHL
tTHL
tTLH
VM
90 %
10 %
Measurement points are given in Table 8.
Fig 8. Pulse width latch enable input (LE), propagation delay latc h en ab le input (LE) to output (Qn) and ou tpu t
transition time
VM
VM
tPLH
tPHL
tW
LE input
Qn output
001aae083
tTLH
tTHL
90 %
10 %
74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 5 March 2013 11 of 20
NXP Semiconductors 74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Enable and disable times
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 10. Set-up and hold times for data input (Dn) to latch input (LE)
001aae084
V
M
LE input
Dn input V
M
t
h
t
su
t
h
t
su
Table 8. Measurement points
Type Input Output
VMVM
74HC573-Q100 0.5VCC 0.5VCC
74HCT573-Q100 1.3 V 1.3 V
74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 5 March 2013 12 of 20
NXP Semiconductors 74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 11. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
VIVO
RT
RLS1
CL
open
G
Table 9. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC573-Q100 VCC 6ns 15pF, 50 pF 1kopen GND VCC
74HCT573-Q100 3 V 6 ns 15 pF, 50 pF 1 kopen GND VCC
74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 5 March 2013 13 of 20
NXP Semiconductors 74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
12. Package outline
Fig 12. Package outline SOT163-1 (SO20)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 13.0
12.6 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT163-1
10
20
wM
bp
detail X
Z
e
11
1
D
y
0.25
075E04 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.51
0.49 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
0 5 10 mm
scale
X
θ
A
A1
A2
HE
Lp
Q
E
c
L
vMA
(A )
3
A
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
99-12-27
03-02-19
74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 5 March 2013 14 of 20
NXP Semiconductors 74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
Fig 13. Package outline SOT339-1 (SSOP20)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQ(1)
Zywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 7.4
7.0 5.4
5.2 0.65 7.9
7.6 0.9
0.7 0.9
0.5 8
0
o
o
0.131.25 0.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT339-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
110
20 11
y
0.25
pin 1 index
0 2.5 5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
A
max.
2
74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 5 March 2013 15 of 20
NXP Semiconductors 74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
Fig 14. Package outline SOT360-1 (TSSOP20)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 6.6
6.4 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.5
0.2 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT360-1 MO-153 99-12-27
03-02-19
wM
bp
D
Z
e
0.25
110
20 11
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
A
max.
1.1
74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 5 March 2013 16 of 20
NXP Semiconductors 74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
Fig 15. Package outline SOT764-1 (DHVQFN20)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 4.6
4.4
Dh
3.15
2.85
y1
2.6
2.4 1.15
0.85
e1
3.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT764-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT764-1
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
29
19 12
11
10
1
20
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 5 March 2013 17 of 20
NXP Semiconductors 74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
MIL Military
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT573_Q10 0 v.3 20130305 Product data sheet - 74HC_HCT573_Q100 v.2
Modifications: •74HC573DB-Q100 and 74HCT 573DB-Q100 added.
74HC_HCT573_Q10 0 v.2 20120816 Product data sheet - 74HC_HCT573_Q100 v.1
74HC_HCT573_Q10 0 v.1 20120802 Product data sheet - -
74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 5 March 2013 18 of 20
NXP Semiconductors 74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly object s to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains t he product specification.
74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 5 March 2013 19 of 20
NXP Semiconductors 74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of rele ase: 5 March 2013
Document identi fier: 74HC_HCT573_Q100
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16 Contact information. . . . . . . . . . . . . . . . . . . . . 19
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20