W24100 128K x 8 CMOS STATIC RAM GENERAL DESCRIPTION The W24100 is a normal-speed, very low-power CMOS static RAM organized as 131072 x 8 bits that operates on a single 5-volt power supply. This device is manufactured using Winbond's high performance CMOS technology. FEATURES * * * * * * Low power consumption: - Active: 385 mW (max.) Access time: 70 nS Single 5V power supply Fully static operation All inputs and outputs directly TTL compatible Three-state outputs * Battery back-up operation capability Data retention voltage: 2V (min.) * Package: 32-pin 600 mil DIP, 32-pin 450 mil SOP, standard type one TSOP (8 mm x 20 mm) and small type one TSOP (8 mm x 13.4 mm) * BLOCK DIAGRAM PIN CONFIGURATIONS CLK GEN. PRECHARGE CKT. R O W CORE CELL ARRAY A16 A14 NC 1 32 VDD A12 A16 2 31 A15 A4 A14 3 30 CS2 A3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 A1 A0 29 #WE A2 28 A13 A7 27 A8 A6 26 A9 A5 25 A11 24 #OE 10 23 A10 11 22 #CS1 12 21 I/O8 I/O1 13 20 I/O7 I/O2 14 19 I/O6 I/O3 15 18 I/O5 #CS1 CS2 VSS 16 17 I/O4 #OE 32-pin SOP / 32-pin DIP D E C O D E R 1024 ROWS 128 X 8 COLUMNS A9 I/O1 : I/O8 DATA CNTRL. I/O CKT. COLUMN DECODER CLK GEN. A15 A13 A8 A1 A0 A11A10 #WE PIN DESCRIPTION A11 A9 A8 A13 #WE CS2 A15 V DD NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-pin TSOP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 #OE A10 #CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 SYMBOL A0-A16 I/O1-I/O8 #CS1, CS2 #WE #OE VDD VSS NC -1- DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Input Write Enable Input Output Enable Input Power Supply Ground No Connection Publication Release Date: September 6, 2001 Revision A3 W24100 TRUTH TABLE #CS1 CS2 #OE #WE MODE H X L L L X L H H H X X H L X X X H H L Not Selected Not Selected Output Disable Read Write VDD CURRENT I/O1-I/O8 High Z High Z High Z Data Out Data In ISB, ISB1 ISB, ISB1 IDD IDD IDD DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +7.0 V Input/Output to VSS Potential -0.5 to VDD +0.5 V Allowable Power Dissipation 1.0 W -65 to +150 C L/LL 0 to 70 C LE -20 to 85 Supply Voltage to VSS Potential Storage Temperature Operating Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VDD = 5V 10%; VSS = 0V; TA (C) = 0 to 70 for LL, -20 to 85 for LE) PARAMETER SYM. TEST CONDITIONS MIN. TYP.* MAX. UNIT Input Low Voltage VIL - -0.5 - +0.8 V Input High Voltage VIH - +2.2 - VDD +0.5 V Input Leakage Current ILI VIN = VSS to VDD -1 - +1 A Output Leakage Current ILO VI/O = VSS to VDD, #CS1 = VIH (min.) or #OE = VIH (min.) or #WE = VIL (max.) -1 - +1 A Output Low Voltage VOL IOL = +2.1 mA - - 0.4 V Output High Voltage VOH IOH = -1.0 mA 2.4 - - V Operating Power Supply Current IDD #CS1 = VIL (max.) and CS2 = VIH (min.), I/O = 0 mA Cycle = min., Duty = 100% - - 70 mA Standby Power Supply Current ISB #CS1 = VIH (min.), Cycle = min. Duty = 100% - - 3 mA ISB1 #CS1 VDD -0.2V or LL/LE - - 50/70 A L - - 100 CS2 0.2V -2- W24100 DC Characteristics, Continued Note: Typical parameter is measured under ambient temperature TA = 25 C and VDD = 5V. CAPACITANCE (VDD = 5 V, TA = 25 C, f = 1 MHz) PARAMETER SYM. CONDITIONS MAX. UNIT Input Capacitance CIN VIN = 0V 6 pF Input/Output Capacitance CI/O VOUT = 0V 8 pF Note: These parameters are sampled but not 100% tested. AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0V to 3.0V Input Rise and Fall Times 5 nS Input and Output Timing Reference Level 1.5V Output Load See the drawing below AC Test Loads and Waveform 1 TTL 1 TTL OUTPUT OUTPUT 5 pF Including Jig and Scope 100 pF Including Jig and Scope (For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW ) 3.0V 90% 90% 10% 10% 0V 5 nS 5 nS -3- Publication Release Date: September 6, 2001 Revision A3 W24100 AC Characteristics, continued (VDD = 5V 10%; VSS = 0V; TA (C) = 0 to 70 for LL, -20 to 85 for LE) Read Cycle PARAMETER SYM. W24100-70L W24100-70LL/LE MIN. MAX. MIN. MAX. UNIT Read Cycle Time TRC 70 - 70 - nS Address Access Time TAA - 70 - 70 nS Chip Select Access Time TACS - 70 - 70 nS Output Enable to Output Valid TAOE - 35 - 35 nS Chip Selection to Output in Low Z TCLZ* 10 - 10 - nS Output Enable to Output in Low Z TOLZ* 5 - 5 - nS Chip Deselection to Output in High Z TCHZ* - 30 - 30 nS Output Disable to Output in High Z TOHZ* - 30 - 30 nS Output Hold from Address Change TOH 10 - 10 - nS These parameters are sampled but not 100% tested Write Cycle PARAMETER SYM. W24100-70L W24100-70LL/LE MIN. MAX. MIN. MAX. UNIT Write Cycle Time TWC 70 - 70 - nS Chip Selection to End of Write TCW 50 - 50 - nS Address Valid to End of Write TAW 50 - 50 - nS Address Setup Time TAS 0 - 0 - nS Write Pulse Width TWP 50 - 50 - nS TWR 0 - 0 - nS Data Valid to End of Write TDW 30 - 30 - nS Data Hold from End of Write TDH 0 - 0 - nS Write to Output in High Z TWHZ* - 25 - 25 nS Output Disable to Output in High Z TOHZ* - 25 - 25 nS Output Active from End of Write TOW 5 - 5 - nS Write Recovery Time #CS1, CS2, #WE These parameters are sampled but not 100% tested -4- W24100 TIMING WAVEFORMS Read Cycle 1 (Address Controlled) TRC Address TAA TOH TOH DOUT Read Cycle 2 (Chip Select Controlled) #CS1 CS2 TACS TCHZ TCLZ DOUT Read Cycle 3 (Output Enable Controlled) T RC Address T AA #OE T OH T AOE T OLZ #CS1 CS2 T ACS D OUT T CHZ T OHZ TCLZ -5- Publication Release Date: September 6, 2001 Revision A3 W24100 Timing Waveforms, continued Write Cycle 1 TWC Address T WR #OE TCW #CS1 CS2 T AW #WE T WP TAS TOHZ (1, 4) D OUT T DW TDH D IN Write Cycle 2 (#OE = VIL Fixed) T WC Address TWR TCW #CS1 CS2 TAW #WE TWP TAS TOH TWHZ (1, 4) D OUT TDW (2) (3) TOW TDH DIN Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested. -6- W24100 DATA RETENTION CHARACTERISTICS (TA (C) = 0 to 70 for LL, -20 to 85 for LE) PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT 2.0 - - V VDD for Data Retention VDR #CS1 VDD -0.2V Data Retention Current IDDDR #CS1 VDD -0.2V, VDD = 3V - - 50 A Chip Deselect to Data Retention Time TCDR See data retention waveform 0 - - nS Operation Recovery Time TR TRC* - - nS * Read Cycle Time DATA RETENTION WAVEFORM VDD 0.9 V DD > 2V VDR = TCDR #CS1 0.9 V DD TR #CS1 > = V DD - 0.2V CS2 -7- Publication Release Date: September 6, 2001 Revision A3 W24100 ORDERING INFORMATION PART NO. ACCESS TIME (nS) OPERATING CURRENT MAX. (mA) STANDBY CURRENT MAX. (A) PACKAGE W24100-70L 70 70 100 600 mil DIP W24100-70LL 70 70 50 600 mil DIP W24100-70LE 70 70 70 600 mil DIP W24100S-70L 70 70 100 450 mil SOP W24100S-70LL 70 70 50 450 mil SOP W24100S-70LE 70 70 70 450 mil SOP W24100T-70L 70 70 100 Standard type one TSOP W24100T-70LL 70 70 50 Standard type one TSOP W24100T-70LE 70 70 70 Standard type one TSOP W24100Q-70L 70 70 100 Small type one TSOP W24100Q-70LL 70 70 50 Small type one TSOP W24100Q-70LE 70 70 70 Small type one TSOP Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. -8- W24100 BONDING PAD DIAGRAM 7 66 5 A5 A6 4 3 2 A7 A12 A14 1 33 32 31 30 A16 VDD VDD A15 CS2 29 28 27 26 WEB A13 A8 A9 AC5405 25 A11 A4 Y X 24 8 OEB A3 9 10 11 A2 A1 A0 I/O0 I/O1 I/O2 VSS VSS I/O3 I/O4 I/O5 I/O6 I/O7 CS1B A10 12 13 14 15 16 17 18 19 20 21 22 23 PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 X -485.31 -1200.87 -1341.05 -1480.80 -1622.21 -1767.47 -1993.03 -1990.55 -1789.57 -1556.20 -1405.83 -1169.73 -870.28 -567.65 -336.94 -112.55 224.85 497.55 772.25 1044.95 1319.65 1537.77 1773.94 1985.78 1987.47 1669.63 1451.03 1196.59 956.65 219.67 79.47 -145.06 -353.56 Y 2376.64 2376.64 2376.64 2376.64 2376.64 2376.64 2228.49 -2275.79 -2382.05 -2382.05 -2382.05 -2383.00 -2383.00 -2383.00 -2385.00 -2385.00 -2383.00 -2383.00 -2383.00 -2383.00 -2383.00 -2382.05 -2382.05 -2297.62 2221.27 2376.64 2376.64 2376.64 2376.64 2376.64 2376.64 2343.58 2343.58 Note: For bare chip form (C.O.B.) applications, the substrate must be connected to VDD or left floating in the PCB layout. -9- Publication Release Date: September 6, 2001 Revision A3 W24100 PACKAGE DIMENSIONS 32-pin P-DIP Dimension in inches Symbol A A1 A2 B B1 c D E E1 e1 L D 17 32 E1 16 1 E S c A A2 A1 L Base Plane Seating Plane B e1 eA a B1 Min. Nom. Max. Dimension in mm Min. Nom. Max. 5.33 0.210 0.010 0.25 0.155 0.160 3.81 3.94 4.06 0.016 0.018 0.022 0.41 0.46 0.56 0.048 0.050 0.054 1.22 1.27 1.37 0.008 0.010 0.014 0.20 0.25 0.36 1.650 1.660 41.91 42.16 0.600 0.610 14.99 15.24 15.49 0.150 0.590 0.545 0.550 0.555 13.84 13.97 14.10 0.090 0.100 0.110 2.29 2.54 2.79 0.120 0.130 0.140 3.05 3.30 3.56 15 0 0.670 16.00 16.51 17.02 a 0 eA S Notes: 0.630 0.650 15 0.085 2.16 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches 6. General appearance spec. should be based on final visual inspection spec. 32-pin SOP Wide Body Symbol A A1 A2 b c D E e HE L LE S y 17 32 e1 E HE L Detail F 1 b 16 Dimension in Inches Min. Nom. Max. Dimension in mm Min. Nom. 0.004 Max. 3.00 0.118 0.10 0.101 0.106 0.111 2.57 2.69 0.014 0.016 0.020 0.36 0.41 0.51 0.006 0.008 0.012 0.15 0.20 0.31 20.45 20.75 11.18 11.30 11.43 0.440 0.805 0.817 0.445 0.450 2.82 0.044 0.050 0.056 1.12 1.27 1.42 0.546 0.556 0.556 13.87 14.12 14.38 0.023 0.031 0.039 0.58 0.79 0.99 0.047 0.055 0.063 1.19 1.40 1.60 0 0.036 0.91 0.004 0.10 10 0 10 Notes: e1 D c A2 S y A e LE A1 See Detail F Seating Plane - 10 - 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimensions D & E include mismatch . moldmold and determined at the parting line. 4. Controlling dimension: Inches 5. General appearance spec should be based on final visual inspection spec. W24100 Package Dimensions, continued 32-pin Standard Type One TSOP HD Dimension in Inches Dimension in mm Symbol D A c A1 1 M e E 0.10(0.004) b L A1 __ 0.002 __ Min. Nom. __ __ 0.047 0.006 0.05 __ Max. 1.20 0.15 0.037 0.039 0.041 0.95 1.00 1.05 0.007 0.008 0.009 0.17 0.20 0.23 c 0.005 0.006 0.007 0.12 0.15 0.17 D 0.720 0.724 0.728 18.30 18.40 18.50 E 0.311 0.315 0.319 7.90 8.00 8.10 HD 0.780 0.787 0.795 19.80 20.00 20.20 __ __ 0.024 0.40 __ __ L A2 __ Max. b L1 Nom. A2 e A Min. __ 0.016 __ Y 0.000 1 0.020 0.020 0.031 __ 3 0.004 0.00 5 1 0.50 0.50 0.80 __ 3 __ 0.60 __ 0.10 5 Y L1 Controlling dimension: Millimeters 32-pin Small Type One TSOP HD Symbol D Min. c A A1 1 A2 b c D E e E b A 2 A A1 L Dimension in Inches Y L1 Nom. Max. 0.002 Dimension in mm Min. Nom. Max. 0.049 1.25 0.006 0.05 0.15 0.037 0.039 0.041 0.95 1.00 1.05 0.007 0.008 0.009 0.17 0.20 0.27 0.0056 0.0059 0.0062 0.14 0.15 0.16 0.461 0.465 0.469 11.70 11.80 11.90 0.311 0.315 0.319 7.90 8.00 8.10 HD e L L1 0.520 0.528 0.536 13.20 13.40 13.60 Y 0.000 0.020 0.50 0.012 0.020 0.028 0.027 0 0.30 0.50 0.70 0.675 3 0.004 0.00 5 0 0.10 3 5 Controlling dimension: Millimeters - 11 - Publication Release Date: September 6, 2001 Revision A3 W24100 VERSION HISTORY VERSION DATE PAGE A1 Oct. 1999 - A2 May 2000 1, 2, 7, 8, 9 9 2, 8 A3 Sep. 6, 2001 Headquarters 1, 8, 10 DESCRIPTION Initial Issued Add LE in Operating Characteristics, Data Retention Characteristics, Ordering Info; & Delete 32-pin P-DIP Package. Add in Bonding Pad Diagram Standby Current for LE is 70 A Add in 32-pin P-DIP Package Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 12 - Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798