REV. A
ADG3241
2.5 V/3.3 V, 1-Bit, 2-Port
Level Translator Bus Switch in SOT-66
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Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
225 ps Propagation Delay through the Switch
4.5 Switch Connection between Ports
Data Rate 1.5 Gbps
2.5 V/3.3 V Supply Operation
Selectable Level Shifting/Translation
Level Translation
3.3 V to 2.5 V
3.3 V to 1.8 V
2.5 V to 1.8 V
Small Signal Bandwidth 770 MHz
Tiny 6-Lead SC70 Package and 6-Lead SOT-66 Package
APPLICATIONS
3.3 V to 1.8 V Voltage Translation
3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Voltage Translation
Bus Switching
Bus Isolation
Hot Swap
Hot Plug
Analog Switch Applications
FUNCTIONAL BLOCK DIAGRAM
BE
A B
GENERAL DESCRIPTION
The ADG3241 is a 2.5 V or 3.3 V, single digital switch. It is
designed on a low voltage CMOS process, which provides low
power dissipation yet gives high switching speed and very low on
resistance. This allows the input to be connected to the output
without additional propagation delay or generating additional
ground bounce noise.
The switch is enabled by means of the bus enable (BE) input
signal. This digital switch allows a bidirectional signal to be
switched when ON. In the OFF condition, signal levels up to
the supplies are blocked.
This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs is allowed. Similarly, if the device is
operated from a 2.5 V supply and 2.5 V inputs are applied, the
device will translate the outputs to 1.8 V. In addition to this, a
level translating select pin (SEL) is included. When SEL is low,
V
CC
is reduced internally, allowing for level translation between
3.3 V inputs and 1.8 V outputs. This makes the device suited to
applications requiring level translation between different supplies,
such as converter to DSP/microcontroller interfacing.
PRODUCT HIGHLIGHTS
1. 3.3 V or 2.5 V supply operation.
2. Extremely low propagation delay through switch.
3. 4.5 Ω switches connect inputs to outputs.
4. Level/voltage translation.
5. Tiny SC70 package and SOT-66 package.
REV. A–2–
ADG3241–SPECIFICATIONS
1
B Version
Parameter Symbol Conditions Min Typ
2
Max Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage V
INH
V
CC
= 2.7 V to 3.6 V 2.0 V
V
INH
V
CC
= 2.3 V to 2.7 V 1.7 V
Input Low Voltage V
INL
V
CC
= 2.7 V to 3.6 V 0.8 V
V
INL
V
CC
= 2.3 V to 2.7 V 0.7 V
Input Leakage Current I
I
±0.01 ±1µA
OFF State Leakage Current I
OZ
0 ≤ A, B ≤ V
CC
±0.01 ±1µA
ON State Leakage Current 0 ≤ A, B ≤ V
CC
±0.01 ±1µA
Maximum Pass Voltage V
P
V
A
/V
B
= V
CC
= SEL = 3.3 V, I
O
= –5 µA2.2 2.5 2.7 V
V
A
/V
B
= V
CC
= SEL = 2.5 V, I
O
= –5 µA1.5 1.8 2.1 V
V
A
/V
B
= V
CC
= 3.3 V, SEL = 0 V, I
O
= –5 µA1.5 1.8 2.1 V
CAPACITANCE
3
A Port Off Capacitance C
A
OFF f = 1 MHz 3.5 pF
B Port Off Capacitance C
B
OFF f = 1 MHz 3.5 pF
A, B Port On Capacitance C
A
, C
B
ON f = 1 MHz 7 pF
Control Input Capacitance C
IN
f = 1 MHz 4 pF
SWITCHING CHARACTERISTICS
3
Propagation Delay A to B or B to A, t
PD4
t
PHL
, t
PLH
C
L
= 50 pF, V
CC
= SEL = 3 V 0.225 ns
Bus Enable Time BE to A or B
5
t
PZH
, t
PZL
V
CC
= 3.0 V to 3.6 V; SEL = V
CC
13.2 4.6 ns
Bus Disable Time BE to A or B
5
t
PHZ
, t
PLZ
V
CC
= 3.0 V to 3.6 V; SEL = V
CC
13 4 ns
Bus Enable Time BE to A or B
5
t
PZH
, t
PZL
V
CC
= 3.0 V to 3.6 V; SEL = 0 V 1 3 4 ns
Bus Disable Time BE to A or B
5
t
PHZ
, t
PLZ
V
CC
= 3.0 V to 3.6 V; SEL = 0 V 1 2.5 3.8 ns
Bus Enable Time BE to A or B
5
t
PZH
, t
PZL
V
CC
= 2.3 V to 2.7 V; SEL = V
CC
13 4 ns
Bus Disable Time BE to A or B
5
t
PHZ
, t
PLZ
V
CC
= 2.3 V to 2.7 V; SEL = V
CC
12.5 3.4 ns
Maximum Data Rate V
CC
= SEL = 3.3 V; V
A
/V
B
= 2 V 1.5 Gbps
Channel Jitter V
CC
= SEL = 3.3 V; V
A
/V
B
= 2 V 45 ps p-p
DIGITAL SWITCH
On Resistance R
ON
V
CC
= 3 V, SEL = V
CC
, V
A
= 0 V, I
BA
= 8 mA 4.5 8 Ω
V
CC
= 3 V, SEL = V
CC
, V
A
= 1.7 V, I
BA
= 8 mA 12 28 Ω
V
CC
= 2.3 V, SEL = V
CC
, V
A
= 0 V, I
BA
= 8 mA 5 9 Ω
V
CC
= 2.3 V, SEL = V
CC
, V
A
= 1 V, I
BA
= 8 mA 9 18 Ω
V
CC
= 3 V, SEL = 0 V, V
A
= 0 V, I
BA
= 8 mA 5 8 Ω
V
CC
= 3 V, SEL = 0 V, V
A
= 1 V, I
BA
= 8 mA 12 Ω
POWER REQUIREMENTS
V
CC
2.3 3.6 V
Quiescent Power Supply Current I
CC
Digital Inputs = 0 V or V
CC
; SEL = V
CC
0.01 1 µA
Digital Inputs = 0 V or V
CC
; SEL = 0 V 0.1 0.2 mA
Increase in I
CC
per Input
6
⌬I
CC
V
CC
= 3.6 V, BE = 3.0 V; SEL = V
CC
0.15 8 µA
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Typical values are at 25°C, unless otherwise stated.
3
Guaranteed by design, not subject to production test.
4
The digital switch contributes no propagation delay other than the RC delay of the typical R
ON
of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5
See Timing Measurement Information section.
6
This current applies to the control pin BE only. The A and B ports contribute no significant ac or dc currents as they transition.
Specifications subject to change without notice.
(VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX, unless
otherwise noted.)
REV. A
ADG3241
–3–
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25°C, unless otherwise noted.)
V
CC
to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Output Current . . . . . . . . . . . . . . . . . 25 mA per Channel
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
SC70 Package
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 332°C/W
SOT-66 Package
JA
Thermal Impedance . . . . . . . . . 191°C/W (4-Layer Board)
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG3241 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
Table I. Truth Table
BE SEL*Function
LL A = B, 3.3 V to 1.8 V Level Shifting
LH
A = B, 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting
HX Disconnect
*SEL = 0 V only when V
DD
= 3.3 V ± 10%.
REV. A–4–
ADG3241
TERMINOLOGY
V
CC
Positive Power Supply Voltage.
GND Ground (0 V) Reference.
V
INH
Minimum Input Voltage for Logic 1.
V
INL
Maximum Input Voltage for Logic 0.
I
I
Input Leakage Current at the Control Inputs.
I
OZ
OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.
I
OL
ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.
V
P
Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when
the switch input voltage is equal to the supply voltage.
R
ON
Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.
C
X
OFF OFF Switch Capacitance.
C
X
ON ON Switch Capacitance.
C
IN
Control Input Capacitance. This consists of BE and SEL.
I
CC
Quiescent Power Supply Current. This current represents the leakage current between the V
CC
and ground pins.
It is measured when all control inputs are at a logic high or low level and the switches are OFF.
⌬I
CC
Extra power supply current component for the BE control input when the input is not driven at the supplies.
t
PLH
, t
PHL
Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant
R
ON
× C
L
, where C
L
is the load capacitance.
t
PZH
, t
PZL
Bus Enable Times. These are the times taken to cross the V
T
voltage at the switch output when the switch turns on
in response to the control signal, BE.
t
PHZ
, t
PLZ
Bus Disable Times. This is the time taken to place the switch in the high impedance OFF state in response to the control
signal. It is measured as the time taken for the output voltage to change by V
⌬
from the original quiescent level,
with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.)
Max Data Rate Maximum Rate at which Data Can Be Passed through the Switch.
Channel Jitter Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.
PIN CONFIGURATION
6-Lead SC70
1
GND
A
VCC
B
BE SEL
ADG3241
TOP VIEW
(Not to Scale)
2
3
6
5
4
6-Lead SOT-66
1
SEL
A
B
GND
VCC BE
ADG3241
TOP VIEW
(Not to Scale)
2
3
6
5
4
Table II. Pin Function Descriptions
Pin No.
SC70 SOT-66 Mnemonic Description
16 BE Bus Enable (Active Low)
24 GND Ground Reference
33 A Port A, Input or Output
45 B Port B, Input or Output
51 V
CC
Positive Power Supply Voltage
62 SEL
Level Translation Select
ORDERING GUIDE
Temperature Package
Model Range Description Package Branding
ADG3241BKS-REEL –40°C to +85°CThin Shrink Small Outline Transistor Package (SC70) KS-6 SKA
ADG3241BKS-REEL7 –40°C to +85°CThin Shrink Small Outline Transistor Package (SC70) KS-6 SKA
ADG3241BKS-500RL7 –40°C to +85°CThin Shrink Small Outline Transistor Package (SC70) KS-6 SKA
ADG3241BRY-REEL7 –40°C to +85°CSmall Outline Transistor Package (SOT-66) RY-6-1 00
REV. A
Typical Performance Characteristics–ADG3241
–5–
V
A
/V
B
(V
)
R
ON (
)
00 0.5
T
A
= 25C
SEL = V
CC
5
10
15
20
25
30
35
40
1.5 2.5 3.5
V
CC
= 3V
V
CC
= 3.3V
V
CC
= 3.6V
3.02.01.0
TPC 1. On Resistance vs.
Input Voltage
V
A
/V
B
(V)
R
ON
()
00 0.5
5
10
15
20
1.5 2.01.0
25C
85C
40C
= 3.3V
SEL = V
CC
V
CC
TPC 4. On Resistance vs. Input
Voltage for Different Temperatures
V
A
/V
B
(V)
V
OUT
(V)
00 0.5
0.5
1.5
2.5
1.5 2.5
V
CC
= 2.7V
V
CC
= 2.5V
V
CC
= 2.3V
T
A
= 25C
SEL = V
CC
I
O
= –5A
2.0
1.0
1.0 2.0 3.0
TPC 7. Pass Voltage vs. V
CC
V
A
/V
B
(V
)
R
ON (
)
00 0.5
5
10
15
20
25
30
35
40
1.5 2.5
V
CC
= 2.3V
V
CC
= 2.5V
V
CC
= 2.7V
T
A
= 25C
SEL = V
CC
3.02.01.0
TPC 2. On Resistance vs.
Input Voltage
VA/VB(V)
RON ()
00 0.5
5
10
15
85C
25C
1.0
40C
= 2.5V
SEL = VCC
VCC
1.2
TPC 5. On Resistance vs. Input
Voltage for Different Temperatures
V
A
/V
B
(V)
V
OUT
(V)
00 0.5
0.5
1.5
2.5
1.5 2.5
V
CC
= 3.6V
V
CC
= 3.3V
V
CC
= 3V
3.5
T
A
= 25C
SEL = 0V
I
O
= –5A
2.0
1.0
1.0 2.0 3.0
TPC 8. Pass Voltage vs. V
CC
V
A
/V
B
(V
)
R
ON (
)
00 0.5
5
10
15
20
25
30
35
40
1.5 2.5
V
CC
= 3V
V
CC
= 3.3V
V
CC
= 3.6V
3.5
T
A
= 25C
SEL = 0V
1.0 2.0 3.0
TPC 3. On Resistance vs.
Input Voltage
V
A
/V
B
(V)
V
OUT
(V)
00 0.5
0.5
1.5
2.5
1.5 2.5 3.5
V
CC
= 3.6V
V
CC
= 3.3V
V
CC
= 3V
3.0
2.0
1.0
1.0 2.0 3.0
T
A
= 25C
SEL = V
CC
I
O
= –5A
TPC 6. Pass Voltage vs. V
CC
500
051015 20 25 30 35 40 45
ENABLE FREQUENCY (MHz)
ICC (A)
50
50
100
150
200
250
300
350
400
450
0
TA = 25C
VCC = 3.3V
SEL = 0V
VCC = SEL = 3.3V
VCC = SEL = 2.5V
TPC 9. I
CC
vs. Enable Frequency
REV. A–6–
ADG3241
I
O
(A)
V
OUT
(V)
0
0.5
1.0
1.5
2.0
2.5
3.0
0.02 0.04 0.06 0.08 0.100
V
CC
= 3.3V; SEL = 0V
V
CC
= SEL = 3.3V
V
CC
= SEL = 2.5V
T
A
= 25C
V
A
= 0V
BE = 0
TPC 10. Output Low Characteristic
2
0
1
–2
–1
–4
–3
0.03 0.1 1.0
FREQUENCY (MHz)
ATTENUATION (dB)
10 1000100
–6
–7
–5
–8
T
A
= 25C
V
CC
= 3.3V/2.5V
SEL = V
CC
V
IN
= 0dBm
N/W ANALYZER:
R
L
= R
S
= 50
TPC 13. Bandwidth vs. Frequency
4.0
3.5
3.0
–40 –20 0
TEMPERATURE (C)
TIME (ns)
20 806040
2.5
2.0
1.5
1.0
0.5
0
VCC = SEL = 2.5V
ENABLE
DISABLE
TPC 16. Enable/Disable Time
vs. Temperature
I
O
(A)
V
OUT
(V)
0
–0.10
0.5
1.0
1.5
2.0
2.5
3.0
T
A
= 25C
V
A
= V
CC
BE = 0
V
CC
= SEL = 2.5V
V
CC
= 3.3V; SEL = 0V
V
CC
= SEL = 3.3V
–0.08 –0.06 –0.04 –0.02 0
TPC 11. Output High Characteristic
FREQUENCY (MHz)
ATTENUATION (dB)
0.1 1000110
–90
0TA = 25C
VCC = 3.3V/2.5V
SEL = VCC
VIN = 0dBm
N/W ANALYZER
:
RL = RS = 50
–100
–80
–70
–60
–50
–40
–30
–20
–10
100
TPC 14. Off Isolation vs.
Frequency
DATA RATE (Gbps)
JITTER (ps p-p)
0.5
60
70
80
90
100
50
40
30
20
10
0
VCC = SEL = 3.3V
VIN = 1.5V p-p
20dB ATTENUATION
0.7 0.9 1.1 1.3 1.5 1.7 1.9
TPC 17. Jitter vs. Data Rate;
PRBS 31
0
–0.2
–0.4
0 0.5 1.0
V
A
/V
B
(V)
Q
INJ
(pC)
1.5 3.02.52.0
–0.6
–0.8
–1.0
–1.2
V
CC
= 3.3V
V
CC
= 2.5V
T
A
= 25C
SEL = V
CC
ON OFF
C
L
= 1nF
TPC 12. Charge Injection vs.
Source Voltage
4.0
3.5
3.0
–40 –20 0
TEMPERATURE (C)
TIME (ns)
20 806040
2.5
2.0
1.5
1.0
0.5
0
V
CC
= SEL = 3.3V
ENABLE
DISABLE
ENABLE
DISABLE
V
CC
= 3.3V, SEL = 0V
TPC 15. Enable/Disable Time
vs. Temperature
DATA RATE (Gbps)
EYE WIDTH (%)
0.5
60
70
80
85
90
95
100
75
65
55
50
1.51.31.10.90.7 1.7 1.9
V
CC
= SEL = 3.3V
V
IN
= 1.5V p-p
20dB ATTENUATION
% EYE WIDTH = ((CLOCK PERIOD –
JITTER p-p)/CLOCK PERIOD) 100%
TPC 18. Eye Width vs. Data
Rate; PRBS 31
REV. A
ADG3241
–7–
VCC = 3.3V
SEL = 3.3V
VIN = 1.5V p-p
20dB
ATTENUATION
TA = 25C
50mV/DIV
200ps/DIV
TPC 19. Eye Pattern; 1.5 Gbps,
V
CC
= 3.3 V, PRBS 31
20mV/DIV
200ps/DIV
VCC = 2.5V
SEL = 2.5V
VIN = 1.5V p-p
20dB
ATTENUATION
TA = 25C
TPC 20. Eye Pattern; 1.244 Gbps,
V
CC
= 2.5 V, PRBS 31
REV. A–8–
ADG3241
For the following load circuit and waveforms, the notation that is used is V
IN
and V
OUT
where
VVand V V or V V and V V
IN A OUT B IN B OUT A
====
CONTROL
INPUT BE
0V
tPLH
V
OUT
V
T
V
IH
V
H
V
T
V
L
tPLH
Figure 2. Propagation Delay
V
CC
V
IN
V
OUT
C
L
R
L
R
L
SW1
GND
2 V
CC
R
T
DUT
PULSE
GENERATOR
NOTES
PULSE GENERATOR FOR ALL PULSES:
tR
ⱕ 2.5ns,
tF
ⱕ 2.5ns,
FREQUENCY ⱕ 10MHz.
C
L
INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.
R
T
IS THE TERMINATION RESISTOR, SHOULD BE EQUAL TO Z
OUT
OF THE PULSE GENERATOR.
Figure 1. Load Circuit
Test Conditions
Symbol V
CC
= 3.3 V ± 0.3 V (SEL = V
CC
)V
CC
= 2.5 V ± 0.2 V (SEL = V
CC
)V
CC
= 3.3 V ± 0.3 V (SEL = 0 V) Unit
R
L
500 500 500 Ω
V
⌬
300 150 150 mV
C
L
50 30 30 pF
V
T
1.5 0.9 0.9 V
TIMING MEASUREMENT INFORMATION
ENABLE DISABLE
CONTROL INPUT BE
VIN = 0V
VIN = VCC
VOUT
SW1 @ 2VCC
VOUT
SW1 @ GND
tPLZ
tPZH tPHZ
tPZL
VT
0V
VCC
VT
VH
VH –V
VL
VL +
V
VCC
0V
VT
VINH
0V
Figure 3. Enable and Disable Times
Table III. Switch Position
Test S1
t
PLZ
, t
PZL
2 × V
CC
t
PHZ
, t
PZH
GND
REV. A
ADG3241
–9–
BUS SWITCH APPLICATIONS
Mixed Voltage Operation, Level Translation
Bus switches can provide an ideal solution for interfacing
between mixed voltage systems. The ADG3241 is suitable for
applications where voltage translation from 3.3 V technology to
a lower voltage technology is needed. This device can translate
from 3.3 V to 1.8 V, from 2.5 V to 1.8 V, or bidirectionally
from 3.3 V directly to 2.5 V.
Figure 4 shows a block diagram of a typical application in which
a user needs to interface between a 3.3 V ADC and a 2.5 V
microprocessor. The microprocessor may not have 3.3 V toler-
ant inputs, therefore placing the ADG3241 between the two
devices allows the devices to communicate easily. The bus
switch directly connects the two blocks, thus introducing
minimal propagation delay, timing skew, or noise.
3.3V ADC
2.5V
3.3V
2.5V
MICROPROCESSOR
ADG3241
3.3V
Figure 4. Level Translation between a 3.3 V ADC
and a 2.5 V Microprocessor
3.3 V to 2.5 V Translation
When V
CC
is 3.3 V (SEL = 3.3 V) and the input signal range is
0 V to V
CC
, the maximum output signal will be clamped to
within a voltage threshold below the V
CC
supply.
ADG3241
2.5V
2.5V
3.3V
2.5V
3.3V
Figure 5. 3.3 V to 2.5 V Voltage Translation,
SEL
= V
CC
In this case, the output will be limited to 2.5 V, as shown in
Figure 6. This device can be used for translation from 2.5 V to
3.3 V devices and also between two 3.3 V devices.
V
IN
2.5V
V
OUT
0V 3.3V
SWITCH
INPUT
SWITCH
OUTPUT
3.3V SUPPLY
SEL = 3.3V
Figure 6. 3.3 V to 2.5 V Voltage Translation,
SEL
= V
CC
2.5 V to 1.8 V Translation
When V
CC
is 2.5 V (SEL = 2.5 V) and the input signal range is
0 V to V
CC
, the maximum output signal will, as before, be clamped
to within a voltage threshold below the V
CC
supply. In this case,
the output will be limited to approximately 1.8 V, as shown
in Figure 8.
ADG3241 1.8V
2.5V
2.5V
Figure 7. 2.5 V to 1.8 V Voltage Translation,
SEL
= 2.5 V
CC
V
IN
1.8V
V
OUT
0V 2.5V
SWITCH
INPUT
SWITCH
OUTPUT
2.5V SUPPLY
SEL = 2.5V
Figure 8. 2.5 V to 1.8 V Voltage Translation,
SEL
= V
CC
3.3 V to 1.8 V Translation
The ADG3241 offers the option of interfacing between a 3.3 V
device and a 1.8 V device. This is possible through use of the
SEL pin. The SEL pin is an active low control pin. SEL acti-
vates internal circuitry in the ADG3241 that allows voltage
translation between 3.3 V devices and 1.8 V devices.
ADG3241 1.8V
3.3V
3.3V
Figure 9. 3.3 V to 1.8 V Voltage Translation,
SEL
= 0 V
When V
CC
is 3.3 V and the input signal range is 0 V to V
CC
, the
maximum output signal will be clamped to 1.8 V, as shown in
Figure 9. To do this, the SEL pin must be tied to Logic 0. If
SEL is unused, it should be tied directly to V
CC
.
VIN
1.8V
VOUT
0V 3.3V
SWITCH
INPUT
SWITCH
OUTPUT
3.3V SUPPLY
SEL = 0V
Figure 10. 3.3 V to 1.8 V Voltage Translation,
SEL
= 0 V
REV. A–10–
ADG3241
Bus Isolation
A common requirement of bus architectures is low capacitance
loading of the bus. Such systems require bus bridge devices that
extend the number of loads on the bus without exceeding the
specifications. Because the ADG3241 is designed specifically for
applications that do not need drive yet require simple logic
functions, it solves this requirement. The device isolates access
to the bus, thus minimizing capacitance loading.
BUS/
BACKPLANE
LOAD A LOAD C
LOAD B LOAD D
BUS SWITCH
LOCATION
Figure 11. Location of Bus Switched in a Bus
Isolation Application
Hot Plug and Hot Swap Isolation
The ADG3241 is suitable for hot swap and hot plug applications.
The output signal of the ADG3241 is limited to a voltage that is
below the V
CC
supply, as shown in Figures 6, 8, and 10. Therefore
the switch acts like a buffer to take the impact from hot insertion,
protecting vital and expensive chipsets from damage.
In hot plug applications, the system cannot be shut down when
new hardware is being added. To overcome this, a bus switch can
be positioned on the backplane between the bus devices and the
hot plug connectors. The bus switch is turned off during hot plug.
Figure 12 shows a typical example of this type of application.
PLUG-IN
CARD (1) CARD I/O
CARD I/O
RAM
CPU
PLUG-IN
CARD (2)
ADG3241 ADG3241
Figure 12. ADG3241 in a Hot Plug Application
There are many systems, such as docking stations, PCI boards
for servers, and line cards for telecommunications switches, that
require the ability to handle hot swapping. If the bus can be
isolated prior to insertion or removal, there is more control over
the hot swap event. This isolation can be achieved using bus
switches. The bus switches are positioned on the hot swap card
between the connector and the devices. During hot swap, the
ground pin of the hot swap card must connect to the ground pin
of the backplane before any other signal or power pins.
Analog Switching
Bus switches can be used in many analog switching applications,
for example, video graphics. Bus switches can have lower on
resistance, smaller ON and OFF channel capacitance, and thus
improved frequency performance than their analog counterparts.
The bus switch channel itself, consisting solely of an NMOS
switch, limits the operating voltage (see TPC 1 for a typical
plot), but in many cases, this does not present an issue.
High Impedance During Power-Up/Power-Down
To ensure the high impedance state during power-up or power-
down, BE should be tied to V
CC
through a pull-up resistor; the
minimum value of the resistor is determined by the current-
sinking capability of the driver.
REV. A
ADG3241
–11–
6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
0.22
0.08 0.46
0.36
0.26
8
4
0
0.30
0.15
1.00
0.90
0.70
SEATING
PLANE
1.10 MAX
3
5 4
2
6
1
2.00 BSC
PIN 1
2.10 BSC
0.65 BSC
1.25 BSC
1.30 BSC
0.10 MAX
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203AB
OUTLINE DIMENSIONS
6-Lead Small Outline Transistor Package [SOT-66]
(RY-6-1)
Dimensions shown in millimeters
SEATING
PLANE
0.60
0.57
0.53
12 MAX
TOP VIEW
0.34 MAX
0.27 NOM
0.18
0.17
0.13
BOTTOM
VIEW
1.70
1.66
1.50
PIN 1
1.30
1.20
1.10
1.70
1.65
1.50
1 3
5
6
2
4
0.10 NOM
0.05 MIN
0.20
MIN
0.50
BSC
0.25 MAX
0.17 MIN
0.30
0.23
0.10
0.26
0.19
0.11
REV. A
C04221–0–11/04(A)
–12–
ADG3241
Revision History
Location Page
10/04—Data Sheet changed from REV. 0 to REV. A.
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
