THC63LVDR84C_Rev.1.20_E
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THC63LVDR84C
24bit Color LVDS Receiver (Rising Edge Strobe Output)
General Description
The THC63LVDR84C receiver supports wide
temperature range as -40 to +85C, and wide
frequency range as 8 to 112MHz.
The THC63LVDR84C converts the four LVDS data
streams back into 24bits of LVCMOS data with
Rising edge clock. At a transmit clock frequency of
112MHz, 24bits of RGB data and 4bits of timing and
control data (HSYNC, VSYNC, DE, etc.) are
transmitted at an effective rate of 3.1Gbps.
Application
･Medium and Small Size Panel
･Security Camera
･Multi Function Printer
･Machine Vision (Frame Grabber Board)
･Medical Equipment Monitor
Features
･1:7 LVDS to LVCMOS Deserializer
･Operating Temperature Range : -40 to +85C
･No Special Start-up Sequence Required
･Spread Spectrum Clocking Tolerant up to 100kHz
Frequency Modulation and +/-2.5% Deviations
･Pixel Clock Range: 8 to 112MHz
･56pin TSSOP Package
･Power Down Mode
･Rising Edge Strobe Output
･EU RoHS Compliant
Recommended LVDS Transmitter ICs
･THC63LVDM83D
･THC63LVDM87
Block Diagram
PLL
RA +/-
RB +/-
RC +/-
RD +/-
/PDWN
7
LVDS Inputs
(56 to 784Mbps/ch)
RA0-6
CLKOUT
(8 to 112MHz)
LVCMOS Outputs
THC63LVDR84C
RB0-6
RC0-6
RD0-6
RCLK +/-
(8 to 112MHz)
7
7
7
LVDS to LVCMOS
1:7 Deserializer
Figure 1. Block Diagram
THC63LVDR84C_Rev.1.20_E
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Pin Diagram
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 46
12 45
13 44
14 43
15 42
16 41
17 40
18 39
19 38
20 37
21 36
22 35
23 34
24 33
25 32
26 31
27 30
28 29
RC3
RD6
RC4
GND
RC5
RC6
RD0
LVDS GND
RA-
RA+
RB-
RB+
LVDS VCC
LVDS GND
RC-
RC+
RCLK-
RCLK+
RD-
RD+
LVDS GND
PLL GND
PLL VCC
PLL GND
/PDWN
CLKOUT
RA0
GND
VCC
RC2
RC1
RC0
GND
RB6
RD5
RD4
VCC
RB5
RB4
RB3
GND
RB2
RD3
RD2
VCC
RB1
RB0
RA6
GND
RA5
RD1
RA4
RA3
VCC
RA2
RA1
Figure 2. Pin Diagram
Pin Description
Pin Name
Pin #
Direction
Type
Description
RA+, RA-
10, 9
Input
LVDS
LVDS Data Inputs
RB+, RB-
12, 11
RC+, RC-
16, 15
RD+, RD-
20, 19
RCLK+,
RCLK-
18, 17
LVDS Clock Inputs
RA0 ~ RA6
27, 29, 30, 32, 33, 35, 37
Output
LVCMOS
Pixel Data Outputs
RB0 ~ RB6
38, 39, 43, 45, 46, 47, 51
RC0 ~ RC6
53, 54, 55, 1, 3, 5, 6
RD0 ~ RD6
7, 34, 41, 42, 49, 50, 2
CLKOUT
26
Pixel Clock Output
/PDWN
25
Input
H : Normal Operation
L : Power Down (All outputs are pulled to
ground)
VCC
31, 40, 48, 56
-
Power
Power Supply Pins for LVCMOS outputs
and digital circuitry
GND
4, 28, 36, 44, 52
Ground Pins for LVCMOS outputs and
digital circuitry
LVDS VCC
13
Power Supply Pins for LVDS inputs
LVDS GND
8, 14, 21
Ground Pins for LVDS inputs
PLL VCC
23
Power Supply Pins for PLL circuitry
PLL GND
22, 24
Ground Pins for PLL circuitry
Table 1. Pin Description
THC63LVDR84C_Rev.1.20_E
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Absolute Maximum Ratings
Parameter
Min
Max
Unit
Supply Voltage (VCC, LVDS VCC, PLL VCC)
-0.3
+4.0
V
LVCMOS Input Voltage
-0.3
VCC + 0.3
V
LVCMOS Output Voltage
-0.3
VCC + 0.3
V
LVDS Input Pin
-0.3
VCC + 0.3
V
Junction Temperature
-
+125
C
Storage Temperature
-55
+150
C
Reflow Peak Temperature
-
+260
C
Reflow Peak Temperature Time
-
10
sec
Maximum Power Dissipation @+25C
-
1.9
W
Table 2. Absolute Maximum Ratings
Recommended Operating Conditions
Symbol
Parameter
Min
Typ
Max
Unit
VCC33
All Supply Voltage(VCC, LVDS VCC, PLL VCC)
3.0
-
3.6
V
Ta
Operating Ambient Temperature
-40
+25
+85
C
PCLK
RCLK and CLKOUT Clock Frequency
8
-
112
MHz
Table 3. Recommended Operating Conditions
“Absolute Maximum Ratings” are those values beyond which the safety of the device can not be guaranteed.
They are not meant to imply that the device should be operated at these limits. The tables of “Electrical
Characteristics Table4, 5, 6, 7” specify conditions for device operation.
“Absolute Maximum Rating” value also includes behavior of overshooting and undershooting.
THC63LVDR84C_Rev.1.20_E
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Equivalent LVDS Input Schematic Diagram
LVDS +
LVDS -
AMP
CMP
LVDS VCC
LVDS VCC
Output
Control
LVDS VCC
Figure 3. LVDS Input Schematic Diagram
Output Control
/PDWN
RCLK +/- Input
LVCMOS Output
H
Valid Clock
Active Clock & Data
H
Invalid Clock
Unfixed Clock & Data
H
Open or Hi-z
All Low
L
Don’t Care
All Low
Table 4. LVCMOS Output Data Control
THC63LVDR84C_Rev.1.20_E
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Power Consumption Over recommended operating supply and temperature range unless otherwise specified
Symbol
Parameter
Conditions
Typ*
Max
Unit
IRCCG
LVDS Receiver Operating Current
Gray Scale Pattern 16 (Fig.4)
CL=8pF, PCLK=65MHz,
VCC33=3.3V
55
70
mA
CL=8pF, PCLK=112MHz,
VCC33=3.3V
90
110
mA
IRCCW
LVDS Receiver Operating Current
Worst Case Pattern(Fig.5)
CL=8pF, PCLK=65MHz,
VCC33=3.3V
90
110
mA
CL=8pF, PCLK=112MHz,
VCC33=3.3V
130
160
mA
IRCCS
LVDS Receiver
Power Down Current
/PDWN=L
-
500
µA
*Typ values are at the conditions of Ta = +25ºC
Table 5. Power Consumption
16 Grayscale Pattern
CLKOUT
RA3, RB4, RC5
RA2, RB3, RC4
RA1, RB2, RC3
RA0, RB1, RC2
TA4-6, TB0/5/6
TC0/1/6, TD0-2
TD3-6
Steady State Low
Steady State High
Figure 4. 16 Grayscale Pattern
Worst Case Pattern
CLKOUT
Rx0-6
X=A,B,C,D
Figure 5. Worst Case Pattern
THC63LVDR84C_Rev.1.20_E
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Electrical Characteristics
LVDS Receiver DC Specifications
Over recommended operating supply and temperature range unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ*
Max
Unit
VTH
Differential Input High
Threshold
RL=100Ω, VIC=+1.2V
-
-
100
mV
VTL
Differential Input Low
Threshold
-100
-
-
mV
IIN
Input Current
VIN=+2.4 / 0V
LVDS VCC=3.6V
-
-
30
A
Table 6. LVDS Receiver DC Specifications
LVCMOS DC Specifications
Over recommended operating supply and temperature range unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
High Level Input Voltage
-
2.0
-
VCC
V
VIL
Low Level Input Voltage
-
GND
-
0.8
V
VOH
High Level Output Voltage
IOH=-4mA (Data)
IOH=-8mA (Clock)
2.4
-
-
V
VOL
Low Level Output Voltage
IOL=4mA (Data)
IOL=8mA (Clock)
-
-
0.4
V
IIN
Input Current
GND VIN VCC
-
-
10
A
Table 7. LVCMOS DC Specifications
LVCMOS Output Load Limitation
The output load is limited so that the junction temperature does not exceed 125C.
0.0
5.0
10.0
15.0
20.0
25.0
8 28 48 68 88 108
CLKOUT [MHz]
Output Load [pF]
Ta=70℃
Ta=85℃
Figure 6. LVCMOS Output Load Limitation
THC63LVDR84C_Rev.1.20_E
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Switching Characteristics
Over recommended operating supply and temperature range unless otherwise specified
Symbol
Parameter
Min
Typ*
Max
Unit
tRCP
RCLK and CLKOUT Transition Time
8.92
T
125
ns
tRCH
LVCMOS CLKOUT High Time
-
T/2
-
ns
tRCL
LVCMOS CLKOUT Low Time
-
T/2
-
ns
tRCD
RCLK IN to CLKOUT Delay
-
(3/14+3)×T
-
ns
tRS
LVCMOS Data Setup to CLKOUT
0.35×T - 0.3
-
-
ns
tRH
LVCMOS Data Hold from CLKOUT
0.45×T - 1.6
-
-
ns
tTLH
LVCMOS Low to High Transition Time
-
0.7
1.0
ns
tTHL
LVCMOS High to Low Transition Time
-
0.7
1.0
ns
tSK
LVDS Receiver Skew Margin
PCLK=65MHz
-0.55
-
0.55
ns
PCLK=112MHz
-0.25
-
0.25
tRIP1
LVDS Input Data Position0
- tSK
0.0
+ tSK
ns
tRIP0
LVDS Input Data Position1
T/7- tSK
T/7
T/7+ tSK
ns
tRIP6
LVDS Input Data Position2
2T/7- tSK
2T/7
2T/7+ tSK
ns
tRIP5
LVDS Input Data Position3
3T/7- tSK
3T/7
3T/7+ tSK
ns
tRIP4
LVDS Input Data Position4
4T/7- tSK
4T/7
4T/7+ tSK
ns
tRIP3
LVDS Input Data Position5
5T/7- tSK
5T/7
5T/7+ tSK
ns
tRIP2
LVDS Input Data Position6
6T/7- tSK
6T/7
6T/7+ tSK
ns
tRPLL
Phase Lock Loop Set
-
-
10.0
ms
*Typ values are at the conditions of VCC33=3.3V and Ta = +25ºC
Table 8. LVCMOS & LVDS Receiver AC Specifications
THC63LVDR84C_Rev.1.20_E
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AC Timing Diagrams
LVDS Input
RCLK+
RA+/- RA6 RA5 RA4 RA3 RA2 RA1 RA0
RB6 RB5 RB4 RB3 RB2 RB1 RB0
RC6 RC5 RC4 RC3 RC2 RC1 RC0
RD6 RD5 RD4 RD3 RD2 RD1 RD0
tRIP6
tRIP5
tRIP4
tRIP3
tRIP2
tRIP1
tRIP0
(Differential)
RB+/-
RC+/-
RD+/-
Next Cycle
Vdiff = 0V Vdiff = 0V
tRCP
Current CyclePrevious Cycle
Note:Vdiff=(RCLK+)-(RCLK-)
Figure 7. LVDS Input Data Position
LVCMOS Output
tTLH
80％
20％
80％
20％
tTHL
CL=8pF
Figure 8. LVCMOS Output Load and Transition Time
CLKOUT
tRCP
tRCH tRCL
VCC/2 VCC/2
VCC/2
tRS tRH
RA0-RA6
RB0-RB6
RC0-RC6
RD0-RD6
VCC/2
VCC/2 Valid Data
Figure 9. LVCMOS Output Setup and Hold Time
THC63LVDR84C_Rev.1.20_E
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Input to Output Delay
RCLK+ Vdiff = 0V
VCC/2
tRCD
CLKOUT
Note:Vdiff=(RCLK+)-(RCLK-)
Figure 10.Input Clock to Output Clock Delay Time
Phase Lock Loop Set Time
VCC33 3.0V
RCLK+/-
/PDWN VCC/2
CLKOUT VCC/2
tRPLL
Figure 11. PLL Lock Loop Set Time
THC63LVDR84C_Rev.1.20_E
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Application note
Display Data Mapping Example
Transmitter
Pin
VESA format
JEIDA format
Receiver
Pin
6bit(18bpp)
8bit(24bpp)
6bit(18bpp)
8bit(24bpp)
TA0
R0
R0
R2
R2
RA0
TA1
R1
R1
R3
R3
RA1
TA2
R2
R2
R4
R4
RA2
TA3
R3
R3
R5
R5
RA3
TA4
R4
R4
R6
R6
RA4
TA5
R5
R5
R7
R7
RA5
TA6
G0
G0
G2
G2
RA6
TB0
G1
G1
G3
G3
RB0
TB1
G2
G2
G4
G4
RB1
TB2
G3
G3
G5
G5
RB2
TB3
G4
G4
G6
G6
RB3
TB4
G5
G5
G7
G7
RB4
TB5
B0
B0
B2
B2
RB5
TB6
B1
B1
B3
B3
RB6
TC0
B2
B2
B4
B4
RC0
TC1
B3
B3
B5
B5
RC1
TC2
B4
B4
B6
B6
RC2
TC3
B5
B5
B7
B7
RC3
TC4
Hsync
Hsync
Hsync
Hsync
RC4
TC5
Vsync
Vsync
Vsync
Vsync
RC5
TC6
DE
DE
DE
DE
RC6
TD0
-
R6
-
R0
RD0
TD1
-
R7
-
R1
RD1
TD2
-
G6
-
G0
RD2
TD3
-
G7
-
G1
RD3
TD4
-
B6
-
B0
RD4
TD5
-
B7
-
B1
RD5
TD6
-
N/A
-
N/A
RD6
Note : Use TA to TC channels and open TD channel for 6bit application.
Table 9. Data Mapping for VESA & JEIDA RGB Color format
THC63LVDR84C_Rev.1.20_E
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System Connection Example
CLKIN
R2
R3
R4
R5
R6
R7
G2
G3
G4
G5
G6
G7
B2
B3
B4
B5
B6
B7
HSYNC
VSYNC
DE
R0
R1
G0
G1
B0
B1
CLKIN
TA0
TA1
TA2
TA3
TA4
TA5
TA6
TB0
TB1
TB2
TB3
TB4
TB5
TB6
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TD0
TD1
TD2
TD3
TD4
TD5
TD6
/PDWN/PDWN
RS
VCC33
R/F
GND
VCC
VCC33
LVDS GND
RA-
RA+
RB-
RB+
LVDS VCC
RC-
RC+
RCLK-
RCLK+
RD-
RD+
PLL GND
PLL VCC
TA-
TA+
TB-
TB+
TC-
TC+
TCLK-
TCLK+
TD-
TD+
Ferrite Bead
Ferrite Bead
0.1uF 0.01uF
THC63LVDM83D
PCB(Transmitter)
0.1uF
0.1uF0.01uF
CLKOUT
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RD0
RD1
RD2
RD3
RD4
RD5
RD6
LVDS GND
PLL GND
PLL VCC
0.1uF 0.01uF
LVDS VCC
0.1uF 0.01uF
/PDWN/PDWN
CLKOUT
R2
R3
R4
R5
R6
R7
G2
G3
G4
G5
G6
G7
B2
B3
B4
B5
B6
B7
HSYNC
VSYNC
DE
R0
R1
G0
G1
B0
B1
OPEN
THC63LVDF(R)84C
GND
VCC
VCC33
Ferrite Bead
Ferrite Bead
0.1uF0.01uF
PCB(Receiver)
100ohm
100ohm
100ohm
100ohm
100ohm
GND GND
0.01uF
100ohm pair Cable
or
PCB trace
Figure 12. Connection Example with JEIDA Format
THC63LVDR84C_Rev.1.20_E
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Notes
1) Cable Connection and Disconnection
Do not connect and disconnect the LVDS cable, when the power is supplied to the system.
2) GND Connection
Connect each GND of the PCB which LVDS-Tx and THC63LVDR84C on it. It is better for EMI reduction
to place GND cable as close to LVDS cable as possible.
3) Multi Drop Connection
Multi drop connection is not recommended.
THC63LVDR84C
LVDS-Tx THC63LVDR84C
RCLK+
RCLK-
Figure 13. Multi Drop Connection
4) Asynchronous use
Asynchronous using such as following systems is not recommended.
THC63LVDR84C
THC63LVDR84CLVDS-Tx
LVDS-Tx
IC
CLKOUT
CLKOUT
DATA
DATA
IC
RCLK+
RCLK-
RCLK+
RCLK-
CLKOUT
DATA
DATA
THC63LVDR84C
THC63LVDR84C
IC
RCLK+
RCLK-
RCLK+
RCLK-
CLKOUT
DATA
DATA
IC
Figure 14. Asynchronous Use
THC63LVDR84C_Rev.1.20_E
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Package
Figure 15. Package Diagram
THC63LVDR84C_Rev.1.20_E
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Reference Land Pattern
Figure 16. Reference of Land Pattern
The recommendation mounting method of THine device is reflow soldering.
The reference pattern is using the calculation result on condition of reflow soldering.
Notes
This land pattern design is a calculated value based on JEITA ET-7501.
Please take into consideration in an actual substrate design about enough the ease of mounting, the intensity of
connection, the density of mounting, and the solder paste used, etc… The optimal land pattern size changes
with these parameters. Please use the value shown by the land pattern as reference data.
THC63LVDR84C_Rev.1.20_E
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Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always apply
to the customer's design. We are not responsible for possible errors and omissions in this material. Please
note if errors or omissions should be found in this material, we may not be able to correct them immediately.
3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties
the contents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this product, we
will be exempted from the responsibility unless it directly relates to the production process or functions of
the product.
5. Product Application
5.1 Application of this product is intended for and limited to the following applications: audio-video
device, office automation device, communication device, consumer electronics, smartphone, feature
phone, and amusement machine device. This product must not be used for applications that require
extremely high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear
power control device, combustion chamber device, medical device related to critical care, or any kind
of safety device.
5.2 This product is not intended to be used as an automotive part, unless the product is specified as a
product conforming to the demands and specifications of ISO/TS16949 ("the Specified Product") in
this data sheet. THine Electronics, Inc. (“THine”) accepts no liability whatsoever for any product other
than the Specified Product for it not conforming to the aforementioned demands and specifications.
5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent
that the user and THine have been previously and explicitly agreed to each other.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a
certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to
have sufficiently redundant or error preventive design applied to the use of the product so as not to have our
product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Testing and other quality control techniques are used to this product to the extent THine deems
necessary to support warranty for performance of this product. Except where mandated by applicable
law or deemed necessary by THine based on the user’s request, testing of all functions and
performance of the product is not necessarily performed.
9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic
goods under the Foreign Exchange and Foreign Trade Control Law.
10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or
malfunction, if pins of the product are shorted by such as foreign substance. The damageｓ may cause a
smoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection
devices, such as fuses.
THine Electronics, Inc.
sales@thine.co.jp
