QPL9503
Ultra Low-Noise, Flat Gain LNA
Data Sheet April 23, 2018 | Subject to change without notice
www.qorvo.com
®
8 Pin 2X2 mm DFN Package
General Description
The QPL9503 is a flat-gain, high-linearity, ultra-low noise
amplifier in a small 2 x 2 mm surface-mount package. The
LNA provides a gain flatness of 2 dB (peak-to-peak) over a
wide bandwidth from 3 to 6 GHz. At 5.5 GHz, the amplifier
typically provides 21.6 dB gain, +35.5 dBm OIP3 at a 56mA
bias setting, and 0.95 dB noise figure. The LNA can be
biased from a single positive supply ranging from 3.3 to 5
volts. The device is housed in a green/RoHS-compliant
industry-standard 2x2 mm package.
The QPL9503 is internally matched using a high
performance E-pHEMT process and only requires five
external components for operation from a single positive
supply: an external RF choke and blocking/bypass
capacitors and a bias resistor going to pin 1. This LNA
integrates a shut-down biasing capability to allow for
operation in TDD applications.
The QPL9503 is optimized for linear performance across
the 3 to 6 GHz frequency band but can operate down to 600
MHz.
Applications
• 4.5G, 5G Massive MIMO
• Repeaters / DAS
• Mobile Infrastructure
• LTE-U / LAA
• L-band, S-band, C-band radios
• General Purpose Wireless
• TDD or FDD systems
Product Features
• 0.6-6 GHz Operational Bandwidth
• Ultra low noise figure, 0.95 dB NF @ 5.5 GHz
• Bias adjustable for linearity optimization
• 35.5 dBm OIP3 at 65mA IDD
• Shut-down mode pin with 1.8V TTL logic
• Unconditionally stable
• Integrated shutdown control pin
• Maintains OFF state with high Pin drive
• +3V to +5V supply; does not require -Vgg
Functional Block Diagram
Top View
Ordering Information
Part No.
Description
QPL9503SR
100 pcs on 7” reel
QPL9503TR7
2500 pcs on 7” reel
QPL9503EVB-01
5-6GHz Tuned Evaluation Board
Standard T/R size = 2500 pieces on a 7” reel
Backside Paddle - RF/DC GND
Pin 1 Reference Mark
8
7
6
5
1
2
3
4
NC
RF Out
GND
Shut Down
Vbias
RF In
NC
GND
QPL9503
Ultra Low-Noise, Flat Gain LNA
Data Sheet April 23, 2018 | Subject to change without notice
www.qorvo.com
®
Absolute Maximum Ratings
Parameter
Rating
Storage Temperature
−65 to 150°C
Supply Voltage (VDD)
+7 V
RF Input Power, CW, 50Ω, T=25°C
+30 dBm
RF Input Power, WCDMA, 10dB PAR
+27 dBm
RF Input Power, CW, OFF State
+30 dBm
Operation of this device outside the parameter ranges given
above may cause permanent damage.
Recommended Operating Conditions
Parameter
Min
Typ
Max
Units
Supply Voltage (VDD)
3.3
5.0
5.25
V
TCASE
−40
+105
°C
Tj for >106 hours MTTF
+190
°C
Electrical specifications are measured at specified test
conditions. Specifications are not guaranteed over all
recommended operating conditions.
Electrical Specifications
Test conditions unless otherwise noted: VDD =+5V, Temp=+25°C, 50 Ω system.
Parameter
Conditions
Min
Typ
Max
Units
Operational Frequency Range
600
6000
MHz
Test Frequency
5500
MHz
Gain
18.5
21.6
22.5
dB
Input Return Loss
10
dB
Output Return Loss
9
dB
Noise Figure (1)
0.9
1.3
dB
Output P1dB
+19
dBm
Output IP3
Pout=+5 dBm/tone, Δf=1 MHz
+30
+35.5
dBm
Power Shutdown Control (pin 5)
On state
0
0.63
V
Off state (Power down)
1.17
VDD
V
Current, IDD
On state
35
56
90
mA
Off state (Power down)
3
mA
Shutdown pin current, ISD
VPD ≥ 1.17 V
140
µA
Switching Speed
LNA ON to OFF
20
ns
LNA OFF to ON
400
ns
Thermal Resistance, θjc
channel to case
48
°C/W
Note:
1) Noise figure data has input trace loss de-embedded.
QPL9503
Ultra Low-Noise, Flat Gain LNA
Data Sheet April 23, 2018 | Subject to change without notice
www.qorvo.com
®
QPL9503 Evaluation Board
Notes:
1. See Evaluation Board PCB Information section for material and stack-up.
2. R3 (0 Ω jumper) is not shown on the schematic and may be replaced with copper trace in the target application layout.
3. All components are of 0402 size unless stated on the schematic.
4. For TDD Applications: R1 = 20K & R2 = 0Ω
5. For FDD Applications: R1 = 20K ‘OR’ Pin 5 tied to ground. R2 = DNP/Omitted
6. A through line is included on the evaluation board to de-embed the board losses.
7. R4 sets the current draw. Can be changed for the desired bias point.
Bill of Material – QPL9503 Evaluation Board
Reference Des.
Value
Description
Manuf.
Part Number
N/A
N/A
Printed Circuit Board
Qorvo
U1
n/a
Ultra Low Noise, Flat Gain LNA
Qorvo
QPL9503
R4
4.3K
Resistor, Chip, 0402, 5%, 1/16W
various
R2
20K
Resistor, chip, 0402, 5%, 1/16W
various
R1, 3
0 Ω
Resistor, Chip, 0402, 5%, 1/16W
various
L1
18 nH
Inductor, 0402, 5%, coil
Coilcraft
0402CS-18NXJL
C1
10 pF
CAP, 0402, +/-1%, 50V
Murata
GJM1555C1H100FB01D
C2
5.6 pF
CAP, 0402, +/-0.1pF, 25V
AVX
04023J6R8BBSTR
C8
0.2 pF
CAP, 0402, +/-0.05pF, 50V
Murata
GJM1555C1HR20WB01
C9
0.4 pF
CAP, 0402, +/-0.05pF, 50V
AVX
04023J0R4ABSTR
C4
1.0 uF
Cap., Chip, 0402, 10%, 10V, X5R
various
C3, C5, C6, C7
100 pF
Cap., Chip, 0402, 5%, 50V, NPO/COG
various
L1
C3
J5 J3
J1 J2
C4
R1
U1
C7C6
J6 J7
J4
C1 C2
R3
R4
C5
R2
C8
C9
Q1 J2
RF
Output
J4 GND
J3 VDD
2
3,4,6,8
7
J1
RF
Input
L1
18 nH C2
5.6 pF
C1
10 pF
C3
100 pF
C4
1 uF
R1
0
R2
20K
J5 PD
5
R4
4.3K
1
C8
0.2pF C9
0.4pF
C5
100 pF
See notes 4 & 5.
QPL9503
Ultra Low-Noise, Flat Gain LNA
Data Sheet April 23, 2018 | Subject to change without notice
www.qorvo.com
®
Performance Plots – QPL9503 Evaluation Board
Test conditions unless otherwise noted: VDD=+5 V, IDD = 65mA, Temp=+25°C. Noise figure data has input trace loss de-embedded.
10
13
16
19
22
25
1000 2000 3000 4000 5000 6000 7000
Gain (dB)
Frequency (MHz)
Gain vs. Frequency
+105 °C
+25 °C
−40 °C
-15
-10
-5
0
1000 2000 3000 4000 5000 6000 7000
|S11| (dB)
Frequency (MHz)
Input Return Loss vs. Frequency
+105 °C
+25 °C
−40 °C
-15
-10
-5
0
1000 2000 3000 4000 5000 6000 7000
|S22| (dB)
Frequency (MHz)
Output Return Loss vs. Frequency
+105 °C
+25 °C
−40 °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
3 3.5 4 4.5 5 5.5 6
Noise Figure (dB)
Frequency (GHz)
Noise Figure vs Frequency
28
29
30
31
32
33
34
35
36
37
38
-3 -2 -1 01234567
OIP3 (dBm)
Pout/tone (dBm)
OIP3 vs Pout
3GHz
4GHz
4.5GHz
5GHz
5.5GHz
6GHz
Temp.=+25 °C
25
28
31
34
37
40
3 3.5 4 4.5 5 5.5 6
OIP3 (dBm)
Frequency (GHz)
OIP3 vs Frequency
+105 °C
+25 °C
−40 °C
10
15
20
25
3 3.5 4 4.5 5 5.5 6
P1dB (dBm)
Frequency (GHz)
P1dB vs Frequency
+105 °C
+25 °C
−40 °C
0
5
10
15
20
25
30
35
40
-45
-40
-35
-30
-25
-20
-15
-10
-5
-10 -5 0 5 10 15 20 25
IDD (mA)
Gain (dB)
Pin (dBm)
Gain & IDD vs Pin (LNA OFF)
Gain
IDD
VPD = 1.2V
QPL9503
Ultra Low-Noise, Flat Gain LNA
Data Sheet April 23, 2018 | Subject to change without notice
www.qorvo.com
®
Evaluation Board PCB Information
Qorvo PCB 281645 Material and Stack-up
50 ohm line dimensions: width = 0.0182”, spacing = 0.020”
Pin Configuration and Description
Pin No.
Label
Description
1
Vbias
Sets the Icq bias point for the device.
2
RF In
RF Input pin. A DC Block is required.
5
Shut Down
A high voltage(>1.17V) turns off the device. If the pin is pulled to ground or driven
with a voltage less than 0.63V, then the device will operate under LNA ON state.
7
RF Out / DCBias
RF Output pin. DC bias will also need to be injected through a RF bias
choke/inductor for operation.
3 ,8
NC
No electrical connection. Provide grounded land pads for PCB mounting integrity.
Backside
Paddle, 4, 6
RF/DC GND
RF/DC ground. Use recommended via pattern to minimize inductance and thermal
resistance; see PCB Mounting Pattern for suggested footprint.
Rogers 4003C
εr=3.5 typ.
1 oz. Cu bottom layer
FR4
FR4
1 oz. Cu top layer
1 oz. Cu inner layer
1 oz. Cu inner layer
0.062" ± 0.006"
Finished Board
Thickness
0.008"
0.008"
Backside Paddle - RF/DC GND
Pin 1 Reference Mark
8
7
6
5
1
2
3
4
NC
RF Out
GND
Shut Down
Vbias
RF In
NC
GND
QPL9503
Ultra Low-Noise, Flat Gain LNA
Data Sheet April 23, 2018 | Subject to change without notice
www.qorvo.com
®
Mechanical Information
Package Marking and Dimensions
Notes:
1. All dimensions are in millimeters. Angles are in degrees.
2. Except where noted, this part outline conforms to JEDEC standard MO-220, Issue E (Variation VGGC) for thermally enhanced
plastic very thin fine pitch quad flat no lead package (QFN).
3. Dimension and tolerance formats conform to ASME Y14.4M-1994.
4. The terminal #1 identifier and terminal numbering conform to JESD 95-1 SPP-012.
PCB Mounting Pattern
Notes:
1. All dimensions are in millimeters. Angles are in degrees.
2. Use 1 oz. copper minimum for top and bottom layer metal.
3. Vias are required under the backside paddle of this device for proper RF/DC grounding and thermal dissipation. We recommend
a 0.35mm (#80/.0135") diameter bit for drilling via holes and a final plated thru diameter of 0.25 mm (0.10”).
4. Ensure good package backside paddle solder attach for reliable operation and best electrical performance.
9503
Trace Code
QPL9503
Ultra Low-Noise, Flat Gain LNA
Data Sheet April 23, 2018 | Subject to change without notice
www.qorvo.com
®
RoHS Compliance
This part is compliant with 2011/65/EU RoHS directive (Restrictions on the Use of Certain Hazardous Substances in Electrical and
Electronic Equipment) as amended by Directive 2015/863/EU.
This product also has the following attributes:
• Lead Free
• Halogen Free (Chlorine, Bromine)
• Antimony Free
• TBBP-A (C15H12Br402) Free
• PFOS Free
• SVHC Free
Handling Precautions
Parameter
Rating
Standard
Caution!
ESD-Sensitive Device
ESD – Human Body Model (HBM)
1C
ESDA / JEDEC JS-001-2014
ESD – Charged Device Model (CDM)
C3
ESDA / JEDEC JS-002-2014
MSL – Moisture Sensitivity Level
Level 1
IPC/JEDEC J-STD-020
Solderability
Compatible with lead-free (260°C max. reflow temp.) soldering process.
Solder profiles available upon request.
Contact plating: NiPdAu
Important Notice
The information contained herein is believed to be reliable; however, Qorvo makes no warranties regarding the information contained
herein and assumes no responsibility or liability whatsoever for the use of the information contained herein. All information contained
herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for
Qorvo products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any
patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by
such information. THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED
HEREIN, AND QORVO HEREBY DISCLAIMS ANY AND ALL WARRANTIES WITH RESPECT TO SUCH PRODUCTS WHETHER
EXPRESS OR IMPLIED BY LAW, COURSE OF DEALING, COURSE OF PERFORMANCE, USAGE OF TRADE OR OTHERWISE,
INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Without limiting the generality of the foregoing, Qorvo products are not warranted or authorized for use as critical components in medical,
life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal
injury or death.
Copyright 2018 © Qorvo, Inc. | Qorvo is a registered trademark of Qorvo, Inc.
Contact Information
For the latest specifications, additional product information, worldwide sales and distribution locations:
Web: www.qorvo.com
Tel: 1-844-890-8163
Email: customer.support@qorvo.com
For technical questions and application information: Email: appsupport@qorvo.com
Pb