Standard Products QCOTSTM UT9Q512E 512K x 8 SRAM Data Sheet April 11, 2007 INTRODUCTION FEATURES 20ns maximum (5 volt supply) address access time Asynchronous operation for compatibility with industrystandard 512K x 8 SRAMs TTL compatible inputs and output levels, three-state bidirectional data bus Typical radiation performance - Total dose: 50krads The QCOTSTM UT9Q512E Quantified Commercial Off-theShelf product is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (E), an active LOW Output Enable (G), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (E) input LOW and Write Enable (W) inputs LOW. Data on the eight I/O pins (DQ0 through DQ7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (E) and Output Enable (G) LOW while forcing Write Enable (W) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. - SEL Immune 110 MeV-cm2/mg - SEU LETTH(0.25) = 52 cm2 MeV - Saturated Cross Section (cm2) per bit, 2.8E-8 -<1.1E-9 errors/bit-day, Adams 90% worst case environment geosynchronous orbit Packaging: - 36-lead ceramic flatpack (3.831 grams) Standard Microcircuit Drawing 5962-00536 - QML Vand Q compliant part The eight input/output pins (DQ0 through DQ7) are placed in a high impedance state when the device is deselected (E) HIGH), the outputs are disabled (G HIGH), or during a write operation (E LOWand W LOW). Clk. Gen. Pre-Charge Circuit I/O Circuit Column Select A9 Data Control A10 A11 CLK Gen. A18 DQ 0 - DQ 7 Memory Array 1024 Rows 512x8 Columns A12 A13 A14 A15 A16 A17 A3 A4 A5 A6 A7 A8 Row Select A0 A1 A2 E W G Figure 1. UT9Q512E SRAM Block Diagram 1 DEVICE OPERATION A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A1 A2 A3 A4 E DQ0 DQ1 VDD VSS DQ2 DQ3 W A5 A6 A7 A8 A9 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 The UT9Q512E has three control inputs called Enable (E), Write Enable (W), and Output Enable (G); 19 address inputs, A(18:0); and eight bidirectional data lines, DQ(7:0). E controls device selection, active, and standby modes. Asserting E enables the device, causes IDD to rise to its active value, and decodes the 19 address inputs to select one of 524,288 words in the memory. W controls read and write operations. During a read cycle, G must be asserted to enable the outputs. NC A18 A17 A16 A15 G DQ7 DQ6 VSS VDD DQ5 DQ4 A14 A13 A12 A11 A10 NC Table 1. Device Operation Truth Table Figure 2. UT9Q512E 20ns SRAM Pinout (36) PIN NAMES A(18:0) Address DQ(7:0) Data Input/Output E Enable W Write Enable G Output Enable VDD Power VSS Ground G W E I/O Mode Mode X1 X 1 3-state Standby X 0 0 Data in Write 1 1 0 3-state Read2 0 1 0 Data out Read Notes: 1. "X" is defined as a "don't care" condition. 2. Device active; outputs disabled. READ CYCLE A combination of W greater than VIH (min) and E less than VIL (max) defines a read cycle. Read access time is measured from the latter of Device Enable, Output Enable, or valid address to valid data output. SRAM Read Cycle 1, the Address Access in figure 4a, is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid data appears on data outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as Device Enable and Output Enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV). SRAM read Cycle 2, the Chip Enable - Controlled Access in figure 4b, is initiated by E going active while G remains asserted, W remains deasserted, and the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(18:0) is accessed and appears at the data outputs DQ(7:0). SRAM read Cycle 3, the Output Enable - Controlled Access in figure 4c, is initiated by G going active while E is asserted, W is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied. 2 active. For the W initiated write, unless the outputs have been previously placed in the high-impedance state by G, the user must wait tWLQZ before applying data to the eight bidirectional pins DQ(7:0) to avoid bus contention. WRITE CYCLE A combination of W less than VIL(max) and E less than VIL(max) defines a write cycle. The state of G is a "don't care" for a write cycle. The outputs are placed in the high-impedance state when either G is greater than VIH(min), or when W is less than VIL(max). TYPICAL RADIATION HARDNESS Table 2. Radiation Hardness Design Specifications1 Write Cycle 1, the Write Enable - Controlled Access in figure 5a, is defined by a write terminated by W going high, with E still active. The write pulse width is defined by tWLWH when the write is initiated by W, and by tETWH when the write is initiated by E. Unless the outputs have been previously placed in the highimpedance state by G, the user must wait tWLQZ before applying data to the nine bidirectional pins DQ(7:0) to avoid bus contention. Total Dose 50 krad(Si) Heavy Ion Error Rate2 <1.1E-9 Errors/Bit-Day Notes: 1. The SRAM will not latchup during radiation exposure under recommended operating conditions. 2. Adam's 0% worst case environment, Geosynchronous orbit, 100 mils of Aluminum. Write Cycle 2, the Chip Enable - Controlled Access in figure 5b, is defined by a write terminated by E going inactive. The write pulse width is defined by tWLEF when the write is initiated by W, and by tETEF when the write is initiated by the E going 3 ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS) SYMBOL PARAMETER LIMITS VDD DC supply voltage -0.5 to 7.0V VI/O Voltage on any pin -0.5 to 7.0V TSTG Storage temperature -65 to +150C PD Maximum power dissipation TJ Maximum junction temperature2 +150C Thermal resistance, junction-to-case3 10C/W DC input current 10 mA JC II 1.0W Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Maximum junction temperature may be increased to +175C during burn-in and steady-static life. 3. Test per MIL-STD-883, Method 1012. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS VDD Positive supply voltage 4.5 to 5.5V TC Case temperature range (C) screening: -55C to +125C (W) screening: -40C to +125C VIN DC input voltage 0V to VDD 4 DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* -55C to +125C for (C) screening and -40oC to +125oC for (W) screening (VDD = 5.0V + 10%) SYMBOL PARAMETER CONDITION MIN MAX VIH High-level input voltage (TTL) VIL Low-level input voltage (TTL) 0.8 V VOL1 Low-level output voltage IOL = 8mA, VDD =4.5V (TTL) 0.4 V VOL2 Low-level output voltage IOL = 200A,VDD =4.5V (CMOS) 0.05 V VOH1 High-level output voltage IOH = -4mA,VDD =4.5V (TTL) 2.4 V VOH2 High-level output voltage IOH = -200A,VDD =4.5V (CMOS) 3.2 V CIN1 Input capacitance = 1MHz @ 0V 10 pF CIO1 Bidirectional I/O capacitance = 1MHz @ 0V 12 pF IIN Input leakage current VIN = VDD and VSS, VDD = VDD (max) -2 2 A IOZ Three-state output leakage current VO = VDD and VSS VDD = VDD (max) G = VDD (max) -2 2 A VDD = VDD (max), VO = VDD -90 90 mA IOS2, 3 Short-circuit output current 2 UNIT V VDD = VDD (max), VO = 0V IDD(OP)4 Supply current operating @ 1MHz Inputs: VIL = 0.8V, VIH = 2.0V IOUT = 0mA VDD = VDD (max) 50 mA IDD(OP)4 Supply current operating @50MHz Inputs: VIL = 0.8V, VIH = 2.0V IOUT = 0mA VDD = VDD (max) 76 mA IDD(SB) Supply current standby @0MHz Inputs: VIL = VSS IOUT = 0mA E = VDD - 0.5 VDD = VDD (max) VIH = VDD - 0.5V 10 mA 45 mA -55C, -40C, 25C 125C Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. Supplied as a design limit but not guaranteed or tested. 3. Not more than one output may be shorted at a time for maximum duration of one second. 4. G = V1H 5 AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)* -55C to +125C for (C) screening and -40oC to +125oC for (W) screening (VDD = 5.0V + 10%) SYMBOL PARAMETER MIN MAX tAVAV1 Read cycle time tAVQV Read access time tAXQX Output hold time 3 ns tGLQX G-controlled Output Enable time 0 ns tGLQV G-controlled Output Enable time (Read Cycle 3) 10 ns tGHQZ2 G-controlled output three-state time 10 ns tETQX3 E-controlled Output Enable time tETQV3 E-controlled access time 20 ns E-controlled output three-state time 10 ns tEFQZ1,2,4 20 UNIT ns 20 3 ns Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Functional test. 2. Three-state is defined as a 500mV change from steady-state output voltage (see Figure 3). 3. The ET (enable true) notation refers to the falling edge of E. SEU immunity does not affect the read parameters. 4. The EF (enable false) notation refers to the rising edge of E. SEU immunity does not affect the read parameters. High Z to Active Levels Active to High Z Levels VH - 500mV VLOAD + 500mV } VLOAD { { } VLOAD - 500mV VL + 500mV Figure 3. 5-Volt SRAM Loading 6 ns tAVAV A(18:0) DQ(7:0) Previous Valid Data Valid Data tAVQV tAXQX Assumptions: 1. E and G < VIL (max) and W > VIH (min) Figure 4a. SRAM Read Cycle 1: Address Access A(18:0) E tETQV tETQX tEFQZ DQ(7:0) DATA VALID Assumptions: 1. G < VIL (max) and W > VIH (min) Figure 4b. SRAM Read Cycle 2: Chip Enable-Controlled Access Fi 4b SRAM R d C l 2 Chi E bl C ll d A tAVQV A(18:0) G tGHQZ tGLQX DATA VALID DQ(7:0) tGLQV Assumptions: 1. E< VIL (max) and W > VIH (min) Figure 4c. SRAM Read Cycle 3: Output Enable-Controlled Access 7 AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)* -55C to +125C for (C) screening and -40oC to +125oC for (E) screening (VDD = 5.0V + 10%) SYMBOL PARAMETER 9Q512-25 5.0V MIN MAX UNIT tAVAV1 Write cycle time 20 ns tETWH Device Enable to end of write 20 ns tAVET Address setup time for write (E - controlled) 0 ns tAVWL Address setup time for write (W - controlled) 0 ns tWLWH Write pulse width 20 ns tWHAX Address hold time for write (W - controlled) 2 ns tEFAX Address hold time for Device Enable (E - controlled) 0 ns tWLQZ2 W - controlled three-state time 10 tWHQX W - controlled Output Enable time 4 ns tETEF Device Enable pulse width (E - controlled) 20 ns tDVWH Data setup time 15 ns tWHDX Data hold time 2 ns tWLEF Device Enable controlled write pulse width 20 ns tDVEF Data setup time 15 ns tEFDX Data hold time 2 ns tAVWH Address valid to end of write 20 ns tWHWL1 Write disable time 5 ns Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Functional test performed with outputs disabled (G high). 2. Three-state is defined as 500mV change from steady-state output voltage (see Figure 3). 8 ns A(18:0) tAVAV2 E tAVWH tETWH tWHWL W tAVWL tWLWH tWHAX Q(7:0) tWLQZ D(7:0) tWHQX APPLIED DATA Assumptions: 1. G < VIL (max). If G > VIH (min) then Q(7:0) will be in three-state for the entire cycle. 2. G high for tAVAV cycle. tDVWH tWHDX Figure 5a. SRAM Write Cycle 1: Write Enable - Controlled Access 9 tAVAV3 A(18:0) tETEF tAVET tEFAX E or tAVET E W tETEF tEFAX tWLEF APPLIED DATA D(7:0) tWLQZ tDVEF Q(7:0) tEFDX Assumptions & Notes: 1. G < VIL (max). If G > VIH (min) then Q(7:0) will be in three-state for the entire cycle. 2. Either E scenario above can occur. 3. G high for tAVAV cycle. Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access 10 CMOS 90% VDD-0.05V 300 ohms 10% 0.5V VLOAD = 1.55V 10% < 5ns 50pF < 5ns Input Pulses Notes: 1. 50pF including scope probe and test socket capacitance. 2. Measurement of data output occurs at the low to high or high to low transition mid-point (i.e., CMOS input = VDD/2). Figure 6. AC Test Loads and Input Waveforms 11 DATA RETENTION MODE VDD VDR > 2.5V 4.5V 4.5V tR tEFR E Figure 7. Low VDD Data Retention Waveform DATA RETENTION CHARACTERISTICS (Pre-Radiation)* (VDD = VDD (min), 1 Sec DR Pulse) SYMBOL PARAMETER TEMP MINIMUM MAXIMUM UNIT VDR VDD for data retention -- 2.5 -- V IDDR 1 Data retention current -40oC -- 10 mA -55oC -- 10 mA 25oC -- 10 mA 125oC -- 45 mA Chip select to data retention time -- 0 -- ns Operation recovery time -- tAVAV -- ns tEFR1 tR1 Notes: * Post-radiation performance guaranteed at 25oC per MIL-STD-883 Method 1019. 1. E1 = VDD all other inputs = VDD or VSS. 12 PACKAGING 1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance to MIL-PRF-38535. 4. Dimension are in accordance with MIL-PRF-38535. 5. Lead position and coplanarity are not measured. 6. ID mark symbol is vendor option: no alphanumerics. One or both ID methods ma y be used for Pin 1 ID. 7. Letter designators are in accordance with MIL-STD-1835. 8. Dimensions shown are in inches. Figure 8. 36-pin Ceramic FLATPACK 13 ORDERING INFORMATION 512K x 8 SRAM: UT9Q512E- * * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = Military Temperature Range Flow (P) = Prototype flow (W) = Extended Industrial Temperature Range Flow (-40oC to +125oC) Package Type: (Y) = 36-lead flatpack package (bottom brazed) 20 = 20ns access time, 5.0V operation -Aeroflex Core Part Number Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Prototype flow per Aeroflex Manufacturing Flows Document. Tested at 25C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. Military Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -55C, room temp, and +125C. Radiation neither tested nor guaranteed. 5. Extended Industrial Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -40C to +125C. Radiation neither tested nor guaranteed. 14 512K x 8 SRAM: SMD 5962 - 00536 ** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (Y) = 36-lead ceramic flatpack (bottom-brazed) Class Designator: (V) = QML Class V (Q) = QML Class Q Device Type 01 = 25ns access time, 5.0V operation, Mil-Temp 02 = 25ns access time, 5.0V operation, Extended Industrial Temp (-40C to +125C) 03 = 20ns access time, 5.0V operation, Mil-Temp 04 = 20ns access time, 5.0V operation, Extended Industrial Temp (-40C to +125C) 05 = 20ns access time, 5.0V operation, Mil-Temp 06 = 20ns access time, 5.0V operation, Extended Industrial Temp (-40C to +125C) Drawing Number: 00536 Total Dose: (D) = 1E4 (10 krad)(Si)) (P) = 3E4 (30 krad)(Si)), Contact Factory (L) = 5E4 (50krad(Si)), Contact Factory Federal Stock Class Designator: No options Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3.Total dose radiation must be specified when ordering. 15 Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com Aeroflex Colorado Springs, Inc., reserves the right to make changes to any products and services herein at any time without notice. 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