Data Sheet Mono 2.9 W Class-D Audio Amplifier with Digital Current and Voltage Output SSM4321 FEATURES Filterless Class-D amplifier with spread-spectrum - modulation Digitized output of output voltage, output current, and PVDD supply voltage 72 dB signal-to-noise ratio (SNR) on output current sensing and 77 dB SNR on output voltage sensing TDM or multichip I2S slave output interface Up to 4 chips supported on a single bus 8 kHz to 48 kHz operation I2S/left justified slave output interface 1 or 2 chips supported on a single bus 8 kHz to 48 kHz operation PDM output interface operates from 1 MHz to 6.144 MHz 2.2 W into 4 load and 1.4 W into 8 load at 5.0 V supply with <1% total harmonic distortion plus noise (THD + N) 89% efficiency at 5.0 V, 1.4 W into 8 + 0.2 RSENSE speaker >100 dB signal-to-noise ratio (SNR) High PSRR at 217 Hz: 86 dB Amplifier supply operation from 2.5 V to 5.5 V Input/output supply operation from 1.42 V to 3.6 V Flexible gain adjustment pin: 0 dB to 12 dB in 3 dB steps with fixed input impedance of 80 k <1 A shutdown current Smart power-down with loss of BCLK Short-circuit and thermal protection with autorecovery Available in a 16-ball, 0.4 mm pitch, 1.74 mm x 1.74 mm WLCSP Pop-and-click suppression APPLICATIONS Mobile phones MP3 players Portable electronics GENERAL DESCRIPTION The SSM4321 is a fully integrated, high efficiency, Class-D audio amplifier with digitized output of output voltage, output current, and the PVDD supply voltage. It is designed to maximize performance for mobile phone applications. The application circuit requires a minimum of external components and operates from a 2.5 V to 5.5 V supply for the amplifier and a 1.42 V to 3.6 V supply for input/output. The SSM4321 is capable of delivering 2.2 W of continuous output power with <1% THD + N driving a 4 load from a 5.0 V supply with a 0.1 V/I sense resistor. Rev. 0 The SSM4321 features a high efficiency, low noise modulation scheme that requires no external LC output filters. The modulation scheme provides high efficiency even at low output power. The SSM4321 operates with 89% efficiency at 1.4 W into 8 from a 5.0 V supply with an SNR of >100 dB. The SSM4321 includes circuitry to sense output current, output voltage, and the PVDD supply voltage. Current sense is performed using an external sense resistor that is connected between an output pin and the load. The output current and voltage are sent to ADCs with 16-bit resolution; the PVDD supply voltage is sent to an ADC with 8-bit resolution. The outputs of these ADCs are available on the TDM or I2S output serial port. The SLOT pin is used to determine which of four possible output slots is used on the TDM interface. A stereo I2S interface can be selected by reversing the pin connections for BCLK and FSYNC. Also, a direct PDM bit stream of voltage and current data can be selected via the SLOT pin. Spread-spectrum pulse density modulation (PDM) is used to provide lower EMI-radiated emissions compared with other Class-D architectures. The inherent randomized nature of spread-spectrum PDM eliminates the clock intermodulation (beating effect) of several amplifiers in close proximity. The SSM4321 produces ultralow EMI emissions that significantly reduce the radiated emissions at the Class-D outputs, particularly above 100 MHz. The ultralow EMI emissions of the SSM4321 are also helpful for antenna and RF sensitivity problems. The device includes a highly flexible gain select pin that requires only one series resistor to select a gain setting of 0 dB, 3 dB, 6 dB, 9 dB, or 12 dB. Input impedance is fixed at 80 k, independent of the selected gain. The SSM4321 has a shutdown mode with a typical shutdown current of <1 A. Shutdown is enabled by removing the BCLK input. A clock must be present on the BCLK pin for the part to operate. The device also includes pop-and-click suppression circuitry, which minimizes voltage glitches at the output during turn-on and turn-off, reducing audible noise on activation and deactivation. The SSM4321 is specified over the industrial temperature range of -40C to +85C. It has built-in thermal shutdown and output short-circuit protection. It is available in a halide-free, 16-ball, 0.4 mm pitch, 1.74 mm x 1.74 mm wafer level chip scale package (WLCSP). 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Technical Support www.analog.com SSM4321 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Output Current Sensing ............................................................ 15 Applications ....................................................................................... 1 Output Voltage Sensing ............................................................. 15 General Description ......................................................................... 1 PVDD Sensing ............................................................................ 15 Revision History ............................................................................... 2 Serial Data Input/Output............................................................... 16 Functional Block Diagram .............................................................. 3 TDM Operating Mode .............................................................. 16 Specifications..................................................................................... 4 I2S and Left Justified Operating Mode .................................... 16 Digital Input/Output Specifications........................................... 5 Multichip I2S Operating Mode ................................................. 17 Absolute Maximum Ratings ............................................................ 6 PDM Output Mode .................................................................... 17 Thermal Resistance ...................................................................... 6 Timing Diagrams, TDM Mode ................................................ 18 ESD Caution .................................................................................. 6 Timing Diagrams, I2S and Left Justified Modes ..................... 18 Pin Configuration and Function Descriptions ............................. 7 Timing Diagrams, Multichip I2S Mode ................................... 19 Typical Performance Characteristics ............................................. 8 Timing Diagrams, PDM Mode................................................. 20 Theory of Operation ...................................................................... 14 Applications Information .............................................................. 21 Overview...................................................................................... 14 Layout .......................................................................................... 21 Power-Down Operation ............................................................ 14 Input Capacitor Selection .......................................................... 21 Gain Selection ............................................................................. 14 Power Supply Decoupling ......................................................... 21 Pop-and-Click Suppression ....................................................... 14 Outline Dimensions ....................................................................... 22 Output Modulation Description .............................................. 14 Ordering Guide .......................................................................... 22 EMI Noise .................................................................................... 15 REVISION HISTORY 10/12--Revision 0: Initial Version Rev. 0 | Page 2 of 24 Data Sheet SSM4321 FUNCTIONAL BLOCK DIAGRAM 1.42V TO 3.6V VREG IOVDD 2.5V TO 5.5V GND PVDD PVDD ADC BCLK_TDM/PDM_CLK/LRCLK_I2S FSYNC_TDM/BCLK_I2S SDATAO/PDM_DATA SLOT TDM OUTPUT DIGITAL DECIMATION FILTERING SSM4321 - ADC VOLTAGE SENSE - ADC CURRENT SENSE SENSE- SENSE+ IN- OUT+ - CLASS-D MODULATOR FULL-BRIDGE POWER STAGE GAIN Figure 1. Rev. 0 | Page 3 of 24 OUT- 10752-001 IN+ SSM4321 Data Sheet SPECIFICATIONS PVDD = 5.0 V, IOVDD = 1.8 V, fS = 24 kHz with I2S output, TA = 25C, RL = 8 +33 H, unless otherwise noted. For RL = 8 , use a 200 m V/I sense resistor; for RL = 4 , use a 100 m V/I sense resistor; for RL = 3 , use a 75 m V/I sense resistor. Table 1. Parameter DEVICE CHARACTERISTICS Output Power, RMS Symbol Test Conditions/Comments POUT f = 1 kHz, 20 kHz bandwidth RL = 8 , THD = 1%, PVDD = 5.0 V RL = 8 , THD = 1%, PVDD = 3.6 V RL = 8 , THD = 1%, PVDD = 2.5 V RL = 8 , THD = 10%, PVDD = 5.0 V RL = 8 , THD = 10%, PVDD = 3.6 V RL = 8 , THD = 10%, PVDD = 2.5 V RL = 4 , THD = 1%, PVDD = 5.0 V RL = 4 , THD = 1%, PVDD = 3.6 V RL = 4 , THD = 1%, PVDD = 2.5 V RL = 4 , THD = 10%, PVDD = 5.0 V RL = 4 , THD = 10%, PVDD = 3.6 V RL = 4 , THD = 10%, PVDD = 2.5 V RL = 3 , THD = 1%, PVDD = 5.0 V RL = 3 , THD = 1%, PVDD = 3.6 V RL = 3 , THD = 1%, PVDD = 2.5 V RL = 3 , THD = 10%, PVDD = 5.0 V RL = 3 , THD = 10%, PVDD = 3.6 V RL = 3 , THD = 10%, PVDD = 2.5 V POUT = 1.4 W into 8 , PVDD = 5.0 V POUT = 2.8 W into 3 , PVDD = 5.0 V POUT = 1 W into 8 , f = 1 kHz, PVDD = 5.0 V POUT = 0.5 W into 8 , f = 1 kHz, PVDD = 3.6 V Efficiency Total Harmonic Distortion Plus Noise THD + N Input Common-Mode Voltage Range Common-Mode Rejection Ratio Average Switching Frequency Clock Frequency Differential Output Offset Voltage POWER SUPPLY Supply Voltage Range VCM VCM = 100 mV rms at 1 kHz Guaranteed from PSRR test Power Supply Rejection Ratio PVDD IOVDD PSRRGSM Supply Current, PVDD ISYPVDD ISYIOVDD ISDPVDD ISDIOVDD Typ VRIPPLE = 100 mV at 217 Hz, inputs are ac-grounded, CIN = 0.1 F VIN = 0 V No load, PVDD = 5.0 V No load, PVDD = 3.6 V No load, PVDD = 2.5 V RL = 8 , PVDD = 5.0 V RL = 8 , PVDD = 3.6 V RL = 8 , PVDD = 2.5 V IOVDD = 1.8 V No BCLK, PVDD = 5.0 V No BCLK, IOVDD = 1.8 V Rev. 0 | Page 4 of 24 Unit W W W W W W W W W W W W W W W W W W % % % 0.01 % 50 256 6.2 0.3 Gain = 6 dB Max 1.35 0.70 0.32 1.70 0.86 0.4 2.22 1.12 0.51 2.8 1.42 0.64 3.00 1.51 0.68 3.77 1.90 0.86 89 82 0.01 1.0 CMRRGSM fSW fOSC VOOS Supply Current, IOVDD Shutdown Current, PVDD Shutdown Current, IOVDD Min 2.5 1.42 PVDD - 1 V 5.0 dB kHz MHz mV 5.5 3.6 86 V V dB 3.7 3.1 2.9 3.8 3.2 2.9 0.41 0.1 0.77 mA mA mA mA mA mA mA A A Data Sheet Parameter GAIN CONTROL Closed-Loop Gain Input Impedance SHUTDOWN CONTROL Turn-On Time Turn-Off Time Output Impedance AMPLIFIER NOISE PERFORMANCE Output Voltage Noise Signal-to-Noise Ratio OUTPUT SENSING Output Sampling Rate, TDM BCLK Frequency, TDM Voltage Sense Signal-to-Noise Ratio Voltage Sense Full-Scale Output Voltage Voltage Sense Absolute Accuracy Voltage Sense Gain Drift Current Sense Signal-to-Noise Ratio Current Sense Full-Scale Input Voltage Current Sense Absolute Accuracy Current Sense Gain Drift PVDD Sense Full-Scale Range PVDD Sense Absolute Accuracy Current and Voltage Sense Linearity ADC -3 dB Corner Frequency SSM4321 Symbol Gain ZIN Test Conditions/Comments Min Typ Unit 12 BCLK enabled, fixed input impedance (0 dB to 12 dB) 80 dB k tWU tSD ZOUT From BCLK start From BCLK removal No BCLK 12.5 5 >100 ms s k en SNR f = 20 Hz to 20 kHz, inputs are ac-grounded, gain = 6 dB, A-weighted PVDD = 5.0 V PVDD = 3.6 V POUT = 1.3 W, RL = 8 , A-weighted 30 30 101 V V dB fS fBCLK SNRV LRCLK/FSYNC pulse rate 1 to 4 slots used A-weighted VFS Amplifier voltage with 0 dBFS ADC output SNRI VIS PVFS 0 Max 8 0.512 48 6.144 TA = 10C to 60C A-weighted ISENSE converter voltage with 0 dBFS ADC output TA = 10C to 60C, ideal RSENSE PVDD with full-scale ADC output 77 kHz MHz dB 6 VP 1.5 1 72 % % dB 0.150 VP 3 1 % % V % dB 2 6 3 From -80 dBr to 0 dBr fC 1 Digital high-pass filter Output fS = 48 kHz Output fS = 24 kHz 3.75 1.875 Hz Hz DIGITAL INPUT/OUTPUT SPECIFICATIONS Table 2. Parameter BCLK, FSYNC PINS Input Voltage High Input Voltage Low Input Leakage Current High Input Leakage Current Low Input Capacitance SDATAO/PDM_DATA PIN Output Drive Strength Symbol Test Conditions/Comments Ball D2 and Ball D3 VIH VIL IIH IIL CIN Min Typ 0.7 x IOVDD -0.3 Ball D1 IOVDD = 1.5 V IOVDD = 1.8 V Rev. 0 | Page 5 of 24 3.5 4.5 Max Unit 3.6 0.3 x IOVDD 1 1 5 V V A A pF mA mA SSM4321 Data Sheet ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25C, unless otherwise noted. THERMAL RESISTANCE Table 3. Junction-to-air thermal resistance (JA) is specified for the worst-case conditions, that is, a device soldered in a printed circuit board (PCB) for surface-mount packages. Parameter PVDD Supply Voltage IOVDD Supply Voltage Input Voltage Common-Mode Input Voltage Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) ESD Susceptibility Rating 6V 3.6 V PVDD PVDD -65C to +150C -40C to +85C -65C to +165C 300C 4 kV Table 4. Thermal Resistance Package Type 16-Ball, 1.74 mm x 1.74 mm WLCSP 1 JA1 665 Unit C/W The JA specification is measured on a JEDEC standard 4-layer PCB. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 6 of 24 Data Sheet SSM4321 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 INDICATOR 1 2 3 4 OUT+ OUT- PVDD VREG SENSE+ GAIN GND GND SENSE- SLOT IOVDD IN+ A B C BCLK_TDM/ SDATAO/ FSYNC_TDM/ PDM_CLK/ PDM_DATA BCLK_I2S LRCLK_I2S IN- TOP VIEW (BALL SIDE DOWN) Not to Scale 10752-002 D Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. A1 A2 A3 A4 B1 B2 B3, B4 C1 C2 C3 C4 D1 D2 D3 D4 Mnemonic OUT+ OUT- PVDD VREG SENSE+ GAIN GND SENSE- SLOT IOVDD IN+ SDATAO/PDM_DATA FSYNC_TDM/BCLK_I2S BCLK_TDM/PDM_CLK/ LRCLK_I2S IN- Description Noninverting Output. Inverting Output. Amplifier Power Supply. Internal LDO Regulator Output. Current Sense Positive Input. Gain Control Pin. Ground. Current Sense Negative Input. TDM Slot Selection Input. Input/Output Digital Power Supply. Noninverting Input. TDM Serial Data Output/PDM Data Output. TDM Frame Synchronization Input/I2S Bit Clock Input. TDM Bit Clock Input/PDM Clock Input/I2S LRCLK Input. Inverting Input. Rev. 0 | Page 7 of 24 SSM4321 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS PVDD = 5.0 V, IOVDD = 1.8 V, fS = 24 kHz with I2S output, gain = 6 dB, TA = 25C, unless otherwise noted. For RL = 8 , use a 200 m V/I sense resistor; for RL = 4 , use a 100 m V/I sense resistor; for RL = 3 , use a 75 m V/I sense resistor. 100 100 RL = 8 + 33H RL = 8 + 33H PVDD = 3.6V 10 10 THD + N (%) THD + N (%) PVDD = 2.5V 1 PVDD = 5.0V 0.1 1 0.1 250mW 0.1 1 10 OUTPUT POWER (W) 0.001 10 500mW 100 1k 10k 100k FREQUENCY (Hz) 10752-106 0.01 10752-103 0.001 0.001 Figure 6. THD + N vs. Frequency, PVDD = 5 V, RL = 8 Figure 3. THD + N vs. Output Power into 8 100 1W 0.01 0.01 100 RL = 4 + 15H RL = 4 + 15H PVDD = 3.6V 10 10 THD + N (%) THD + N (%) PVDD = 2.5V 1 0.1 1 2W 0.1 500mW 0.01 0.01 PVDD = 5.0V 0.1 1 10 OUTPUT POWER (W) 10752-104 0.01 0.001 10 1k 10k 100k FREQUENCY (Hz) Figure 7. THD + N vs. Frequency, PVDD = 5 V, RL = 4 Figure 4. THD + N vs. Output Power into 4 100 100 10752-107 1W 0.001 0.001 100 RL = 3 + 7.5H RL = 3 + 7.5H PVDD = 3.6V 10 10 THD + N (%) 0.1 1 2.5W 0.1 2W 0.001 0.001 0.01 PVDD = 5.0V 0.01 0.1 1 OUTPUT POWER (W) 10 1W 0.001 10 100 1k 10k FREQUENCY (Hz) Figure 8. THD + N vs. Frequency, PVDD = 5 V, RL = 3 Figure 5. THD + N vs. Output Power into 3 Rev. 0 | Page 8 of 24 100k 10752-108 0.01 10752-105 THD + N (%) PVDD = 2.5V 1 Data Sheet 100 RL = 8 + 33H 10 THD + N (%) THD + N (%) 10 RL = 8 + 33H 1 0.1 1 0.1 62.5mW 125mW 0.01 0.01 250mW 100 1k 125mW 500mW 10k 100k FREQUENCY (Hz) 0.001 10 10752-109 0.001 10 10k 100k Figure 12. THD + N vs. Frequency, PVDD = 2.5 V, RL = 8 100 RL = 4 + 15H RL = 4 + 15H 10 THD + N (%) 10 THD + N (%) 250mW 1k FREQUENCY (Hz) Figure 9. THD + N vs. Frequency, PVDD = 3.6 V, RL = 8 100 100 10752-112 100 SSM4321 1 1W 0.1 1 500mW 0.1 250mW 0.01 125mW 0.01 250mW 1k 10k 100k FREQUENCY (Hz) 10752-110 100 0.001 10 10k 100k Figure 13. THD + N vs. Frequency, PVDD = 2.5 V, RL = 4 100 RL = 3 + 7.5H RL = 3 + 7.5H 10 THD + N (%) 10 1 0.1 1 0.1 1.2W 125mW 0.01 500mW 0.01 250mW 375mW 0.001 10 100 1k 10k 100k FREQUENCY (Hz) Figure 11. THD + N vs. Frequency, PVDD = 3.6 V, RL = 3 0.001 10 100 1k 10k 100k FREQUENCY (Hz) Figure 14. THD + N vs. Frequency, PVDD = 2.5 V, RL = 3 Rev. 0 | Page 9 of 24 10752-114 750mW 10752-111 THD + N (%) 1k FREQUENCY (Hz) Figure 10. THD + N vs. Frequency, PVDD = 3.6 V, RL = 4 100 100 10752-113 500mW 0.001 10 SSM4321 Data Sheet 3.0 5.0 RL = 4 + 15H 2.5 4.6 THD + N = 10% OUTPUT POWER (W) 4.4 4.2 RL = 4 4.0 3.8 RL = 8 3.6 3.4 THD + N = 1% 1.5 1.0 0.5 3.0 3.5 4.5 4.0 5.0 SUPPLY VOLTAGE (V) 0 2.5 Figure 15. Quiescent Current vs. PVDD Supply Voltage, ADC Sense Enabled 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 10752-118 3.0 2.5 Figure 18. Maximum Output Power vs. PVDD Supply Voltage, RL = 4 3.0 4.0 2.8 RL = 3 + 7.5H 3.5 2.6 3.0 2.4 OUTPUT POWER (W) RL = 8 2.2 RL = 4 2.0 1.8 NO LOAD 1.6 THD + N = 10% 2.5 2.0 THD + N = 1% 1.5 1.0 1.4 0.5 1.2 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) Figure 16. Quiescent Current vs. PVDD Supply Voltage, ADC Sense Disabled 2.0 0 2.5 10752-116 1.0 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 10752-119 QUIESCENT CURRENT (mA) 2.0 NO LOAD 3.2 10752-115 QUIESCENT CURRENT (mA) 4.8 Figure 19. Maximum Output Power vs. PVDD Supply Voltage, RL = 3 0.7 RL = 8 + 33H RL = 8 + 33H 0.6 PVDD = 3.6V SUPPLY CURRENT (A) OUTPUT POWER (W) 1.5 THD + N = 10% 1.0 THD + N = 1% 0.5 0.5 0.4 PVDD = 2.5V PVDD = 5.0V 0.3 0.2 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 4.5 5.0 Figure 17. Maximum Output Power vs. PVDD Supply Voltage, RL = 8 Rev. 0 | Page 10 of 24 0 0 0.5 1.0 1.5 2.0 2.5 OUTPUT POWER (W) Figure 20. Supply Current vs. Output Power into 8 3.0 10752-120 0 2.5 10752-117 0.1 Data Sheet 0.7 SSM4321 100 RL = 4 + 15H PVDD = 3.6V PVDD = 3.6V 80 0.5 EFFICIENCY (%) SUPPLY CURRENT (A) PVDD = 5.0V PVDD = 2.5V 0.6 0.4 PVDD = 2.5V PVDD = 5.0V 0.3 60 40 0.2 20 0.1 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT POWER (W) 0 0.8 1.2 1.6 2.0 2.4 2.8 OUTPUT POWER (W) Figure 21. Supply Current vs. Output Power into 4 0.8 0.4 10752-124 0 RL = 4 + 15H 0 10752-121 0 Figure 24. Efficiency vs. Output Power into 4 100 RL = 3 + 7.5H PVDD = 5.0V PVDD = 3.6V 0.7 PVDD = 3.6V PVDD = 2.5V 80 EFFICIENCY (%) SUPPLY CURRENT (A) 0.6 0.5 PVDD = 5.0V 0.4 PVDD = 2.5V 0.3 60 40 0.2 20 0.1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT POWER (W) RL = 3 + 7.5H 0 0 PVDD = 3.6V PVDD = 2.5V 0.8 1.2 1.6 2.0 2.4 2.8 OUTPUT POWER (W) Figure 22. Supply Current vs. Output Power into 3 100 0.4 10752-125 0 10752-122 0 Figure 25. Efficiency vs. Output Power into 3 0 PVDD = 5.0V RL = 8 + 33H -10 80 -20 CMRR (dB) 60 40 -40 -50 -60 -70 20 -80 0 0 0.3 0.6 0.9 1.2 OUTPUT POWER (W) 1.5 Figure 23. Efficiency vs. Output Power into 8 -100 10 100 1k 10k 100k FREQUENCY (Hz) Figure 26. Common-Mode Rejection Ratio (CMRR) vs. Frequency, PVDD = 5 V, RL = 8 Rev. 0 | Page 11 of 24 10752-126 -90 RL = 8 + 33H 10752-123 EFFICIENCY (%) -30 SSM4321 0 Data Sheet 1.0 RL = 8 + 33H RL = 8 + 33H -10 0.8 PVDD SENSE LEVEL (FS) -20 PSRR (dB) -30 -40 -50 -60 -70 0.6 0.4 0.2 -80 200 2k 20k FREQUENCY (Hz) 0 2.5 10752-127 -100 20 3.5 4.0 4.5 5.0 5.5 PVDD (V) Figure 30. PVDD ADC Sense Level vs. PVDD Range, RL = 8 Figure 27. Power Supply Rejection Ratio (PSRR) vs. Frequency, PVDD = 5 V, RL = 8 0 3.0 10752-130 -90 0 RL = 8 +33H RL = 8 + 33H -10 -20 PVDD = 2.5V -20 -40 THD + N (dBFS) PVDD = 5.0V -80 PVDD = 3.6V -100 -40 48kHz I SENSE -50 24kHz I SENSE -60 -70 24kHz V SENSE -120 48kHz V SENSE -80 -140 -90 100 1k 10k 100k FREQUENCY (Hz) -100 0.01 10752-128 -160 10 0.1 1 10 OUTPUT POWER (W) Figure 28. Output Spectrum vs. Frequency (FFT), POUT = 100 mW, RL = 8 10752-131 SPECTRUM (dBV) -30 -60 Figure 31. Sense ADC THD + N vs. Output Power into 8 0 1.0 RL = 4 + 15H -10 THD + N (dBFS) -30 0 -40 48kHz I SENSE 24kHz V SENSE -50 -60 24kHz I SENSE -70 -0.5 -80 48kHz V SENSE -1.0 -80 -70 -60 -50 -40 -30 -20 INPUT LEVEL (dBr) -10 0 Figure 29. Current Sense Linearity -100 0.01 0.1 1 OUTPUT POWER (W) Figure 32. Sense ADC THD + N vs. Output Power into 4 Rev. 0 | Page 12 of 24 10 10752-132 -90 10752-129 CURRENT SENSE (dBFS) -20 0.5 Data Sheet 0 SSM4321 0 RL = 3 + 7.5H RL = 3 + 7.5H 2W VSENSE 2W ISENSE 1W VSENSE 1W ISENSE 500mW VSENSE 500mW ISENSE -10 -10 -20 -20 THD + N (dBFS) THD + N (dBFS) -30 48kHz I SENSE -40 24kHz V SENSE -50 -60 24kHz I SENSE -70 -80 -30 -40 -50 48kHz V SENSE -60 1 10 OUTPUT POWER (W) -70 20 800mW 800mW 400mW 400mW 200mW 200mW -10 0 VSENSE ISENSE VSENSE ISENSE VSENSE ISENSE -40 -50 -80 -100 -120 -70 -140 2k 20k FREQUENCY (Hz) Figure 34. Sense ADC THD + N vs. Frequency, PVDD = 5 V, RL = 8 0 RL = 4 + 15H -20 -30 -40 -50 -60 200 2k 20k FREQUENCY (Hz) 10752-135 -70 -80 20 -160 10 100 1k 10k 100k FREQUENCY (Hz) Figure 37. Output Spectrum of Sense ADC vs. Frequency (FFT), POUT = 100 mW, RL = 8 2W VSENSE 2W ISENSE 1W VSENSE 1W ISENSE 500mW VSENSE 500mW ISENSE -10 THD + N (dBFS) -60 -60 200 24kHz V SENSE 24kHz I SENSE 48kHz V SENSE 48kHz I SENSE -40 -30 -80 20 RL = 8 +33H -20 10752-134 THD + N (dBFS) -20 20k Figure 36. Sense ADC THD + N vs. Frequency, PVDD = 5 V, RL = 3 SPECTRUM (dBFS) RL = 8 + 33H 2k FREQUENCY (Hz) Figure 33. Sense ADC THD + N vs. Output Power into 3 0 200 Figure 35. Sense ADC THD + N vs. Frequency, PVDD = 5 V, RL = 4 Rev. 0 | Page 13 of 24 10752-137 0.1 10752-133 -100 0.01 10752-136 -90 SSM4321 Data Sheet THEORY OF OPERATION OVERVIEW POP-AND-CLICK SUPPRESSION The SSM4321 mono Class-D audio amplifier features a filterless modulation scheme that greatly reduces the external component count, conserving board space and, thus, reducing system cost. The SSM4321 does not require an output filter but, instead, relies on the inherent inductance of the speaker coil and the natural filtering of the speaker and human ear to fully recover the audio component of the square wave output. Voltage transients at the output of audio amplifiers can occur when shutdown is activated or deactivated. Voltage transients as low as 10 mV can be heard as an audible pop in the speaker. Pops and clicks can also be classified as undesirable audible transients generated by the amplifier system and, therefore, as not coming from the system input signal. Most Class-D amplifiers use some variation of pulse-width modulation (PWM), but the SSM4321 uses - modulation to determine the switching pattern of the output devices, resulting in a number of important benefits. * * * - modulators do not produce a sharp peak with many harmonics in the AM frequency band, as pulse-width modulators often do. - modulation reduces the amplitude of spectral components at high frequencies, thus reducing EMI emissions that might otherwise be radiated by speakers and long cable traces. Due to the inherent spread-spectrum nature of - modulation, the need for oscillator synchronization is eliminated for designs that incorporate multiple SSM4321 amplifiers. The SSM4321 has a pop-and-click suppression architecture that reduces these output transients, resulting in noiseless activation and deactivation. OUTPUT MODULATION DESCRIPTION The SSM4321 uses three-level, - output modulation. Each output can swing from GND to PVDD and vice versa. Ideally, when no input signal is present, the output differential voltage is 0 V because there is no need to generate a pulse. In a real-world situation, noise sources are always present. Due to the constant presence of noise, a differential pulse is generated, when required, in response to this stimulus. A small amount of current flows into the inductive load when the differential pulse is generated. POWER-DOWN OPERATION Most of the time, however, the output differential voltage is 0 V, due to the Analog Devices, Inc., three-level, - output modulation. This feature ensures that the current flowing through the inductive load is small. The SSM4321 contains a clock loss detect circuit that works with the BCLK input clock. When no BCLK is present, the part automatically powers down all internal circuitry to its lowest power state. When a BCLK is returned, the part automatically powers up. When the user wants to send an input signal, an output pulse (OUT+ and OUT-) is generated to follow the input voltage. The differential pulse density (VOUT) is increased by raising the input signal level. Figure 38 depicts three-level, - output modulation with and without input stimulus. The SSM4321 also integrates overcurrent and overtemperature protection. If BCLK is active but FSYNC or LRCLK is not present, the amplifier continues to operate, but the ADC, sense blocks, and digital processing are shut down, reducing quiescent current when the output sense data is not needed. The ADC shutdown feature is not available in PDM operating mode. OUTPUT = 0V +5V OUT+ 0V +5V OUT- 0V +5V VOUT -5V GAIN SELECTION OUTPUT > 0V The gain of the SSM4321 can be set from 0 dB to 12 dB in 3 dB steps using the GAIN pin and one (optional) external resistor. The external resistor is used to select the 9 dB or 12 dB gain setting (see Table 6). +5V OUT+ 0V +5V OUT- 0V +5V VOUT Table 6. Setting the Gain of the SSM4321 with the GAIN Pin GAIN Pin Configuration Tie to GND Open Tie to PVDD Tie to GND through a 47 k resistor Tie to PVDD through a 47 k resistor 0V OUTPUT < 0V +5V OUT+ 0V +5V OUT- 0V 0V VOUT -5V Figure 38. Three-Level, - Output Modulation With and Without Input Stimulus Rev. 0 | Page 14 of 24 10752-015 Gain Setting (dB) 0 3 6 9 12 0V Data Sheet SSM4321 EMI NOISE The SSM4321 uses a proprietary modulation and spread-spectrum technology to minimize EMI emissions from the device. For applications that have difficulty passing FCC Class B emission tests or experience antenna and RF sensitivity problems, the ultralow EMI architecture of the SSM4321 significantly reduces the radiated emissions at the Class-D outputs, particularly above 100 MHz. EMI emission tests on the SSM4321 were performed in an FCCcertified EMI laboratory with a 1 kHz input signal, producing 0.5 W of output power into an 8 load from a 5.0 V supply. The SSM4321 passed FCC Class B limits with 50 cm of unshielded twisted pair speaker cable. Note that reducing the power supply voltage greatly reduces radiated emissions. OUTPUT CURRENT SENSING The SSM4321 uses an external sense resistor to determine the output current flowing to the load. As shown in Figure 1, one end of the sense resistor is tied to one amplifier output pin (OUT+); the other end of the sense resistor is tied to the load, which is also connected to one sense input pin (SENSE-). The voltage across the sense resistor is proportional to the load current and is sent to an analog-to-digital converter (ADC) running nominally at 128 fS. The output of this ADC is downsampled using digital filtering. The downsampled signal is output at a rate of 8 kHz to 48 kHz on Slot 1 of the TDM bus. The 16-bit data is in signed fractional format. The current sense output is scaled so that an output current of 0.75 A (6 V/8 ) with a 200 m sense resistor results in full-scale output from the ADC. Table 7 lists the optimal sense resistor values for commonly used output loads. Table 7. Optimal Sense Resistor for Typical Loads Load Value () 8 4 3 Peak Current (A) 0.75 1.5 2 Sense Resistor (m) 200 100 75 OUTPUT VOLTAGE SENSING The output voltage level is monitored and sent to an ADC running nominally at 128 fS. The output of this ADC is downsampled using digital filtering. The downsampled signal is output at a rate of 8 kHz to 48 kHz on Slot 2 of the TDM bus. The 16-bit data is in signed fractional format. PVDD SENSING The SSM4321 contains an 8-bit ADC that measures the voltage of the PVDD supply in real time. The output of the ADC is in 8-bit unsigned format and is presented on the 8 MSBs of Slot 3 on the TDM bus. The eight LSBs are driven low. Rev. 0 | Page 15 of 24 SSM4321 Data Sheet SERIAL DATA INPUT/OUTPUT The SSM4321 includes circuitry to sense output current, output voltage, and the PVDD supply voltage. The output current, output voltage, and PVDD voltage are sent to ADCs. The output of these ADCs is available on the TDM or I2S output serial port. A direct PDM bit stream of voltage and current data (or current and PVDD data) can also be selected. TDM OPERATING MODE The digitized output current, output voltage, and PVDD sense signals can be output on a TDM serial port. This serial port is always a slave and requires a bit clock (BCLK) and a frame synchronization signal (FSYNC) to operate. The output data is driven on the SDATAO/PDM_DATA pin at the IOVDD voltage. (See the Timing Diagrams, TDM Mode section.) The FSYNC signal operates at the desired sample rate. A rising edge of the FSYNC signal indicates the start of a new frame. For proper operation, this signal should be one BCLK cycle wide, transitioning on a falling BCLK edge. The MSB of the Slot 1 data is output on the SDATAO/PDM_DATA pin one BCLK cycle later. The SDATAO signal should be latched on a rising edge of BCLK. Each slot is 64 BCLK cycles wide. The SSM4321 can drive only four slots on its output, but it can work with 8 slots, 12 slots, or 16 slots. In this way, up to four SSM4321 devices can use the same TDM bus. At startup, the number of slots used is recognized automatically by the number of BCLK cycles between FSYNC pulses. Internal clocking is automatically generated from BCLK based on the determined BCLK rate. The set of four TDM slots to be driven is determined by the configuration of the SLOT pin on the SSM4321 (see Table 8). The value of the SLOT pin must be stable at startup. Table 8. TDM Slot Selection Device Setting TDM Slot 1 to Slot 4 used TDM Slot 5 to Slot 8 used TDM Slot 9 to Slot 12 used TDM Slot 13 to Slot 16 used With a single SSM4321 operating with four slots, Slot 1 is for the output current, Slot 2 is for the output voltage, Slot 3 is for the PVDD supply, and Slot 4 is not driven. With more than four slots, this pattern is repeated. Table 9 shows an example with three SSM4321 devices and 12 TDM slots. Table 9. TDM Output Slot Example--Three SSM4321 Devices TDM Slot 1 2 3 4 5 6 7 8 9 10 11 12 Data Present Output current, Device 1 Output voltage, Device 1 PVDD voltage, Device 1 High-Z Output current, Device 2 Output voltage, Device 2 PVDD voltage, Device 2 High-Z Output current, Device 3 Output voltage, Device 3 PVDD voltage, Device 3 High-Z I2S AND LEFT JUSTIFIED OPERATING MODE An I2S or left justified output interface can be selected by reversing the pin connections for BCLK and FSYNC; that is, the I2S LRCLK is connected to Ball D3 (BCLK_TDM/PDM_CLK/LRCLK_I2S), and the I2S BCLK is connected to Ball D2 (FSYNC_TDM/ BCLK_I2S). The I2S interface requires 64 BCLK cycles per LRCLK cycle. The voltage information is sent when LRCLK is low, and the current information is sent when LRCLK is high. (See the Timing Diagrams, I2S and Left Justified Modes section.) The SLOT pin configures the I2S or left justified output as follows (see Table 10). SLOT Pin Configuration Tie to IOVDD Open Tie to GND Tie to IOVDD through a 47 k resistor * * The SSM4321 sets the SDATAO/PDM_DATA pin to a high impedance state when a slot is present that is not being driven. Connect a pull-down resistor to the SDATAO/PDM_DATA pin so that it is always in a known state. * Selection of I2S or left justified mode. Output of PVDD sense information. When PVDD data is output, eight bits are appended to the 16-bit voltage sense data to create a 24-bit output. The 16 MSBs represent the voltage data; the eight LSBs represent the PVDD data. Sample rate range. The sample rate ranges from 16 kHz to 48 kHz. A range of 32 kHz to 48 kHz is also allowed in low power I2S mode. Table 10. I2S and Left Justified Slot Selection Device Setting I2S mode at 16 kHz to 48 kHz; voltage and current data only Left justified mode at 16 kHz to 48 kHz; voltage and current data only I2S mode at 16 kHz to 48 kHz; PVDD data appended to voltage data Left justified mode at 16 kHz to 48 kHz; PVDD data appended to voltage data Low power I2S mode at 32 kHz to 48 kHz; voltage and current data only Rev. 0 | Page 16 of 24 BCLK Setting 64 x fS 64 x fS 64 x fS 64 x fS 32 x fS or 64 x fS SLOT Pin Configuration Tie to IOVDD Open Tie to GND Tie to IOVDD through a 47 k resistor Tie to GND through a 47 k resistor Data Sheet SSM4321 MULTICHIP I2S OPERATING MODE A special multichip I2S mode is enabled when the part is wired for TDM mode (BCLK and FSYNC not reversed) but the FSYNC signal has a 50% duty cycle. If the FSYNC signal consists of oneclock-cycle pulses, TDM operating mode is active instead. The multichip I2S interface allows multiple chips to drive a single I2S bus. Each chip takes control of the bus every two or four frames (depending on the number of chips placed on the bus), allowing a maximum of four chips on the bus. The SLOT pin assignments determine the order of control. (See the Timing Diagrams, Multichip I2S Mode section.) Each frame also contains a 1-bit ID code, which is appended to the current data in the frame. This code indicates the chip that sent the data for that frame. Table 11 provides the mapping of SLOT pin assignments to ID code. Table 11. Multichip I2S Slot Selection Chip No. 1 2 3 4 ID Code 0001 0010 0100 1000 SLOT Pin Configuration Tie to IOVDD Open Tie to GND Tie to IOVDD through a 47 k resistor The part is automatically configured for two-chip or four-chip operation, depending on the number of chips detected on the bus. The part starts up in four-chip operation, but after it detects that Slot 3 and Slot 4 are unused, the part switches to two-chip operation. For two-chip operation, the first and second slots must be used. If there are three chips on the bus, Slot 1 must be used along with any two other slots. Table 12 lists the FSYNC and BCLK rates that are supported in multichip I2S mode. Table 12. FSYNC and BCLK Rates in Multichip I2S Mode, fS = 16 kHz to 48 kHz Valid Slots 1 and 2 1, 2, 3, 4 FSYNC Rate 2 x fS (32 kHz to 96 kHz) 4 x fS (64 kHz to 128 kHz) BCLK Rate 128 x fS (2.048 MHz to 6.144 MHz) 256 x fS (4.096 MHz to 12.288 MHz) PDM OUTPUT MODE By connecting the SLOT pin to GND through a 47 k resistor, the 1-bit PDM data from the ADCs can be output directly. In PDM mode, a 1 MHz to 6.144 MHz clock must be provided on Ball D3 (BCLK_TDM/PDM_CLK/LRCLK_I2S). PDM data is sent on both edges of the clock and is output on Ball D1 (SDATAO/ PDM_DATA). (See the Timing Diagrams, PDM Mode section.) In PDM mode, Ball D2 (FSYNC_TDM/BCLK_I2S) is used to select the information that is output on the two possible channels (see Table 13). Table 13. FSYNC_TDM Pin Settings for PDM Mode Output Data Current data on rising edge; voltage data on falling edge Current data on rising edge; PVDD data on falling edge Rev. 0 | Page 17 of 24 FSYNC_TDM Pin Tie to IOVDD Tie to GND SSM4321 Data Sheet TIMING DIAGRAMS, TDM MODE TDM Mode, One Device SLOT pin is tied to IOVDD. BCLK_TDM 64 BCLKs CURRENT SDATAO 16 BCLKs VOLTAGE PVDD 16 BCLKs 8 BCLKs 10752-016 FSYNC_TDM Figure 39. TDM Mode, One Device TDM Mode, Two Devices IC 1: SLOT pin is tied to IOVDD; IC 2: SLOT pin is open. BCLK_TDM 128 BCLKs FSYNC_TDM 16 BCLKs CURRENT, IC 1 VOLTAGE, IC 1 8 BCLKs 16 BCLKs PVDD, IC 1 CURRENT, IC 2 16 BCLKs 8 BCLKs VOLTAGE, IC 2 64 BCLKs 10752-017 16 BCLKs SDATAO PVDD, IC 2 64 BCLKs Figure 40. TDM Mode, Two Devices TDM Mode, Three Devices IC 1: SLOT pin is tied to IOVDD; IC 2: SLOT pin is open; IC 3: SLOT pin is tied to GND. BCLK_TDM 192 BCLKs FSYNC_TDM SDATAO 16 BCLKs 8 BCLKs CURRENT, IC 1 VOLTAGE, IC 1 PVDD, IC 1 16 BCLKs 16 BCLKs 8 BCLKs 16 BCLKs CURRENT, IC 2 VOLTAGE, IC 2 PVDD, IC 2 64 BCLKs 16 BCLKs 8 BCLKs CURRENT, IC 3 VOLTAGE, IC 3 PVDD, IC 3 64 BCLKs 64 BCLKs 10752-018 16 BCLKs Figure 41. TDM Mode, Three Devices TIMING DIAGRAMS, I2S AND LEFT JUSTIFIED MODES I2S and Left Justified Modes with Voltage, Current, and PVDD Output, 64 x fS I2S output mode: SLOT pin is tied to GND. Left justified output mode: SLOT pin is tied to IOVDD through a 47 k resistor. BCLK_I2S 64 BCLKs LRCLK_I2S SDATAO LJ VOLTAGE 16 BCLKs VOLTAGE 16 BCLKs PVDD 8 BCLKs PVDD 8 BCLKs CURRENT 16 BCLKs CURRENT 16 BCLKs Figure 42. I2S and Left Justified Modes with Voltage, Current, and PVDD Output, 64 x fS Rev. 0 | Page 18 of 24 10752-019 SDATAO I2S Data Sheet SSM4321 I2S and Left Justified Modes with Voltage and Current Output Only, 64 x fS I2S output mode: SLOT pin is tied to IOVDD (or tied to GND through a 47 k resistor for low power operation at 64 x fS). Left justified output mode: SLOT pin is open. BCLK_I2S 64 BCLKs LRCLK_I2S SDATAO LJ VOLTAGE 16 BCLKs CURRENT 16 BCLKs VOLTAGE 10752-020 SDATAO I2S CURRENT 16 BCLKs 16 BCLKs Figure 43. I2S and Left Justified Modes with Voltage and Current Output Only, 64 x fS I2S Low Power Mode with Voltage and Current Output Only, 32 x fS SLOT pin is tied to GND through a 47 k resistor for low power operation at 32 x fS. BCLK_I2S 32 BCLKs SDATAO I2S VOLTAGE 10752-021 LRCLK_I2S CURRENT 16 BCLKs 16 BCLKs Figure 44. I2S Low Power Mode with Voltage and Current Output Only, 32 x fS TIMING DIAGRAMS, MULTICHIP I2S MODE Multichip I2S Mode with Two Devices on the Bus IC 1: SLOT pin is tied to IOVDD; IC 2: SLOT pin is open. BCLK_TDM 64 BCLKs FSYNC_TDM SDATAO VOLTAGE, IC 1 8 BCLKs 16 BCLKs PVDD, IC 1 16 BCLKs CURRENT, IC 1 ID VOLTAGE, IC 2 8 BCLKs PVDD, IC 2 16 BCLKs CURRENT, IC 2 ID 10752-022 4 BCLKs 4 BCLKs 16 BCLKs 2 Figure 45. Multichip I S Mode with Two Devices on the Bus Multichip I2S Mode with Three or Four Devices on the Bus IC 1: SLOT pin is tied to IOVDD; IC 2: SLOT pin is open; IC 3: SLOT pin is tied to GND; IC 4: SLOT pin is tied to IOVDD through a 47 k resistor. BCLK_TDM 64 BCLKs FSYNC_TDM 4 BCLKs 4 BCLKs 16 BCLKs SDATAO VOLTAGE, IC 1 8 BCLKs PVDD, IC 1 16 BCLKs CURRENT, IC 1 16 BCLKs ID VOLTAGE, IC 2 8 BCLKs PVDD, IC 2 16 BCLKs CURRENT, IC 2 ID BCLK_TDM FSYNC_TDM SDATAO VOLTAGE, IC 3 8 BCLKs PVDD, IC 3 16 BCLKs CURRENT, IC 3 16 BCLKs ID VOLTAGE, IC 4 8 BCLKs PVDD, IC 4 Figure 46. Multichip I2S Mode with Three or Four Devices on the Bus Rev. 0 | Page 19 of 24 16 BCLKs CURRENT, IC 4 ID 10752-023 4 BCLKs 4 BCLKs 16 BCLKs SSM4321 Data Sheet TIMING DIAGRAMS, PDM MODE PDM Mode with Current and Voltage Output SLOT pin is tied to GND through a 47 k resistor; FSYNC_TDM pin is tied to IOVDD. PDM_CLK PDM_DATA I V I V I V I V I V I V I V I V I V I V I V I V I 10752-024 FSYNC_TDM Figure 47. PDM Mode with Current and Voltage Output PDM Mode with Current and PVDD Output SLOT pin is tied to GND through a 47 k resistor; FSYNC_TDM pin is tied to GND. PDM_CLK PDM_DATA I PVDD I PVDD I PVDD I PVDD I PVDD I PVDD I PVDD I PVDD Figure 48. PDM Mode with Current and PVDD Output Rev. 0 | Page 20 of 24 I PVDD I PVDD I PVDD I PVDD I 10752-025 FSYNC_TDM Data Sheet SSM4321 APPLICATIONS INFORMATION LAYOUT INPUT CAPACITOR SELECTION As output power increases, care must be taken to lay out PCB traces and wires properly between the amplifier, load, and power supply. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. Ensure that track widths are at least 200 mil for every inch of track length for lowest DCR, and use 1 oz or 2 oz copper PCB traces to further reduce IR drops and inductance. A poor layout increases voltage drops, consequently affecting efficiency. Use large traces for the power supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. The SSM4321 does not require input coupling capacitors if the input signal is biased from 1.0 V to PVDD - 1.0 V. Input capacitors are required if the input signal is not biased within this recommended input dc common-mode voltage range, if high-pass filtering is needed, or if a single-ended source is used. If high-pass filtering is needed at the input, the input capacitor (CIN) and the input impedance of the SSM4321 (80 k) form a high-pass filter with a corner frequency determined by the following equation: Proper grounding helps to improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. To maintain high output swing and high peak output power, the PCB traces that connect the output pins to the load, as well as the PCB traces to the supply pins, should be as wide as possible to maintain the minimum trace resistances. It is also recommended that a large ground plane be used for minimum impedances. The input capacitor value and the dielectric material can significantly affect the performance of the circuit. Not using input capacitors degrades both the output offset voltage of the amplifier and the dc PSRR performance. In addition, good PCB layout isolates critical analog paths from sources of high interference. Separate high frequency circuits (analog and digital) from low frequency circuits. Properly designed multilayer PCBs can reduce EMI emissions and increase immunity to the RF field by a factor of 10 or more compared with double-sided boards. A multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double-sided board is often disrupted by signal crossover. If the system has separate analog and digital ground and power planes, the analog ground plane should be directly beneath the analog power plane, and, similarly, the digital ground plane should be directly beneath the digital power plane. There should be no overlap between the analog and digital ground planes or between the analog and digital power planes. fC = 1/(2 x 80 k x CIN) POWER SUPPLY DECOUPLING To ensure high efficiency, low total harmonic distortion (THD), and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short-duration voltage spikes. These spikes can contain frequency components that extend into the hundreds of megahertz. The power supply input must be decoupled with a good quality, low ESL, low ESR capacitor, with a minimum value of 4.7 F. This capacitor bypasses low frequency noises to the ground plane. For high frequency transient noises, use a 0.1 F capacitor as close as possible to the PVDD pin of the device. Placing the decoupling capacitors as close as possible to the SSM4321 helps to maintain efficient performance. Rev. 0 | Page 21 of 24 SSM4321 Data Sheet OUTLINE DIMENSIONS 1.780 1.740 SQ 1.700 4 3 2 1 A BALL A1 IDENTIFIER B 1.20 REF C D 0.40 REF TOP VIEW BOTTOM VIEW (BALL SIDE DOWN) (BALL SIDE UP) 0.560 0.500 0.440 SIDE VIEW 0.300 0.260 0.220 SEATING PLANE 0.230 0.200 0.170 07-13-2011-A COPLANARITY 0.05 Figure 49. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16-15) Dimensions shown in millimeters ORDERING GUIDE Model1 SSM4321ACBZ-R7 SSM4321ACBZ-RL EVAL-SSM4321Z 1 2 Temperature Range -40C to +85C -40C to +85C Package Description 16-Ball Wafer Level Chip Scale Package [WLCSP] 16-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board Z = RoHS Compliant Part. This package option is halide free. Rev. 0 | Page 22 of 24 Package Option2 CB-16-15 CB-16-15 Branding Y4E Y4E Data Sheet SSM4321 NOTES Rev. 0 | Page 23 of 24 SSM4321 Data Sheet NOTES (c)2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 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