Document Number: MMA685x
Rev. 5, 03/2012
Freescale Semiconductor
Data Sheet: Technical Data
© 2010-2012 Freescale Semiconductor, Inc. All rights reserved.
Single-Axis SPI Inertial Sensor
MMA685x, a SafeAssure solution, is a SPI-based, single-axis, medium-g, over-
damped lateral accelerometer designed for use in auto motive airbag systems.
Features
• ±20g to ±120g full-scale range
• 3.3V or 5V single supply operation
• SPI-compatible serial interface
• 10-bit digital signed or unsigned SPI data output
• Programmable arming functions
• 12 low-pass filter options, ranging from 50 Hz to 1000 Hz
• Optional offset cancellation with > 6s averaging period and < 0.25 LSB/s slew
rate
• Pb-Free 16-Pin QFN-6 by 6 Package
Referenced Documents
• AECQ100, Revision G, dated May 14, 2007 (http://www.aecouncil.com/)
ORDERING INFORMATION
Device Axis Axis Range Shipping
MMA6851BKW X±25g Tubes
MMA6853BKW X±50g Tubes
MMA6855BKW X±120g Tubes
MMA6856BKW X±60g Tubes
MMA6851BKWR2 X±25g Tape & Reel
MMA6853BKWR2 X±50g Tape & Reel
MMA6855BKWR2 X±120g Tape & Reel
MMA6856BKWR2 X±60g Tape & Reel
16 LEAD QFN
6 mm by 6 mm
CASE 2086-01
Pin Connections
Bottom View
Top View
V
REGA
V
SS
N/C
V
SSA
N/C
V
SSA
TEST/V
PP
MISO
MOSI
SCLK
V
CC
V
SS
V
REG
ARM/PCM
1
2
3
4
5 6 7 8
12
11
10
9
16 15 14 13
CS
N/C
17
MMA685x
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MMA685x
Application Diagram
Figure 1. Application Diagram
Device Orientation
Figure 2. Device Orientation Diagram
Table 1. External Component Recommen dations
Ref Des Type Description Purpose
C1 Ceramic 0.1 μF, 10%, 10V Minimum, X7R VCC Power Supply Decoupling
C2 Ceramic 1 μF, 10%, 10V Minimum, X7R Voltage Regulator Output Capacitor (CREG)
C3 Ceramic 1 μF, 10%, 10V Minimum, X7R Voltage Regulator Output Capacitor (CREGA)
C3C1 C2
VCC
MMA685x
VCC
VREG
VREGA
VSS
VPP/TEST
CS
SCLK
ARM
CS_A
SCLK1
MOSI1
Main MCU
MISO1
CS_D
SCLK2
MOSI2
MISO2
CS
SCLK
MOSI
MISO
Deployment IC
DEPLOY_EN
VSSA
MOSI
MISO
X: 0g
EARTH GROUND
X: +1g X: 0g X: -1g X: 0g X: 0g
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
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Internal Block Diagram
Figure 3. Block Diagram
ΣΔ
Converter
Oscillator
8 MHz
1
MHz
Regulator
Digital
X-Axis g-Cell
Over-Damped
SINC Filter Compensation
Low-Pass Filter Cancellation
Offset
ARM_X
V
REGA
V
REG
Monitoring
Clock
V
REGA
V
REG
V
CC
IIR
V
PP
V
CC
V
REG
V
SS
V
REGA
V
SSA
ARM
CS
SCLK
MOSI
MISO
Odd Register
Array
Generation
Clock CRC
I/O
SPI
Mismatch
SPI
Even Register
Array
Verification
Clock & bias
Generator
SPI
Odd
Register
SPI
Even
Register
OTP
Array Memory
Analog
Regulator
Self
Test Voltage
Monitoring
Linear
Interpolation Output
Scaling
Offset
Monitor
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MMA685x
1 Pin Connections
Figure 4. 16-Pin QFN Package, Top View
Table 2. Pin Description
Pin Pin
Name Formal Name Definition
1 VREGA Analog
Supply This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be
connected between this pin and VSSA. Reference Figure 1.
2 VSS Digital GND This pin is the power supply return node for the digital circuitry.
3 VREG Digital
Supply This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be
connected between this pin and VSS. Reference Figure 1.
4 VSS Digital GND This pin is the power supply return node for the digital circuitry.
5 N/C No Connect No Connection
6ARM/
PCM Arm Output /
PCM Output
The function of this pin is configurable via the DEVCFG register as described in Section 3.1.6.5. When the
arming output is selected, ARM can be configured as an open drain, active low output with a pullup current; or
an open drain, active high output with a pulldown current. Alternatively, this pin can be configured as a digital
output with a PCM signal proportional to the acceleration data. Reference Section 3.8.9 and Section 3.8.10. If
unused, this pin must be left unconnected.
7TEST/
VPP
Programming
Voltage This pin provides the power for factory programming of the OTP registers. This pin must be connected to VSS
in the application.
8MISO SPI Data Out This pin functions as the serial data output for the SPI port.
9 VCC Supply This pin supplies power to the device. An external capacitor must be connected between this pin and VSS.
Reference Figure 1.
10 SCLK SPI Clock This input pin provides the serial clock to the SPI port. An internal pulldown device is connected to this pin.
11 MOSI SPI Data In This pin functions as the serial data input to the SPI port. An internal pulldown device is connected to this pin.
12 CS Chip Select This input pin provides the chip select for the SPI port. An internal pullup device is connected to this pin.
13 VSSA Analog GND This pin is the power supply return node for analog circuitry.
14 N/C No Connect No Connection
15 N/C No Connect No Connection
16 VSSA Analog GND This pin is the power supply return node for analog circuitry.
17 PAD Die Attach
Pad This pin is the die attach flag, and is internally connected to VSS.
Corner
Pads Corner Pads The corner pads are internally connected to VSS.
V
REGA
V
SS
N/C
V
SSA
N/C
V
SSA
TEST/V
PP
MISO
MOSI
SCLK
V
CC
V
SS
V
REG
ARM/PCM
1
2
3
4
5678
12
11
10
9
16 15 14 13
CS
N/C
17
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2 Electrical Characteristics
2.1 Maximum Rati ngs
Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it.
2.2 Operating Range
The operating ratings are the limits normally expected in the application and define the range of operation.
# Rating Symbol Value Unit
1Supply Voltage VCC -0.3 to +7.0 V(3)
2 CREG, CREGA VREG -0.3 to +3.0 V(3)
3SCLK, CS, MOSI,VPP/TEST VIN -0.3 to VCC + 0.3 V(3)
4ARM VIN -0.3 to VCC + 0.3 V(3)
5MISO (high impedance state) VIN -0.3 to VCC + 0.3 V(3)
6Acceleration without hitti ng internal g-cell stops ggcell_Clip ±500 g(3, 18)
7Acceleration without saturation of internal circuitry gADC_Clip ±375 g(3)
8Powered Shock (six sides, 0.5 ms duration) gpms ±1500 g(5, 18)
9Unpowered Shock (six sides, 0.5 ms duration) gshock ±2000 g(5, 18)
10 Drop Shock (to concrete surface) hDROP 1.2 m(5)
11
12
13
Electrostatic Discharge
Human Body Model (HBM)
Charge Device Model (CDM)
Machine Model (MM)
VESD
VESD
VESD
±2000
±750
±200
V
V
V
(5)
(5)
(5)
14 Storage Temperature Range Tstg -40 to +125 °C (5)
15 Thermal Resistance - Junction to Case qJC 2.5 °C/W (14)
# Characteristic Symbol Min Typ Max Units
16
17
Supply Voltage
Standard Operating Voltage, 3.3V
Standard Operating Voltage, 5.0V VCC VL
+3.135 VTYP
+3.3
+5.0
VH
+5.25 V
V(15)
(15)
18 Operating Ambient Temperature Range
Verified by 100% Final Test TATL
-40 ⎯TH
+105 C (1)
20 Power-on Ramp Rate (VCC)V
CC_r 0.000033 ⎯3300 V/μs (19)
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2.3 Electrical Characteristics - Power Supply and I/O
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified
# Characteristic Symbol Min Typ Max Units
21 Supply Current * IDD 3.0 ⎯7.0 mA (1)
22
23
24
25
26
27
28
29
Power Supply Monitor Thresholds (See Figure 8)
VCC Undervoltage (Falling)
VREG Undervoltage (Falling)
VREG Overvoltage (Rising)
VREGA Undervoltage (Falling)
VREGA Overvoltage (Rising)
Power Supply Monitor Hysteresis
VCC Undervoltage (Falling)
VREG Undervoltage, VREG Overvoltage
VREGA Undervoltage, VREGA Overvoltage
*
*
*
*
*
VCC_UV_f
VREG_UV_f
VREG_OV_r
VREGA_UV_f
VREGA_OV_r
VHYST
VHYST
VHYST
2.74
2.10
2.65
2.20
2.65
65
20
20
⎯
⎯
⎯
⎯
⎯
100
100
100
3.02
2.25
2.85
2.35
2.85
110
210
150
V
V
V
V
V
mV
mV
mV
(3, 6)
(3, 6)
(3, 6)
(3, 6)
(3, 6)
(3)
(3)
(3)
30
31
32
Power Supply RESET Thresholds
(See Figure 5, and Figure 8)
VREG Undervoltage RESET (Falling)
VREG Undervoltage RESET (Rising)
VREG RESET Hysteresis
*
*VREG_UVR_f
VREG_UVR_r
VHYST
1.764
1.876
80
⎯
⎯
⎯
2.024
2.152
140
V
V
mV
(3, 6)
(3, 6)
(3)
33
34
Internally Regulated Voltages
VREG
VREGA *
*VREG
VREGA 2.42
2.42 2.50
2.50 2.58
2.58 V
V(1, 3)
(1, 3)
35
36
Extern al F i lter Capacitor (CREG, CREGA)
Value
ESR (including interconnect resistance) CREG
ESR 700
⎯1000
⎯1500
400 nF
mΩ(19)
(19)
37
38
Power Supply Coupling
50 kHz ≤ fn ≤ 300 kHz
4 MHz ≤ fn ≤ 100 MHz ⎯
⎯
⎯
⎯0.004
0.004 LSB/mv
LSB/mv (19)
(19)
39
40
Output High Voltage (MISO, PCM)
3.15V ≤ (VCC - VSS) ≤ 3.45V (ILoad = -1 mA)
4.75V ≤ (VCC - VSS) ≤ 5.25V (ILoad = -1 mA) *
*VOH_3
VOH_5 VCC - 0.2
VCC - 0.4 ⎯
⎯
⎯
⎯V
V(2, 3)
(2, 3)
41
42
Output Low Voltage (MISO, PCM)
3.15V ≤ (VCC - VSS) ≤ 3.45V (ILoad = 1 mA)
4.75V ≤ (VCC - VSS) ≤ 5.25V (ILoad = 1 mA) *
*VOL_3
VOL_5
⎯
⎯
⎯
⎯0.2
0.4 V
V(2, 3)
(2, 3)
43
44
Open Drain Output High Voltage (ARM)
3.15V ≤ (VCC - VSS) ≤ 3.45V (IARM = -1 mA)
4.75V ≤ (VCC - VSS) ≤ 5.25V (IARM = -1 mA) *
*VODH_3
VODH_5 VCC - 0.2
VCC - 0.4 ⎯
⎯
⎯
⎯V
V(2, 3)
(2, 3)
45
46
Open Drain Output Pulldown Current (ARM)
3.15V ≤ (VCC - VSS) ≤ 3.45V (VARM = 1.5 V)
4.75V ≤ (VCC - VSS) ≤ 5.25V (VARM = 1.5 V) *
*IODPD_3
IODPD_5 50
50 ⎯
⎯100
100 μA
μA(2, 3)
(2, 3)
47
48
Open Drain Output Low Voltage (ARM)
3.15V ≤ (VCC - VSS) ≤ 3.45V (IARM = 1 mA)
4.75V ≤ (VCC - VSS) ≤ 5.25V (IARM = 1 mA) *
*VODH_3
VODH_5
⎯
⎯
⎯
⎯0.2
0.4 V
V(2, 3)
(2, 3)
49
50
Open Drain Output Pullup Current (ARM)
3.15V ≤ (VCC - VSS) ≤ 3.45V (VARM = 1.5 V)
4.75V ≤ (VCC - VSS) ≤ 5.25V (VARM = 1.5 V) *
*IODPU_3
IODPU_5 -100
-100 ⎯
⎯-50
-50 μA
μA(2, 3)
(2, 3)
51 Input High Voltage CS, SCLK, MOSI * VIH 2.0 ⎯⎯V(3, 6)
52 Input Low Voltage CS, SCLK, MOSI * VIL ⎯⎯1.0 V (3, 6)
53 Input Voltage Hysteresis CS, SCLK, MOSI * VI_HYST 0.125 ⎯0.500 V (19)
54
55
Input Current
High (at VIH) (S CL K, MOSI)
Low (at VIL) (CS)*
*IIH
IIL -260
30 -50
50 -30
260 μA
μA(2, 3)
(2, 3)
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2.4 Electrical Characteristics - Sensor and Signal Chain
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified
# Characteristic Symbol Min Typ Max Units
56
57
58
59
Digital Sensitivity (SPI, 10 -Bit Output)
25g (MMA6851)
50g (MMA6853)
60g (MMA6856)
120g (MMA6855)
*
*
*
*
SENS
SENS
SENS
SENS
⎯
⎯
⎯
⎯
20.479
9.766
8.192
4.096
⎯
⎯
⎯
⎯
LSB/g
LSB/g
LSB/g
LSB/g
(1, 9)
(1, 9)
(1, 9)
(1, 9)
60
61
67
Sensitivity Error
TA = 25°C
-40°C ≤ TA ≤ 105°C
-40°C ≤ TA ≤ 105°C,VCC_UV_f ≤ VCC - VSS ≤ VL
*
*ΔSENS
ΔSENS
ΔSENS
-4
-5
-5
⎯
⎯
⎯
+4
+5
+5
%
%
%
(1)
(1)
(3)
68
69
70
71
Offset at 0g (No Offset Cancellation)
10-Bits, unsigned
10-Bits, signed
10-Bits, unsigned, VCC_UV_f ≤ VCC - VSS ≤ VL
10-Bits, signed, VCC_UV_f ≤ VCC - VSS ≤ VL
*
*OFFSET
OFFSET
OFFSET
OFFSET
452
-60
452
-60
512
0
512
0
572
+60
572
+60
LSB
LSB
LSB
LSB
(1)
(1)
(3)
(3)
72
73
Offset Monitor Thresholds
Positive Threshold (10-Bits, unsigned)
Negative Threshold (10-Bits, unsigned) OFFTHRPOS
OFFTHRNEG —
—612
412 —
—LSB
LSB (7)
(7)
74
75
76
77
Range of Output (SPI, 10-Bits, unsigned)
Normal
Fault Response Code
Unused Codes
Unused Codes
RANGE
FAULT
UNUSED
UNUSED
32
—
1
993
—
0
—
—
992
—
31
1023
LSB
LSB
LSB
LSB
(7)
(7)
(7)
(7)
78
79
80
81
Range of Output (SPI, 10-Bits, signed)
Normal
Fault Response Code
Unused Codes
Unused Codes
RANGE
FAULT
UNUSED
UNUSED
-480
—
-511
481
—
-512
—
—
480
—
-481
511
LSB
LSB
LSB
LSB
(7)
(7)
(7)
(7)
82 Nonlinearity * NLOUT -1 — 1 % FSR (3)
83
84
System Output Noise
RMS (10-Bit, All Ranges, 400 Hz, 4-pole LPF)
Peak to Peak (10-Bit, All Ranges, 400 Hz, 4-pole LPF) nRMS
nP-P —
——
—0.5
1.0 LSB
LSB (3)
(3)
85
86
Cross-Axis Sensitivity
VZX
VYX *
*VZX
VYX -4
-4 —
—+4
+4 %
%(3)
(3)
87
88
89
90
91
92
Self-Test Output Change (Ref Section 3.6)
STMAG = 0, TA = 25°C
STMAG = 0, -40°C ≤ TA ≤ 105°C
STMAG = 1, TA = 25°C
STMAG = 1, -40°C ≤ TA ≤ 105°C
STMAG = 0, -40°C ≤ TA ≤ 105°C
VCC_UV_f ≤ VCC - VSS ≤ VL
STMAG = 1, -40°C ≤ TA ≤ 105°C
VCC_UV_f ≤ VCC - VSS ≤ VL
*
*
*
*
ΔSTLow25
ΔSTLow
ΔSTHI25
ΔSTHI
ΔSTLow
ΔSTHI
ΔSTMIN
11.25
10.68
22.5
21.37
10.68
21.37
ΔSTNOM
15
15
30
30
15
30
ΔSTMAX
18.75
19.69
37.5
39.38
19.69
39.38
g
g
g
g
g
g
(1)
(1)
(1)
(1)
(3)
(3)
93 Acceleration (without hitting internal g-cell stops)
Any Range Positive/Negative gg-cell_Clip 500 560 600 g (19)
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MMA685x
2.5 Dynamic Electrical Characteristics - Signal Chain
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified
# Characteristic Symbol Min Typ Max Units
94
95
96
DSP Sample Rate (LPF 0,1,2,3,4,5)
DSP Sample Rate (LPF 8,9,10 ,11,12,13)
Interpolation Sample Rate
tS
tS
tINTERP
⎯
⎯
⎯
64/fOSC
128/fOSC
tS/2
⎯
⎯
⎯
s
s
s
(7)
(7)
(7)
97
98
Datapath Latency (excluding g-cell and Low Pass Filter)
TS = 64/fOSC
TS = 128/fOSC *
*tDataPath_8
tDataPath_16 33.0
51.9 34.8
54.6 36.5
57.4 μs
μs(7, 16)
(7, 16)
99
100
101
102
103
104
Low-Pass Filter (ts = 8 μs)
Cutoff frequency 0: 100 Hz, 4-pole
Cutoff frequency 1: 300 Hz, 4-pole
Cutoff frequency 2: 400 Hz, 4-pole
Cutoff frequency 3: 800 Hz, 4-pole
Cutoff frequency 4: 1000 Hz, 4-pole
Cutoff frequency 5: 400 Hz, 3-pole
*
*
*
*
*
*
fC0(LPF)
fC1(LPF)
fC2(LPF)
fC3(LPF)
fC4(LPF)
fC5(LPF)
95
285
380
760
950
380
100
300
400
800
1000
400
105
315
420
840
1050
420
Hz
Hz
Hz
Hz
Hz
Hz
(3, 7, 17)
(7, 17)
(7, 17)
(7, 17)
(7, 17)
(7, 17)
105
106
107
108
109
110
Low-Pass Filter (ts = 16μs)
Cutoff frequency 8: 50 Hz, 4-pole
Cutoff frequency 9: 150 Hz, 4-pole
Cutoff frequency 10: 200 Hz, 4-pole
Cutoff frequency 11: 400 Hz, 4-pole
Cutoff frequency 12: 500 Hz, 4-pole
Cutoff frequency 13: 200 Hz, 3-pole
*
*
*
*
*
*
fC8(LPF)
fC9(LPF)
fC10(LPF)
fC11(LPF)
fC12(LPF)
fC13(LPF)
47.5
142.5
190
380
475
190
50
150
200
400
500
200
52.5
157.5
210
420
525
210
Hz
Hz
Hz
Hz
Hz
Hz
(7, 17)
(7, 17)
(7, 17)
(7, 17)
(7, 17)
(7, 17)
111
112
113
114
115
116
117
Offset Cancellation (Normal Mode, 10-Bit Output)
Offset Averaging Period
Offset Slew Rate
Offset Update Rate
Offset Correction Value per Update Positive
Offset Correction Value per Update Negative
Offset Correction Threshold Positive
Offset Correction Threshold Negative
*
*
*
*
*
*
*
OFFAVEPER
OFFSLEW
OFFRATE
OFFCORRP
OFFCORRN
OFFTHP
OFFTHN
⎯
⎯
⎯
⎯
⎯
⎯
⎯
6.291456
0.2384
1049
0.25
-0.25
0.125
0.125
⎯
⎯
⎯
⎯
⎯
⎯
⎯
s
LSB/s
ms
LSB
LSB
LSB
LSB
(7)
(7)
(7)
(7)
(7)
(7)
(7)
118 Offset Monitor Bypass Time after Self-Test Deactivation tST_OMB ⎯320 ⎯tS(3, 7)
119 Time Between Acceleration Data Requests tACC_REQ 15 ⎯⎯μs (3, 7, 20)
120
121
122
Arming Output Activation Time (ARM, IARM = 200 μA)
Moving Average and Count Arming Modes (2,3, 4,5)
Unfiltered Mode Activation Delay (Reference Figure 28)
Unfiltered Mode Arm Assertion Time (Reference Figure 28)
tARM
tARM_UF_DLY
tARM_UF_ASSERT
0
0
5.00
⎯
⎯
⎯
1.05
1.05
6.579
μs
μs
μs
(3, 12)
(3, 12)
(3)
123 Sensing Element Natural Frequency (-40°C ≤ TA ≤ 105°C) fgcell 10791 ⎯15879 Hz (19)
124 Sensing Element Cutoff Frequency (-3 dB ref. to 0 Hz, -40°C ≤ TA ≤ 105°C) fgcell 0.851 ⎯2.29 kHz (19)
125 Sensing Element Damping Ra tio (-40°C ≤ TA ≤ 105°C) ζgcell 2.46 ⎯9.36 ⎯(19)
126 Sensing Element Delay (@100 Hz, -40°C ≤ TA ≤ 105°C) fgcell_delay 70 ⎯187 μs (19)
127 Package Resonance Frequency fPackage 100 ⎯⎯kHz (19)
128 Package Quality Factor qPackage 1⎯5 (19)
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MMA685x
2.6 Dynamic Electrical Characteristics - Supply and SPI
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified
1. Parameters tested 100% at final test.
2. Parameters tested 100% at wafer probe.
3. Parameters verified by characterization
4. (*) Indicates a critical characteristic.
5. Verified by qualification testing.
6. Parameters verified by p ass/fail testing in production.
7. Functionality guaranteed by modeling, simulation and/or design verification. Circuit integrity assured through IDDQ and scan testing. Timing is deter-
mined by internal system clock frequency.
8. N/A
9. Devices are trimmed at 100 Hz with 1000 Hz low-pass filter option selected. Response is corrected to 0 Hz response.
10. Low-pass filter cutoff frequencies shown are -3dB referenced to 0 Hz response.
11. Power supply ripple at frequencies greater than 900 kHz should be minimized to the greatest extent possible.
12. Time from falling edge of CS to ARM output valid.
13. N/A
14. Thermal resistance bet ween the die junction and the exposed pad; cold plate is attached to the exposed pad.
15. Device characterized at all values of VL and VH. Production test is conducted at all typical voltages (VTYP) unless otherwise noted.
16. Data path Latency is the signal latency from g-cell to SPI output disregarding filter group delays.
17. Filter characteristics are specified independently, and do not include g-cell frequency response.
18. Electrostatic Deflection Test completed during wafer probe.
19. Verified by simulation.
20. Acceleration Data Request timing constraint only applies for proper operation of the Arming Function.
#Characteristic Symbol Min Typ Max Units
129
130 Power-On Recovery Time (VCC = VCCMIN to first SPI access)
Power-On Recovery Time (Internal POR to first SPI access) tOP
tOP
⎯
⎯
⎯
⎯10
840 ms
μs(3)
(3, 7)
131
132 Internal Oscillator Frequency
Test Frequency - Divided from Internal Oscillator * fOSC
fOSCTST 7.6
0.95 8
18.4
1.05 MHz
MHz (7)
(1)
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
Serial Interface Timing (See Figure 6, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)
Clock (SCLK) period (10% of VCC to 10% of VCC)
Clock (SCLK) high time (90% of VCC to 90% of VCC)
Clock (SCLK) low time (10% of VCC to 10% of VCC)
Clock (SCLK) rise time (10% of VCC to 90% of VCC)
Clock (SCLK) fall time (90% of VCC to 10% of VCC)
CS asserted to SCLK high (CS = 10% of VCC to SCLK = 10% of VCC)
CS asserted to MISO valid (CS = 10% of VCC to MISO = 10/90% of VCC)
Data setup time (MOSI = 10/90% of VCC to SCLK = 10% of VCC)
MOSI Data hold time (SCLK = 90% of VCC to MOSI = 10/90% of VCC)
MISO Data hold time (SCLK = 90% of VCC to MISO = 10/90% of VCC)
SCLK low to data valid (SCLK = 10% of VCC to MISO = 10/90% of VCC)
SCLK low to CS high (SCLK = 10% of VCC to CS = 90% of VCC)
CS high to MISO disable (CS = 90% of VCC to MISO = Hi Z)
CS high to CS low (CS = 90% of VCC to CS = 90% of VCC)
SCLK low to CS low (SCLK = 10% of VCC to CS = 90% of VCC)
CS high to SCLK high (CS = 90% of VCC to SCLK = 90% of VCC)
*
*
*
*
*
*
*
*
*
*
*
*
*
tSCLK
tSCLKH
tSCLKL
tSCLKR
tSCLKF
tLEAD
tACCESS
tSETUP
tHOLD_IN
tHOLD_OUT
tVALID
tLAG
tDISABLE
tCSN
tCLKCS
tCSCLK
120
40
40
⎯
⎯
60
⎯
20
10
0
⎯
60
⎯
526
60
60
⎯
⎯
⎯
15
15
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
40
28
⎯
60
⎯
⎯
⎯
40
⎯
60
⎯
⎯
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3)
(3)
(3)
(19)
(19)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(19)
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10 Freescale Semiconductor, Inc.
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Figure 5. Power-Up Timing
Figure 6. Serial Interface Timing
VCC
POR
VREGA
VREG
DEVRES
VCC_UV_f
VREGA_UV_f
DEVRES Flag Cleared by User
VCC_UV_r
VREGA_UV_r
VREG_UVR_r VREG_UVR_f
Time
Note: VREGA & VREG rise and fall slopes will be dependent
on output capacitance and load curren t
tSCLK
SCLK
MOSI
CS
MISO
tSCLKH
tSCLKL
tACCESS
tSCLKR tSCLKF
tLEAD tCSN
tSETUP
tHOLD_IN
tVALID tDISABLE
tHOLD_OUT
tLAG tCLKCS
tCSCLK
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3 Functional Description
3.1 Customer Accessible Data Array
A customer accessible data array allows for each device to be customized. The array consists of an OTP factory programma-
ble block and read/write registers for device programmability and st atus. The OTP and writable register blocks incorporate inde-
pendent CRC circuitry for fault detection (reference Section 3.2). The writable register block includes a locking mechanism to
prevent unintended changes during normal operation. Portions of the array are reserved for factory-programmed trim values. The
customer accessible data is shown in Table 3.
Type codes
F: Factory programmed OT P location
R/W: Read/write register
R: Read-only register
N/A: Not applicable
Table 3. Customer Accessible Data
Location Bit Function Type
Addr Register 76543210
$00 SN0 SN[7] SN[6] SN[5] SN[4] SN[3] SN[2] SN[1] SN[0]
F
$01 SN1 SN[15] SN[14] SN[13] SN[12] SN[11] SN[10] SN[9] SN[8]
$02 SN2 SN[23] SN[22] SN[21] SN[20]SN[19]SN[18]SN[17]SN[16]
$03 SN3 SN[31] SN[30] SN[29] SN[28] SN[27] SN[26] SN[25] SN[24]
$04 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
$05 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
$06 FCTCFG STMAG 0 0 0 0 0 0 0
$07 Invalid Address: “Invalid Register Request”
$08 PN PN[7] PN[6] PN[5] PN[4] PN[3] PN[2] PN[1] PN[0]
$09 Invalid Address: “Invalid Register Request”
$0A DEVCTL RES_1 RES_0 Reserved Reserved Reserved Reserved Reserved Reserved
R/W
$0B DEVCFG Reserved Reserved ENDINIT SD OFMON A_CFG[2] A_CFG[1] A_CFG[0]
$0C DEVCFG_X ST Reserved Reserved Reserved LPF[3] LPF[2] LPF[1] LPF[0]
$0D Invalid Address: “Invalid Register Request”
$0E ARMCFG Reserved Reserved APS[1] APS[0] AWS_N[1] AWS_N[0] AWS_P[1] AWS_P[0]
$0F Invalid Address: “Invalid Register Request”
$10 ARMT_P AT_P[7] AT_P[6] AT_P[5] AT_P[4] AT_P[3] AT_P[2] AT_P[1] AT_P[0]
$11 Invalid Address: “Invalid Register Request”
$12 ARMT_N AT_N[7] AT_N[6] AT_N[5] AT_N[4] AT_N[3] AT_N[2] AT_N[1] AT_N[0]
$13 Invalid Address: “Invalid Register Request”
$14 DEVSTAT UNUSED IDE SDOV DEVINIT MISOERR 0 OFFSET DEVRES
R
$15 COUNT COUNT[7] COUNT[6] COUNT[5] COUNT[4] COUNT[3] COUNT[2] COUNT[1] COUNT[0]
$16 OFFCORR_X OFFCORR_X[7] OFFCORR_X[6] OFFCORR_X[5] OFFCORR_X[4] OFFCORR_X[3] OFFCORR_X[2] OFFCORR_X[1] OFFCORR_X[0]
$17 Invalid Address: “Invalid Register Request”
$1C Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
$1D Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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3.1.1 Device Serial Number Registers
A unique serial number is programmed into the serial number registers of each MMA685x device during manufacturing. The
serial number is composed of the following information:
Serial numbers begin at 1 for all produced devices in each lot, and are sequentially assigned. Lot numbers begin at 1 and are
sequentially assigned. No lot will contain more devices than can be uniquely identified by the 13-bit serial number . Depending on
lot size and quantities, all possible lot numbers and seri al numbers may not be assigned.
The serial number registe r s are included in the OTP shadow registe r arra y CRC verification. Reference Section 3.2.1 for de-
tails regarding the CRC verification. Beyond this, the contents of the serial number registers have no impact on device operation
or performance, and are only used for traceability purposes.
3.1.2 Reserved Registers
These reserved registers are read-only and have no impact on device operation or performance.
3.1.3 Factory Configuration Registers
The factory configuration register is a one time programmable, read only register which contains customer specific device con-
figuration information that is programmed by Freescale.
3.1.3.1 Self-Test Magnitude Selection Bits (STMAG)
The self-test magnitude selection bits indicate if the nominal self-test deflection value is set to the low or high value as shown
in the table below.
Bit Range Content
S12 - S0 Serial Number
S31 - S13 Lot Number
Table 4. Reserved Registers
Location Bit
AddressRegister76543210
$04 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
$05 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Table 5. Factory Configuration Register
Location Bit
AddressRegister76543210
$06FCTCFGSTMAG0000000
STMAG Full-Scale
Acceleration Range Nominal Self-Test Deflection Value
(Reference Section 2.4)
0≤ 60g ΔSTLow
1 > 60g ΔSTHI
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3.1.4 Part Number Register (PN)
The part number register is a one time programmable, read onl y regi ster whi ch con t a ins two digits of the device part number
to identify the axis and range informa tio n. The contents of this register have no impact on device operation or performance.
3.1.5 Device Control Register (DEVCTL)
The device control register is a read-write register which contains device control operations that can be applied during both
initialization and normal operation .
3.1.5.1 Reset Control (RES_1, RES_0)
A series of three consecutive register write operations to the reset control bits in the DEVCTL register will cause a device reset.
To reset the internal digital circuitry, the following register write operations must be performed in the order shown below . The reg-
ister write operations must be consecutive SPI commands in the order shown or the device will not be reset.
The response to the Register Write returns ‘0’ for RES_1 and RES_0. A Register Read of RES_1 and RES_0 returns ‘0’ and
terminates the reset sequence.
3.1.5.2 Reserved Bits (DEVCTL[5:0])
Bits 5 through 0 of the DEVCTL register are reserved. A write to the reserved bits must always be logic ‘0’ for normal device
operation and performance.
Table 6. Part Number Register
Location Bit
AddressRegister76543210
$08 PN PN[7] PN[6] PN[5] PN[4] PN[3] PN[2] PN[1] PN[0]
PN Register Value Range
Reference Section 2.4
Decimal HEX
51 $33 20
52 $34 35
53 $35 50
54 $36 75
55 $37 100
56 $38 60
Table 7. Device Control Register
Location Bit
AddressRegister76543210
$0A DEVCTL RES_1 RES_0 Reserved Reserved Reserved Reserved Reserved Reserved
Reset Value 00000000
Register Write to DEVCTL RES_1 RES_0 Effect
SPI Register Write 1 0 0 No Effect
SPI Register Write 2 1 1 No Effect
SPI Register Write 3 0 1 Device RESET
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3.1.6 Device Configuration Register (DEVCFG)
The device configuration register is a read/write register which contains data for general device configuration. The register can
be written during initialization but is locked once the ENDINIT bit is set. This register is included in the writable register CRC
check. Refer to Section 3.2.2 for details.
3.1.6.1 Reserved Bits (Reserved)
Bits 6 and 7 of the DEVCFG register are reserved. A write to the reserved bits must always be logic ‘0’ for normal device op-
eration and performance.
3.1.6.2 End of Initialization Bit (ENDINIT)
The ENDINIT bit is a control bit used to indicate that the user has completed all device and system level initialization tests,
and that MMA685x will operate in normal mode. Once the ENDINIT bit is set, writes to all writable register bits are inhibited except
for the DEVCTL register. Once written, the ENDINIT bit can only be cleared by a device reset. The writable register CRC check
(reference Section 3.2.2) is only enabled when the ENDINIT bit is set.
3.1.6.3 SD Bit
The SD bit determines the format of acceleration data results. If the SD bit is set to a logic ‘1’, unsigned results are transmitted,
with the zero-g level represented by a nominal value of 512. If the SD bit is cleared, signed results are transmitted, with the zero-
g level represented by a nominal value of 0.
3.1.6.4 OFMON Bit
The OFMON bit determines if the offset monitor circuit is enabled. If the OFMON bit is set to a logic ‘1’, the offset monitor is
enabled. Refer to Section 3.8.5 for more information. If the OFMON bit is cleared, the offset monitor is disabled.
Table 8. Device Configuration Register
Location Bit
AddressRegister76543210
$0B DEVCFG Reserved Reserved ENDINIT SD OFMON A_CFG[2] A_CFG[1] A_CFG[0]
Reset Value 00000000
SD Operating Mode
1 Unsigned Data Output
0 Signed Data Output
OFMON Operating Mode
1 Offset Monitor Circuit Enabled
0 Offset Monitor Circuit Disabled
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3.1.6.5 ARM Configuration Bits (A_CFG[2:0])
The ARM Configuration Bits (A_CFG[2:0]) select th e mode of operation for the ARM/PCM pins.
3.1.7 Axis Configuration Register (DEVCFG_X)
The Axis configuration register is a read/write register which contains axis specific configuration information. This register can
be written during initialization, but is locked once the ENDINIT bit is set. This register is included in the writable register CRC
check. Refer to Section 3.2.2 for details
3.1.7.1 Self-Test Control (ST)
The ST bit enables and disables the self-test circuitry . Self-test circuitry is enabled if a logic ‘1’ is written to ST and the ENDINIT
bit has not been set. Enabling the self-test circuitry results in a positive acceleration value. Self-test deflection values are specified
in Section 2.4. ST is always cleared following internal reset.
When the self-test circuitry is active, the offset cancellation block and the offset monitor status are suspended, and the status
bits in the Acceleration Data Request Response will indicate “Self-Test Active”. Reference Section 3.8.4 and Section 4.2 for de-
tails. When the self-test circuitry is disabled by clearing the ST bit, the offset monitor remains disabled until the time tST_OMB spec-
ified in Section 2.4 expires. However, the status bits in the Acceleration Data Request Response will immediately indicate that
self-test has been deactivated.
3.1.7.2 Reserved Bits (Reserved)
Bits 6 through 4 of the DEVCFG_X register are reserved. A write to the reserved bits must always be logic ‘0’ for normal device
operation and performance.
Table 9. Arming Output Configuration
A_CFG[2] A_CFG[1] A-CFG[0] Operating Mode Output Type Reference
0 0 0 Arm Output Disabled Hi Impedance
0 0 1 PCM Output Digital Output Section 3.8.10
0 1 0 Moving Average Mode Active High with Pulldown Current Section 3.8.9.1
0 1 1 Moving Average Mode Active Low with Pullup Current Section 3.8.9.1
1 0 0 Count Mode Active High with Pulldown Current Section 3.8.9.2
1 0 1 Count Mode Active Low with Pullup Current Section 3.8.9.2
1 1 0 Unfiltered Mode Active High with Pulldown Current Section 3.8.9.3
1 1 1 Unfiltered Mode Active Low with Pullup Current Section 3.8.9.3
Table 10. Axis Configuration Registers
Location Bit
AddressRegister76543210
$0C DEVCFG_X ST Reserved Reserved Reserved LPF[3] LPF[2] LPF[1] LPF[0]
Reset Value 00000000
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3.1.7.3 Low-Pass Filter Selection Bits (LPF[3:0])
The Low Pass Filter selection bit selects a low-pass filter as shown in Table 11. Refer to Section 3.8.3 for details regarding
filter configurations.
Note: Filter characteristics do not include g-cell frequency response.
3.1.8 Arming Configuration Registers (ARMCFG)
The arming configuration register contains configuration information for the arming function. The values in this register are only
relevant if the arming function is operating in moving average mode, or count mode.
This register can be written during initialization but is locked once the ENDINIT bit is set. Refer to Section 3.1.6.2 . This register
is included in the writable register CRC check. Refer to Secti on 3.2.2 for details.
3.1.8.1 Reserved Bits (Reserved)
Bits 7 through 6 of the ARMCFG register are reserved. A write to the reserved bits must always be logic ‘0’ for normal device
operation and performance.
Table 11. Low Pass Filter Selection Bits
LPF[3] LPF[2] LPF[1] LPF[0] Low Pass Filter Selected Nominal Sample Rate (μs)
0 0 0 0 100 Hz, 4-pole 8
0 0 0 1 300 Hz, 4-Pole 8
0 0 1 0 400 Hz, 4-Pole 8
0 0 1 1 800 Hz, 4-Pole 8
0 1 0 0 1000 Hz, 4-Pole 8
0 1 0 1 400 Hz, 3-Pole 8
0 1 1 0 Reserved Reserved
0 1 1 1 Reserved Reserved
1 0 0 0 50 Hz, 4-Pole 16
1 0 0 1 150 Hz, 4-Pole 16
1 0 1 0 200 Hz, 4-Pole 16
1 0 1 1 400 Hz, 4-Pole 16
1 1 0 0 500 Hz, 4-Pole 16
1 1 0 1 200 Hz, 3-Pole 16
1 1 1 0 Reserved Reserved
1 1 1 1 Reserved Reserved
Table 12. Arming Configuration Register
Location Bit
AddressRegister76543210
$0E ARMCFG Reserved Reserved APS[1] APS[0] AWS_N[1] AWS_N[0] AWS_P[1] AWS_P[0]
Reset Value 00001111
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3.1.8.2 Arming Pulse Stretch (A PS[1:0])
The APS[1:0] bit sets the programmable pulse stretch time for the arming outputs. Refer to Section 3.8.9 for more details re-
garding the arming function.
3.1.8.3 Arming Window Size (AWS_x[1:0])
The AWS_x[1:0] bit has a different function depending on the state of the A_CFG bits in the DEVCFG register.
If the arming function is set to moving average mode, the AWS bits set the number of acceleration samples used for the arming
function moving average. The number of samples is set independently for polarity. If the arming function is set to count mode,
the AWS bits set the sample count limit for the arming function. The sample count limit is set independently.
Refer to Section 3.8.9 for more details regarding the arming function.
Table 13. Arming Pulse Stre tc h De finitions
APS[1] APS[0] Pulse Stretch Time(1) (Typical Oscillator)
1.Pulse stretch times are derived from the internal oscillator, so the tolerance on this oscillator applies.
00 0 mS
0 1 16.256 ms - 16.384 ms
1 0 65.408 ms - 65.536 ms
1 1 261.888 ms - 262.016 ms
Table 14. Positive Arming Window Size Definitions (Moving Average Mode)
AWS_P[1] AWS_P[0] Positive Window Size
00 2
01 4
10 8
11 16
Table 15. Negative Arming Wind ow Size Definitions (Moving Average Mode)
AWS_N[1] AWS_N[0] Negative Window Size
00 2
01 4
10 8
11 16
Table 16. Arming Count Limit Definitions (Count Mode)
AWS_N[1] AWS_N[0] AWS_P[1] AWS_P[0] Sample Count Limit
Don’t Care Don’t Care 0 0 1
Don’t Care Don’t Care 0 1 3
Don’t Care Don’t Care 1 0 7
Don’t Care Don’t Care 1 1 15
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3.1.9 Arming Threshold Registers (ARMT_P, ARMT_N)
These registers contain the positive and negative thresholds to be used by the arming function. Refer to Section 3.8.9 for more
details regarding the arming function.
These registers can be written during initialization but are locked once the ENDINIT bit is set. Refer to Section 3.1.6.2. These
registers are included in the writable register CRC check. Refer to Section 3.2.2 for details.
The values programmed into the threshold registers are the threshold values used for the arming function as described in
Section 3.8.9. The threshold registers hold independent unsigned 8-bit values for polarity . Each threshold increment is equivalent
to one output LSB. Table 18 shows examples of some threshold register values and the corresponding threshold.
If either the positive or negative threshold is programmed to $00, comparisons are disabled for only that polarity. The arming
function still operates for the opposite polarity. If both the positive and negative arming thresholds are programmed to $00, the
Arming function is disabled, and the output pin is disabled, regardless of the value of the A_CFG bits in the DEVCFG register.
3.1.10 Device Status Register (DEVSTAT)
The device status register is a read-only register . A read of this register clears the status flags affected by tra nsient conditions.
Reference Section 4.5 for details on the MMA685x response for each status condition.
3.1.10.1 Unused Bit (UNUSED)
The unused bit has no impact on operation or performance. When read this bit may be ‘1’ or ‘0’.
3.1.10.2 Internal Data Error Flag (IDE)
The internal data error flag is set if a customer or OTP register data CRC fault or other internal fault is detected as defined in
Section 4.5.5. The internal data error flag is cleared by a read of the DEVSTA T register . If the error is associated with a CRC fault
in the writable register array, the fault will be re-asserted and will require a device reset to clear . If the error is associated with the
data stored in the fuse array, the fault will be re-asserted even after a device reset.
3.1.10.3 Sigma Delta Modulator Over Range Flag (SDOV)
The sigma delta modulator over range flag is set if the sigma delta modulator becomes saturated. Th e SDOV flag is cleared
by a read of the DEVSTAT register.
Table 17. Arming Threshold Registers
Location Bit
AddressRegister76543210
$10 ARMT_P AT_P[7] AT_P[6] AT_P[5] AT_P[4] AT_P[3] AT_P[2] AT_P[1] AT_P[0]
$12 ARMT_N AT_N[7] AT_N[6] AT_N[5] AT_N[4] AT_N[3] AT_N[2] AT_N[1] AT_N[0]
Reset Value 00000000
Table 18. Threshold Register Value Examples
Axis Type Programmed Thresholds
Range
(g) Sensitivity
(g/LSB) Positive
(Decimal) Negative
(Decimal) Positive Threshold
(g) Negative Threshold
(g)
20 0.04097 100 50 4.10 -2.05
20 0.04097 255 0 10.45 Disabled
50 0.1024 50 20 5.12 -2.05
120 0.24414 20 10 4.88 -2.44
Table 19. Device Status Register
Location Bit
AddressRegister76543210
$14 DEVSTAT UNUSED IDE SDOV DEVINIT MISOERR 0 OFFSET DEVRES
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3.1.10.4 Device Initialization Flag (DEVINIT)
The device initialization flag is set during the interval between negation of internal reset and completion of internal device ini-
tialization. DEVINIT is cleared automatically. The device initialization flag is not affected by a read of the DEVSTAT register.
3.1.10.5 SPI MISO Data Mismatch Error Flag (MISOERR)
The MISO data mismatch flag is set when a MISO Data mismatch fault occurs as specified in Section 4.5.2. The MISOERR
flag is cleared by a read of the DEVSTAT register.
3.1.10.6 Offset Monitor Over Range Flags (OFFSET)
The offset monitor over range flag is set if the acceleration signal reaches the specified offset limit. The offset monitor over
range flags are cleared by a read of the DEVSTAT register.
3.1.10.7 Device Reset Flag (DEVRES)
The device reset flag is set during device initialization following a device reset. The devi ce rese t flag is cleared by a read of
the DEVSTAT register.
3.1.11 Count Register (COUNT)
The count register is a read-only register which provides the cu rrent va lue of a free-running 8-bit counter derived from the pri-
mary oscillator . A 10-bit pre-scaler divides the primary oscillator frequency by 1024. Thus, the value in the register increases by
one count every 128 μs and the counter rolls over every 32.768 ms.
3.1.12 Offset Correction Value Registers (OFFCORR)
The offset correction value register is a read-only register which contain the most recent offset correction increment / decre-
ment value from the offset cancellation circuit. The value stored in this register indicates the amount of offset correction being
applied to the SPI output data. The values have a resolution of 1 LSB.
3.1.13 Reserved Registers (Reserved)
Registers $1C and $1D are reserved. A write to the reserved bits must always be logic ‘0’ for normal device operation and
performance.
Table 20. Count Registe r
Location Bit
AddressRegister76543210
$15 COUNT COUNT[7] COUNT[6] COUNT[5] COUNT[4] COUNT[3] COUNT[2] COUNT[1] COUNT[0]
Reset Value 00000000
Table 21. Offset Correction Value Register
Location Bit
AddressRegister76543210
$16 OFFCORR_X OFFCORR_X[7] OFFCORR_X[6] OFFCORR_X[5] OFFCORR_X[4] OFFCORR_X[3] OFFCORR_X[2] OFFCORR_X[1] OFFCORR_X[0]
Reset Value 00000000
Table 22. Reserved Registers
Location Bit
AddressRegister76543210
$1C Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
$1D Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reset Value 00000000
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3.2 Customer Accessible Data Array CRC Verification
3.2.1 OTP Shadow Register Array CRC Verification
The OTP shadow register array is verified for errors using a 3-bit CRC. The CRC verification uses a generator polynomial of
g(x) = X 3+ X + 1, with a seed value = ‘1 11’. If a CRC error is detected in the OTP array , the IDE bit is set in the DEVST AT register .
3.2.2 Writable Register CRC Verification
The writable registers in the data array are verified for errors using a 3-bit CRC. The CRC verification is enabled only when
the ENDINIT bit is set in the DEVCFG register. The CRC verification uses a generator polynomial of g(x) = X3 + X + 1, with a
seed value = ‘111’. If a CRC error is detected in the writable register array, the IDE bit is set in the DEVSTAT register.
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3.3 Voltage Regulators
Separate internal voltage regulators supply the analog and digital circuitry . External filter capacitors are required, as shown in
Figure 1. The voltage regulator module includes voltage monitoring circuitry which indicates a device reset until the external sup-
ply and all internal regulated voltages are within predetermined limits. A reference ge nerator provides a stable voltage which is
used by the ΣΔ converters.
Figure 7. Power Supply
Figure 8. Voltage Monitoring
CREGA
CREG
VCC
TRACKING
REGULATOR
VOLTAGE
REGULATOR
REFERENCE
GENERATOR
VREGA = 2.50 V
DIGITAL
LOGIC
DSP
OTP
ARRAY
PRIMARY
OSCILLATOR
ΣΔ
CONVERTER
BIAS
GENERATOR
TRIM TRIM
VREF = 1.250 V
VREG = 2.50 V
BANDGAP
REFERENCE
Tracks VREGA
SET DEVRES Flag
V
CC
V
REGA
V
REG
V
REF
MONITOR
BANDGAP
V
CCUV
V
REGOV
V
REGUV
V
REGAUV
V
REGAOV
V
REFOV
V
REFUV
GROUND LOSS
MONITOR
V
REG
POR
V
BGMON
V
PORREF
Note: No external access to reference voltage
Limits verified by characterization only
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3.3.1 CREG Failure Detection
The digital supply voltage regulator is designed to be unstable with low capacitance. If the connection to the VREG capacitor
becomes open, the digital supply voltage will oscillate and cause either an undervoltage, or overvoltage failure within one internal
sample time. This failure will result in one of the following:
1. The DEVRES flag in the DEVSTAT register will be set. MMA685x will respond to SPI acceleration requests as
defined in Table 27.
2. MMA685x will be held in RESET and be non-responsive to SPI requests.
3.3.2 CREGA Failure Detection
The analog supply voltage regulator is designed to be unstable with low capacitance. If the connection to the VREGA capacitor
becomes open, the analog supply voltage will oscillate and cause either an undervoltage, or overvoltage failure within one internal
sample time. The DEVRES flag in the DEVSTAT register will be set. MMA685xMMA685x will respond to SPI acceleration re-
quests as defined in Table 27.
Note: This fe ature is only supported with a VCC supply voltage in the range of 4.75V to 5.25V.
3.3.3 VSS and VSSA Ground Loss Monitor
MMA685x detects the loss of ground connection to either VSS or VSSA. A loss of ground connection to VSS will result in a VREG
overvoltage failure. A loss of ground connection to VSSA will result in a VREG undervoltage failure. Both failures result in a device
reset.
3.3.4 SPI Initiated Re set
In addition to voltage monitoring, a device reset can be initiat ed by a specific series of three write operations involving the
RES_1 and RES_0 bits in the DEVCTL register. Reference Section 3.1.5.1. for details regarding the SPI initiated reset.
3.4 Internal Oscillator
MMA685x includes a factory trimmed oscillator as specified in Section 2.6.
3.4.1 Oscillator Monitor
The COUNT register in the customer accessible array is a read-only register which provides the current value of a free-running
8-bit counter derived from the primary oscillator . A 10-bit pre-scaler divides the primary oscillator by 1024. Thus, the value in the
COUNT register increases by one count every 128μs, and the register rolls over every 32.768 ms. The SPI master can periodi-
cally read the COUNT register, and verify the difference between subsequent register reads against the system time base.
1. The SPI access rates and devi a ti o ns mu st be taken into account for this oscillator verification.
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Freescale Semiconductor, Inc. 23
MMA685x
3.5 Transducer
The MMA685x transducer is an overdamped mass-spring-damper system described by the following transfer function:
where:
ζ = Damping Ratio
ωn = Natural Frequen cy = 2∗Π∗fn
Reference Section 2.4 for transducer parameters.
3.6 Self-Test Interface
The self-test interface applies a voltage to the g-cell, causing deflection of the proof mass. The self-test interface is controlled
through SPI write operations to the DEVCFG_X register described in Section 3.1.7. The ENDINIT bit in the DEVCFG register
must also be low to enable self-test. A diagram of the self-test interface is shown in Figure 9.
Figure 9. Self-Test Interface
The raw self-test deflection can be verified against raw self-test limits using the following equations:
where:
ΔSTMIN The minimum self-test deflection over temper ature as specified in Section 2.4.
ΔSTMAX The maximum self-test deflection over temperature as specified in Section 2.4.
SENS The sensitivity of the device
ΔSENS The sensitivity tolerance
Hs()
ωn
2
s22ξω
ns⋅⋅ ⋅ ω
n
2
++
---------------------------------------------------------=
SELF-TEST
VOLTAGE
GENERATOR
ENDINIT
ST
g-CELL
ENDINIT
ΔSTMINLIMIT FLOOR ΔSTMIN
()SENS 1 ΔSENS–()⋅[]⋅⋅=
ΔSTMAXLIMIT CEIL ΔSTMAX
()SENS 1 ΔSENS+()⋅[]⋅⋅=
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24 Freescale Semiconductor, Inc.
MMA685x
3.7 ΣΔ Converters
Two sigma delta converters provide the interface between the g-cell and the DSP. The output of each ΣΔ converter is a data
stream at a nominal frequency of 1 MHz.
Figure 10. ΣΔ Converter Block Diagram
3.8 Digital Signal Processing Block
A digital signal processing (DSP) block is used to perform signal filtering and compensation operations. A diagram illustrating
the signal processing flow is shown in Figure 11.
Figure 11. Signal Chain Diagram
1-BIT
QUANTIZER
z
-1
1 - z
-1
z
-1
1 - z
-1
FIRST
INTEGRATOR SECOND
INTEGRATOR
α
1
=
β
1
α
2
β
2
V
X
C
INT1
g-CELL
C
BOT
C
TOP
Δ
C = C
TOP
- C
BOT
ΣΔ
_OUT
V =
±
2
×
V
REF
ADC
DAC
V =
Δ
C x V
X
/ C
INT1
ΣΔ
_OUT
To SPI
To ARM
ABCEG
To SPI
H
I
DF
SINC Filter
Section 3.8.2 Low Pass Filter
Section 3.8.3 Compensation
Section 3.8.6 Interpolation
Section 3.8.7 Offset Cancellation
Section 3.8.4 Offset Cancellation
Output Scaling
Raw Output
Scaling
Arm/PCM Output
Section 3.8.9
Section 3.8.10
Table 23. MMA685x Signal Chain Characteristics
Description Sample
Time (μs) Data Width
Bits Over
Bits Effective
Bits Rounding
Resolution Bits Typical Block
Latency Reference
AΣΔ 1 1 1 — 3.2 μsSection 3.7
BSINC Filter 8 14 13 — 11.2 μsSection 3.8.2
CLow Pass Filter 8/16 20 6 10 4 Reference Section 3.8.3 Section 3.8.3
DCompensation 8/16 20 6 10 4 7.875 μsSection 3.8.6
EInterpolation 4/8 20 6 10 4 ts / 2 Section 3.8.7
FOffset
Cancellation 256 20 6 10 4 N/A Section 3.8.4
G, H SPI Output 4/8 — — 10 — ts / 2 —
IPCM Output 4/8 — — 9 — — Section 3.8.10
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Freescale Semiconductor, Inc. 25
MMA685x
3.8.1 DSP Clock
The DSP is clocked at 8 MHz, with an effective 6MHz operating frequency. The clock to the DSP is disabled for 1 clock prior
to each edge of the ΣΔ modulator clock to minimize noise during data conversion. The bit streams from the two ΣΔ converters
are processed through independent data paths within the DSP.
Figure 12. Clock Generation
3.8.2 Decimation Sinc Filter
The serial data stream produced by the ΣΔ converter is decimated and converted to parallel values by a 3rd order 16:1 sinc
filter with a decimation factor of 8 or 16, depending on the Low Pass Fil te r selected.
Figure 13. Sinc Filter Response, tS = 8 μs
8 MHz OSC
6 MHz Dig ita l
1MHz Modulator
Hz() 1z
16–
–
16 1 z 1–
–()×
-------------------------------------3
=
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26 Freescale Semiconductor, Inc.
MMA685x
3.8.3 Low Pass Filter
Data from the Sinc filter is processed by an infinite impulse response (IIR) low pass filter.
MMA685x provides the option for one of twelve low-pass filters. The filter is selected with the LPF[3:0] bits in the DEVCFG_X
register . The filter selection options are listed in Section 3.1.7.3, Table 11. Response parameters for the low-pass filter are spec-
ified in Section 2.4. Filter characte ristics are illustrated in Figures 14, 15, 16, 17, 18 and 19.
Note: Low Pass Filter Figures do not include g-cell freq uency response.
Table 24. Low Pass Filter Coefficients
Description Sample Time (μs) Filter Coefficients Group Delay
50 Hz LPF 16
n02.08729034056887e-10 d01
26816/fosc
n18.349134489240434e-10 d1-3.976249694824219
n21.25237777794924e-09 d25.929003009577855
100 Hz LPF 8 n38.349103355433541e-10 d3-3.929255528257727
n42.087307211059861e-10 d40.9765022168437554
150 Hz LPF 16
n01.639127731323242e-08 d01
9024/fosc
n16.556510925292969e-08 d1-3.928921222686768
n29.834768482194806e-08 d25.789028996785419
300 Hz LPF 8 n36.556510372902331e-08 d3-3.791257019240902
n41.639128257923422e-08 d40.9311495074496179
200 Hz LPF 16
n05.124509334564209e-08 d01
6784/fosc
n12.049803733825684e-07 d1-3.905343055725098
n23.074705789151505e-07 d25.72004239520561
400 Hz LPF 8 n32.049803958150164e-07 d3-3.723967810019985
n45.124510693742625e-08 d40.9092692903507213
200 Hz LPF
3-pole 16
n02.720393240451813e-06 d01
5632/fosc
n18.161179721355438e-06 d1-2.931681632995605
n28.161180123840722e-06 d22.865296718275204
400 Hz LPF
3-pole 8n32.720393634345496e-06 d3-0.9335933215174919
n40d
40
400 Hz LPF 16
n07.822513580322266e-07 d01
3392/fosc
n13.129005432128906e-06 d1-3.811614513397217
n24.693508163398543e-06 d25.450666051045118
800 Hz LPF 8 n33.129005428784364e-06 d3-3.465805771100349
n47.822513604678875e-07 d40.8267667478030489
500 Hz LPF 16
n01.865386962890625e-06 d01
2688/fosc
n17.4615478515625e-06 d1-3.765105724334717
n21.119232176112846e-05 d25.319861050818872
1000 Hz LPF 8 n37.4615478515625e-06 d3-3.34309015036024
n41.865386966264658e-06 d40.7883646729233078
Hz() n0n1z1–
⋅()n2z2–
⋅()n3z3–
⋅()n4z4–
⋅()++++
d0d1z1–
⋅()d2z2–
⋅()d3z3–
⋅()d4z4–
⋅()++++
-----------------------------------------------------------------------------------------------------------------------------------------=
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Freescale Semiconductor, Inc. 27
MMA685x
Figure 14. Low-Pass Filter Characteristics: fC = 100 Hz, Poles = 4, tS = 8 μs
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28 Freescale Semiconductor, Inc.
MMA685x
Figure 15. Low-Pass Filter Characteristics: fC = 300 Hz, Poles = 4, tS = 8 μs
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Freescale Semiconductor, Inc. 29
MMA685x
Figure 16. Low-Pass Filter Characteristics: fC = 400 Hz, Poles = 4, tS = 8 μs
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30 Freescale Semiconductor, Inc.
MMA685x
Figure 17. Low-Pass Filter Characteristics: fC = 400 Hz, Poles = 3, tS = 8 μs
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Freescale Semiconductor, Inc. 31
MMA685x
Figure 18. Low-Pass Filter Characteristics: fC = 800 Hz, Poles = 4, tS = 8 μs
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32 Freescale Semiconductor, Inc.
MMA685x
Figure 19. Low-Pass Filter Characteristics: fC = 1000 Hz, Poles = 4, tS = 8 μs
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Freescale Semiconductor, Inc. 33
MMA685x
3.8.4 Offset Cancellation
MMA685x provides the option to read offset cancelled acceleration data via the SPI by clearing the OC bit in the SPI command
(reference Section 4.1). A block diagram of the offset cancellation is shown in Figure 20, and response parameters are specified
in Section 2.4 and in Table 25.
Figure 20. Offset Cancellation Bloc k Diagram
In normal operation, the offset cancellation circuit computes a 24,576 sample running average of the acceleration data down-
sampled to 256 μs. The running average is compared against positive and negative thresholds to determine the offset correction
value that will be applied to the acceleratio n data.
During start up, three phases of moving average sizes are used to allow for faster convergence of misuse input signals. Refer
to Table 25 for offset cancellation timing information during startup and normal operation.
When the self-test circuitry is active, the offset cancellation block and th e offset monitor block are suspended, and the offset
correction value is constant. Once the self-test circuitry is disabled, the offset cancellation block remains suspended for the time
tST_OMB to allow the acceleration output to return to its nominal offset.
3.8.5 Offset Monitor
MMA685x provides the option for an offset monitor circuit. The offset monitor circuit is enabled when the OFMON bit in the
DEVCFG register is programmed to a logic ‘1’. The output of the offset cancellation circuit is compared against a high and low
threshold. If the offset correction value exceeds either the OFFTHRPOS, or OFFTHRNEG threshold, an Offset Over Range con-
dition is indicated.
The offset correction value update rate is listed in Table 25: “Maximum Slew Rate”. Because the offset monitor uses this value,
the offset monitor will also update at this rate. The time to indicate an Offset Over Range is dependent upon the input signal.
The offset monitor status remains frozen during self-test, because the offset monitor is based on the offset cancellation circuit,
which is also suspended during self-test. The offset monitor is disabled for 2.1 seconds following reset regardless of the state of
the OFMON bit.
3.8.6 Signal Compensation
MMA685x includes internal OTP and signal processing to compensate for sensitivity error and offset error . This compensation
is necessary to achieve the specified parameters in Section 2.4.
Table 25. Offset Cancellation Timing Specifications
Phase Start Time of
Phase
(from POR)
Typical
Time in Phase
(ms)
# of Samples in
Phase Samples
Averaged
OFF_CORR_VALUE
Update Rate
(ms)
Averaging
Period
(ms)
Maximum
Slew Rate
(LSB/s)
Averaging Filter
-3dB Frequency
(Hz)
Start 1 tOP 524.288 2048 48 2.048 12.288 122.1 36.05
Start 2 tOP + 524.288 524.288 2048 384 16.38 98.304 15.26 4.506
Start 3 tOP + 1048.576 524.288 2048 3072 131.1 786.432 1.907 0.5632
Normal tOP + 1572.864 — — 24576 1049 6291.456 0.2384 0.07040
Accumulator T1
up to 4096 samples Shift
LPF
OUT
T2 T5T4T3 T6
Offset Inc/Dec
OFFCORRP
OFFCORRN
OFFTHN
OFFTHP
INC
DEC
Downsampled to 256μs
OFF_CORR_VALUE
OFFTHRNEG
OFFTHRPOS OFF_ERR
OFF_ERR
Correction
for Start Phase
OCOUT
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34 Freescale Semiconductor, Inc.
MMA685x
3.8.7 Data Interpolation
MMA685x includes 2 to 1 data interpolation to minimize the system sample jitter. Each result produced by the digital signal
processing chain is delayed one half of a sample time, and the interpolated value of successive samples is provided between
sample times. This operation is illu strated in Figure 21.
Figure 21. Data Interpolation Timing
The effect of this interpolation at the system level is a 50% reduction in sample jitter . Figure 22 shows the resulting output data
for an input signal.
Figure 22. Data Interpolation Example
Sn-3 Sn-2
t
t
Sn-1
tsts
Sn-1
ts
Sn
Sn-2
Sn3–Sn2–
+
2
--------------------------------Sn2–Sn1–
+
2
--------------------------------Sn1–Sn
+
2
-------------------------
Sn-3
Response to SPI acceleration request occurring in this window receives interpolated sample
Response to SPI acceleration request occurring in this window receives true sample.
Internal Sample Rate
Output Sample Rate
40
45
50
55
60
65
70
75
80
0 5 10 15 20 25 30 35 40
Time
Counts
Input Signal
Internally Sampled Signal
Interpolated Samples
Internally
Sampled Values
Earliest Transmission
Point of Interpola ted
Values
Earliest Transmission
Point of Internally
Sampled Values
Wi ndow of
Transmission for
Sampl ed Values
(Maximum: tS / 2)
W indow of
Transmission for
Interpol ated Values
(Maximum : tS / 2)
Fixed Latency:
tS / 2
= Signal Jitter =
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MMA685x
3.8.8 Acceleration Data Timing
The MMA685x SPI uses a request/response protocol, where a SPI transfer is completed through a sequence of 2 phases.
Reference Section 4 for more details regarding the SPI protocol. In order to provide the mo st recent acceleration data for each
request, MMA685x latches the associated data for an acceleration request at the falling edge of CS for the acceleration response
message (the subsequent SPI transfer). The most recent sample available from the DSP (including interpolation), is latched, pro-
viding a maximum latency of 1* tS relative to the falling edge of CS.
Figure 23. Acceleration Dat a Timing
SCLK
MOSI
MISO
CS
Request Accel. Request Accel.
Acceleration Data Acceleration Data
Request Accel. Request Accel.
Acceleration Data
Acceleration Data Latched
Arm Function updated if applicable
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36 Freescale Semiconductor, Inc.
MMA685x
3.8.9 Arming Function
MMA685x provides the option for an arming function with 3 modes of operation. The operation of the arming function is se-
lected by the state of the A_CFG bits in the DEVCFG register.
Reference Section 4.5 for the operation of the Arming function with exception conditions. Error conditions do not impact prior
arming function responses. If an error occurs after an arming activation, the corresponding pulse stretch for the existing arming
condition will continue. However , new acceleration reads will not update the arming function regardless of the acceleration value.
3.8.9.1 Arming Function: Moving Average Mode
In moving average mode, the arming function runs a moving average on the offset cancelled output. The number of samples
used for the moving average (k) is programmable via the AWS_x[1:0] bits in the ARMCFGX register . Reference Section 3.1.8 for
register details.
ARM_MAn = (OCn + OCn-1 + ... + OCn+1-k)/k
Where n is the current sample.
The sample rate is determined by the SPI acceleration data sample rate. At the falling edge of CS for an accelerati on data SPI
response, the moving average is updated with a new sample. Reference Figure 26. The SPI acceleration data sample rate must
meet the minimum time between requests (tACC_REQ_x) specified in Section 2.5.
The moving average output is compared against positive and negative 8-bit thresholds that are programmed via the ARMT_x
registers. Reference Section 3.1.9 for register details. If the moving average equals or exceeds either threshold, an arming con-
dition is indicated, the ARM output is asserted, and the pulse stretch counter is set as described in Section 3.8.9.4.
The ARM output is de-asserted only when the pulse stretch counter expires. Figure 26 shows the arming output operation for
different SPI conditions.
Figure 24. Arming Function Block Diagram - Moving Average Mode
Offset Cancellation
AWS_P[1:0]
APS[3:0]
Pulse Stretch ARM
Gating I/O
ARMT_N[7:0]
ARMT_P[7:0]
Moving Average
Positive
Moving Average
Negative
AWS_N[1:0]
OffCanc_ARM[10:0]
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3.8.9.2 Arming Function: Count Mode
In count mode, the arming function compares each input samp le against positive and negative thresholds that are pro-
grammed via the ARMT_x registers. Reference Section 3.1.9 for register details. If the sample equals or exceeds either thresh-
old, a sample counter is incremented. If the sample does not exceed either threshold, the sample counter is reset to zero.
The sample rate is determined by the SPI acceleration data sample rate. At the falling edge of CS for an accelera tion data SPI
response, a new sample is compared against the thresholds. Reference Figure 26. The SPI acceleration data sample rate must
meet the minimum time between requests (tACC_REQ_x) specified in Section 2.5.
A sample count limit is programmable via the AWS_x[1:0] bits in the ARMCFG register. If the sample count reaches the pro-
grammable sample count limit, an arming condition is indicated, the ARM output is asserted and the pulse stretch counter is set
as described in Section 3.8.9.4.
The ARM output is de-asserted only when the pulse stretch counter expires. Figure 26 shows the arming output operation for
different SPI conditions.
Figure 25. Arming Function Block Diagram - Count Mode
Figure 26. MMA685x Arming Condition, Moving Average and Count Mode
ARMT_N[7:0]
Offset Cancellation
AWS_P[1:0]
APS[1:0]
Pulse Stretch ARM
ARMT_P[7:0]
Gating I/O
1-4 Sample
Counter
OffCanc_ARM[10:0]
X-Axis Arm Condition
Not Present
X-Axis Data Latched for
Arm Funct i on and SPI
SCLK
MOSI
MISO
CS
Request X-Axis Request X-Axis
X-Axis Response X-Axis Response
Request X-Axis Request X-Axis
X-Axis Response
ARM
X-Axis Response
X-Axis Arm Condition
Not Present X-Axis Arm Condition
Not Present
X-Axis Arm Condition
Present
tARM
Pulse Stretch Time
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38 Freescale Semiconductor, Inc.
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3.8.9.3 Arming Function: Unfiltered Mode
On the falling edge of CS for an acce leration response, the most recent available DSP sample is compared against positive
and negative thresholds that are programmed via the ARMT_x registers. Reference Section 3.1.9 for register details. If the sam-
ple equals or exceeds either threshold, an arming condition is indicated.
Once an arming condition is indicated for the ARM output is asserted when CS is asserted and the MISO data includes an
acceleration response.
The pulse stretch function is not app lied in Unfiltered mode.
Figure 27 contains a block diagram of the Arming Function operation in Unfiltered Mode. Figure 28 shows the Arming output
operation under the different SPI request conditions.
Figure 27. Arming Function Block Diag ram - Unfilte re d Mode
Figure 28. MMA685x Arming Conditions, Unfiltered Mode
ACFG[2]
CS
AXIS Select ARM
I/O
ACFG[1]
ARMING FUNCTION
Interpolated Sample Rate
X-Axis Arm Condition
Not Present
X-Axis Data Latched for
Arm Funct i on and SPI
SCLK
MOSI
MISO
CS
Request X-Axis Request X-Axis
X-Axis Response X-Axis Response
Request X-Axis Request X-Axis
X-Axis Response
ARM
X-Axis Response
X-Axis Arm Condition
Not Present X-Axis Arm Condition
Not Present
X-Axis Arm Condition
Present
tARM_UF_DL
tARM_UF_ASSERT
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MMA685x
3.8.9.4 Arming Pulse Stretch Function
A pulse stretch function can be applied to the ar ming output in moving average mode, or count mode.
If the pulse stretch function is not used (APS[1:0] = ‘00’), the arming output is asserted if and only if an arming condition exists
after the most recent evaluated sample. The arming output is de-asserted if and only if an arming condition does not exist after
the most recent evaluated sample.
If the pulse stretch function is used, (APS[1:0] not equal ‘00’), the arming output is controlled only by the value of the pulse
stretch timer value. If the pulse stretch timer value is non-zero, the arming output is asserted. If the pulse stretch timer is zero,
the arming output is de-asserted. The pulse stretch counter continuously decrements until it reaches zero. The pulse stretch
counter is reset to the programmed pulse stre tch value if and only if an arming condition exists after the most recent evaluated
sample. Reference Figure 26
The desired pulse stretch time is programmable for via the APS[1:0] bits in the ARMCFG register.
Exception conditions listed in Section 4.5 do not impact prior arming function responses. If an exception occurs after an arming
activation, the corresponding pulse stretch for the existing arming condition will continue. However, new acceleration reads will
not reset the pulse stretch counter rega rdless of the acceleration value.
3.8.9.5 Arming Pin Output Structure
The arming output pin structure can be set to active high, or active low with the A_CFG bits in the DEVCFG register as de-
scribed in Section 3.1.6.5 . The active high and active low pin output structures are shown in Figure 29.
Figure 29. Arming Function - Pin Output Structure
3.8.10 PCM Output Function
MMA685x provides the option for a PCM output function. The PCM output is enabled by setting the A_CFG bits in the
DEVCFG register to the appropriate state as described in Section 3.1.6.5. When the PCM function is enabled, the upper 9 bits
of the 10-bit, offset cancelled, output scaled acceleration values are used to generate 8 MHz Pulse Code Modulated signals pro-
portional to the acceleration onto the PCM pin. A block diagram of the PCM output is shown in Figure 30.
Exception conditions affect the PCM output as listed in Section 4.5.
Figure 30. PCM Output Function Block Diagra m
Arm Function
ARM
Gating
VCC
Arm Function ARM
Gating
VCC
Open Drain, Active High Open Drain, Active Low
Output Scaling
OC[9:1]
A
9 Bit ADDER
ARM/PCM
B
CARRY
SUM
fCLK = 8 MHz
Sample updated every 8μS9
9
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
9
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40 Freescale Semiconductor, Inc.
MMA685x
3.9 Serial Peripheral Interface
MMA685x includes a Serial Peripheral Interface (SPI) to provide access to the configuration registers and digital data. Refer-
ence Section 4 for details regarding the SPI protocol and available commands.
3.10 Device Initialization
Following power-up, under-voltage reset, or a SPI reset command sequence, MMA685x proceeds through an internal initial-
ization process as shown in Figure 31. Figure 31 also shows the MMA685x performance for an example externa l system level
initialization procedure.
Figure 31. Initialization Process
Dly
POR
OTP Copy to
Mirror Registers
Offset Cancellation
Startup Phase 2
Initialize R/W
Registers to
Desired Stat e
Verify
Offset
Verify
Self Test &
ARM Asserted
Offset Cancellation
Startup Phase 1
Offset Cancellation
Startup Phase 3
Offset Cancellation
Normal Mode
Ready for SPI
Command
ENDINIT Clear
Dly
Re-Initialize
R/W Registe r s
(if needed)
Activate
Self Test
Internal
Offset Error
Corrected to ‘0 ’
DeActivate
Self Test
Normal
Mode
Internal Initialization
External Initialization
Delay
DeAssertion
Dependent on P ul s e
St retch and/or Arming Mode
Assertion
Dependent on
Arming Mode
Set ENDINIT
Read DEVSTAT
to clear flags
Re-read DEVSTA T
to verify Status
tST_OMB
tOC_PHASE1 tOC_PHASE2 tOC_PHASE3
tOP
and
ST
ARM
Notes:1) Self Test can be enable d and evaluated simultane ously to reduce test time.
For failure mode coverage of the arming pins and of potentia l common axis failures, Freescal e recommends independent sel f t est activation.
tSTRISE
2) tSTRISE and tSTFALL are dependent on the se lected LPF group delay.
Verify
Offset &
ARM DeAsserted
Dly
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MMA685x
3.11 Overload Response
3.11.1 Overload Performance
MMA685x is designed to operate within a specified range. Acceleration beyond that range (ove rload) impacts the output of
the sensor. Acceleration beyond the range of the device can generate a DC shift at the output of the device that is dependent
upon the overload frequency and amplitude. The MMA685x g-cell is overdamped, providing the optimal design for overload per-
formance. However , the performance of the device during an overload condition is affected by many other parameters, including:
• g-cell damp ing
• Non-linearity
• Clipping limits
• Symmetry
Figure 32 shows the g-cell, ADC and output clipping of MMA685x over frequency. The relevant parameters are specified in
Section 2.1, and Section 2.6.
Figure 32. Output Clipping Vs. Frequency
3.11.2 Sigma Delta Over Range Response
Over range conditions exist when the signal level is beyond the full-scale range of the device but within the computational limits
of the DSP. The ΣΔ converter can saturate at levels above those specified in Section 2.1 (GADC_CLIP). The DSP operates pre-
dictably under all cases of over range, although the signal may include residual high frequency components for some time after
returning to the normal range of operation due to non-linear effects of the sensor.
5kHz fg-Cell fLPF
gADC_Clip
gg-cell_Clip
Determined by g-cell
10kHz
g-cellRolloff
Acceleration (g)
Frequency (kHz)
LPFRolloff
Region Clipped by g-cell
Region Clipped by ADC
Region of Signal Distortion due to
Asymmetry and Non-Linearity
Region of No Signal Distortion Beyond
Specification
Region of Interest
roll-off and ADC clipping
gRange_Norm
Determined by g-cell
roll-off and full scale range
Region Clipped
by Output
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42 Freescale Semiconductor, Inc.
MMA685x
4 SPI Communications
Communication with MMA685x is completed through synchronous serial transfer s via SPI. MMA685x is a slave device con-
figured for CPOL = 0, CPHA = 0, MSB first. SPI transfers are completed through a sequence of two phases. During the first
phase, the type of transfer and associated control information is transmitted from the SPI master to MMA685x. Data from
MMA685x is transmitted during the second phase. Any activity on MOSI or SCLK is ignored when CS is negated. Consequently ,
intermediate transfers involving other SPI devices may occur between phase one and phase two. Refer to Figure 33.
Figure 33. SPI Transfer Detail
T3P1
SCLK
MOSI
MISO
CS
T1P1 T2P1
T1P2 T2P2 T3P2
SCLK
MOSI
MISO
CS
Phase One: Command
Phase Two: Response
Phase One: Response -Previous Command
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Freescale Semiconductor, Inc. 43
MMA685x
4.1 SPI Command Format
Commands are transferred from the SPI master to MMA685x. Valid command s fall into two categories: register operations,
and acceleration data requests.
Table 26. SPI Command Message Summary
MSB LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0AX AOC 000000000SD ARM PC o mm a nd Type Reference
AX= Axis Selec tion
0 Acceleration Data
1N/A
A = Acceleration Data Requ est
0 Register Operation
1 Accelerati on Data Request
OC = Offset Cancelled Data Request
0 Offset Cancelled Data Request
1 Raw Acceleration Data Request
SD = Signed Data Confir m ati on
Signed Data Enabled 0
Unsigned Data Enabled 1
ARM = ARM Functi on Status Confirmation
Disabled / PCM Output Enabled 0
Arming Function Enabled 1
P = Odd Parity
0AX AOC 000000000SD ARM PAccel Data
0010000000000000 OC, Signed Data, Disabled/PCM
0010000000000011 OC, Signed Data, ARM Enabled
0010000000000101 OC, Unsigned Data, Disabled/PCM
0010000000000110 OC, Unsigned Data, ARM Enabled
0011000000000001 Raw, Signed Data, Disabled/PCM
0011000000000010 Raw, Signed Data, ARM Enabled
0011000000000100 Raw, Unsigned Data, Disabled/PCM
0011000000000111 Raw, Unsigned Data, ARM Enabled
0110000000000001 Invalid Command
0110000000000010 Invalid Command
0110000000000100 Invalid Command
0110000000000111 Invalid Command
0111000000000000 Invalid Command
0111000000000011 Invalid Command
0111000000000101 Invalid Command
0111000000000110 Invalid Command
PAX AD12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Command Type Reference
P00
A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 Register Read Section 4.4
Register Address
P10
A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Register Write Section 4.4
Register Address Data to be Written to Register
P = Odd Parity
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44 Freescale Semiconductor, Inc.
MMA685x
4.2 SPI Response Format
Table 27. SPI Response Message Summary
MSB LSB
1514131211109876543210
CMD AAX Response to Valid Acceleration Request Data Type Reference
OC 0AX PS1 S0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
OC = Offset Cancelled Data Requested
0 Transferred Accel Data is Offset Cancelled Data
1 Transferred Accel Data is Raw Data
AX = Axis Requested
0 Acceleration Data Response
1N/A
P = Odd Parity
S[1:0] = Device Status
0 0 In Initialization (ENDINIT = ‘0’)
0 1 Normal Data Request
1 0 ST Active, ΣΔ/Offset Over range Present
1 1 Internal Error Present / SPI Error
CMD AAX OC 0AX PS1 S0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data Type Reference
Valid
Accel
Data
Request
1 0 OC 0 0 P 0 1 Acceleration Data Accel
Section 4.3
1 0 OC 0 0 P 1 0 Self-Test Active Acceleration Data Accel
1 0 OC 0 0 P 0 0 Acceleration Data, Initialization in Process (ENDINIT=’0’) Accel
1 1 OC 0 1 P 0 1 Invalid Accel Request N/A
1 1 OC 0 1 P 1 0 Invalid Accel Request N/A
1 1 OC 0 1 P 0 0 Invalid Accel Request N/A
MSB LSB
1514131211109876543210
CMD AAX Response to Valid Register Access Data Type Reference
D15 D14 AX PD11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Register
Write 01 0 0 1P1110
D7 D6 D5 D4 D3 D2 D1 D0 Register Write Section 4.4.1
New Contents of Register
Register
Read 00 0 1 0P1110
D7 D6 D5 D4 D3 D2 D1 D0 Register Read Section 4.4.2
Contents of Register
MSB LSB
1514131211109876543210
CMD AAX Error Responses Data Type Reference
D15 D14 AX PD11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Invalid
Accel
Request xx
000P11 SD = 1: 00 0000 0000
SD = 0: 10 0000 0000
Register Setting
Mismatch Section 4.3
Internal
Error
Present xx
IDE Bit Set
(Excl. Self-Test),
DEVINIT Bit Set
DEVRES Bit Set
Section 4.5.5
MISO
Error xx MISO Error on
Previous Msg Section 4.5.2
SPI Error x x
MOSI Parity
CMD Bit 15 = 1
SPI Timing Err
SPI Mismatch Err
SPI Protocol Errs
Section 4.5.1
Invalid
Register
Request 0x 0 0 00111000000000
Invalid Reg Addr,
Write while
ENDINIT set,
Write to R/O Reg
Section 4.4
Self-Test
Error 0x 0 0 1 P 1 1 SD = 1: 00 0000 0000
SD = 0: 10 0000 0000 IDE Bit set due to
Self-Test Error Section 4.5.5
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MMA685x
4.3 Acceleration Data Transfers
Acceleration data requests are initiated when the Acceleration bit of the SPI command message (A) is set to a logic ‘1’. The
Axis Selection bit (AX) and the Offset Cancellation Selection bit (OC) of the command message select the type of acceleration
data requested, as shown in Table 28
To verify that MMA685x is configured as expected, each acceleration data request includes the configuration information that
impacts the output data. The requested configuration is compared against the data programmed in the writable register array.
Details are shown in Table 29.
If the data listed in Table 29 does not does not match, an Acceleration Data Request Mismatch failure is detected and no ac-
celeration data is transmitted. Reference Section 4.5.3 .1 .
Acceleration data request commands include a parity bit (P). Odd parity is employed. The number of logic ‘1’ bits in the accel-
eration data request command must be an odd number.
Acceleration data is transmitted on the next SPI message if and only if all of the following conditions are met:
• The DEVINIT bit in the DEVSTAT register is not set
• The DEVRES bit in the DEVSTAT register is not set
• The IDE bit in the DEVSTAT register is not set (Reference Section 4.5.5)
• No SPI Error is detected (Reference Section 4.5.1)
• No MISO Error is detected (Reference Section 4.5.2)
• No Acceleration Data Request Mismatch failure is detected (Reference Section 4.5.3.1)
• No Self-Test Error is present (reference Section 4.5.5.2)
If the above conditions are met, MMA685x responds with a “valid acceleration data request” response as shown in Table 27.
Otherwise, MMA685x responds as specified in Section 4.5.
4.4 Register Access Operations
Two types of register access operations are supported; register write, and register read. Register access operations are ini ti -
ated when the acceleration bit (A) of the command message is set to a logic ‘0’. The operation to be performed is indicated by
the Access Selection bit (AX) of the command message.
Register Access operations include a parity bit (P). Odd parity is employed. The number of logic ‘1’ bits in the Register Access
operation must be an odd numbe r.
Table 28. Acceleration Data Request
Acceleration Data Request Command Information Data Type
Axis Selection Bit (AX) Offset Cancellation Select (OC)
0 0 Offset Cancelled Data
0 1 Raw Data
1 0 Invalid Accel Request
1 1 Invalid Accel Request
Table 29. Acceleration Data Request Configuration Information
Programmable Option Command Message Bit Writable Register Information
Signed or Unsigned Data SD DEVCFG[4] (SD)
Arming Function or PCM Output ARM DEVCFG[2] || DEVCFG[1] (A_CFG[2] || A_CFG[1])
Access Selection Bit (AX) Operation
0 Register Read
1 Register Write
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46 Freescale Semiconductor, Inc.
MMA685x
4.4.1 Register Write Request
During a register write request, bits 12 through 8 contain a five-bit address, and bits 7 through 0 contain the data value to be
written. Writable registers are defined in Table 3.
The response to a register write operation is shown in Table 27. The response is transmitted on the next SPI message if and
only if all of the following conditio ns are met:
• No SPI Error is detected (Reference Section 4.5.1)
• No MISO Error is detected (Reference Section 4.5.2)
• The ENDINIT bit is cleared (Reference Section 3.1.6.2)
– This applies to all registers with the exception of the DEVCTL register
• No Invalid Register Request is detected (Reference Section 4.5.3.2)
If the above conditions are met, MMA685x responds to the register write request as shown in Table 27. Otherwise, MMA685x
Responds as specified in Section 4.5.
Register write operations do not occur internally until the transfer during which they are requested has been completed. In the
event that a SPI Error is detected during a register write transfer, the write operation is not completed.
4.4.2 Register Read Request
During a register read request, bits 12 through 8 contain the five-bit address for the register to be read. Bits 7 through 0 must
be logic ‘0’. Readable registe r s are defined in Table 3.
The response to a register read operation is shown in Table 27. The response is transmitted on the next SPI message if and
only if all of the following conditio ns are met:
• No SPI Error is detected (Reference Section 4.5.1)
• No MISO Error is detected (Reference Section 4.5.2)
• No Invalid Register Request is detected (Reference Section 4.5.3.2)
If the above conditions are met, MMA685x responds to the register read request as shown in Table 27. Otherwise, MMA685x
responds as specified in Section 4.5.
4.5 Exception Handling
The following sections describe the conditions for each detectable exception, and the MMA685x response for each exception.
In the event that multiple exceptions exist, the exception response is determined by the priority listed in Table 30.
Table 30. SPI Error Response Priority
Error Priority Exception Effect on Data
SPI Data Arming Output PCM Output
1 SPI Error Error Response No Update No Effect
2 SPI MISO Error Error Response No Update No Effect
3 Invalid Request Error Response No Update No Effect
4 DEVINIT Bit Set Error Response No Update Disabled
5 DEVRES Error Error Response No Update Disabled
6 CRC Error Error Response No Update No Effect
7 Self-Test Error Error Response No Update No Effect
8 Offset Monitor Over Range No Effect No Effect No Effect
9ΣΔ Over Range No Effect No Effect No Effect
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MMA685x
4.5.1 SPI Error
The following SPI conditions result in a SPI error:
• SCLK is high when CS is asserted
• the number of SCLK rising edges detected while CS is asserted is not equal to 16
• SCLK is high when CS is negated
• Command message parity error (MOSI)
• Bit 15 of Acceleration Data Request is not equal to ‘0’
• Bits 3 through 11 of an Acceleration Request are not equal to ‘0’
• Bits 0 through 7 of a Register Read Request are not equal to ‘0’
MMA685x responds to a SPI error with a “SPI Error” response as shown in Table 27. This applies to both acceleration data
request SPI errors, and Register Access SPI errors.
The arming function will not be updated if a SPI Error is detected. The PCM output is not affected by a SPI Error.
4.5.2 SPI Data Output Verification Error
MMA685x includes a function to verify the integrity of the data output to the MISO pin. The function reads the data transmitted
on the MISO pin and compares it against the data intended to be transmitted. If any one bit doesn’t match, a SPI MISO Mismatch
Fault is detected and the MISOERR flag in the DEVSTAT register is set.
If a valid SPI acceleration request message is received during the SPI transfer with the MISO mismatch failure, the SPI accel-
eration request message is ignored and MMA685x responds with a “MISO Error” response during the subsequent SPI message
(reference Table 27). The Arming function is not updated if a MISO mismatch failure occurs. The PCM function is not affected by
the MISO mismatch failure.
If a valid SPI register write request message is received during the SPI transfer with the MISO mismatch failure, the register
write is completed as requested, but MMA685x responds with a “MISO Error” response as shown in Table 27, during the subse-
quent SPI message.
If a valid SPI register read request message is received during the SPI transfer with the MISO mismatch failure, the register
read is ignored and MMA685x responds with a “MISO Error” response as shown in Table 27, during the subsequent SPI mes-
sage. If the register read request is for the DEVSTAT register, th e DEVSTAT register will not be cleared.
In all cases, the MISOERR flag in the DEVSTAT register will remain set until a successful SPI Register Read Request of the
DEVSTAT register is completed.
Figure 34. SPI Data Output Verification
4.5.3 I nvalid Re quests
4.5.3.1 Invalid Acceleration Request
The following conditions result in an “Invalid Acceleration Request” error:
• The Axis Selection bit (AX) in the Command message is set
• The SPI “Acceleration Data Request” Command data listed in Section 4.3, Table 29 does not match the internal
register settings
MMA685x responds to an “Invalid Acceleration Request” error with an “Invalid Acce l Request” response as specified in
Table 27 on the subsequent SPI message only. No internal fault is recorded. The arming function will not be updated if an “Ac-
celeration Data Request Mismatch” Error is detected. The PCM output is not affected by the “Acceleratio n Data Request Mis-
match” error.
Register operations will be executed as specified in Section 4.4.
D Q
R
D Q
R
DQ
SCLK
SPI DATA OUT SHIFT REGISTER DATA OUT BUFFER
MISO
MISO ERR
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48 Freescale Semiconductor, Inc.
MMA685x
4.5.3.2 Invalid Register Request
The following conditions result in an “Invalid Register Request” error:
• An attempt is made to write to an un-writable register (Writable registers are defined in Section 3.1, Table 3).
Attempts to write to registers $0D, $0F, $11, and $13 will also result in an error.
• An attempt is made to write to a register while the ENDINIT bit in the DEVCFG register is set
– This applies to all registers with the exception of the DEVCTL register
• An attempt is made to read an un-readable register (Readable registers are defined in Section 3.1, Table 3).
Attempts to read registers $07, $0D, $0F, $11, and $13 will also result in an error.
MMA685x responds to an Invalid Register Request” error with an “Invalid Regi ster Request” response as shown in Table 27.
4.5.4 Device Reset Indications
If the DEVINIT, or DEVRES bit is set in the DEVSTAT register as described in Section 3.1.10, MMA685x will respond to ac-
celeration data requests with an “Internal Error Present” response until the bits are cleared in the DEVST A T register. The DEVINIT
bit is cleared automatically when device initialization is complete (Reference tOP in Section 2.6). The DEVRES bit is cleared on
a read of the DEVST A T register . The arming function will not be updated on Acceleration Data Request commands if the DEVINIT
or DEVRES bit is set in the DEVSTAT register. The PCM output is disabled if the DEVINIT or DEVRES bit is set.
4.5.5 Internal Error
The following errors will result in an internal error, and set the IDE bit in the DEVSTAT register:
• OTP CRC Failure
• Writable Register CRC Failure
• Self-Test Error
• Invalid internal logic states
4.5.5.1 CRC Error
If the IDE bit is set in the DEVSTA T register due to an OTP Shadow Register or Writ able Register CRC failure as described in
Section 3.2, MMA685x will respond to acceleration data requests with an “Internal Error Present” response until the IDE bit is
cleared in the DEVSTAT register. The arming function will not be updated on Acceleration Data Request commands if a CRC
Error is detected. The PCM output is not aff ect ed by th e C R C error.
If the CRC error is in the writable register array, and the ENDINIT bit in the DEVCFG register has been set, the error can only
be cleared by a device reset. The IDE bi t will not be cleared on a read of the DEVSTAT register.
If the CRC error is in the OTP shadow register array, the error cannot be cleared.
Register operations will be executed as specified in Section 4.4.
4.5.5.2 Self-Test Error
If the IDE bit is set in the DEVSTAT register due to a Self-Test activation failure, MMA685x will respond to acceleration data
requests with a “Self-Test Error” response until the IDE bit is cleared in the DEVSTAT register. The arming function will not be
updated on Acceleration Data Request commands if a Self-Test Error is detected. The PCM output is not affected by the Self-
Test Error. The IDE bit in the DEVSTAT register will remain set until a read of the DEVSTAT register occurs, even if the internal
failure is removed. If the internal error is still present when the DEVSTAT register is read , the IDE bit will remain set.
Register operations will be executed as specified in Section 4.4.
4.5.6 Offset Monitor Over Range
If an offset monitor over range is present as described in Section 3.8.5, MMA685x will respond to an acceleration request with
a “Valid Acceleration Data Request” response, but the Status bits (S[1:0]) will be set to ‘10’. The arming function will be updated
on Acceleration Data Request commands even if an Offset Monitor Over Range is detected. Once the over range condition is
removed, MMA685x will respond to acceleration requests with a “Valid Acceleration Data Request” response with the S tatus bits
(S[1:0]) set to ‘10’ on the next SPI transfer , and a “V alid Acceleration Data Request” response with normal status on subsequent
SPI transfers. The OFF bit in the DEVSTAT register will remain set until a read of the DEVSTAT register occurs.
The PCM output is not affected by the offset monitor over range condition.
Register operations will be executed as specified in Section 4.4.
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MMA685x
4.5.7 ΣΔ Over Range
If a ΣΔ Over Range failure is present as described in Section 3.1 1.2 , MMA685x will respond to acceleration data requests with
a “Valid Acceleration Data Request” response, but the Status bits (S[1:0]) will be set to ‘10’. The arming function will be updated
on Acceleration Data Request commands even if a ΣΔ Over Range is detected. Once the over range condition is removed,
MMA685x will respond to acceleration requests with a “Valid Acceleration Data Request” response with the Status bits (S[1:0])
set to ‘10’ on the next SPI transfer , and a “Valid Acceleration Data Request” response with normal status on subsequent SPI
transfers. The SDOV bit in the DEVSTAT register will remain set until a read of the DEVSTAT register occurs.
The PCM output is not affected by the ΣΔ over range condition.
Register operations will be executed as specified in Section 4.4.
4.6 Initialization SPI Response
The first data transmitted by MMA685x following reset is the SPI Error response shown in Table 27. This ensures that an un-
expected reset will always be detectable. MMA685x will respond to all acceleration data requests with the “Invalid Acceleration
Data Request” response until the DEVRES bit in the DEVST A T register is cleared via a read of the DEVST A T register . The arming
function will not be updated on Acceleration Data Request commands until the DEVRES bit in the DEVSTAT register is cleared.
4.7 Acceleration Data Representation
Acceleration values are determined from the 10-bit digital output (DV) using the following equations:
The linear range of digital values for signed data is -480 to +480, and for unsigned data is 32 to 992. Resulting ranges and
some nomina l acc el e ra ti on v al u es are shown in Table 31.
Figure 35 shows the how the possib le output data codes are determined from the input data and the error sources. The rele-
vant parameters are specified in Section 2.4.
Acceleration SensitivityLSB DV 512–()×=
Acceleration SensitivityLSB DV×=For Signed Data
For Unsigned Data
Table 31. Nominal Acceleration Data Values
Unsigned
Digital Value Signed
Digital Value
Nominal Acceleration
Trimmed for
Maximum Sensitivity
(g)
Trimmed for
Maximum Range
(g)
993 - 1023 481 - 511 Unused
992 480 19.666 117.19
991 479 19.625 116.94
•
•
•
•
•
•
•
•
•
•
•
•
514 2 +0.082 +0.488
513 1 +0.041 +0.244
512 0 0 0
511 -1 -0.041 -0.244
510 -2 -0.082 -0.488
•
•
•
•
•
•
•
•
•
•
•
•
33 -479 -19.625 -116.94
32 -480 -19.666 -117.19
1 - 31 -481 to -511 Unused
0 -512 Fault
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50 Freescale Semiconductor, Inc.
MMA685x
Figure 35. MMA685x Acceleration Data Output Vs. Acceleration Input
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MMA685x
5 Package
5.1 Case Outline Drawing
Reference Freescale Case Outli ne Drawing # 98ASA00090D
http://www.freescale.com/files/shared/doc/package_info/98ASA00090D.pdf
5.2 Recommended Footprint
Reference Freescale Application Note AN3111, latest revision:
http://www.freescale.com/files/sensors/doc/app_note/AN3111.pdf
Table 32. Revision History
Revision
number Revision
date Description of changes
4 12/2011 • Updated ordering table to include Tube options; deleted MMA6852 and MMA6854.
• Deleted MMA6852 and MMA6854 de vices from Electrical Characteristics table, lines 57 and 60.
Removed “QR2” from device names, lines 56-59.
• Updated equation in section 3.6, Self-Test Interface.
5 03/2012 • Added SafeAssure logo, changed first paragraph and disclaimer to inclu de trademark
information.
MMA685x
Rev. 5
03/2012
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