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April 2013
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDMF6823B • Rev. 1.0.3
FDMF6823B — Extra-Small, High-Performance, High-Frequency DrMOS Module
FDMF6823B — Extra-Small, High-Performance,
High-Frequency DrMOS Module
Benefits
Ultra-Compact 6x6 mm PQFN, 72% Space-Saving
Compared to Conventional Discrete Solutions
Fully Optimized System Efficiency
Clean Switching Waveforms with Minimal Ringing
High-Current Handling
Features
Over 93% Peak-Efficiency
High-Current Handling: 55 A
High-Performance PQFN Copper-Clip Package
3-State 5 V PWM Input Driver
Skip-Mode SMOD# (Low-Side Gate Turn Off) Input
Thermal Warning Flag for Over-Temperature
Condition
Driver Output Disable Function (DISB# Pin)
Internal Pull-Up and Pull-Down for SMOD# and
DISB# Inputs, Respectively
Fairchild PowerTrench® Technology MOSFETs for
Clean Voltage Waveforms and Reduced Ringing
Fairchild SyncFET™ (Integrated Schottky Diode)
Technology in Low-Side MOSFET
Integrated Bootstrap Schottky Diode
Adaptive Gate Drive Timing for Shoot-Through
Protection
Under-Voltage Lockout (UVLO)
Optimized for Switching Frequencies up to 1 MHz
Low-Profile SMD Package
Fairchild Green Packaging and RoHS Compliance
Based on the Intel® 4.0 DrMOS Standard
Description
The XS™ DrMOS family is Fairchild’s next-generation,
fully optimized, ultra-compact, integrated MOSFET plus
driver power stage solution for high-current, high-
frequency, synchronous buck DC-DC applications. The
FDMF6823B integrates a driver IC, two power
MOSFETs, and a bootstrap Schottky diode into a
thermally enhanced, ultra-compact 6x6 mm package.
With an integrated approach, the complete switching
power stage is optimized with regard to driver and
MOSFET dynamic performance, system inductance,
and power MOSFET RDS(ON). XS™ DrMOS uses
Fairchild's high-performance PowerTrench® MOSFET
technology, which dramatically reduces switch ringing,
eliminating the need for snubber circuit in most buck
converter applications.
A driver IC with reduced dead times and propagation
delays further enhances the performance. A thermal
warning function warns of a potential over-temperature
situation. The FDMF6823B also incorporates a Skip
Mode (SMOD#) for improved light-load efficiency. The
FDMF6823B also provides a 3-state 5 V PWM input for
compatibility with a wide range of PWM controllers.
Applications
High-Performance Gaming Motherboards
Compact Blade Servers, V-Core and Non-V-Core
DC-DC Converters
Desktop Computers, V-Core and Non-V-Core
DC-DC Converters
Workstations
High-Current DC-DC Point-of-Load Converters
Networking and Telecom Microprocessor Voltage
Regulators
Small Form-Factor Voltage Regulator Modules
Ordering Information
Part Number Current Rating Package Top Mark
FDMF6823B 55 A 40-Lead, Clipbond PQFN DrMOS, 6.0 mm x 6.0 mm Package FDMF6823B
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDMF6823B • Rev. 1.0.3 2
FDMF6823B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Typical Application Circuit
V5V
DISB#
PWM
Input
OFF
ON
CVDRV CVIN
CBOOT
RBOOT
LOUT COUT
VIN
FDMF6823C
Open-
Drain
Output
VDRV VCIN VIN
PWM
THWN#
BOOT
CGND PGND
DISB#
PHASE
SMOD#
CVCIN
VOUT
VSWH
3V ~ 16V
RVCIN
Figure 1. Typical Application Circuit
DrMOS Block Diagram
Figure 2. DrMOS Block Diagram
SMOD#
PWM
VCIN
VDRV VIN
PGND
PHASE
GH
DBoot
BOOT
GL
CGND
DISB#
THWN#
Q1
HS Power
MOSFET
Input
3- State
Logic
RUP_PWM
VCIN
VCIN
UVLO
GH
Logic
Level-Shift
Dead-Time
Control
Temp.
Sense
30kΩ
GL
Logic
10µA
10µA
RDN_PWM
Q2
LS Power
MOSFET
VSWH
VDRV
30kΩ
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDMF6823B • Rev. 1.0.3 3
FDMF6823B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Pin Configuration
Figure 3. Bottom View Figure 4. Top View
Pin Definitions
Pin # Name Description
1 SMOD#
When SMOD#=HIGH, the low-side driver is the inverse of the PWM input. When
SMOD#=LOW, the low-side driver is disabled. This pin has a 10 µA internal pull-up current
source. Do not add a noise filter capacitor.
2 VCIN IC bias supply. Minimum 1 µF ceramic capacitor is recommended from this pin to CGND.
3 VDRV
Power for the gate driver. Minimum 1 µF ceramic capacitor is recommended to be connected
as close as possible from this pin to CGND.
4 BOOT
Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a
bootstrap capacitor from this pin to PHASE.
5, 37, 41 CGND IC ground. Ground return for driver IC.
6 GH For manufacturing test only. This pin must float; it must not be connected to any pin.
7 PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin.
8 NC
No connect. The pin is not electrically connected internally, but can be connected to VIN for
convenience.
9 - 14, 42 VIN Power input. Output stage supply voltage.
15, 29 -
35, 43 VSWH Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point
for the adaptive shoot-through protection.
16 – 28 PGND Power ground. Output stage ground. Source pin of the low-side MOSFET.
36 GL For manufacturing test only. This pin must float; it must not be connected to any pin.
38 THWN#
Thermal warning flag, open collector output. When temperature exceeds the trip limit, the
output is pulled LOW. THWN# does not disable the module.
39 DISB#
Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are
held LOW). This pin has a 10 µA internal pull-down current source. Do not add a noise filter
capacitor.
40 PWM
PWM signal input. This pin accepts a three-state 5 V PWM signal from the controller.
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDMF6823B • Rev. 1.0.3 4
FDMF6823B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Absolute Maximum Ratings
Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol Parameter Min. Max. Unit
VCIN Supply Voltage Referenced to CGND -0.3 6.0 V
VDRV Drive Voltage Referenced to CGND -0.3 6.0 V
VDISB# Output Disable Referenced to CGND -0.3 6.0 V
VPWM PWM Signal Input Referenced to CGND -0.3 6.0 V
VSMOD# Skip Mode Input Referenced to CGND -0.3 6.0 V
VGL Low Gate Manufacturing Test Pin Referenced to CGND -0.3 6.0 V
VTHWN# Thermal Warning Flag Referenced to CGND -0.3 6.0 V
VIN Power Input Referenced to PGND, CGND -0.3 25.0 V
VBOOT Bootstrap Supply Referenced to VSWH, PHASE -0.3 6.0 V
Referenced to CGND -0.3 25.0 V
VGH High Gate Manufacturing Test Pin Referenced to VSWH, PHASE -0.3 6.0 V
Referenced to CGND -0.3 25.0 V
VPHS PHASE Referenced to CGND -0.3 25.0 V
VSWH Switch Node Input Referenced to PGND, CGND (DC Only) -0.3 25.0 V
Referenced to PGND, <20 ns -8.0 28.0 V
VBOOT Bootstrap Supply Referenced to VDRV 22.0 V
Referenced to VDRV, <20 ns 25.0 V
ITHWN# THWN# Sink Current -0.1 7.0 mA
IO(AV) Output Current(1) fSW=300 kHz, VIN=12 V, VO=1.0 V 55
A
fSW=1 MHz, VIN=12 V, VO=1.0 V 50
θJPCB Junction-to-PCB Thermal Resistance 2.7 °C/W
TA Ambient Temperature Range -40 +125 °C
TJ Maximum Junction Temperature +150 °C
TSTG Storage Temperature Range -55 +150 °C
ESD Electrostatic Discharge Protection Human Body Model, JESD22-A114 2000 V
Charged Device Model, JESD22-C101 2500
Note:
1. IO(AV) is rated using Fairchild’s DrMOS evaluation board, at TA = 25°C, with natural convection cooling. This rating
is limited by the peak DrMOS temperature, TJ = 150°C, and varies depending on operating conditions and PCB
layout. This rating can be changed with different application settings.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol Parameter Min. Typ. Max. Unit
VCIN Control Circuit Supply Voltage 4.5 5.0 5.5 V
VDRV Gate Drive Circuit Supply Voltage 4.5 5.0 5.5 V
VIN Output Stage Supply Voltage 3.0 12.0 16.0(2) V
Note:
2. Operating at high VIN can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes
during MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must
remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the “Application
Information” and “PCB Layout Guidelines” sections of this datasheet for additional infor mat ion.
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDMF6823B • Rev. 1.0.3 5
FDMF6823B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Electrical Characteristics
Typical values are VIN = 12 V, VCIN = 5 V, VDRV = 5 V, and TA = TJ = +25°C unless otherwise noted.
Symbol Parameter Condition Min. Typ. Max. Unit
Basic Operation
IQ Quiescent Current IQ=IVCIN+IVDRV, PWM=LOW or HIGH or Float 2 mA
VUVLO UVLO Threshold VCIN Rising 2.9 3.1 3.3 V
VUVLO_Hys UVLO Hysteresis 0.4 V
PWM Input (VCIN = VDRV = 5 V ±10%)
RUP_PWM Pull-Up Impedance VPWM=5 V 10 kΩ
RDN_PWM Pull-Down Impedance VPWM=0 V 10 kΩ
VIH_PWM PWM High Level Voltage 3.04 3.55 4.05 V
VTRI_HI 3-State Upper Threshold 2.95 3.45 3.94 V
VTRI_LO 3-State Lower Threshold 0.98 1.25 1.52 V
VIL_PWM PWM Low Level Voltage 0.84 1.15 1.42 V
tD_HOLD-OFF 3-State Shut-Off Time 160 200 ns
VHiZ_PWM 3-State Open Voltage 2.20 2.50 2.80 V
tPWM-OFF_MIN PWM Minimum Off Time 120 ns
PWM Input (VCIN = VDRV = 5 V ±5%)
RUP_PWM Pull-Up Impedance VPWM=5 V 10 kΩ
RDN_PWM Pull-Down Impedance VPWM=0 V 10 kΩ
VIH_PWM PWM High Level Voltage 3.22 3.55 3.87 V
VTRI_HI 3-State Upper Threshold 3.13 3.45 3.77 V
VTRI_LO 3-State Lower Threshold 1.04 1.25 1.46 V
VIL_PWM PWM Low Level Voltage 0.90 1.15 1.36 V
tD_HOLD-OFF 3-State Shut-Off Time 160 200 ns
VHiZ_PWM 3-State Open Voltage 2.30 2.50 2.70 V
tPWM-OFF_MIN PWM Minimum Off Time 120 ns
DISB# Input
VIH_DISB High-Level Input Voltage 2 V
VIL_DISB Low-Level Input Voltage 0.8 V
IPLD Pull-Down Current 10 µA
tPD_DISBL Propagation Delay PWM=GND, Delay Between DISB# from
HIGH to LOW to GL from HIGH to LOW 25 ns
tPD_DISBH Propagation Delay PWM=GND, Delay Between DISB# from
LOW to HIGH to GL from LOW to HIGH 25 ns
SMOD# Input
VIH_SMOD High-Level Input Voltage 2 V
VIL_SMOD Low-Level Input Voltage 0.8 V
IPLU Pull-Up Current 10 µA
tPD_SLGLL Propagation Delay PWM=GND, Delay Between SMOD# from
HIGH to LOW to GL from HIGH to LOW 10 ns
tPD_SHGLH Propagation Delay PWM=GND, Delay Between SMOD# from
LOW to HIGH to GL from LOW to HIGH 10 ns
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDMF6823B • Rev. 1.0.3 6
FDMF6823B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Electrical Characteristics
Typical values are VIN = 12 V, VCIN = 5 V, VDRV = 5 V, and TA = TJ = +25°C unless otherwise noted.
Symbol Parameter Condition Min. Typ. Max. Unit
Thermal Warning Flag
TACT Activation Temperature 150 °C
TRST Reset Temperature 135 °C
RTHWN Pull-Down Resistance IPLD=5 mA 30 Ω
250 ns Timeout Circuit
tD_TIMEOUT Timeout Delay SW=0V, Delay Between GH from HIGH to
LOW and GL from LOW to HIGH 250 ns
High-Side Driver (fSW = 1000 kHz, IOUT = 30 A, TA = +25°C)
RSOURCE_GH Output Impedance, Sourcing Source Current=100 mA 1 Ω
RSINK_GH Output Impedance, Sinking Sink Current=100 mA 0.8 Ω
tR_GH Rise Time GH=10% to 90% 10 ns
tF_GH Fall Time GH=90% to 10% 10 ns
tD_DEADON LS to HS Deadband Time GL Going LOW to GH Going HIGH,
1.0 V GL to 10% GH 15 ns
tPD_PLGHL PWM LOW Propagation
Delay
PWM Going LOW to GH Going LOW,
VIL_PWM to 90% GH 20 30 ns
tPD_PHGHH PWM HIGH Propagation
Delay (SMOD# =0)
PWM Going HIGH to GH Going HIGH,
VIH_PWM to 10% GH (SMOD# =0, ID_LS>0) 30 ns
tPD_TSGHH Exiting 3-State Propagation
Delay
PWM (From 3-State) Going HIGH to GH
Going HIGH, VIH_PWM to 10% GH 30 ns
Low-Side Driver (fSW = 1000 kHz, IOUT = 30 A, TA = +25°C)
RSOURCE_GL Output Impedance, Sourcing Source Current=100 mA 1 Ω
RSINK_GL Output Impedance, Sinking Sink Current=100 mA 0.5 Ω
tR_GL Rise Time GL=10% to 90% 25 ns
tF_GL Fall Time GL=90% to 10% 10 ns
tD_DEADOFF HS to LS Deadband Time SW Going LOW to GL Going HIGH,
2.2 V SW to 10% GL 15 ns
tPD_PHGLL PWM-HIGH Propagation
Delay
PWM Going HIGH to GL Going LOW,
VIH_PWM to 90% GL 10 25 ns
tPD_TSGLH Exiting 3-State Propagation
Delay
PWM (From 3-State) Going LOW to GL
Going HIGH, VIL_PWM to 10% GL 20 ns
Boot Diode
VF Forward-Voltage Drop IF=20 mA 0.3 V
VR Breakdown Voltage IR=1 mA 22 V
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDMF6823B • Rev. 1.0.3 7
FDMF6823B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Figure 5. PWM Timing Diagram
t
D_DEADON
PWM
VSWH
GH
to
VSWH
GL
tPD_PHGLL
tD_DEADOFF
V
IH
_
PWM
VIL
_
PWM
90%
90%
1.0V
10%
tPD PLGHL
10%
1.2V
250ns Timeout)
D
_
TIMEOUT
t
(
2.2V
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDMF6823B • Rev. 1.0.3 8
FDMF6823B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Typical Performance Characteristics
Test Conditions: VIN=12 V, VOUT=1 V, VCIN=5 V, VDRV=5 V, LOUT=250 nH, TA=25°C, and natural convection cooling,
unless otherwise specified.
Figure 6. Safe Operating Area Figure 7. Power Loss vs. Output Current
Figure 8. Power Loss vs. Switching Frequ ency Figure 9. Power Loss vs. Input Voltage
Figure 10. Power Loss vs. Driver Supply Voltage Figure 11. Power Loss vs. Output Voltage
0
5
10
15
20
25
30
35
40
45
50
55
0 25 50 75 100 125 150
Module Output Current, I
OUT
(A)
PCB Temperature, T
PCB
(°C)
F
SW
= 300kHz
F
SW
= 1000kHz
V
IN
= 12V, V
DRV
& V
CIN
= 5V, V
OUT
= 1V
0
1
2
3
4
5
6
7
8
9
10
11
0 5 10 15 20 25 30 35 40 45 50 55
Module Power Loss, PL
MOD
(W)
Module Output Cur rent, I
OUT
(A)
300kHz
500kHz
800kHz
1000kHz
V
IN
= 12V, V
DRV
& V
CIN
= 5V, V
OUT
= 1V
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
100 200 300 400 500 600 700 800 900 1000 1100
Normalized Module Power Loss
Module Switching Frequency, F
SW
(kHz)
V
IN
= 12V, V
DRV
& V
CIN
= 5V, V
OUT
= 1V, I
OUT
= 30A
0.96
0.98
1.00
1.02
1.04
1.06
1.08
1.10
4 6 8 1012141618
Normalized Module Power Loss
Module Input Voltage, V
IN
(V)
V
DRV
& V
CIN
= 5V, V
OUT
= 1V, F
SW
= 300kHz, I
OUT
= 30A
0.90
0.95
1.00
1.05
1.10
1.15
4.0 4.5 5.0 5.5 6.0
Normalized Module Power Loss
Driver Supply Voltage, V
DRV
& V
CIN
(V)
V
IN
= 12V, V
OUT
= 1V, F
SW
= 300kHz, I
OUT
= 30A
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Normalized Module Power Loss
Module Output Voltage, V
OUT
(V)
V
IN
= 12V, V
DRV
& V
CIN
= 5V, F
SW
= 300kHz, I
OUT
= 30A
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDMF6823B • Rev. 1.0.3 9
FDMF6823B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Typical Performance Characteristics
Test Conditions: VIN=12 V, VOUT=1 V, VCIN=5 V, VDRV=5 V, LOUT=250 nH, TA=25°C, and natural convection cooling,
unless otherwise specified.
Figure 12. Power Loss vs. Output Inductor Figure 13. Driver Supply Current vs. Switching
Frequency
Figure 14. Driver Supply Current vs. Driver Supply
Voltage Figure 15. Driver Supply Current vs. Output Current
Figure 16. UVLO Threshold vs. Temperature Figure 17. PWM Threshold vs. Driver Supply Voltage
0.94
0.95
0.96
0.97
0.98
0.99
1.00
1.01
200 250 300 350 400 450 500
Normalized Module Power Loss
Output Inductor, L
OUT
(nH)
V
IN
= 12V, V
DRV
& V
CIN
= 5V, F
SW
= 300kHz, V
OUT
= 1V, I
OUT
= 30A
0
10
20
30
40
50
60
100 200 300 400 500 600 700 800 900 1000 1100
Driver Supply Current, I
DRV
& I
CIN
(mA)
Module Switching Frequency, F
SW
(kHz)
V
IN
= 12V, V
DRV
& V
CIN
= 5V, V
OUT
= 1V, I
OUT
= 0A
12
14
16
18
20
22
4.0 4.5 5.0 5.5 6.0
Driver Supply Current, I
DRV
& I
CIN
(mA)
Driver Supply Voltage , V
DRV
& V
CIN
(V)
V
IN
= 12V, V
OUT
= 1V, F
SW
= 300kHz, I
OUT
= 0A
0.97
0.98
0.99
1.00
1.01
1.02
1.03
0 5 10 15 20 25 30 35 40 45 50 55
Normalized Driv er Supply Curr ent
Module Output Cur rent, I
OUT
(A)
V
IN
= 12V, V
DRV
& V
CIN
= 5V, V
OUT
= 1V
F
SW
= 300kHz
F
SW
= 1000kHz
2.6
2.7
2.8
2.9
3.0
3.1
3.2
-55 0 25 55 100 125 150
Driver IC Supply Voltage, V
CIN
(V)
Driver IC Junction Temperature, T
J
(
o
C)
UVLO
UP
UVLO
DN
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
4.50 4.75 5.00 5.25 5.50
PWM Threshold Voltage, V
PWM
(V)
Driver IC Supply Voltage, V
CIN
(V)
V
IH_PWM
T
A
= 25°C
V
TRI_HI
V
TRI_LO
V
IL_PWM
V
HIZ_PWM
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDMF6823B • Rev. 1.0.3 10
FDMF6823B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Typical Performance Characteristics
Test Conditions: VCIN=5 V, VDRV=5 V, TA=25°C, and natural convection cooling, unless otherwise specified.
Figure 18. PWM Threshold vs. Temperature Figure 19. SMOD# Threshold vs. Driver Supply
Voltage
Figure 20. SMOD# Threshold vs. Temperature Figure 21. SMOD# Pull-Up Current vs. Temperature
Figure 22. DISB# Threshold vs. Driver Supply
Voltage Figure 23. DISB# Threshold vs. Temperature
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-55 0 25 55 100 125 150
PWM Threshold Voltage, V
PWM
(V)
Driver IC Junction Temperature, T
J
(
o
C)
V
CIN
= 5V
V
IH_PWM
V
TRI_HI
V
HIZ_PWM
V
TRI_LO
V
IL_PWM
1.2
1.4
1.6
1.8
2.0
2.2
4.50 4.75 5.00 5.25 5.50
SMOD# Threshold Voltage, V
SMOD
(V)
Driver IC Supply Voltage, V
CIN
(V)
V
IH_SMOD#
V
IL_SMOD#
T
A
= 25°C
1.2
1.4
1.6
1.8
2
2.2
-55 0 25 55 100 125 150
SMOD# Threshold Voltage, V
SMOD
(V)
Driver IC Junction Te m pe rature, T
J
(
o
C)
V
IH_SMOD#
V
IL_SMOD#
V
CIN
= 5V
-12.0
-11.5
-11.0
-10.5
-10.0
-9.5
-9.0
-55 0 25 55 100 125 150
SMOD# Pull -Up Curren t, I
PLU
(uA)
Driver IC Junction Temperature, T
J
(
o
C)
V
CIN
= 5V
1.2
1.4
1.6
1.8
2.0
2.2
4.50 4.75 5.00 5.25 5.50
DISB# Threshold Voltage, V
DISB
(V)
Driver IC Supply Voltage, V
CIN
(V)
V
IH_DISB#
V
IL_DISB#
T
A
= 25°C
1.2
1.4
1.6
1.8
2.0
2.2
-55 0 25 55 100 125 150
DISB# Threshold Voltage, V
DISB
(V)
Driver IC Junction Te m perature, T
J
(
o
C)
V
IH_DISB#
V
IL_DISB#
V
CIN
= 5V
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDMF6823B • Rev. 1.0.3 11
FDMF6823B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Typical Performance Characteristics
Test Conditions: VCIN=5 V, VDRV=5 V, TA=25°C, and natural convection cooling, unless otherwise specified.
Figure 24. DISB# Pull-Down Current vs.
Temperature Figure 25. Boot Diode Forward Voltage vs.
Temperature
9.0
9.5
10.0
10.5
11. 0
11. 5
12.0
-55 0 25 55 100 125 150
DISB# P ull-Dow n Curren t, I
PLD
(uA)
Driver IC Junction Te m pe rature, T
J
(
o
C)
V
CIN
= 5V
100
150
200
250
300
350
400
450
500
-55 0 25 55 100 125 150
Boot Diode Forward Voltage , V
F
(mV)
Driver IC Junction Temperature, T
J
(
o
C)
I
F
= 20mA
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDMF6823B • Rev. 1.0.3 12
FDMF6823B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Functional Description
The FDMF6823B is a driver-plus-FET module optimized
for the synchronous buck converter topology. A single
PWM input signal is all that is required to properly drive
the high-side and the low-side MOSFETs. Each part is
capable of driving speeds up to 1 MHz.
VCIN and Disable (DISB#)
The VCIN pin is monitored by an Under-Voltage Lockout
(UVLO) circuit. When VCIN rises above ~3.1 V, the driver
is enabled. When VCIN falls below ~2.7 V, the driver is
disabled (GH, GL=0). The driver can also be disabled by
pulling the DISB# pin LOW (DISB# < VIL_DISB), which
holds both GL and GH LOW regardless of the PWM
input state. The driver can be enabled by raising the
DISB# pin voltage HIGH (DISB# > VIH_DISB).
Table 1. UVLO and Disable Logic
UVLO DISB# Driver State
0 X Disabled (GH, GL=0)
1 0 Disabled (GH, GL=0)
1 1 Enabled (see Table 2)
1 Open Disabled (GH, GL=0)
Note:
3. DISB# internal pull-down current source is 10 µA.
Thermal Warning Flag (THWN#)
The FDMF6823B provides a thermal warning flag
(THWN#) to warn of over-temperature conditions. The
thermal warning flag uses an open-drain output that
pulls to CGND when the activation temperature (150°C)
is reached. The THWN# output returns to a high-
impedance state once the temperature falls to the reset
temperature (135°C). For use, the THWN# output
requires a pull-up resistor, which can be connected to
VCIN. THWN# does NOT disable the DrMOS module.
Figure 26. THWN Operation
Three-State PWM Input
The FDMF6823B incorporates a three-state 5 V PWM
input gate drive design. The three-state gate drive has
both logic HIGH level and LOW level, along with a
three-state shutdown window. When the PWM input
signal enters and remains within the three-state window
for a defined hold-off time (tD_HOLD-OFF), both GL and GH
are pulled LOW. This enables the gate drive to shut
down both high-side and low-side MOSFETs to support
features such as phase shedding, which is common on
multi-phase voltage regulators.
Exiting Three-State Condition
When exiting a valid three-state condition, the
FDMF6823B follows the PWM input command. If the
PWM input goes from three-state to LOW, the low-side
MOSFET is turned on. If the PWM input goes from
three-state to HIGH, the high-side MOSFET is turned
on. This is illustrated in Figure 27. The FDMF6823B
design allows for short propagation delays when exiting
the three-state window (see Electrical Characteristics).
Low-Side Driver
The low-side driver (GL) is designed to drive a ground-
referenced, low-RDS(ON), N-channel MOSFET. The bias
for GL is internally connected between the VDRV and
CGND pins. When the driver is enabled, the driver's
output is 180° out of phase with the PWM input. When
the driver is disabled (DISB#=0 V), GL is held LOW.
High-Side Driver
The high-side driver (GH) is designed to drive a floating
N-channel MOSFET. The bias voltage for the high-side
driver is developed by a bootstrap supply circuit
consisting of the internal Schottky diode and external
bootstrap capacitor (CBOOT). During startup, VSWH is held
at PGND, allowing CBOOT to charge to VDRV through the
internal diode. When the PWM input goes HIGH, GH
begins to charge the gate of the high-side MOSFET (Q1).
During this transition, the charge is removed from CBOOT
and delivered to the gate of Q1. As Q1 turns on, VSWH
rises to VIN, forcing the BOOT pin to VIN + VBOOT, which
provides sufficient VGS enhancement for Q1. To complete
the switching cycle, Q1 is turned off by pulling GH to
VSWH. CBOOT is then recharged to VDRV when VSWH falls to
PGND. GH output is in-phase with the PWM input. The
high-side gate is held LOW when the driver is disabled or
the PWM signal is held within the three-state window for
longer than the three-state hold-off time, tD_HOLD-OFF.
150°C
A
ctivation
Tem
p
e
r
ature
TJ_driver IC
Thermal
Warning
Normal
Operation
HIGH
LOW
135°C Reset
Temperature
THWN#
Logic
State
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDMF6823B • Rev. 1.0.3 13
FDMF6823B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Adaptive Gate Drive Circuit
The driver IC advanced design ensures minimum
MOSFET dead-time, while eliminating potential shoot-
through (cross-conduction) currents. It senses the state
of the MOSFETs and adjusts the gate drive adaptively
to ensure they do not conduct simultaneously. Figure 27
provides the relevant timing waveforms. To prevent
overlap during the LOW-to-HIGH switching transition
(Q2 off to Q1 on), the adaptive circuitry monitors the
voltage at the GL pin. When the PWM signal goes
HIGH, Q2 begins to turn off after a propagation delay
(tPD_PHGLL). Once the GL pin is discharged below 1.0 V,
Q1 begins to turn on after adaptive delay tD_DEADON.
To preclude overlap during the HIGH-to-LOW transition
(Q1 off to Q2 on), the adaptive circuitry monitors the
voltage at the GH-to-PHASE pin pair. When the PWM
signal goes LOW, Q1 begins to turn off after a
propagation delay (tPD_PLGHL). Once the voltage across
GH-to-PHASE falls below 2.2 V, Q2 begins to turn on
after adaptive delay tD_DEADOFF.
Figure 27. PWM and 3-StateTiming Diagram
tPD_TSGHH
V
SWH
GH
to
V
SWH
GL
t
PD_PHGLL tD_HOLD-OFF
90%
Exit
3-state
1.0V
PWM
VIL_PWM
VIH_PWM
VTRI_HI
VIH_PWM VIH_PWM
10%
t
R_GL
tD_HOLD-OFF
Exit
3-state
VIH_PWM
VTRI_HI
VTRI_LO
VIL_PWM
t
PD_PLGHL tPD_TSGHH
DCM
tF_GH
tR_GH
tD_HOLD-OFF
10%
CCM DCM
Exit
3-state
90%
10%
90%
Enter
3-state
Enter
3-state
tD_DEADOFF
t
D_DEADON Enter
3-state
tF_GL
VIN
VOUT
2.2
V
tPD_TSGLH
Notes:
tPD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal. Example (tPD_PHGLL – PWM going HIGH to LS VGS (GL) going LOW)
tD_xxx = delay from IC generated signal to IC generated signal. Example (tD_DEADON – LS VGS (GL) LOW to HS VGS (GH) HIGH)
PWM Exiting 3-state
tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS t
PD_TSGHH = PWM 3-state to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS
tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS t
PD_TSGLH = PWM 3-state to LOW to LS VGS rise, VIL_PWM to 10% LS VGS
tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (SMOD# held LOW)
SMOD# Dead Times
tPD_SLGLL = SMOD# fall to LS VGS fall, VIL_SMOD to 90% LS VGS t
D_DEADON = LS VGS fall to HS VGS rise, LS-comp trip value (~1.0V GL) to 10% HS VGS
tPD_SHGLH = SMOD# rise to LS VGS rise, VIH_SMOD to 10% LS VGS t
D_DEADOFF = VSWH fall to LS VGS rise, SW-comp trip value (~2.2V VSWH) to 10% LS VGS
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDMF6823B • Rev. 1.0.3 14
FDMF6823B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Skip Mode (SMOD#)
The Skip Mode function allows for higher converter
efficiency when operated in light-load conditions. When
SMOD# is pulled LOW, the low-side MOSFET gate
signal is disabled (held LOW), preventing discharge of
the output capacitors as the filter inductor current
attempts reverse current flow – known as “Diode
Emulation” Mode.
When the SMOD# pin is pulled HIGH, the synchronous
buck converter works in Synchronous Mode. This mode
allows for gating on the Low Side MOSFET. When the
SMOD# pin is pulled LOW, the low-side MOSFET is
gated off. If the SMOD# pin is connected to the PWM
controller, the controller can actively enable or disable
SMOD# when the controller detects light-load condition
from output current sensing. Normally this pin is active
LOW. See Figure 28 for timing delays.
Table 2. SMOD# Logic
DISB# PWM SMOD# GH GL
0 X X 0 0
1 3-State X 0 0
1 0 0 0 0
1 1 0 1 0
1 0 1 0 1
1 1 1 1 0
Note:
4. The SMOD# feature is intended to have a short propagation delay between the SMOD# signal and the low-side
FET VGS response time to control diode emulation on a cycle-by-cycle basis.
Figure 28. SMOD# Timing Diagram
tD_DEADON
PWM
SWH
GH
to
SWH
GL
tPD_PHGLL tPD_PLGHL
tD_DEADOFF
VIH_PWM
VIL_PWM
90%
10%
90%
1.0V
2.2V
tPD_PHGHH tPD_SHGLH
Delay from SMOD# going
HIGH to LS VGS HIGH
HS turn -on with SMOD# LOW
SMOD
#
tPD_SLGLL
Delay from SMOD# going
LOW to LS VGS LOW
DCM
CCM
CCM
10%
VIH_PWM
10%
VOUT
VIH_SMOD
VIL_SMOD
10%
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDMF6823B • Rev. 1.0.3 15
FDMF6823B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Application Information
Supply Capacitor Selection
For the supply inputs (VCIN), a local ceramic bypass
capacitor is recommended to reduce noise and to
supply the peak current. Use at least a 1 µF X7R or X5R
capacitor. Keep this capacitor close to the VCIN pin and
connect it to the GND plane with vias.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(CBOOT), as shown in Figure 30. A bootstrap capacitance
of 100 nF X7R or X5R capacitor is usually adequate. A
series bootstrap resistor may be needed for specific
applications to improve switching noise immunity. The
boot resistor may be required when operating above
15 VIN and is effective at controlling the high-side
MOSFET turn-on slew rate and VSHW overshoot. RBOOT
values from 0.5 to 3.0 Ω are typically effective in
reducing VSWH overshoot.
VCIN Filter
The VDRV pin provides power to the gate drive of the
high-side and low-side power MOSFET. In most cases,
it can be connected directly to VCIN, the pin that
provides power to the logic section of the driver. For
additional noise immunity, an RC filter can be inserted
between the VDRV and VCIN pins. Recommended
values would be 10 Ω and 1 µF.
Power Loss and Efficiency
Measurement and Calculatio n
Refer to Figure 30 for power loss testing method.
Power loss calculations are:
PIN=(VIN x IIN) + (V5V x I5V) (W) (1)
PSW=VSW x IOUT (W) (2)
POUT=VOUT x IOUT (W) (3)
PLOSS_MODULE=PIN - PSW (W) (4)
PLOSS_BOARD=PIN - POUT (W) (5)
EFFMODULE=100 x PSW/PIN (%) (6)
EFFBOARD=100 x POUT/PIN (%) (7)
Figure 29. Block Diagram With VCIN Filter
Figure 30. Power Loss Measurement
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDMF6823B • Rev. 1.0.3 16
FDMF6823B — Extra-Small, High-Performance, High-Frequency DrMOS Module
PCB Layout Guidelines
Figure 31 and Figure 32 provide an example of a proper
layout for the FDMF6823B and critical components. All
of the high-current paths, such as VIN, VSWH, VOUT,
and GND copper, should be short and wide for low
inductance and resistance. This aids in achieving a
more stable and evenly distributed current flow, along
with enhanced heat radiation and system performance.
Recommendations for PCB Designers
1. Input ceramic bypass capacitors must be placed
close to the VIN and PGND pins. This helps reduce
the high-current power loop inductance and the input
current ripple induced by the power MOSFET
switching operation.
2. The VSWH copper trace serves two purposes. In
addition to being the high-frequency current path
from the DrMOS package to the output inductor, it
serves as a heat sink for the low-side MOSFET in
the DrMOS package. The trace should be short and
wide enough to present a low-impedance path for
the high-frequency, high-current flow between the
DrMOS and inductor. The short and wide trace
minimizes electrical losses as well as the DrMOS
temperature rise. Note that the VSWH node is a high-
voltage and high-frequency switching node with high
noise potential. Care should be taken to minimize
coupling to adjacent traces. Since this copper trace
acts as a heat sink for the lower MOSFET, balance
using the largest area possible to improve DrMOS
cooling while maintaining acceptable noise emission.
3. An output inductor should be located close to the
FDMF6823B to minimize the power loss due to the
VSWH copper trace. Care should also be taken so the
inductor dissipation does not heat the DrMOS.
4. PowerTrench® MOSFETs are used in the output
stage and are effective at minimizing ringing due to
fast switching. In most cases, no VSWH snubber is
required. If a snubber is used, it should be placed
close to the VSWH and PGND pins. The selected
resistor and capacitor need to be the proper size for
power dissipation.
5. VCIN, VDRV, and BOOT capacitors should be
placed as close as possible to the VCIN-to-CGND,
VDRV-to-CGND, and BOOT-to-PHASE pin pairs to
ensure clean and stable power. Routing width and
length should be considered as well.
6. Include a trace from the PHASE pin to the VSWH pin
to improve noise margin. Keep this trace as short as
possible.
7. The layout should include the option to insert a
small-value series boot resistor between the boot
capacitor and BOOT pin. The boot-loop size,
including RBOOT and CBOOT, should be as small as
possible. The boot resistor may be required when
operating above 15 VIN and is effective at controlling
the high-side MOSFET turn-on slew rate and VSHW
overshoot. RBOOT can improve noise operating
margin in synchronous buck designs that may have
noise issues due to ground bounce or high positive
and negative VSWH ringing. Inserting a boot
resistance lowers the DrMOS efficiency. Efficiency
versus noise trade-offs must be considered. RBOOT
values from 0.5 Ω to 3.0 Ω are typically effective in
reducing VSWH overshoot.
8. The VIN and PGND pins handle large current
transients with frequency components greater than
100 MHz. If possible, these pins should be
connected directly to the VIN and board GND
planes. The use of thermal relief traces in series with
these pins is discouraged since this adds inductance
to the power path. This added inductance in series
with either the VIN or PGND pin degrades system
noise immunity by increasing positive and negative
VSWH ringing.
9. GND pad and PGND pins should be connected to
the GND copper plane with multiple vias for stable
grounding. Poor grounding can create a noise
transient offset voltage level between CGND and
PGND. This could lead to faulty operation of the gate
driver and MOSFETs.
10. Ringing at the BOOT pin is most effectively
controlled by close placement of the boot capacitor.
Do not add an additional BOOT to the PGND
capacitor. This may lead to excess current flow
through the BOOT diode.
11. The SMOD# and DISB# pins have weak internal
pull-up and pull-down current sources, respectively.
These pins should not have any noise filter
capacitors. Do not to float these pins unless
absolutely necessary.
12. Use multiple vias on the VIN and VOUT copper
areas to interconnect top, inner, and bottom layers
to distribute current flow and heat conduction. Do
not put many vias on the VSWH copper to avoid
extra parasitic inductance and noise on the
switching waveform. As long as efficiency and
thermal performance are acceptable, place only
one VSWH copper on the top layer and use no vias
on the VSWH copper to minimize switch node
parasitic noise. Vias should be relatively large and
of reasonably low inductance. Critical high-
frequency components, such as RBOOT, CBOOT, RC
snubber, and bypass capacitors; should be located
as close to the respective DrMOS module pins as
possible on the top layer of the PCB. If this is not
feasible, they can be connected from the backside
through a network of low-inductance vias.
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDMF6823B • Rev. 1.0.3 17
FDMF6823B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Figure 31. PCB Layout Example (Top View)
Figure 32. PCB Layout Example (Bottom View)
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDMF6823B • Rev. 1.0.3 18
FDMF6823B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Physical Dimensions
Figure 33. 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0 mm Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the mo st recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
BOTTOM VIEW
LAND PATTERN
RECOMMENDATION
NOTES: UNLESS OTHERWISE SPECIFIED
A) DOES NOT FULLY CONFORM TO JEDEC
REGISTRATION MO-220, DATED
MAY/2005.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
E) DRAWING FILE NAME: PQFN40AREV3
SEE
DETAIL 'A'
DETAIL 'A'
SCALE: 2:1
SEATING
PLANE
0.65
0.40
2.10
0.50 TYP
4.50
5.80
2.50
0.25 1.60
0.60
0.15
2.10
0.35
1
TOP VIEW
FRONT VIEW
C
0.30
0.20
0.05
0.00
1.10
0.90
0.10 C
0.08 C
10
11
20
2130
31
40
0.40
0.50
(0.70)
0.40
2.00±0.10 2.00±0.10
(0.20) (0.20)
1.50±0.10 0.50
0.30 (40X)
0.20
6.00
6.00
0.10 C
2X
B
A
0.10 C
2X
0.30
0.20 (40X)
4.40±0.10
0.10 CAB
0.05 C
(2.20)
0.50
10 1
40
31
30
21
20
11
PIN#1
INDICATOR
PIN #1 INDICATOR
MAY APPEAR AS
OPTIONAL
2.40±0.10
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDMF6823B • Rev. 1.0.3 19
FDMF6823B — Extra-Small, High-Performance, High-Frequency DrMOS Module
www.onsemi.com
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