TS88CO196EC - Intel Corporation

Intel® 88CO196EC CHMOS 16-Bit

Microcontroller

Dat ash e et

Pr oduct Feature s

The Intel® 88CO196EC CHMOS 16-Bit Microcontroller is the first member of

th e MCS®9 6 fam ily of microc ontrollers to integrate flash memory on-chip. T he

Intel® 88CO196EC, with its integrated fla sh memory, brings a new level of

integrat ion that offers embedded system designers cost-effective solutions.

•256 Kbytes on-chip flash program memory

•40 MHz operation

•Opt ional cloc k quadr uple r

•Programmable clock output signal

(CLKOUT)

•2 Mbytes of linear address space

•1.25 Kbytes of register RAM

•2.75 Kbytes of code RAM

•Reg ister-to-register arch itec ture

•Stack overflow/underflow monitor with

user-defined upper and lower stack pointer

boundary limits

•Two periphera l interr upt handlers (PIHs)

provid e dire ct h ardware h andlin g of up to 45

interrupts

•Up to 59 I/O port pins

•Full-duple x serial port with dedicated

baud-rate generator

•Enhanced synchronous serial I/O unit

(SSIO)

•16 10-bit A/D channels with auto-scan

mode and dedicated results registers

•Controller area network (CAN) 2.0

networking protocol

•Serial debug unit provide s read and write

access to code RAM with no CPU overhead

•Chip-selec t unit (CSU)

— Three chip-selec t pi ns

— Dynamic demultiplexed/multiplexed

addres s/data bus fo r eac h chip - select

— Programmable wait states

(0, 1, 2, or 3) for each chip- select

— Programmable bus w idth (8- or 16-bit)

fo r each chip -sel ect

— Progra mm able address range for each

chip-select

•Event pr ocessor array (EPA)

— Two flexible 16-bit timer/counters

— Five high-speed capture/compare

channels with a lock f eature for noise

filtering

— 10 enhanced high-speed

capture/compare channels with period

and duty c ycle measurement capability,

as well as a lock feature for noise

filtering

•Complete system development support

•Packaging

— 1 32- pin PQFP

•Te m p eratur e Off eri n gs

— Commercial (0C - 70C)

— Extended (-40C - 85C)

Order Number: 273970-002

August, 2004

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Designers must not r ely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoev er for conflicts or incompatibilities arising from future changes to them.

The Intel® 88CO196EC CHMOS 16-Bit Microcontroller may contain design defects or errors k nown as errata which may cause the product to deviate

from published spec ifications. Current characterized errata are available on request.

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Intel® 88CO196E C

Contents

1.0 Product Overview...............................................................................................................7

1.1 Nomenclature Overview........................................................................................8

2.0 Pinout.................................................................................................................................9

3.0 Signals..............................................................................................................................11

4.0 Addre ss Ma p.......... ............ ............ ........... ............ ............ ............ ............ ............ ...........21

5.0 Ele ctrical Chara cteris ti c s.... ............ ........... ............ ............ ............ ............ ............ ...........23

5.1 DC Characteristics ..............................................................................................23

6.0 Explanation of AC Symbols....................... ................... ................... .............. ............ .......25

6.1 AC Characteristics — Multiplexed Bu s Mode......................................................26

6.2 AC Charact e ristics — Demul tiplexed Bus Mode......... ............ ............ ....... .........30

6.3 Deferred Bus Timing M ode .................................................................................34

6.4 AC Characteristics — Serial Port, Mode 0......... .... ..... ..... .. ..... .. ..... ..... ....... .. ..... ..35

6.5 AC Charact e r istics — S yn ch r o n ous Ser ial Port. ............ ....... ........... ............ .......36

6.6 A C Characteristics — Serial Debug Unit. .................................................... ........37

6.7 A/D Sample and Convers ion Times....................................................................38

6.7.1 AC Characteristics — A/D Converter, 10-Bi t Mode................................39

6.7.2 AC Characteristics — A/D Converter, 8-Bit Mode..................................40

6.8 Exte r n a l Clock Dri ve................. ............ ........... ............ ....... ............ ............ .........41

6.9 Test Output Wa veforms ......................................................................................42

6.10 Flash Memo ry Era s e Per fo r man ce.. ............ ........... ............ ............ ............ .........42

7.0 Therm a l Ch ar acteristi cs.. ............ ............ ............ ............ ............ ........... ............ ............ ..43

Figures 1 Intel® 88CO196EC CHMOS 16-Bit Microcontroller Block Diagram ......... .... ..... .. ..7

2 Product Nomenclature . ................................... .................................................... ...8

3 Intel® 88CO196EC CHM OS 16-Bit Microcontroller 132-Pin PQFP Package........9

4 Sys te m Bu s Timi n g Diagr a m (Mul tiplexe d Bus Mode).......... ........... ............ .......28

5 READY Timing Diagram (Multiplexed Bus Mode)...............................................29

6 Sys te m Bu s Timi n g Diagr a m (De multiplexed Bu s Mode) ..... ........... ............ .......32

7 READ Y Timing Diagram (Demul tiplexed Bus Mode) ..........................................33

8 Deferred Bus Mode Timing Diagram...................................................................34

9 Serial Port Waveform — Mode............................................................................35

10 Synchronous Se rial Port... ...................................................................................36

11 Serial Debug Unit................................................................................................37

12 External Cl ock Drive Waveforms.........................................................................41

13 AC Testing Output Wavef o r ms........ ............ ........... ............ ............ ............ .........42

14 F lo a t Wav ef o r ms Dur ing 5. 0 Volt Testing.... ....... ............ ........... ............ ....... .......42

Intel® 88CO196E C

Tables 1 Descripti on o f Pro duct Nomenclature ...................................................................8

2 Intel® 88CO 196E C CHMOS 16-Bit Microcontroller

132-Pin PQFP Pa ckage Pin Assignm ent s .... ......................................................10

3 Signal Descriptions .............................................................................................11

4 Intel® 88CO 196E C CHMOS 16-Bit Microcontroller Address Map.................. .....21

5 DC Characteristics at Vcc = 4.7 5 V – 5.25 V............. ............ ............ ............ ......23

6 AC Timing Symbol Definitions .............................................................................25

7 AC Characteristics, Multip lexed Bus Mode.........................................................26

8 AC Characteristics, Demultiplexed Bus Mode ....................................................30

9 Serial Port Timing — Mode 0†.............................................................................35

10 Synchro nous Se r ial Port Timin g.... ............ ............ ............ ........... ............ ...........36

11 Serial Debug Unit Timing....................................................................................37

12 10-bit A/D Operating Conditi ons ... ....... ..... ....... .. ....... .......... .. ....... ....... ..... ....... ....39

13 10-Bit Mode A/D Characteristics Over Specified Operating Conditions..............39

14 8-Bit A/D Operating Con ditions...........................................................................40

15 8-Bit Mode A/D Characteristics Ov er Specified Operating Condition s................40

16 External Clock Drive............................................................................................41

17 Flash Memory Erase Performance .....................................................................42

18 Thermal Characteristics ......................................................................................43

Intel® 88CO196EC

Revision History

Date Revision Description

February 2004 001 Initial release

August 2004 002 To address the fact that many of the package prefix variables

have changed, all package prefix variables in this document

are now indicated with an "x".

Intel® 88CO196E C

In tel® 88CO 196EC

Datasheet 7

1.0 Product Overview

The Intel® 88CO196EC CHMOS 16-Bit Microcontroller is highly integrated with an enhanc ed

peripheral set. The integrated CAN 2. 0 networking protocol p rovides for efficient communi cation

to a high-spee d CAN bus. The serial debug unit (SDU) provides system de bug and development

capabil it ies. T he SDU can set a single hardwa re b reakpoi nt. In a dditi on, the SDU prov ide s read a nd

write acce ss to code RAM through a high -speed, de dicat ed serial l ink. A stack ove rflow/unde rfl ow

monitor assists in code development by causing a nonm askable interrupt if the stack pointer

cros se s a user-defined boundary. The 16-cha nnel A/D converter supports an auto-sca n mod e that

operates with no CPU overhead. Ea ch A/D channel has a dedicat ed resu lt register. The E PA

supports high-sp eed eve nt captures and out put compares wi th 15 programmable, hi gh-speed

channels.

Figure 1. Intel® 88CO196EC CHMOS 16-Bit Microcontroller Block Diagram

Code/Data

RAM

2.75 Kbytes

Port 6

Queue

A20:16

Source (16)

Destination (16)

AD15:0

SIO Baud-rate

Generator

EPA 2 Timers

Ports 7,8

5 Capture/

Compares

A/D

Converter

Bus

Controller

A15:0

Serial Debug

Unit

Watchdog

Timer Stack

Overflow

Module CAN SSIO0

SSIO1

Flash

256 Kbytes

A4324-01

Port 9

Bus-Control

Interface Unit

Microcode

Engine

Chip-select

Unit

Peripheral

Transaction

Server

Memory

Interface

Unit

RAM

1.25 Kbytes

ALU

Interrupt

Controller

Peripheral

Interrupt

Handler

Bus Control

Peripheral Addr Bus (10)

Peripheral Data Bus (16)

Memory Addr Bus (24)

Port 3,4,5

10 Enhanced

Capture/

Compares

Port 2

Memory Data Bus (16)

Intel® 88CO196E C

8Datasheet

1.1 Nomenclature Overview

Figu re 2. Product Nom encla ture

Table 1. Description of Product Nomenclature

Parameter Options Description

Tem p er a tu r e Op ti on s x

xCommercial tempera ture range (0° C to 70° C ca se)

Extended temper atur e range (–40° C to 85° C case)

Program-Memory xInternal flash memory

Process Inform ation C CHMOS

Product Type O Standard Embedded Product

Product Family 196EC

Device Speed no mark 40 MHz

B3165-01

Program Memory Options

XX8XX

Temperature

Process Information

XXXXX XX

Product Type

Product Family

Stepping Identifier

In tel® 88CO 196EC

Datasheet 9

2.0 Pinout

Figure 3. Intel® 88CO196EC CHMOS 16-Bit Microcontroller 132-Pin PQFP Package

B3055-01

P3.3 / AD3 / PBUS3

P3.4 / AD4 / PBUS4

P3.5 / AD5 / PBUS5

P3.6 / AD6 / PBUS6

P3.7 / AD7 / PBUS7

P4.0 / AD8 / PBUS8

P4.1 / AD9 / PBUS9

P4.2 / AD10 / PBUS10

P4.3 / AD11 / PBUS11

P4.4 / AD12 / PBUS12

P4.5 / AD13 / PBUS13

P4.6 / AD14 / PBUS14

P4.7 / AD15 / PBUS15

CRBUSY#

CROUT

CRDCLK

VSS

VPP

CRIN

VSS

PLLEN

VSS

VCC

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

ACH7

ACH8

ACH9

ANGND

VREF

VCC

VSS

ACH10

ACH11

ACH12

ACH13

ACH14

ACH15

VSS

VCC

P8.0 / EPAPWM8 / BLK0#

P8.1 / EPAPWM9 / BLK1#

P8.2 / EPA10 / T1CLK / BLK2#

P8.3 / EPA11 / T1RST / BLK3#

P8.4 / EPA12 / T2CLK

P8.5 / EPA13 / T2RST

P8.6 / EPA14

P8.7

VCC

VSS

P7.0 / EPAPWM0

P7.1 / EPAPWM1

P7.2 / EPAPWM2

P7.3 / EPAPWM3

P7.4 / EPAPWM4

P7.5 / EPAPWM5

P7.6 / EPAPWM6

P7.7 / EPAPWM7

ACH6

ACH5

ACH4

ACH3

ACH2

ACH1

ACH0

VCC

VSS

P2.0 / TXD

P2.1 / RXD / PALE#

P2.2 / EXTINT / PROG#

P2.3

P2.4 / AINC#

P2.5

P2.6 / HOLD# / CPVER / ONCE# / HLDA#

P2.7 / CLKOUT / PACT#

VSS

VCC

TXCAN

RXCAN

P9.2 / SC0

P9.3 / SD0

P9.4 / SC1 / CHS#

P9.5 / SD1

P9.6

P9.7

NMI

RESET#

EA#

P3.0 / AD0 / PBUS0

P3.1 / AD1 / PBUS1

P3.2 / AD2 / PBUS2

A15

A14

A13

A12

VCC

VSS

A11

P6.0 / A16 / PBUS16

P6.1 / A17/ PBUS17

P6.2 / A18/ PBUS18

P6.3 / A19/ PBUS19

P6.4 / A20/ PBUS20

P6.5 / CS0# / PMODE0

P6.6 / CS1#/ PMODE1

P6.7 / CS2#/ PMODE2

VSS

VCC

P5.0 / ALE / ADV#

P5.1 / INST

P5.2 / WR# / WRL#

P5.3 / RD#

P5.4 / BREQ# / TMODE0#

VSSPLL

VCCPLL

XTAL2

XTAL1

VCC

P5.5 / BHE# / WRH# / TMODE1#

P5.6 / READY

P5.7 / RPD

A10

88CO196EC

View of component as mounted on PC board.

Intel® 88CO196E C

10 Datasheet

Table 2. Intel® 88CO196E C CHMO S 16-Bit Microc ontroller 132 -Pin PQFP P ackag e Pin

Assignments

Pin Name Pin Name Pin Name

1 ACH7 45 P6.4/A20/PBUS20 89 P4.5/AD13/PBUS13

2 ACH8 46 P6.5/CS0#/PMODE0 90 P4.4/AD12/PBUS12

3 ACH9 47 P6.6/CS1#/PMODE1 91 P4.3/AD11/PBUS11

4 ANGND 48 P6.7/CS2#/PMODE2 92 P4.2/AD10/PBUS10

REF 49 VSS 93 P4.1/AD9/PBUS9

CC 50 VCC 94 P4.0/AD8/PBUS8

SS 51 P5.0/ALE/ADV# 95 P3.7/AD7/PBUS7

8 ACH10 52 P5.1/INST 96 P3.6/AD6/PBUS6

9 ACH11 53 P5.2/WR#/WRL# 97 P3.5/AD5/PBUS5

10 ACH12 54 P5.3/RD# 98 P3.4/AD4/PBUS4

11 ACH13 55 P5.4/BREQ#/TMODE0# 99 P3.3/AD3/PBUS3

12 ACH14 56 VSSPLL 100 P3.2/AD2/PBUS2

13 ACH15 57 VCCPLL 101 P3.1/AD1/PBUS1

14 VSS 58 XTAL2 102 P3.0/AD0/PBUS0

15 VCC 59 XTAL1 103 EA#

16 P8.0/EPAPWM8/BLK0# 60 VCC 104 RESET#

17 P8.1/EPAPWM9/BLK1# 61 P5.5/BHE#/WRH#/TMODE1# 105 NMI

18 P8.2/EPA10/T1CLK/BLK2# 62 P5.6/READY 106 P9.7

19 P8.3/EPA11/T1RST/BLK3# 63 P5.7/RPD 107 P9.6

20 P8.4/EPA12/T2CLK 64 A10 108 P9.5/SD1

21 P8.5/EPA13/T2RST 65 A9 109 P9.4/SC1/CHS#

22 P8.6/EPA14 66 A8 110 P9.3/SD0

23 P8.7 67 A0 111 P9.2/SC0

24 VCC 68 A1 112 RXCAN

25 VSS 69 A2 113 TXCAN

26 P7.0/EPAPWM0 70 A3 114 VCC

27 P7.1/EPAPWM1 71 A4 115 VSS

28 P7.2/EPAPWM2 72 A5 116 P2.7/CLKOUT/PACT#

29 P7.3/EPAPWM3 73 A6 117 P2.6/HLDA#/ONCE#/CPVER

30 P7.4/EPAPWM4 74 A7 118 P2.5 HOLD#

31 P7.5/EPAPWM5 75 VCC 119 P2.4/AINC#

32 P7.6/EPAPWM6 76 VSS 120 P2.3

33 P7.7/EPAPWM7 77 PLLEN 121 P2.2/EXTINT/PROG#

34 A15 78 VSS 122 P2.1/RXD/PALE#

35 A14 79 VSS 123 P2.0/TXD

36 A13 80 VSS 124 VSS

37 A12 81 CRIN 125 VCC

38 VCC 82 VPP 126 ACH0

39 VSS 83 VSS 127 ACH1

40 A11 84 CRDCLK 128 ACH2

41 P6.0/A16/PBUS16 85 CROUT 129 ACH3

42 P6.1/A17/PBUS17 86 CRBUSY# 130 ACH4

43 P6.2/A18/PBUS18 87 P4.7/AD15/PBUS15 131 ACH5

44 P6.3/A19/PBUS19 88 P4.6/AD14/PBUS14 132 ACH6

In tel® 88CO 196EC

Datasheet 11

3.0 Signals

Table 3. Signal Descriptions (Sheet 1 of 9)

Name Type Description

A15:0 O System Address Bus

These address pins provide address bits 0–15 during the entire external memory

cycle during both multiplexed and demultiplexed bus modes.

A20:16 O

Address Pins 16–20

These address pins provide address bits 16–20 during the entire external memory

cycle during both multiplexed and demultiplexed bus modes, supporting extended

addressing of the 2-Mby te addr ess space.

NOTE: Internally, there are 24 address bits; however, only 21 external address pins

(A20:0) are implemen ted. The internal address space is 16 Mbytes

(000000–FFFFFFH) and the external address space i s 2 Mbytes

(000000–1FFFFFH). The microcontroller resets t o F F2080H in internal

mem ory or 1F208 0H in exte rnal me m ory.

A20:16 share package pins with P6.4:0 and PBUS20:16.

ACH15:0 I Analog Channels

These signals are analog inputs to the A/D converter .

The ANGND and VREF pins must be connec ted for the A/D converter to function.

AD15:0 I/O

Ad dres s/D a ta Li nes

The function of these pins depends on the bus width and mode.

16-bit Multiplexed Bus Mode:

AD15:0 drive address bits 0–15 during the first half of the bus cycle a nd drive or

receive d ata during the second half of the bus cyc le.

8-bit Multiplexed Bus Mode:

AD 15:8 drive ad dress bits 8–15 during the entire bus cycle. AD7:0 drive address

bits 0–7 durin g the fi rst ha lf of the bus cycle and drive or receive data during the

s econd half of the bus cycl e.

16-bit Demultiplexed Mode:

AD 15:0 drive or receive data durin g the ent ire bu s cycle.

8-bit Dem ulti ple xe d Mo de :

AD7 :0 dr i ve or rece iv e d at a d ur ing th e e ntir e bus cyc le . A D15 :8 dr i ve the da t a that

is currently on the high byte of the internal bus.

AD15:8 share package pins with P4.7:0. AD7:0 share package pins with P3.7:0.

ADV# O

Address Valid

This active-low out put signal is asserted only during exter nal memory accesses.

ADV# indicates that valid address information is available on the system

addr e ss /dat a bu s. Th e si gn al re ma ins lo w whi le a vali d b us cy cl e is in pr og res s an d is

returned high as soon as the bus cycle completes.

An e xt ern al l atch ca n u se thi s s ig na l to de mu ltip l ex the a dd r ess f r om the ad dres s/ da ta

bus. A decoder can also use this signal to generate chip selects for external memory.

AD V# shares a package pin wit h P5.0 and ALE.

AINC# I

Auto In crem en t

During slave program m ing, t his active-low input enables the auto-increment feature.

(Auto increment allows reading or writing of sequential flash memory locations,

without requiring address transactions across the programming bus for each read or

wr ite.) AINC# is sampled after each location i s programmed or dumped. If AI NC# is

asserted, the address is incremented and the next data word is programmed or

dumped.

AINC# shares a packag e pin with P2.4.

Intel® 88CO196E C

12 Datasheet

ALE O

Addres s Latch E nable

This active-high output sign al is asserted only du ring e xternal memory cycles. ALE

s ignals the sta rt of an external bus cycle an d indicates that val id addr ess information

is available on the system address/data bus.

An e xtern al latch can us e this signal to demultiplex address bits 0–15 from the

addres s/dat a bus in multiplexed mo de.

ALE shares a package pin with P5.0 and ADV#.

ANGND GND Analog Ground

ANGND must be connected for A/D converter operation. ANGND and VSS should be

nomina ll y at t he sam e potent ial .

BHE# O

Byte High E nable†

During 16-bit bus cycles, this active-low output signal is asserted for word and

high-byte reads and writes to external memory. BHE# indicates that valid data is

being transferred over the upper half of the system data bus. Use BHE#, in

conjunction with address bit 0 (A0 for a demultiplexed address bus, AD0 for a

m ultip lexed address/data bus), to determine which memory byte is be ing transfer red

over the system bus:

BHE# AD0 or A0 Byte(s) Accessed

0 0 bot h by te s

0 1 high byte only

1 0 low byte only

BHE# shares a package pin with P5.5, TMODE1# and WRH#.

When thi s pin is configured a s a special-function sig nal (P5_MODE.5 = 1), the chip

configuration register 0 (CCR0) determin es whether it functions as BHE# or WRH#.

CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.

BLK3:0# O

Block x Active.

When activ e, these signals indica te that programming of d ata is occurring with in the

corresponding flash memory address range or that the corresponding physical block

is being erased. The address range and physical block associated with the BLKx#

signals are as follows:

Address Range Physical Block

BLK0# FC0000–FCFFFFH eve n bytes at FC0 00 0–FDFFFEH

BLK1# FD0000–FDFFF FH odd bytes at FC 0001–FDFFFFH

BLK2# FE0000–FEFFFFH even bytes at FE000 0–FFFFFEH

BLK3# FF0000–FFFFFFH odd bytes at FE0001–FFFFFFH

During test -ROM execution mode, the contents of pages FFH and FBH are swapped.

BLK1:0# s hares a package pin with P8.1:0 and EPAPWM9:8. BLK2# shares a

package pin with P8.2, EPA10, and T1 CLK. BL K3# shares a pa c kage pin with P8.3,

EPA11, and T1RST.

BREQ# O

Bus Request

This active-low output si gnal is a s sert ed during a hold cycle when t he bus controller

has a pending external memory cycle. When the bus-hold protocol is enabled

(WSR.7 is set), the P5.4/BREQ# pin can function only as BREQ#, regardless of the

configuration selected through the port configuration registers (P5_MODE, P5_DIR,

and P5_REG). An attemp t to chan ge the pin configuration i s ignored until t he

bus-hold protocol is disabled (WSR.7 is cleared).

The microcontroller can assert BREQ# at the same time as or after it asserts HLDA#.

On ce it is asserted, BREQ# remains asserted un til HOLD# is deassert ed.

BREQ# shares a package pin with P5.4 and TMODE0#.

CLKOUT O

Clock Out put

Output of the internal clock generator . You can select one of four frequencies: f/2, f/4,

f/8, or f/16. CLKOUT has a 50% duty cycle.

CLKOUT shares a package pin with P2.7 and PACT#.

Table 3. Signal Descrip tions (Sheet 2 of 9)

Name Type Description

In tel® 88CO 196EC

Datasheet 13

CPVER O

Cumulative Program Verification

During slave or U PROM programming, a hi gh signal indicates that the program

operat ion was s uccessful, while a low signal indicates t hat an error occurr ed duri ng

th e pro gr a m operati on .

CPVER shares a package pin with P2.6, HLDA#, and ONCE#.

CRBUSY# O Code RAM Busy

When active, this signal indicates that the serial debug unit (SDU) is busy processing

a code RAM command. No data can be transferred during this time.

CRDCLK I Code RAM Clock

Prov ides the clock signal for the serial de bug unit (SDU). The maximum clock

frequency equals one-half the operating frequency (f/2).

CRIN I

Code RAM Dat a Input

Serial input for test instructions and data into the serial debug unit (SDU). Data is

transferred in 8-bit bytes with the most-significant bit (MSB) first. Each byte is

sampled on th e rising edge of CRDCLK.

CROUT O

Code RAM Data Output

Serial output for data from the seri al debug unit (SDU). Data is transferred in 8-bit

bytes with the most-significant bit (MSB) first. Each byte is valid on the rising edge of

CRDCLK.

CS2:0# O

Chip-select Lines 0–2

The active-low output CSx# is asserted during an external memory cycle when the

address to be accessed is in the range programmed fo r chip select x. If the external

memory address is outside the rang e assigned to the three chip selects, no

chip-select output is asserted and the bus configuration defaults to the CS2# values.

Immediately fol lowing reset, C S0# is automatically assigned to the range

(1F2000–1F20FFH if external).

CS 2:0# share package pins with P6.7: 5 and PMOD E2:0.

EA# I

External Access

This input determines whether memory accesses to flash program memory partitions

(FC0000–F FF FFF H) are di rect e d to i nt er na l or ext er nal me mory. T he se acc ess es are

dir e cted to i nte rn al fl a sh me mo ry if EA# is h eld hi gh an d to ex te r nal me mor y i f EA # is

held low. For an access to any other m emory location, the value of EA# is irrelevant .

EA # i s s ample d an d l at ched on ly on t he ris in g e dge of RE SET #. Ch an gi ng th e le vel of

EA# after reset has no effect. Always connect EA# to VSS whe n us in g a

microcontroller that has no internal nonvolatile me mory or VCC when using the

internal flash memory.

EPA14:10 I/O

Event Processo r Array (EPA) Capture/Compare Channe ls

High-speed input/outpu t signals for t he E PA capture/compare channels.

EPA14 :10 sh ar e pack age pi ns wi th th e fol lo win g si gn als: EPA10/ P 8.2/ T 1CL K/B L K2#,

EPA11/P8.3/T1RST/BLK3#, EPA12/P8.4/T2CLK, EPA13/P8.5/T2RST, EPA14/P8.6.

EPAPWM9:0 I/O

Event Processor Array (EPA) PWM Receiver/Transmitter Channels

High-speed in put/ou tput si gnals for the enhanced E PA PWM receiver/t ransmi tter

channels.

EPAPWM9:8 share package pins with P8.1:0 and BLK1:0#. EPAPWM7:0 share

packag e pi ns wi th P7.7:0 .

Table 3. Signal Descriptions (Sheet 3 of 9)

Name Type Description

Intel® 88CO196E C

14 Datasheet

EXTINT I

External Interrupt

In normal operating mode, a rising edge on EXTINT sets the EXTINT interrupt

pending bit. EXTINT is sampled durin g phase 2 (CLKOUT high). The m inimum high

time is one state time.

In powerdown mode, asserting the EXTINT signal for at least 50 ns causes the

device to res ume normal operation. The int errupt does n ot need to b e enabled, bu t

the pin must be configured as a spec ial- function input. I f the EXT INT interrupt is

enabled, the CPU executes the interrupt serv ice routine. Oth erwise, the CPU

ex ecutes the i nstru ction t hat immediately follows the command tha t i nvoked t he

power-saving mode.

In i dle mode, asser ting any enabled interr upt causes the dev ice to resume normal

operation.

EXTINT shares a package pin with P2.2 an d PROG#.

HLDA# O

Bus Hold Acknowledge

The HLDA# pin is used in systems with more than one processor using the system

bus. The microcontroller asserts HLDA# to indicate that it has released the bus in

re sp on se to H OL D# a nd anot he r pr oc es sor c an take cont r ol. (Thi s s ig na l is a ct iv e l ow

to avoid misinterpretation by external hardware immediately after reset.)

When the bus-hold protocol is enabled (WSR.7 is set), the P2.6/HLDA# pin can

function only as HLDA#, regardless of the configuration selected through the port

configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change the

pin configuratio n is ignored until the bus-hold protocol is disabled (WSR.7 is cleared).

HOLD# I

Bus Hold Request

An e xternal device uses this active-l ow input signal to request contr ol of the bus.

When the bus-hold protocol is enabled (WSR.7 is set), the P2.5/HOLD# pin can

function only as HOLD#, regardless of the configuration selected through the port

configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change the

pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is cleared).

If P2.5 is configured as a genera l-purpose I/ O signal, the device does not r ecognize

s ignals on this pin as HOLD#. Instea d, t he bus controller receiv es an internal HOLD

signal. This enables the device to access the external bus while it is performing I/O at

P2.5.

INST O

Instruction Fetch

When high, IN ST i ndicates t hat an instructi on is being fetched from external memory.

The signal remains high during the entire bus cycle of an external instruction fetch.

IN ST is l ow for data accesses, including interrupt vector fetches and chip

configuration byte reads. INST is low during internal memory fetches.

INST shares a package pin with P5.1.

NMI I

Non ma s kabl e Interrupt

In normal operating mode, a rising edge on NMI generates a nonmaskable interrupt.

NMI has the highest priority of all prioritized interrupts. Assert NMI for greater than

one state time to guarantee that it is recognized.

ONCE# I

On-circuit Emul ation

Ho ld in g ONC E# lo w duri ng the r is in g edge of RES ET# pla ce s the mi cr oc on tro ll er i nt o

on-circuit emulation (ONCE) mode. This mode puts all pins i nto a high-impedan ce

state, thereby isolating the microcontroller from other components in the system. The

value of ON C E# is lat c he d w he n the RESET# pin goes inacti v e. Wh ile the

microcontroller is in ONCE mode, you can debug the system using a clip-on emulator .

To exit ONCE mode, reset the microcontroller by pulling the RESET# signal low. To

prevent inadve rtent entry into ON CE mode, either configure this pin as an output or

hold it high during reset and ensure t hat your system meets the VIH sp ec if ic ation .

ON CE # sh ar e s a pack ag e pin wi th P 2. 6, T M O DE 1 #, an d CP V ER .

Table 3. Signal Descrip tions (Sheet 4 of 9)

Name Type Description

In tel® 88CO 196EC

Datasheet 15

P2.7:0 I/O

Port 2

This is a standard, 8-bit, bidirectional port that shares package pins with individually

select ab le sp ec i al-fun ctio n si gn als .

P2.6 is mu ltiplexed with the ONCE function. If you choose to co nfigure this pin as an

input, alw ays hold it high during reset and ensure that your system meets the VIH

specification to prevent inadve rtent entry into ONCE mode.

Port 2 shares package pins with the following signals: P2.0/TXD, P2.1/RXD/PALE#,

P2.2/EXTINT/PROG#, P2.4/AINC#, P2.5 HOLD# P2.6/ONCE#/CPVER, HLDA#, and

P2.7/CLKOUT/PACT#.

P2.3 is a dedicated general-purpose I/O signal.

P3.7:0 I/O

Port 3

This is a memory-mapped, 8-bit, bidirectional port with pro gramma ble open-drain or

comp le men t ary ou tput mo de s. T he pi ns are s ha red w ith t h e mult i pl ex ed ad dr es s/da t a

bus, whic h has co m ple m en t ary dr iv ers .

P3.7:0 share package pins with AD7:0 and PBUS7:0.

P4.7:0 I/O

Port 4

This is a memory-mapped, 8-bit, bidirectional port with pro gramma ble open-drain or

comp le men t ary ou tput mo de s. T he pi ns are s ha red w ith t h e mult i pl ex ed ad dr es s/da t a

bus, whic h has co m ple m en t ary dr iv ers .

P4.7:0 s hare package pins with AD 15:8 and PBUS15:8.

P5.7:0 I/O

Port 5

This is a memory-mapped, 8-bit, bidire ctional port that shares package pins wi th

individually selectable control signals. P5.4 shares a package pin with TMODE0#. If

this pin is held low during reset, the device will enter a test mode. To prevent

inadver tent en try in to a reserved t est mode, either configure this pin as an output or

hold it high durin g reset and ensur e that your system meet s the VIH specification.

Port 5 shares package pins with the following signals: P5.0/ALE/ADV#, P5.1/INST,

P5.2/WR#/WRL#, P5.3/RD#, P5.4/BREQ#/TMODE0#, P5.5/BHE#/WRH#,

P5.6/ READY, and P5. 7/RP D.

P6.7:0 O

Port 6

This is a standard, 8-bit, bidirectional port individually selectable special-function

signals.

Por t 6 shar es package pins with the following signals: P6.0/A16/PBUS16,

P6.1/A17/PBUS17, P6.2/A18/PBUS18, P6.3/A19/PBUS19, P6.4/A20/PBUS20,

P6.5/CS0#/PMODE0, P6.6/CS1#/PMODE1, and P6.7/CS2#/PMODE2.

P7.7:0 I/O

Port 7

This is a standard, 8-bit, bidirectional port that shares package pins with individually

select ab le sp ec i al-fun ctio n si gn als .

P7.7:0 share package pins with EPAPWM7:0.

P8.7:0 I/O

Port 8

This is a standard, 8-bit, bidirectional port that shares package pins with individually

select ab le sp ec i al-fun ctio n si gn als .

Por t 8 shar es package pins with the following signals: P8.0/EPAPWM8/BLK0#,

P8.1/ EPAPWM9 /BL K1 #, P8. 2/E PA10/T1 CLK /BL K 2#, P8.3 /E PA11/T 1RST /BL K3 #,

P8.4/EPA12/T2CLK, P8.5/EPA13/T2RST, P8.6/EPA14.

P8.7 is a dedicated general-purpose I/O signal.

Table 3. Signal Descriptions (Sheet 5 of 9)

Name Type Description

Intel® 88CO196E C

16 Datasheet

P9.7:2 I/O

Port 9

This is a standard, 6-bit, bidirectional port that shares packa ge pins with individually

selectable special-function signals.

Port 9 shares package pins with the following signals: P9.2/SC0, P9.3/SD0,

P9.4/S C1, an d P9.5/S D 1.

P9.6 an d P9.7 are dedicated general-purpose I/O signals.

PACT#

O Pr ogramming Active

During slave or U PROM programming, a low signal indicates that programming is in

progress, while a hig h signal indi cates that the operation is comple te.

PACT# shares a pa ckage pin with P2.7 and CLKOUT.

PALE# I

Programming ALE

During slave or UPROM progra mming, a falling edge causes the m icrocontroller to

read the programming bus.

PALE# is mul tiplexed with P2.1 and RXD.

PBUS20:0 I/O

Addres s/Command/Data Bus

Address and data input/ou tput b us during slave and UPROM programming .

PBUS20:16 share package pins with A20:16 and P6.4:0; PBUS15:8 share package

pins with AD15:8 and P4.7:0; PBUS7:0 share package pins with AD7:0 and P3.7:0.

PLLEN I

Pha s e-locke d Loop Enab le

This active-high input pin enables the on-chip clock multiplier. This pin should be tied

to VCC to activate the PLL or VSS to disable the PLL. The state of the PLL can only be

change d at th e t im e of r es et .

PMODE2:0 I

Programming Mode Select

These pins, along with the TM ODE 1:0# pins, determine the programming mode.

PMODE2:0 are sampled af ter a device re set and must be static while the

microcontroller is operating.

PMODE2:0 share package pins with P6.7:5 and CS2:0#.

PROG# I

Programming Start

Du rin g pr ogr am mi ng, a fa ll i ng edge lat ch es dat a on th e pro gr a mming bus an d be gi ns

programming, while a rising edge ends programming. The current location is

programmed with the same data as long as PROG# remains asserted, so the data on

the programming bus must remain stable while PRO G# is active.

Du rin g a wor d dum p, a fa l li ng edg e ca us es t he con te nt s of a flas h me mory loc at ion t o

be output on the PBUS, while a rising edge ends the data transfer.

PR OG# shares a pac kage pin with P2.2 and EXTINT.

RD# O

Read

Re ad -si gn al ou tput t o ext er nal memo r y. RD# is ass ert ed only duri ng ex ter na l m emor y

reads.

RD # sh ares a package pin wit h P 5.3 .

READY I

Ready Input

This active-high input can be used to insert wait states in addition to those

programmed in the chi p configuration byte 0 (C CB0) and the bus cont rol x register

(BUSCONx). CCB0 is programmed with the mi nimum number of wait s tates (0–3) fo r

an external fetch of CCB1, and BUSCONx is programmed w ith t he minimum number

of wait states (0–3) for all external accesses to the address range assigned to t he

chip-select x chan nel. If READY is low when th e programmed number of wait states

is reached, additional wait states are added until READY is pulled high.

READY shares a package pin with P5.6.

Table 3. Signal Descrip tions (Sheet 6 of 9)

Name Type Description

In tel® 88CO 196EC

Datasheet 17

RESET# I/O

Reset

A level-sensitive reset input to, and an open- drain system reset output from, the

microcontroller. Either a falling edge on RESET# or an internal reset turns on a

pull-down transistor connected to the RESET# pin for 16 state times.

In the powerdown and idle modes, asserting RE SET# causes the microcontr oller to

re set and retu rn to nor ma l op era tin g mode . After a res et , the firs t ins tr uc tio n fet ch is

from FF2080H (or 1F2080H in external memory).

RPD I

Return from Powerdown

T iming pin fo r the return-from-powerdown circuit.

If your application uses powerdown mode, connect a capacitor between RPD and VSS

if either of the following conditions are true.

•The internal oscillator is the clock source

•The phase-locked loop (PLL) circuitry is enabled (see PLLEN signal description)

The capacitor causes a delay that enables the oscillator and PLL circuitry to stabilize

before the internal CPU and peripheral clocks are enabled. Refer to the “Special

Operating Modes” chapter of the for details on selecting the capacitor.

The capacitor is not required if your application uses powerdown mode and if both of

th e fol lo w in g co nd it i on s are tru e.

•An external clock input is the clock source

•The phase-locked loop circuitry is disabled

If your application does not use powerdown mode, leave this pin unconnected.

RP D s hares a package pin with P5 .7.

RXCAN I Receive CAN Mess age

This signal carr ies messages from ot her nod es on the CA N bus to the integrated

CAN controller.

RXD I/O

Re ce iv e S erial Da ta

In modes 1, 2, and 3, RXD recei ves serial port input data. In mode 0, it function s as

either an input or an open-drain output for data.

RX D s hares a package pin w ith P2 .1 and PALE#.

SC1:0 I/O

Clock Pins for SSIO0 and 1

In standard mo de, S C0 i s t he seri al cl ock pi n f or ch an ne l 0 and S C1 i s t he seri al cl ock

pin for channel 1. In duplex and channel-select modes, SC0 is the serial clock pin for

both channels 0 and 1 and S C1 is not available.

SC0 shares a package pin with P9.2, and SC1 shares a package pin with P9.4.

SD1:0 I/O

Dat a Pins for SSIO0 and 1

These pins are the data I/O pins for SSIO0 and 1. For transmissions, configure SD x

as a complementary output signal. For receptions, configure SDx as a

high-impedance input signal.

SD0 shares a package pin with P9.3, and SD1 shares a package pin with P9.5.

T1CLK I

T imer 1 External Clock

Ext ern al clo ck f or ti me r 1. T im er 1 is progr amma bl e t o in crem en t or de crem en t on the

rising edge, the falling edge, or both rising and falling edges of T1CLK.

T1CLK shares a package pin with P8.2, EPA10, and BLK2#.

T2CLK I

T imer 2 External Clock

Ext ern al clo ck f or ti me r 2. T im er 2 is progr amma bl e t o in crem en t or de crem en t on the

rising edge, the falling edge, or both rising and falling edges of T2CLK. and

External clock for the serial I/O baud-rate generato r input (program selec t able).

T2CLK shares a package pin with P8.4 and EPA12.

Table 3. Signal Descriptions (Sheet 7 of 9)

Name Type Description

Intel® 88CO196E C

18 Datasheet

T1RST I

Timer 1 External Reset

External reset for timer 1. Timer 1 is programmable to reset on the rising edge, the

falling edg e, or both rising and falling edges of T1RST.

T1RST shares a package pin with P8.3, EPA11, and BLK3#.

T2RST I

Timer 2 External Reset

External reset for timer 2. Timer 2 is programmable to reset on the rising edge, the

falling edg e, or both rising and falling edges of T2RST.

T2R ST sha res a packag e pin with P8.5 and EPA13.

TMODE1:0#

Test-Mode Entry

If these pins are held low during reset, the microcontroller will enter a test mode. The

v alue of s everal other pins defines the act ual test mode. All test modes, except

TR OM execution, are reserved for Intel fac tory u se. If you choose to configure these

signals as inputs, always hold them high during reset and ensure that your system

meets the VIH specification to prevent inadvertent entry into test mode.

TMO DE0# shares a p ackage pin with P5.4 and BREQ#; TMODE1# shares a

package pin with P5.5, BHE#, WRH#.

TXCAN O Transmit CAN Me ssage

This signal carries messages from the integrated CAN controller to other nodes on

the CAN bus.

TXD O

T ransmit Serial Data

In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode 0, it is

the serial clock output.

TXD sh ares a package pin wit h P2.0.

VCC PWR Digital Supply Voltage

Connec t each VCC pin to the digital supply voltage.

VCCPLL PWR Digital Sup ply Voltage for the Phase-locked Loop (PLL) Ci rcuit ry

Connect this pin to the digital supply voltage. VCCPLL and VCC should be nominally at

the same voltage.

VPP PWR Programming Voltage

During Flash Program/Erase, th e VPP pin is typically at +12 V (VPP voltage).

During normal operatio n the VPP pin is tied to VSS.

VREF PWR Ref e re nc e Voltag e for the A/ D Co nv er t er

This pin supplies operating voltage to the A/D converter.

VSS GND Digital Circuit Ground

These pins supply ground fo r the di gital circuitry. Connect each VSS pin to ground

through the lowest possible impedance path.

VSSPLL GND Digital Circuit Ground for the Phase-locked Loop (PLL) Circuitry

Connect this pin to ground through the lowest possible imp edance path . VSSPLL an d

VSS sho uld be nominally at the same potent ial.

WR# O

Write†

This active-low output indicates that an external write is occurring. This signal is

asserted only during external memory writes.

WR# shares a package pin with P5.2 and WRL#.

†When thi s pin is confi gured as a special-function sig nal (P5_MODE.2 = 1), the chip

configuration re gister 0 (CCR0) d etermines whe t her it functions as WR# or WRL#.

CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.

Table 3. Signal Descrip tions (Sheet 8 of 9)

Name Type Description

In tel® 88CO 196EC

Datasheet 19

WRH# O

Write High†

During 16-bit bus cycl es, this active-low output signal is asserted for high-byte writ es

and word writes to external memory. During 8-bit bus cycles, WRH# is asserted for all

write op era t io ns .

WRH# shares a package pin with P5.5 and BH E#.

†When this pin is configured as a special-function signal (P5_MODE.5 = 1), the chip

configuration register 0 (CCR0) determines whether it functions as BHE# or W RH#.

CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.

WRL# O

Write Low†

During 16-bit bus cycles, thi s active-low output signal is asserted for low-byte writes

and w ord wri tes to ext ern al memo ry. Duri ng 8- b it bu s cycl es , WRL # is asse r ted f or al l

write op era t io ns .

WRL# shares a package pin with P5.2 and WR#.

†When this pin is config ured as a special- function signal (P5_MODE.2 = 1), the chip

configuration register 0 (CCR0) determines wheth er it functions as WR# or WRL#.

CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.

XTAL1 I

Inpu t Crys tal/ Res o na tor or Ext ern al Clock Inp ut

Input to the on-chip oscillator and the internal clock generators. The internal clock

generators pr ovide the peripheral clocks, CPU clock, and CLKOUT signal. When

us ing an external cloc k source instead of the on-chi p oscillato r, connect the clock

input to XTAL1. The external clock signal must m eet the VIH specification for XTAL1.

XTAL2 O Inverted Output for the Crystal/Resonator

Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design uses

an external clock source instead of the on-chi p oscillator.

Table 3. Signal Descriptions (Sheet 9 of 9)

Name Type Description

Intel® 88CO196E C

20 Datasheet

In tel® 88CO 196EC

Datasheet 21

4.0 Address Map

Table 4. Intel® 88C O196EC CHM OS 16-Bit Microcon troller Addr ess Map (Sheet 1 of 2)

Hex

Address Description Addressing Modes

for Data Accesses

FFFFFF

FF2140 Internal flash program memory or external program memory (Not es 1 and 2) Extended

FF213F

FF20C0 Internal flash special-purpose memor y or ext ernal special-purpose me mory

(PIH vectors) (Notes 1 and 2)Extended

FF20BF

FF2080 Internal flash progra m memory or external program memory

(Notes 1 and 2). After reset, the first instruction is fetched from FF2080H. Extended

FF207F

FF2000 Internal flash special-purpose memory or external special-purpos e memor y

(CCBs, interrupt vectors, and PTS vectors) (Notes 1 and 2)Extended

FF1FFF

FC0000 Internal flash progra m memory or external pro gram memory (Notes 1 and 2) Extended

FBFFFF

FB0000 External memory or I/O (Note 1) Extended

FAFFFF

E10000 External memory or I/O Extended

E0FFFF

010000 Re served for future micr ocontrollers, do not access these l ocatio ns. (Not e 3)—

00FFFF

002000 External memory or I/O Indirect, in dexed,

extended

001FFF

001FE0 Memory-mapped special-function registers (SFRs) Indirect, in dexed,

extended

001FDF

001E00 Peripheral special-function registers (SFRs) Indirect, in dexed,

extended,

windowed direct

001DFF

001D00 CAN special-function registers (SFRs) Indirect, in dexed,

extended,

windowed direct

001CFF

001C00 Upper register file (general-purpose register RAM) In direct, indexed,

extended,

windowed direct

001BFF

000F00 External memory or I/O Indirect, in dexed,

extended

NOTES:

1. Du ring test ROM execution mode, the contents of pages FFH and FBH are swapped. This allows t he

microcontroller to enter a test ROM routine after reset.

2. Accesses to these locations go to internal flash if EA# i s high or an external device if EA# is low.

3. Since the upper three address bits, A23:21, are not connected to external pins, these address locations are

unique internally, but not externally. For example, addresses 200F20H, 400F20H, 600F20H appear

externally on address pins A20:0 as 000F20H.

4. The IR AM_CO N register determines whether accesses t o t hese locations go to internal code/data RAM or

ex ternal memory. Accesses to t hese locati ons go internal if IRAM_CON.6 = 0 an d exter nal if

IRAM_CON.6 = 1.

Intel® 88CO196E C

22 Datasheet

000EFF

000400 Internal code/data RAM or external memory (Note 4)Indirect, indexed,

extended

0003FF

000100 Uppe r regist er file (gener al-p urpose register RAM) Indirec t, indexed,

extended,

wi nd ow e d di r ec t

0000FF

000018 Lowe r regist er file (gener al-p urpose register RAM) Di rec t, in di rec t,

indexed, extended

000017

000000 Lower regi ster file (stack pointer and CPU SFRs) Di rec t, in di rec t,

indexed, extended

Table 4. Intel® 88CO196EC CHMOS 16-Bit Microcontroll er Address Map (Sheet 2 of 2)

Hex

Address Description Addressing Modes

for Data Accesses

NOTES:

1. During test ROM execution mode, the contents of pages FFH and FBH are swapped. This allows the

microcontr oller to ent er a test ROM routin e after re set.

2. Accesses to these locations go to internal flash if EA# is high or an external device if EA# is low .

3. Since the upper three address bits, A23:21, ar e not connected t o external pins, these address locati ons ar e

unique internally, but not externall y. For example, addr esses 200F20H, 400F20H , 600F20H appear

ex terna lly on addres s pins A20:0 as 000F20H.

4. The IRAM_C ON reg ister determ ines w hether access es to these lo cations go to internal code/data RAM or

external memory. Accesses to these locations go internal if IRAM_CON.6 = 0 and external if

IRAM_CON.6 = 1.

In tel® 88CO 196EC

Datasheet 23

5.0 Electrical Characteristics

5.1 DC Characteristics

ABSOLUTE MAXIMUM RATINGS†

Storage Temperature ....................................... –60°C to +150°C

VCC Suppl y Vo ltag e with Respec t to VSS .......... –0.5 V to +6.0 V

VPP (max im um) .. .... ....... .... .... .... .... ....... .... .... .... ....... .... .... ...13. 0 V

Power Dissipation............................................................... 1.5 W

OPERATING CONDITIO NS†

TC (Case Temperature Under Bias) (note 4) ................................

Exten de d Tempe rat ure .... ....... .. –40°C to +85°C

Comm erc ia l Te mp e ratu re ........ . 0°C to +70°C

VCC (Digital Supply Vo ltage) ............................. 4.75 V to 5.25 V

VPP (normal operation)..................................................tie to VSS

VPP (Flash program/erase)..................................11.4 V to 12.6 V

VREF (Analog Supply Voltage) .......................... 4.75 V to 5.25 V

FXTAL1 (Input frequency for VCC = 4. 75 V – 5.25 V)

(Notes 1, 2, 3).................................................. 16MHz to 40MHz

NOTICE: This datasheet contains

inf orm a t io n on produc ts be in g sa mp led

or i n the initial production phase of

development. The specifications are

subject to change without notice. Verify

with your local Intel sales office that you

have the lates t da tas he et befo r e

finalizing a design.

†WARNING: Stressing the device

beyond the “ Ab so lute M ax im um

Ratings” may cause permanent

damage. These are stress ratings only.

Operation be yond the “Operating

Conditions” is not recommend ed and

extended exposure beyond the

“Operating Conditions” may affect

device reliability.

NOTE:

1. This device is static and should operate below 1 Hz, but has been tested only down to 16 MHz.

2. When the phase-locked loop (P LL) circuitry is enabled, the minimum input frequency on XTAL1 is 6 MHz.

The PLL cannot be run a t frequencies lower than 24 MHz in 4X mode.

3. Assume an external clock. The maximum frequency for an external crystal oscillator is 20MHz.

4. Flash programming a nd erase operations only guarantee d to work from 0 °C to +70°C.

Table 5. DC Characteristics at VCC = 4.75 V – 5.25 V (Sheet 1 of 2)

Sym Parameter Min Typical

(Note 1) Max Units Test Conditions

ICC VCC supp ly current

40MHz 100 130 mA VCC = 5.25 V

Device in Reset

IIDLE Idle mode current

40MHz 60 85 mA VCC = 5. 25 V

IPD Powerdown mode

current 50 µA VCC = 5.25 V

NOTES:

1. Typical values are based on a limited number of samples and are not guaranteed. The valu es list ed are at

room t emper ature with VCC = 5.0 V.

2. For P2.7:0, P3.7:0, P4.7:0 , P5.7 :0, P6 .7:0, P7. 7:0, P8.7:0, P9.7:0, RESET#, NMI, CRIN, CRDCLK, ONCE#,

and XTAL1.

3. The maximum injection current is not tested. The device is designed to meet this specification.

4. Pin capacitance is not tested. This value is based on design simulations.

Intel® 88CO196E C

24 Datasheet

IREF A/D reference supply

current 6mA

XTAL1 = 4 0 MHz

VCC = V REF = 5.25 V

Device in Reset

IINJD

M aximum in jection

cur rent pe r por t on

bidirec tio nal pi ns

(Note 3)

–10 10 mA

ILI Input l eakage current

(S tandard inputs except

analog inputs) –10 10 µA VSS < VIN < VCC

ILI1 Input leakage current

(analog inp uts) –300 300 nA VSS + 100 mV < VIN < VREF – 10 0 mV

IIH Input high current

(NMI only) 175 µA NMI = VCC = 5.25 V

VIL1 Input low voltage

(Note 2)–0.5 0.3 VCC V

VIH1 Input high voltage

(Note 2)0.7 VCC VCC +

0.5 V

VOL1 Output low volt age

(output configured as

complementary)

0.3

0.45

1.5

IOL = 200 µA

IOL = 3.2 mA

IOL = 7 mA

VOH1 Output high voltage

(output configured as

complementary)

VCC – 0.3

VCC – 0.7

VCC – 1.5

IOH = –200 µA

IOH = –3.2 mA

IOH = –7 mA

IOH2

Output high current in

reset (on any pin

ex cept ONCE# and

TMODEx#)

–30

–65

–75

–140

–280

–350

µA

VOH2 = VCC – 1 V

VOH2 = VCC – 2.5 V

VOH2 = VCC – 4 V

VOL2 Output low voltage in

reset (on ALE) 0.5 V IOL = 15 µA

VHYS Hysteresis voltage on

RESET# 700 mV

CSPin Capacit ance (a ny

pin to VSS) (Note 4)10 pF Not tested

RRST Pull-u p resistor on

RESET# pin 995kΩVCC = 5.25 V

VIN = 4 V

Ipph VPP C urr e nt dur i ng

erase/write operation 40 mA

Table 5. DC Characteristics at VCC = 4.75 V – 5.25 V (She et 2 of 2)

Sym Parameter Min Typical

(No t e 1) Max Units Test Conditions

NOTES:

1. Typical values are based on a limited number o f samples and are not guaranteed. The v alues listed are at

room temperature with VCC = 5.0 V.

2. For P2.7:0, P3.7:0, P4.7:0, P5.7:0, P6.7:0, P7.7:0, P8.7:0, P9.7:0, RESET#, NMI, CRIN, CRDCLK, ONCE#,

and XTAL1.

3. The maximum injection current is not tested. The device is designed to meet this specification.

4. Pin c apacitance i s not tested. This value is ba sed on design simulat ions.

In tel® 88CO 196EC

Datasheet 25

6.0 Explanation of AC Symbols

Table 6 . AC Timi ng S y m bo l De f i ni tio ns

Character Signal(s)

A AD1 5:0, A20:0

BR BREQ#

CCLKOUT

D AD15:0, AD7:0, RXD (SIO mode 0 input data), SDx (SSIO input data)

H CRBUSY#

LALE/ADV#

Q AD15:0, AD7:0, RXD (SIO mode 0 output data), SDx (SSIO output data)

R RD#

SCSx#

W WR#, WRH#, WRL#

X XTAL1, TXD (SIO clock), SCx (SSIO standard mode clock)

YREADY

Character Condition

HHigh

LLow

V Valid

X No Longer Va lid

Z Floating (low impedance)

Intel® 88CO196E C

26 Datasheet

6.1 AC Characteristics — Multiplexed Bus Mode

Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.

Table 7. AC Characteristics, M ult iplexed Bu s Mode (Sheet 1 of 2)

Symbol Parameter Min Max Units

FXTAL1 Frequency o n XTAL1, PLL in 1x mode (d isabled) 16 40 MHz (1, 2)

Frequency on XTAL1, PLL in 4x mode 6 10 MHz

f Operating frequency, f = FXTAL1; PLL in 1x mode (disabled) 16 40 MHz

Operating frequency, f = 4FXTAL1; PLL in 4x mode 24 40 MHz

t Period, t = 1/f; 25 62.5 ns

TAVDV Address Valid to Input Data Valid 3t – 40 ns (3)

TRLDV RD# Low to Input Data Valid t – 30 ns (3)

TCHDV CLKOUT High to Input Data valid 2t – 35 ns (4)

TRHDZ RD# High to Input Data Float t + 3 n s

TRXDX Data Hold after RD# Inactive 0 ns

TXHCH XTAL1 Rising Edge to CLKOUT High or Low 3 50 ns (4)

TCLCL CLKOU T Cycle Time 2t ns (4)

TCHCL CLKOUT High Period t – 10 t + 15 ns (4)

TCLLH CLKOUT Low to ALE High – 10 10 ns (4)

TLLCH ALE Low to CLKOUT High – 15 15 ns (4)

TLHLH ALE Cycle Time 4t n s (3)

TLHLL ALE High Period t – 10 t + 10 ns

TAVLL Address Setup to ALE Low t – 15 ns

TLLAX Add ress Hold af ter ALE L ow t – 10 ns

TLLRL ALE Low to RD# Low t – 15 ns

TRLCL RD# Low to CLKOUT Low – 10 20 ns (4)

TRLRH RD# Low to RD# High t – 10 ns (3)

TRHLH RD# High to ALE High t – 5 t + 15 ns (5)

TRLAZ RD# Low to Address Fl oat 5 ns

TLLWL ALE Low to WR# Low t – 12 ns

TQVWH Output Data Stable to WR# High t – 14 ns (3)

TCHWH CLKOUT High to WR# High – 15 6.5 ns (4)

NOTES:

1. 20MHz is the m aximum input fr equency when using an external crysta l oscillator; however, 40MHz can be

applied with an external clock source.

2. Device is static by design, but has been tested only down to 16MHz.

3. If wait stat es are us ed, add 2t × n, where n = n um b er of wait state s .

4. Assumes CLKOUT is operating in divide-by-two mode (f/2).

5. Assuming back-t o-back bus cycles.

6. 8-bit bus only.

7. When forcing wait states using t he BUSCO Nx register, add 2t × n, where n = number of wait states.

8. Exceeding t he maximum specification causes addition al wait states.

9. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, o ne programmed wait

state is required.

In tel® 88CO 196EC

Datasheet 27

TWLWH WR# Low to WR# High t – 10 n s (3)

TWHQX Output Data Hold after WR# High 40 MHz = t-13 t – 13 ns

TWHLH WR# High to ALE High t – 15 t + 20 ns

TWHBX BHE#, INST Hold after WR# High t – 4ns

TWHAX AD15:8, CSx# Hold after WR# High 40 MHz = t-9 t – 9ns (6)

TRHBX BHE#, INST Hold after RD# High t – 5ns (6)

TRHAX AD15:8, CS x# Hold after RD# High t – 5ns (6)

TWHSH A20:0, CSx# Hold after WR# High – 0.5 ns

TRHSH A20 :0, CSx# Hold after RD# High 0 ns

TAVYV AD15 :0 Va li d to READY Setup 2t – 55 ns (7)

TCLYX READY Hold after CLKOUT Low 0 2t – 45 ns (4,8,9)

TYLYH READY Lo w to READY High No Upper Limit ns

Ta ble 7. AC Characteristics, Multiplexed Bus Mode (Sheet 2 of 2)

Symbol Parameter Min Max Units

NOTES:

1. 20MHz is the maximum input frequency when using an external crystal oscillator; however, 40MHz can be

applied with an external clock source.

2. Device is static by design, but has been tested only down to 16MHz.

3. If wait states a re used, add 2t × n, where n = number of wait states.

4. Assumes CLKOUT is operating in divide-by-two mode (f/2).

5. Assuming back-to-back bus cycles.

6. 8- b it bu s only.

7. When forcing wait states using the BUSCONx register, add 2t × n, where n = number of wait states.

8. Exceeding the maximum specification causes additional wait states.

9. The first fal ling edge of RE ADY is not synchronized to a CLKOUT e dge; therefore, one programme d wait

sta te is require d.

Intel® 88CO196E C

28 Datasheet

Figure 4. System Bus Timing Diagram (Multiplexed Bus Mode)

CLKOUT

ALE

RD#

A3252-01

AD15:0

(read)

WR#

AD15:0

(write)

BHE#, INST

AD15:8

A20:16

LHLH

Address Out

Extended Address Out

CLLH

CLCL

CHDV

RLCL

CHCL

LLCH

LLRL

RHLH

RLRH

RLDV

RHDZ

Data In

RLAZ

LLAX

Address Out

AVDV

AVLL

CHWH

WHLH

LLWL

WLWH

WHQX

Data OutAddress Out

WLWH

QVWH

WHBX

, T

RHBX

High Address Out

WHSH

, T

RHSH

CSx#

WHAX

, T

RHAX

LHLL

In tel® 88CO 196EC

Datasheet 29

Figure 5. READY Ti ming Diagram (Mu ltiplexed Bus Mode)

CLKOUT

READY

ALE

A3249-01

TCLYX (min)

TLHLH + 2t

TAVDV + 2t

RD#

AD15:0

(read)

AD15:0

(write)

BHE#, INST

A20:16

CSx#

TRLRH + 2t

TAVYV

Data Out

Extended Address Out

Address Out

TCLYX (max)

Data InAddress Out

TRLDV + 2t

TWLWH + 2t

TQVWH + 2t

WR#

Intel® 88CO196E C

30 Datasheet

6.2 AC Characteristics — Demultiplexed Bus Mode

Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.

Table 8. AC Characteristics, Dem ultiplexed Bus Mode (Sheet 1 of 2)

Symbol Parameter Min Max Units

FXTAL1 Frequency o n XTAL1, PLL in 1 x mode (d isabled) 16 40 MHz

(1,2)

Frequency on XTAL1, PLL in 4x mode 6 10 MHz

f Operating frequency, f = FXTAL1; PL L in 1x mode (disabled) 16 40 MH z

Operating frequency, f = 2FXTAL1; PLL in 4x mode 24 40 MHz

t P eriod, t = 1/f 25 62.5 ns

TAVDV Address Valid to Input Data Valid 4t –40 ns (3)

TRLDV RD# Low to Input Data Valid 3t – 35 ns (3)

TAVWL Address Valid to WR# Low t ns

TAVRL Address Valid to RD # Low t – 8ns

TSLDV CSx# Low to Data Valid 4t – 40 ns (3)

TCHDV CLKOUT High to Input Data Valid 2t – 35 ns (4)

TRHRL Read High to Rea d Low t – 5ns

TRXDX Data Hold after RD# Inactive 0 ns

TXHCH XTAL1 High to CLKOUT High or Low 3 50 ns (4)

TCLCL CLKOUT Cycl e Time 2t ns (4)

TCHCL CLKOUT High Period t – 10 t + 15 ns ( 4)

TCLLH CLKOUT High ALE Low – 10 10 ns (4)

TLLCH ALE High to CLKOUT Low – 15 15 ns (4)

TLHLH ALE Cycle Time 4t ns (3,5)

TLHLL ALE High Period t – 10 t + 10 ns

TRLCL RD# Low to CLKOUT Low – 15 5 ns (4)

TRLRH RD# Low to RD# High 3t – 18 ns (3)

TRHLH RD# High to ALE Low t – 4t + 15ns (5)

TWLCL WR# Low to CLKOUT Low – 15 5 ns (4)

TQVWH Output Data Stable to WR# High 3t – 25 ns (5)

TCHWH CLKOUT High to WR# High – 11 10 ns (4)

1. Device is st atic by design but has been tes ted only down to 16MHz.

2. 20MHz is the m aximum input fr equency when using an external crysta l oscillator; however, 40MHz can be

applied with an external clock source.

3. If wait stat es are us ed, add 2t × n, where n = n um b er of wait state s .

4. Assumes CLKOUT is operating in divide-by-two mode (f/2).

5. Assuming back-t o-back bus cycles.

6. When forcing wait states using t he BUSCO N register, add 2t × n.

7. Exceeding t he maximum specification causes addition al wait states.

8. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, o ne programmed wait

state is required.

9. 8-bit bus only.

In tel® 88CO 196EC

Datasheet 31

TWLWH WR# Low to WR# High 3t – 18 ns (3)

TWHQX Output Data Hold after WR# High t – 2t + 20 ns

TWHLH WR# High to ALE High t – 5 t + 10 ns (3)

TWHBX BHE#, INST Hold after WR# High t – 5ns

TWHAX A20:0, CSx# Hold after WR# High 0 ns

TRHBX BHE#, INST Hold after RD# High t – 5ns

TRHAX A20 :0, CSx# Hold after RD# High 0 ns

TAVYV A20:0 Va lid to READY Setup 3t – 45 ns (6)

TCLYX READY Hold after CLKOUT Low 0 2t – 36 ns ( 7,8,9)

TYLYH READY Lo w to READY High No Upper Limit ns

Ta ble 8. AC Characteri stics, Demultiplexed Bus Mode (Sheet 2 of 2)

Symbol Parameter Min Max Units

1. Device is static by design but has been tested only down t o 16MHz.

2. 20MHz is the maximum input frequency when using an external crystal oscillator; however, 40MHz can be

applied with an external clock source.

3. If wait states a re used, add 2t × n, where n = number of wait states.

4. Assumes CLKOUT is operating in divide-by-two mode (f/2).

5. Assuming back-to-back bus cycles.

6. When forcing wait states using the BUSCON register, add 2t × n.

7. Exceeding the maximum specification causes additional wait states.

8. The first fal ling edge of RE ADY is not synchronized to a CLKOUT e dge; therefore, one programme d wait

sta te is require d.

9. 8- b it bu s only.

Intel® 88CO196E C

32 Datasheet

Figure 6. System Bus T iming Diagram (Demul tiplexed Bus Mode)

A8733-01

CLKOUT

ALE

RD#

AD15:0

(read)

WR#

AD15:0

(write)

BHE#, INST

A20:0

Address Out

CHCL

CLCL

LLCH

CHWH

LHLH

WHLH

RHRL

Data In

RLRH

AVDV

WHQX

WHAX

WLCL

Data Out

WLWH

QVWH

WHBX

, T

RHBX

CSx#

LHLL

CLLH

RHLH

AVRL

RHAX

SLDV

CHDV

RLDV

AVWL

In tel® 88CO 196EC

Datasheet 33

Figure 7. READY Timing Diagram (Demultiplexed Bus Mode)

CLKOUT

READY

ALE

A3259-02

TLHLH + 2t

TAVDV + 2t

RD#

AD15:0

(read)

AD15:0

(write)

BHE#, INST

A20:0

CSx#

TRLRH + 2t

TAVYV

Data Out

Address Out

Data In

TRLDV + 2t

TWLWH + 2t

TQVWH + 2t

WR#

TCLYX (max)

TCLYX (min)

Intel® 88CO196E C

34 Datasheet

6.3 Deferred Bus Timing Mode

The deferred bus cycle mode (enabled by setting CCR1.5) reduces bus contention when using the

Intel® 88CO196EC in demultiplexed mode with slow memories. As shown in Figure 8, a delay of 2t

occurs in the f irst bus cycle following a chip-select output change or the first write cycle f ollowing a

read cycle.

Figu re 8. Def erred Bus Mode Timing Diag ram

CLKOUT

ALE

RD#

A3246-02

TWHLH + 2t

TRHLH + 2t TAVRL + 2t

TAVWL + 2t

AD15:0

(read)

WR#

AD15:0

(write)

BHE#, INST

A20:0

CSx#

TAVDV+ 2t

TLHLH + 2t

Data InData In

Data Out

Valid Valid

Data Out

Address Out

Data Out

In tel® 88CO 196EC

Datasheet 35

6.4 AC Char acter istics — Ser ial Port, Mod e 0

Table 9. Seri a l Port Tim i ng — Mode 0†

Symbol Parameter Min Max Units

TXLXL

S erial Port Clock pe rio d

SP_BAUD ≥ x002H

SP_BAUD = x001H†† 6t

4t ns

TXLXH

Serial Port Clock falling edge to rising edge

SP_BAUD ≥ x002H

SP_BAUD = x001H†† 4t – 27

2t – 27 4t + 2 7

2t + 27 ns

TQVXH Output data setup to clock high 4t – 30 ns

TXHQX Output data hold after clock high 2t – 30 ns

TXHQV Next output data valid after clock high 2t + 30 ns

TDVXH Input data setup to cl ock high 2t + 3 0 ns

TXHDX Input dat a hold after clock hi gh 0 ns

TXHQZ Last clock high to output float t + 30 ns

†These ti mings ar e not tested and not gua ranteed.

†† The minimum baud-rate (SP_BAUD) register value for receptions is x002H and the minimum baud-rate

(S P_BAUD ) register val ue for tr ansmissions i s x001H.

Figure 9. S eri al Port Waveform — Mod e

A5013-01

Valid Valid Valid Valid Valid Valid Valid Valid

RXD

TXD

01 2 34567

TQVXH

TXLXL

TDVXH

TXHQV TXHQZ

TXHDX

TXHQX

TXLXH

RXD

Intel® 88CO196E C

36 Datasheet

6.5 AC Characteristics — Synchronous Serial Port

Tabl e 10. Synchronous Serial Port Timing

Symbol Parameter Min Max Units

TCLCL Synchronous Serial Port Clock period 4t ns

TCLCH Synchronous Serial Port Clock falling edge to rising edge 2t – 10 ns

TD1DV Setup time for MSB output†tns

TCLDX Output data change after clock low 0.5t 1.5t + 20 ns

TDVCX Setup time for input data 10 ns

TDXCX Input data hold after clock high t + 5 ns

†Refer to the “Programming Consideration s” section of ch apter 9, “Synchro n ou s S eri al I/O Port” in the Intel®

88CO196EC CHMOS 16-Bit Microcontroller 196EC User’s Manual.

Figure 10. Synchronous Serial Port

MSB D6 D5 D4 D3 D2 D1 D0

valid valid valid valid valid valid valid valid

1 8765432

SCx

(normal

transfers)

SDx (out)

SDx (in)

SCx

(handshaking

transfers) Slave Receiver Pulls SCx low

A3233-02

TCHCH

TCHCL

TCLCH

STE Bit

TD1DV

TCXDX TCXDV

TDVCX TDXCX

Assumes that the SSIO is configured to sample incoming data on the rising clock edge and sample outgoing

data on the falling clock edge, and that the SSIO is configured to pull the clock signal low while the channel

is idle.

†

In tel® 88CO 196EC

Datasheet 37

6.6 AC Char acter istics — Serial Debug Unit

Table 11. Serial Debug Unit Timing

Symbol Parameter Min Max Units

TCLCL Code RAM clock cycle time 2t ns

TCHCL Code RAM clock high period t ns

TDVCH Input dat a setup to clock high 10 ns

TCHDX Input data hold after clock high t + 10 ns

TQVCH Output data setup to clock high t – 10 ns

TCHQX Output data hold after clock high t – 10 ns

TCHQV Next output data valid after clock high t + 10 ns

TCHHL Las t clock high to CRB USY# low 3t + 20 n s

Figure 11. Serial Debug Unit

TCHHL

CRDCLK

CRIN

CROUT

CRBUSY#

A5335-01

TCLCL

validvalid

valid

TCHCL

TDVCH TCHDX

TCHQX

TCHQV

TQVCH

Intel® 88CO196E C

38 Datasheet

6.7 A/D Sample and Conversion Times

Two paramete rs, sample time and conversion tim e, control the time requi red for an A/D

conversion. Th e sam ple t ime is the l ength of time that the analog input volt age is a ctually

connec ted to the sample capacitor. If this time is too short, the sample capacitor will not charge

com pletely. If the sample time is too long, the input voltage may change and ca use conversion

errors . The conv ersi on time is the lengt h of ti me require d to conver t the ana log input volt age store d

on the s ample capacitor to a digital va lue. The conversion time must be long enou gh for the

com parator and circuitry to settle and resolve the volt age. Exces si vely lon g conversion times a llow

the sample capacitor to discharge, degrading accuracy.

The AD _ TIME reg i ster programs the A/D sample an d convers ion times. Use t h e TSAM and TCONV

specific ations in Table 12 and Table 14 to de termine appropriate values for SAM and CONV;

otherwise, erroneous conversion results may occur .

When the SAM and CONV values are known, write them to the AD_ TIME register. Do not write

to this register whil e a co nversion is in progress; the res ults are unpredictable.

Use the following formulas to determine the SAM and CONV value s.

where:

SAM equals a number, 1 to 7, to be written to the AD_TIME register

CONV equals a number, 2 to 31, to be written to the AD_TIME register

TSAM is the sample time, in µsec (Table 12 and Tabl e 14)

TCONV is the conversion time, in µsec (Table 12 and Ta ble 14)

f is the operating frequency, in MHz

B is the number of bits to be converted (8 or 10)

SAM TSAM f2–×

-------------------------------=

CONV TCONV f×3–

2B×

---------------------------------- 1–=

In tel® 88CO 196EC

Datasheet 39

6.7.1 AC Characteristics — A/D Converter, 10-Bit Mode

Ta ble 12. 10-bit A/D Op erati ng Conditions

Symbol Description Min Max Units Notes

TCCase Temperature – 40 + 125 °C

VCC Di gi tal S up pl y Vo ltag e 4.75 5. 25 V

VREF Analog Supply Voltage 4.75 5.25 V 2

TSAM Samp le Time 1.0 µs3

TCONV Conversion Time 10.0 15.0 µs3

NOTES:

1. ANGND and VSS should nominally be at the same potential.

2. VREF must not exceed VCC by more than + 0.5 V because VREF supplies both t he resistor ladder and the

analog portion of the converter and input port pins.

3. Program the AD_TIME register to meet the TSAM and TCONV specificat ions.

Ta ble 13. 10-Bit M od e A/D Characteristics Over Specified Operating Conditions

Parameter Typical (2) Min Max Units (3) Notes

Resolution 1024

10 1024

10 Levels

Bits

Absolute Error 0 ± 3.0 LSBs

Full- s c ale Er ror 0.25 ± 0.5 LSBs

Zero Offset Error 0.25 ± 0.5 LSBs

Nonlinearity 1.0 ± 2.0 ± 3.0 LSBs

Differential Nonlinearity – 0.75 + 0.75 LSBs

Channel-to-channel Matching ± 0.1 0 ± 1.0 LSBs

Repeatability ± 0.25 0 LSBs

Temperature Coeffici ents:

Offset

Full-scale

Differential Nonlinearity

0.009

LSB/°C

Off-isolation – 60 dB 2, 4, 5

Feedthrough – 60 dB 2, 4

VCC Power Supply Rejection – 60 dB 2, 4

Inpu t Series Resistance 750 1.2k W 6

Voltage on Analog Input Pin ANGND VREF V 7

Sam p lin g C apa c ito r 3.0 pF

DC Input Leakage ± 100 0 ± 300 nA 8

NOTES:

1. All conversions were performed with processor in idle mode.

2. Most devices will need these values at 25°C, b ut they are not tested or guaranteed.

3. An LSB, as used here, has a value of approximately 5 mV.

4. DC to 100 KHz.

5. Multiplexer break-before-make guaranteed.

6. Resistance from device pin, through internal multiplexer, to sample capacitor .

7. Applying voltage beyond these specifications will degrade the accuracy of other channels being converted.

8. 100 mV < VIN < VREF – 100 mV.

Intel® 88CO196E C

40 Datasheet

6.7.2 AC Char acteristics — A/ D Co n verter, 8 -B i t Mo de

Table 14. 8-Bit A/D Op erati ng Conditions

Symbol Description Min Max Units Notes

TCCase Temperature – 40 + 125 °C

vCC Digital Supply Volt age 4.75 5.25 V

vREF An alog Su pp ly Vo ltag e 4. 75 5.25 V 2

TSAM Sample Time 1.0 µs3

TCONV Conversion Time 8.0 12.8 µs3

NOTES:

1. A NG N D an d V SS should nominally be at the same potential.

2. VREF must not exceed VCC by more than + 0.5 V because VREF supplies bot h the resistor ladde r and the

analog portion of th e converter and inpu t port pins.

3. P ro gram the A D_TIM E re gi s ter to me e t th e TSAM and TCONV specifications.

Table 15. 8-Bit Mode A/D Charac teristics Ove r Specified Operating Conditions

Parameter Typical (2) Min Max Units (3) Notes

Resolution 256

8256

8Levels

Bits

Absolute Error 0 ± 1.0 LSBs

Full-scale Error ± 0.5 LSBs

Zero Offset Error ± 0.5 LSBs

Nonlinearity 0 ± 1.0 LS B s

Differential Non linearity – 0.5 + 0.5 LSBs

Channel-to-channel Matching 0 ± 1.0 LSBs

Repeatability ± 0.25 0 LSBs

Temperature Coefficients:

Offset

Full-scale

Differential Non linearity

0.003

LSB/°C

Off Isolation – 60 dB 2, 4, 5

Feedthrough – 60 dB 2, 4

VCC Power Supply Rejection – 60 dB 2, 4

Input Series Resistance 750 1.2K Ω6

Voltage on Analog Input Pin A NGND VREF V7

Sampling Capacitor 3.0 pF

DC Input Leakage 100 0 300 nA 8

NOTES:

1. All conv ersi ons were perfor med with proc essor in idle mode.

2. Most part s will need these val ues at 25°C, but they are not tested or guaranteed.

3. An LSB, as used here, has a value of appr oximately 5 mV.

4. DC to 100 KHz.

5. Multipl exer break-before-make guaranteed.

6. Resistance from device pin, through internal multiplexer, to sample capacitor .

7. Applying voltage beyond these specifications will degrade the accuracy of other channels being converted.

8. 100 mV < VIN < VREF – 100 mV.

In tel® 88CO 196EC

Datasheet 41

6.8 External Clock Drive

Ta ble 16. External Clock Drive

Symbol Parameter Min Max Units

FXTAL1 Frequency on XTAL1 (1/TXLXL), PLL in 1x mode (disab led) 16 40†MHz

Frequency on XTAL1 (1/TXLXL), PLL in 4x mode 6 10 MHz

TXTAL1 Oscillator Period (TXLXL)2562.5ns

TXHXX High Time 0.35TXTAL1 0.65TXTAL1 ns

TXLXX Low Time 0.35TXTAL1 0.65TXTAL1 ns

TXLXH Rise Tim e 10 ns

TXHXL Fall Time 1 0 ns

†20 MHz is the maximu m input frequency whe n using an exte rnal crystal osci llator; howev er, 40 MH z can be

applied with an external clock source.

Figure 12. Extern al Clock Drive Waveforms

TXLXX

A2119-03

TXHXX TXHXL

TXLXL

0.3 VCC – 0.5 V

0.7 VCC

+ 0.5 V

TXLXH

0.7 VCC + 0.5 V

0.3 VCC – 0.5 V

XTAL1

Intel® 88CO196E C

42 Datasheet

6.9 Test Output Waveforms

6.10 F lash Memory E rase Performance

Figure 13. AC Testing Outpu t Waveforms

Figure 14. Float Wa veforms During 5.0 Volt Testing

Tab le 17. Flash Memory Erase Perform anc e

Parameter Note Min Typical

(see note) Max Unit

Flash era s e t ime 2 10 Sec.

NOTE: Typi cal values are based on limi ted number of samples and are not guar anteed. The values listed

ar e at r oo m temp eratu r e w ith VCC = 5 V; VPP= 12 V.

Test Points 2.0 V

0.8 V

Note:

AC testing inputs are driven at 3.5 V for a logic “1” and 0.45 V for a logic

“0”. Timing measurements are made at 2.0 V for a logic “1” and 0.8 V for

a logic “0”.

3.5 V

0.45 V

A2120-04

2.0 V

0.8 V

VLOAD

VLOAD – 0.15 V

VLOAD + 0.15 V Timing Reference

Points

VOH – 0.15 V

VOL + 0.15 V

Note:

For timing purposes, a port pin is no longer floating when a 150 mV change from load

voltage occurs and begins to float when a 150 mV change from the loading V

level occurs with I

≤15 mA.

A2121-03

In tel® 88CO 196EC

Datasheet 43

7.0 Thermal Characteristics

All thermal impedance da ta is ap proximate for static air con ditions at 1 watt of power dissipation.

Values will change depending on operating conditions and the applic ation. The Inte l Packaging

Handbook (order number 240800) describe s Intel’s thermal impedance test methodology. The

Components Quality and Re liability Handbook (order num ber 210997) provides quality and

reliability information.

Table 18. Thermal Characteristics

Packag e Type θJA θJC

132-pin PQ FP wi th he at spr ea der 29.5 °C/W 9 °C/W