CS5509-AP - Cirrus Logic, Inc.



Cirrus Logic, Inc. 1997

(All Rights Rese rved)

Cirrus Logic, Inc.

Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.crystal.com

CS5509

Single Supply, 16-Bit A/D Converter

Features

Delta-Sigma A/D Converter

-16-bit No Missing Codes

-Linearity Error: ±0.0015%FS

Differential Input

-Pin Selectable Unipolar/Bipolar Ranges

-Common Mode Rejection

105 dB @ dc

120 dB @ 50, 60 Hz

Either 5 V or 3.3 V Digital Interface

On-chip Self-Calibration Circuitry

Output Update Rates up to 200/second

Ultra Low Power: 1.7 mW

Description

The CS5509 is a single supply, 16-bit, serial-output

CMOS A/D converter. The CS5509 uses charge-bal-

anced (delta-sigma) techniques to provide a low cost,

high resolution measurement at output word rates up to

200 samples per second.

The on-chip digital filter offers superior line rejection at

50 Hz and 60 Hz when the device is operated from a

32.768 kHz clock (output word rate = 20 Hz. ).

The CS5509 has on-chip self-calibration circuitry which

can be initiated at any time or temperature to ensure

minimum offset and full-scale errors.

Low power, high resolution and small package size

make the CS5509 an ideal solution for loop-powered

transmitters, panel meters, weigh scales and battery

powe red instruments.

ORDERING INFORMATION

CS5509-AP -40° to +85° C 16-pi n Plast ic DIP

CS5509-AS -40° to +85° C 16-pin SOIC

AIN-

VREF+ VREF- DGND VD+

SCLK

SDATA

DRDY

CAL

BP/UP

CONV XIN

AIN+ 7

910 12

XOUT

VA+

4th-Order

Delta-Sigma

Modulator

Digital

Filter

Calibration µC

Serial

Interface

Logic

OSC

Calibr at io n SRAM

Differential

MAR ‘95

DS125F1

Specific ations are subject to change without notice.

* Refer to the Specification Definitions immediately following the Pin Description Section.

ANALOG CHARACTERISTICS (TA = 25°C; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%; VREF+ = 2.5V,

VREF- = 0V; fCLK = 330kHz; Bipolar Mode; Rsource = 50Ω with a 10nF to GND at AIN; AIN- = 2.5V; unless

otherwise speci fied.) (Notes 1, 2)

Parameter* Min Typ Max Units

Accuracy

Linearity Error fCLK = 32.768 kHz

fCLK = 165 kHz

fCLK = 247.5 kHz

fCLK = 330 kHz

0.0015

0.005

0.003

0.0125

±%FS

Differential Nonlinearity - ±0.25 ±0.5 LSB

Full Scale E rror (Note 3) - ±0.25 ±2LSB

Full Scale Dr ift (Note 4) - ±0.5 -LSB

Unipolar Offset (Note 3) - ±0.5 ±2LSB

Unipolar Offset Drift (Note 4) - ±0.5 -LSB

Bipolar Offset (Note 3) - ±0.25 ±1LSB

Bipolar Offs et Drift (Note 4) - ±0.25 -LSB

Noise (R eferred to Output) - 0.16 - LSBrms

Ana log Inpu t

Analog Input Range: Unipolar

Bipolar (Note 5, 6) -

-0 to +2.5

±2.5 -

-Volts

Volts

Common Mode Rejection: dc

fCLK = 32.768kHz 50,60 Hz (Note 2) -

120 105

-dB

Input Capacitance - 15 - pF

DC Bias Current (Note 1) - 5 - nA

Power Supplies

DC Power S upply Currents: ITotal

IAnalog

IDigital

360

300

450

µA

Power Dissi pation (Note 7) - 1.7 2.25 mW

Power Supply Rejection - 80 - dB

Notes: 1. Both source resistance and shunt capacitance are critical in determining the CS5509’s source

impedance requirements. Refer to the text section

Analog Input Impedance Considerations.

2. Specifications guaranteed by design, characterization and/or test.

3. Applies after c alibration at the temperature of i nterest.

4. Total drift over the specified temperature range since calibration at power-up at 25 °C.

5. The input is differential. Therefore, GND ≤ Signal + Common Mode Voltage ≤ VA+.

6. The CS5509 can accept input voltages up to the VA+ analog supply. In unipolar mode the CS5509

will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will

output all 0’s if the input becomes more negative than 0 Volts. In bipolar mode the CS5509 will

output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will output all

0’s if the input becomes more negative in magnitude than -((VREF+)-(VREF-)).

7. All outputs unloaded. All inputs CMOS levels.

CS5509

2DS125F1

DYNAMIC CHARACTERISTICS

Parameter Symbol Ratio Units

Modulator Sampling Frequency fsfclk/2 Hz

Output Update Rate (C ONV = 1) fout fclk/1622 Hz

Filter Corner Frequency f-3dB fclk/1928 Hz

Settling Time to 1/2 LSB (FS St ep) ts1/fout s

5V DIGITAL CHARACTERISTICS (TA = 25°C; VA+, VD+ = 5V ± 10%; GND = 0.)

(Notes 2, 8)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage: XIN

All Pins Except XIN VIH

VIH 3.5

2.0 -

-V

Low-Level Input Voltage: XIN

All Pins Except XIN VIL

VIL -

-1.5

0.8 V

High-Level Output V oltage (Note 9) VOH (VD+)-1.0 - - V

Low-Level Output Voltage Iout = 1.6mA VOL --0.4V

Input Leakage Current Iin -±1±10 µA

3-State Leakage Current IOZ --

±10 µA

Digital Output Pin Capacitance Cout -9-pF

Notes: 8. All measurements are performed under static conditions.

9. Iout = -100 µA. This guarantees the ability to driv e one TTL load. (VOH = 2.4V @ Iout = -40 µA).

3.3V DIGITAL CHARACTERISTICS (TA = 25°C; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%; GND =

0.) (N otes 2, 8)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage: XIN

All Pins Except XIN VIH

VIH 0.7VD+

0.6VD+ -

-V

Low-Level Input Voltage: XIN

All Pins Except XIN VIL

VIL -

-0.3VD+

0.16VD+ V

High-Level Output V oltage Iout = -400µAVOH (VD+)-0.3 - - V

Low-Level Output Voltage Iout = 400µAVOL --0.3V

Input Leakage Current Iin -±1±10 µA

3-State Leakage Current IOZ --

±10 µA

Digital Output Pin Capacitance Cout -9-pF

CS5509

DS125F1 3

5V SWITCHING CHARACTERISTICS (TA = 25°C; VA+, VD+ = 5V ± 10%; Input Level s:

Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)

Parameter Symbol Min Typ Max Units

Master Clock Frequency Internal Os cillator:

External Clock: XIN

fclk 30.0

30 32.768

-53.0

330 kHz

kHz

Master Clock Duty Cycle 40 - 60 %

Rise Times: Any Digital Input (Note 10)

Any Digital Output trise -

50 1.0

-µs

Fall Times: Any Digital Input (Note 10)

Any Digital Output tfall -

20 1.0

-µs

Start-Up

Power-On Reset Peri od (Note 11) tres -10-ms

Oscillator Start-up Time XTAL=32.768 kHz (Note 12) tosu - 500 - ms

Wake-up Period (Note 13) twup - 1800/fclk -s

Calibration

CONV Puls e Width (CAL=1) (Note 14) tccw 100 - - ns

CONV and CAL High to Start of Calibration tscl --2/f

clk+200 ns

Start of Calibration to End of Calibration tcal - 3246/fclk -s

Conversion

CONV Pulse Width tcpw 100 - - ns

CONV High to Start of Conversion tscn --2/f

clk+200 ns

Set Up Time BP/UP stable prior to DRDY

falling tbus 82/fclk --s

Hold Time BP/UP stable after DRDY falls tbuh 0--ns

Start of Conversion to End of Conversion (Note 15) tcon - 1624/fclk -s

Notes: 10. Specified using 10% and 90% points on wav eform of interest.

11. An internal power-on-reset is activated whenever power is applied to the device.

12. Oscillator start-up time varies with the crystal parameters. This specification does not apply when

using an external clock source.

13. The wake-up period begins once the oscillator starts; or when using an external fclk, after the

power-on reset time elapses.

14. Calibration can al so be initiated by pul sing CAL high while CONV=1.

15. Conversion time wi ll be 1622/fclk if CONV remains hi gh continuously.

CS5509

4DS125F1

3.3V SWITCHING CHARACTERISTICS (TA = 25°C; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%;

Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)

Parameter Symbol Min Typ Max Units

Master Clock Frequency Internal Os cillator:

External Clock: XIN

fclk 30.0

30 32.768

-53.0

330 kHz

kHz

Master Clock Duty Cycle 40 - 60 %

Rise Times: Any Digital Input (Note 10)

Any Digital Output trise -

50 1.0

-µs

Fall Times: Any Digital Input (Note 10)

Any Digital Output tfall -

20 1.0

-µs

Start-Up

Power-On Reset Peri od (Note 11) tres -10-ms

Oscillator Start-up Time XTAL=32.768 kHz (Note 12) tosu - 500 - ms

Wake-up Period (Note 13) twup - 1800/fclk -s

Calibration

CONV Puls e Width (CAL=1) (Note 14) tccw 100 - - ns

CONV and CAL High to Start of Calibration tscl --2/f

clk+200 ns

Start of Calibration to End of Calibration tcal - 3246/fclk -s

Conversion

CONV Pulse Width tcpw 100 - - ns

CONV High to Start of Conversion tscn --2/f

clk+200 ns

Set Up Time BP/UP stable prior to DRDY

falling tbus 82/fclk --s

Hold Time BP/UP stable after DRDY falls tbuh 0--ns

Start of Conversion to End of Conversion (Note 15) tcon - 1624/fclk -s

CS5509

DS125F1 5

ccw

XIN

Calibration StandbyStandby t

scl

cal

XIN/2

STATE

CAL

CONV

Figur e 1. Cal ibration T iming (Not to Scale )

XIN

XIN/2

buh

Conversion StandbyStandby

CONV

STATE

scn

con

DRDY

BP/UP t

bus

cpw

Figure 2. Conversion Timing (Not to Scal e)

CS5509

6DS125F1

3.3V SWITCHING CHARACTERISTICS (TA = 25°C; VA+ = 5V ± 10%, VD+ = 3.3V ± 5%;

Input Levels : Logic 0 = 0V , Logic 1 = VD +; CL = 50pF.) ( Note 2)

Parameter Symbol Min Typ Max Units

Serial Clock fsclk 0 - 1.25 MHz

Serial Clock Pulse W idth High

Pulse Width Low tph

tpl 200

200 -

-ns

Access Time: CS Low to data valid (Note 16) tcsd - 100 200 ns

Maximum Delay Time: SCLK falling to new S DATA bit

(Note 17) tdd - 400 600 ns

Output Float Delay CS High to output Hi-Z (Note 18)

SCLK falling to Hi-Z tfd1

tfd2 -

-70

320 150

500 ns

5V SWITCHING CHARACTERISTICS (TA = 25°C; VA+, VD+ = 5V ± 10%; Input Levels : Logic 0

= 0V, Logi c 1 = VD+; CL = 50 pF.) (Note 2)

Parameter Symbol Min Typ Max Units

Serial Clock fsclk 0-2.5MHz

Serial Clock Pulse W idth High

Pulse Width Low tph

tpl 200

200 -

-ns

Access Time: CS Low to data valid (Note 16) tcsd - 60 200 ns

Maximum Delay Time: SCLK falling to new S DATA bit

(Note 17) tdd - 150 310 ns

Output Float Delay CS High to output Hi-Z (Note 18)

SCLK falling to Hi-Z tfd1

tfd2 -

-60

160 150

300 ns

Notes: 16. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high

for 2 clock cycles. The propagation delay time may be as great as 2 fclk cycles plus 200 ns. To

guarantee proper clocki ng of SDATA when usi ng asynchronous CS , SCLK(i) should not be taken high

sooner than 2 f clk + 200 ns after CS goes low.

17. SDATA transi tions on the falling edge of SCLK. Note that a ris ing SCLK must occur to enable the

serial port s hifting mechanism before falling edges can be recognized.

18. If CS is returned high before all data bits are output, the SDATA output will complete the current data

bit and then go to high impedance.

CS5509

DS125F1 7

SCLK(i)

MSB-1MSB MSB-2SDATA(o) Hi-Z

MSB-1MSB LSB+2 LSB+1 LSB

SCLK(i)

SDATA(o) Hi-Z

fd1

csd

DRDY

fd2

Figure 3. Timing Relationships (Not to Scale)

CS5509

8DS125F1

RECOMMENDED OPERATING CONDITIONS (DGND = 0V) (Note 19)

Parameter Symbol Min Typ Max Units

DC Power Supplies : Positiv e Digital

Positiv e Analog VD+

VA+ 3.15

4.5 5.0

5.0 5.5

5.5 V

Analog Reference Voltage (Note 20) (VREF+)-(VREF-) 1.0 2.5 3.6 V

Analog Input Voltage: (Note 6)

Unipolar

Bipolar VAIN

VAIN 0

-((VREF+)-(VREF-)) -

-(VREF+)-(VREF-)

(VREF+)-(VREF-) V

Notes: 19. All voltages with respect to ground.

20. The CS5509 can be operated with a reference vol tage as low as 100 mV; but with a

corresponding reduction in noise-free resolution. The common mode voltage of the voltage reference

may be any value as long as +VREF and -VREF remain inside the supply values of VA+ and GND.

ABSOLUTE MAXIMUM RATINGS*

Parameter Symbol Min Typ Max Units

DC Power Supplies: Ground (Note 21)

Positiv e Digital (Note 22)

Positiv e Analog

GND

VD+

VA+

-0.3

(VD+)-0.3

6.0

Input Current, Any Pin Except Supplies (Notes 23 & 24) Iin --

±10 mA

Output Current Iout --

±25 mA

Power Dissipati on (Total) (Note 25) - - 500 mW

Analog Input Voltage AIN and VREF pins VINA -0.3 - (VA+)+0.3 V

Digital Input Voltage VIND -0.3 - (VD+)+0.3 V

Ambient Operating Temperature TA-40 - 85 °C

Storage Temperature Tstg -65 - 150 °C

Notes: 21. No pin should go more positive than (VA +)+0.3V.

22. VD+ must always be less than (VA +)+0.3V, and can never ex ceed +6.0 V.

23. Applies to all pins includi ng continuous overvoltage condi tions at the analog input (AIN) pin.

24. Transient currents of up to 100mA will not cause SCR latch-up. Max imum input current for a power

supply pin is ± 50 mA.

25. Total power dissipati on, including all input currents and output cur rents.

* WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

CS5509

DS125F1 9

GENERAL DESCRIPTION

The CS5509 is a low power, 16-bit, monolithic

CMOS A/D converter designed specifically for

measurement of dc signals. The CS5509 in-

cludes a delta-sigma charge-balance converter, a

voltage reference, a calibration microcontroller

with SRAM, a digita l filter and a serial interfac e.

The CS5509 is optimized to operate from a

32.768 kHz crystal but can be driven by an ex-

ternal clock whose frequency is between 30 kHz

and 330 kHz. When the digital filter is operated

with a 32.768 kHz clock, the filter has zeros pre-

cisely at 50 and 60 Hz line frequencies and

multiples thereof.

The CS5509 uses a "start convert" command to

start a convolution cycle on the digital filter.

Once the filter cycle is completed, the output

port is updated. When operated with a

32.768 kHz clock the ADC converts and updates

its output port at 20 samples/sec. The output port

operates in a synchronous externally-clocked in-

terface format.

THEORY OF OPERATION

Basic Converter Operation

The CS5509 A/D converter has three operating

states. These are stand-by, calibration, and con-

version. When power is first applied, an internal

power-on reset delay of about 10 ms resets all of

the logic in the device. The oscillator must then

begin oscillating before the device can be con-

sidered functional. After the power-on reset is

applied, the device enters the wake-up period for

1800 clock cycles after clock is present. This

allows the delta-sigma modulator and other cir-

cuitry (which are operating with very low

currents) to reach a stable bias condition prior to

entering into either the calibration or conversion

states. During the 1800 cycle wake-up period,

the device can accept an input command. Execu-

tion of this command will not occur until the

complete wake-up period elapses. If no com-

mand is given, the device enters the standby

state.

Calibration

After the initial application of power, the

CS5509 must enter the calibration state prior to

performing accurate conversions. During calibra-

tion, the chip executes a two-step process. The

device first performs an offset calibration and

then follows this with a gain calibration. The

two calibration steps determine the zero refer-

ence point and the full scale reference point of

the converter’s transfer function. From these

points it calibrates the zero point and a gain

slope to be used to properly scale the output

digital codes when doing conversions.

The calibration state is entered whenever the

CAL and CONV pins are high at the same time.

The state of the CAL and CONV pins at power-

on are recognized as commands, but will not be

executed until the end of the 1800 clock cycle

wake-up period.

If CAL and CONV become active (high) during

the 1800 clock cycle wake-up time, the con-

verter will wait until the wake-up period elapses

before executing the calibration. If the wake-up

time has elapsed, the converter will be in the

standby mode waiting for instruction and will

enter the calibration cycle immediately if CAL

and CONV become active. The calibration lasts

for 3246 clock cycles. Calibration coefficients

are then retained in the SRAM (static RAM) for

use during conversion.

The state of BP/UP is ignored during calibration

but should remain stable throughout the calibra-

tion period to minimize noise.

When conversions are performed in unipolar

mode or in bipolar mode, the converter uses the

same calibration factors to compute the digital

CS5509

10 DS125F1

output code. The only difference is that in bipo-

lar mode the on-chip microcontroller offsets the

computed output word by a code value of

8000H. This means that the bipolar measure-

ment range is not calibrated from full scale

positive to full scale negative. Instead it is cali-

brated from the bipolar zero scale point to full

scale positive. The slope factor is then extended

below bipolar zero to accommodate the negative

input signals. The converter can be used to con-

vert both unipolar and bipolar signals by

changing the BP/UP pin. Recalibration is not re-

quired when switching between unipolar and

bipolar modes.

At the end of the calibration cycle, the on-chip

microcontroller checks the logic state of the

CONV signal. If the CONV input is low the de-

vice will enter the standby mode where it waits

for further instruction. If the CONV signal is

high at the end of the calibration cycle, the con-

verter will enter the conversion state and

perform a conversion on the input channel. The

CAL signal can be returned low any time after

calibration is initiated. CONV can also be re-

turned low, but it should never be taken low and

then taken back high until the calibration period

has ended and the converter is in the standby

state. If CONV is taken low and then high

again with CAL high while the converter is cali-

brating, the device will interrupt the current

calibration cycle and start a new one. If CAL is

taken low and CONV is taken low and then high

during calibration, the calibration cycle will

continue as the conversion command is disre-

garded. The state of BP/UP is not important

during calibrations.

If an "end of calibration" signal is desired, pulse

the CAL signal high while leaving the CONV

signal high continuously. Once the calibration is

completed, a conversion will be performed. At

the end of the conversion, DRDY will fall to in-

dicate the first valid conversion after the

calibration has been completed.

Conversion

The conversion state can be entered at the end of

the calibration cycle, or whenever the converter

is idle in the standby mode. If CONV is taken

high to initiate a calibration cycle ( CAL also

high), and remains high until the calibration cy-

cle is completed (CAL is taken low after CONV

transitions high), the converter will begin a con-

version upon completion of the calibration

period.

The BP/UP pin is not a latched input. The

BP/UP pin controls how the output word from

the digital filter is processed. In bipolar mode

the output word computed by the digital filter is

offset by 8000H (see Understanding Converter

Calibration). BP/UP can be changed after a con-

version is started as long as it is stable for 82

clock cycles of the conversion period prior to

DRDY falling. If one wishes to intermix meas-

urement of bipolar and unipolar signals on

various input signals, it is best to switch the

BP/UP pin immediately after DRDY falls and

leave BP/UP stable until DRDY falls again.

The digital filter in the CS5509 has a Finite Im-

pulse Response and is designed to settle to full

accuracy in one conversion time.

If CONV is left high, the CS5509 will perform

continuous conversions. The conversion time

will be 1622 clock cycles. If conversion is initi-

ated from the standby state, there may be up to

two XIN clock cycles of uncertainty as to when

conversion actually begins. This is because the

internal logic operates at one half the external

clock rate and the exact phase of the internal

clock may be 180° out of phase relative to the

XIN clock. When a new conversion is initiated

from the standby state, it will take up to two

XIN clock cycles to begin. Actual conversion

will use 1624 clock cycles before DRDY goes

low to indicate that the serial port has been up-

dated. See the Serial Interface Logic section of

CS5509

DS125F1 11

the data sheet for information on reading data

from the serial port.

In the event the A/D conversion command

(CONV going positive) is issued during the con-

version state, the current conversion will be

terminated and a new conversion will be initi-

ated.

Voltage Reference

The CS5509 uses a differential voltage reference

input. The positive input is VREF+ and the

negative input is VREF-. The voltage between

VREF+ and VREF- can range from 1 volt mini-

mum to 3.6 volts maximum. The gain slope will

track changes in the reference without recalibra-

tion, accommodating ratiometric applications.

Analog Input Range

The analog input range is set by the magnitude

of the voltage between the VREF+ and VREF-

pins. In unipolar mode the input range will

equal the magnitude of the voltage reference. In

bipolar mode the input voltage range will equate

to plus and minus the magnitude of the voltage

reference. While the voltage reference can be as

great as 3.6 volts, its common mode voltage can

be any value as long as the reference inputs

VREF+ and VREF- stay within the supply volt-

ages VA+ and GND. The differential input

voltage can also have any common mode value

as long as the maximum signal magnitude stays

within the supply voltages.

The A/D converter is intended to measure dc or

low frequency inputs. It is designed to yield ac-

curate conversions even with noise exceeding

the input voltage range as long as the spectral

components of this noise will be filtered out by

the digital filter. For example, with a 3.0 volt

reference in unipolar mode, the converter will

accurately convert an input dc signal up to

3.0 volts with up to 15% overrange for 60 Hz

noise. A 3.0 volt dc signal could have a 60 Hz

component which is 0.5 volts above the maxi-

mum input of 3.0 (3.5 volts peak; 3.0 volts dc

plus 0.5 volts peak noise) and still accurately

convert the input signal (XIN = 32.768 kHz).

This assumes that the signal plus noise ampli-

tude stays within the supply voltages.

The CS5509 converters output data in binary

format when converting unipolar signals and in

offset binary format when converting bipolar

signals. Table 1 outlines the output coding for

both unipolar and bipolar measurement modes.

Converter Performance

The CS5509 A/D converter has excellent linear-

ity performance. Calibration minimizes the

errors in offset and gain. The CS5509 device

has no missing code performance to 16-bits.

Figure 4 illustrates the DNL of the CS5509. The

converter achieves Common Mode Rejection

(CMR) at dc of 105 dB typical, and CMR at 50

and 60 Hz of 120 dB typical.

The CS5509 can experience some drift as tem-

perature changes. The CS5509 uses

chopper-stabilized techniques to minimize drift.

Measurement errors due to offset or gain drift

can be eliminated at any time by recalibrating

the converter.

Unipolar Input

Voltage Output

Codes Bipolar Input

Voltage

>(VREF - 1.5 LSB) FFFF >(VREF - 1.5 LSB)

VREF - 1.5 LSB FFFF

FFFE VREF - 1.5 LSB

VREF/2 - 0.5 LSB 8000

7FFF -0.5 LSB

+0.5 LSB 0001

0000 -VREF +0.5 LSB

<(+0.5 LSB) 0000 <(-VREF +0.5 LSB)

Note: Table exc ludes common mode voltage on the

signal and reference inputs.

Table 1. Output Co ding

CS5509

12 DS125F1

Analog Input Impedance Considerations

The analog input of the CS5509 can be modeled

as illustrated in Figure 5. Capacitors (15 pF

each) are used to dynamically sample each of

the inputs (AIN+ and AIN-). Every half XIN cy-

cle the switch alternately connects the capacitor

to the output of the buffer and then directly to

the AIN pin. Whenever the sample capacitor is

switched from the output of the buffer to the

AIN pin, a small packet of charge (a dynamic

demand of current) is required from the input

source to settle the voltage of the sample capaci-

tor to its final value. The voltage on the output

of the buffer may differ up to 100 mV from the

actual input voltage due to the offset voltage of

the buffer. Timing allows one half of a XIN

clock cycle for the voltage on the sample capaci-

tor to settle to its final value.

An equation for the maximum acceptable source

resistance is derived.

Rsmax = −1

2XIN (15pF + CEXT) ln 







Ve + 15pF(100mv)

(15pF + CEXT









This equation assumes that the offset voltage of

the buffer is 100 mV, which is the worst case.

The value of Ve is the maximum error voltage

which is acceptable. CEXT is the combination

of any external or stray capacitance.

For a maximum error voltage (Ve) of 10 µV in

the CS5509 (1/4LSB at 16-bits), the above equa-

tion indicates that when operating from a

32.768 kHz XIN, source resistances up to

110 kΩ are acceptable in the absence of external

capacitance (CEXT = 0).

The VREF+ and VREF- inputs have nearly the

same structure as the AIN+ and AIN- inputs.

Therefore, the discussion on analog input imped-

ance applies to the voltage reference inputs as

well.

065,535

Codes

32,768

DNL (LSB)

-1

+1/2

-1/2

Figure 4. CS5509 Differential Nonlinearity plot.

15 pF

≤

100 mV

≤

100 mV

Internal

Bias

Voltage

15 pF

AIN+

AIN-

Figure 5. Analog Input Model

CS5509

DS125F1 13

Digital Filter Characteristics

The digital filter in the CS5509 is the combina-

tion of a comb filter and a low pass filter. The

comb filter has zeros in its transfer function

which are optimally placed to reject line interfer-

ence frequencies (50 and 60 Hz and their

multiples) when the CS5509 is clocked at

32.768 kHz. Figures 6, 7 and 8 illustrate the

magnitude and phase characteristics of the filter.

Figure 6 illustrates the filter attenuation from dc

to 260 Hz. At exactly 50, 60, 100, and 120 Hz

the filter provides over 120 dB of rejection. Ta-

ble 2 indicates the filter attenuation for each of

the potential line interference frequencies when

the converter is operating with a 32.768 kHz

clock. The converter yields excellent attenuation

of these interference frequencies even if the fun-

damental line frequency should vary ± 1% from

402.83 80

805.66 120

1208.5 160

1611.3 200

2014.2 240

2416.9

Frequency (Hz)

-160

-140

-120

-100

-80

-60

-40

-20

Attenuation (dB)

XIN = 32.768 kHz

X1 = 32.7 68kHz

X2 = 330.00kHz

Figure 6. Filter Magnitude Plot to 260 Hz

Frequency Notch Frequency Minimum

(Hz) Depth (Hz) Attenuation

(dB) (dB)

50 125.6 50±1% 55.5

60 126.7 60±1% 58.4

100 145.7 100±1% 62.2

120 136.0 120±1% 68.4

150 118.4 150±1% 74.9

180 132.9 180±1% 87.9

200 102.5 200±1% 94.0

240 108.4 240±1% 104.4

Table 2. Filter Notch Attenuation (XIN = 32.768 kHz)

0 5 10 15 20 25 30 35 40 45 50

Frequency (Hz)

-140

-120

-100

-80

-60

-40

-20

Attenuation (dB)

Flatness

-0.010

-0.041

-0.093

-0.166

-0.259

-0.510

-0.667

-0.846

-1.047

-3.093

XIN = 32.768 kHz

Frequency

-0.374

Figure 7. Filter Magnitude Plot to 50 Hz

0 5 10 15 20 25 30 35 40 45 50

Freq uen cy ( H z )

-180

-135

-90

-45

135

180

Phase (De grees)

XIN = 32.768 kHz

Figure 8. Filter Phase Plot to 50 Hz

CS5509

14 DS125F1

its specified frequency. The -3dB corner fre-

quency of the filter when operating from a

32.768 kHz clock is 17 Hz. Figure 8 illustrates

that the phase characteristics of the filter are pre-

cisely linear phase.

If the CS5509 is operated at a clock rate other

than 32.768 kHz, the filter characteristics, in-

cluding the comb filter zeros, will scale with the

operating clock frequency. Therefore, optimum

rejection of line frequency interference will oc-

cur with the CS5509 running at 32.768 kHz.

Anti-Alias Conside rations for Spectral

Measurement Applications

Input frequencies greater than one half the out-

put word rate (CONV = 1) may be aliased by

the converter. To prevent this, input signals

should be limited in frequency to no greater than

one half the output word rate of the converter

(when

CONV =1). Frequencies close to the modulator

sample rate (XIN/2) and multiples thereof may

also be aliased. If the signal source includes

spectral components above one half the output

word rate (when CONV = 1) these components

should be removed by means of low-pass filter-

ing prior to the A/D input to prevent aliasing.

Spectral components greater than one half the

output word rate on the VREF inputs (VREF+

and VREF-) may also be aliased. Filtering of the

reference voltage to remove these spectral com-

ponents from the reference voltage is desirable.

Crystal Oscillator

The CS5509 is designed to be operated using a

32.768 kHz "tuning fork" type crystal. One end

of the crystal should be connected to the XIN

input. The other end should be attached to

XOUT. Short lead lengths should be used to

minimize stray capacitance.

Over the industrial temperature range (-40 to

+85 °C) the on-chip gate oscillator will oscillate

with other crystals in the range of 30 kHz to 53

kHz. The chip will operate with external clock

frequencies from 30 kHz to 330 kHz over the in-

dustrial temperature range. The 32.768 kHz

crystal is normally specified as a time-keeping

crystal with tight specifications for both initial

frequency and for drift over temperature. To

maintain excellent frequency stability, these

crystals are specified only over limited operating

temperature ranges (i.e. -10 °C to +60 °C) by the

manufacturers. Applications of these crystals

with the CS5509 does not require tight initial

tolerance or low tempco drift. Therefore, a lower

cost crystal with looser initial tolerance and tem-

pco will generally be adequate for use with the

CS5509. Also check with the manufacturer

about wide temperature range application of

their standard crystals. Generally, even those

crystals specified for limited temperature range

will operate over much larger ranges if fre-

quency stability over temperature is not a

requirement. The frequency stability can be as

bad as ±3000 ppm over the operating tempera-

ture range and still be typically better than the

line frequency (50 Hz or 60 Hz) stability over

cycle-to-cycle during the course of a day.

Serial Interface Logic

The digital filter in the CS5509 takes 1624 clock

cycles to compute an output word once a con-

version begins. At the end of the conversion

cycle, the filter will attempt to update the serial

port. Two clock cycles prior to the update

DRDY will go high. When DRDY goes high

just prior to a port update it checks to see if the

port is either empty or unselected (CS = 1). If

the port is empty or unselected, the digital filter

will update the port with a new output word.

When new data is put into the port DRDY will

go low.

CS5509

DS125F1 15

Reading Serial Data

SDATA is the output pin for the serial data.

When CS goes low after new data becomes

available (DRDY goes low), the SDATA pin

comes out of Hi-Z with the MSB data bit pre-

sent. SCLK is the input pin for the serial clock.

If the MSB data bit is on the SDATA pin, the

first rising edge of SCLK enables the shifting

mechanism. This allows the falling edges of

SCLK to shift subsequent data bits out of the

port. Note that if the MSB data bit is output and

the SCLK signal is high, the first falling edge of

SCLK will be ignored because the shifting

mechanism has not become activated. After the

first rising edge of SCLK, each subsequent fall-

ing edge will shift out the serial data. Once the

LSB is present, the falling edge of SCLK will

cause the SDATA output to go to Hi-Z and

DRDY to return high. The serial port register

will be updated with a new data word upon the

completion of another conversion if the serial

port has been emptied, or if the CS is inactive

(high).

CS can be operated asynchronously to the

DRDY signal. The DRDY signal need not be

monitored as long as the CS signal is taken low

for at least two XIN clock cycles plus 200 ns

prior to SCLK being toggled. This ensures that

CS has gained control over the serial port.

Power Supplies and Grounding

The analog and digital supply pins to the

CS5509 are brought out on separate pins to

minimize noise coupling between the analog and

digital sections of the chip. In the digital section

of the chip the supply current flows into the

VD+ pin and out of the GND pin. As a CMOS

device, the CS5509 requires that the supply volt-

age on the VA+ pin always be more positive

than the voltage on any other pin of the device.

If this requirement is not met, the device can

latch-up or be damaged. In all circumstances the

VA+ voltage must remain more positive than the

VD+ or GND pins; VD+ must remain more

positive than the GND pin.

Figure 9a illustrates the System Connection Dia-

gram for the CS5509. Note that all supply pins

are bypassed with 0.1 µF capacitors and that the

VD+ digital supply is derived from the VA+

supply. Figure 9b illustrates the CS5509 operat-

ing from a +5V analog supply and +3.3V digital

supply.

When using separate supplies for VA+ and

VD+, VA+ must be established first. VD+

should never become more positive than VA+

under any operating condition. Remember to in-

vestigate transient power-up conditions, when

one power supply may have a faster rise time.

Schematic & Layout Review Service

Confirm Optimum

Schematic & Layout

Before Building Your Board.

Confirm Optimum

Schematic & Layout

Before Building Your Board.

For Our Free Review Service

Call Applications Engineering.

For Our Free Review Service

Call Applications Engineering.

Call:(512)445-7222

CS5509

16 DS125F1

CS5509

+5V

Analog

Supply VD+VA+

VREF+

VREF-

GND

0.1

Analog

Signal AIN+

AIN-

SCLK

SDATA

XIN

XOUT

DRDY

CAL

CONV

BP/UP

32.768 kHz

Ω

Voltage

Reference

Optional

Clock

Source Serial

Data

Interface

Control

Logic

Figure 9a. System Connection Diagram Using a Single Supply

CS5509

DS125F1 17

CS5509

+5V

Analog

Supply VD+VA+

VREF+

VREF-

GND

0.1

Analog

Signal AIN+

AIN-

SCLK

SDATA

XIN

XOUT

DRDY

CAL

CONV

BP/UP

32.768 kHz

Voltage

Reference

Optional

Clock

Source Serial

Data

Interface

Control

Logic

+3.3V to +5V

Digital

Supply

Note: VD+ must never be more positive than VA+

Figure 9b. System Connection Diagram Using Split Supplies

CS5509

18 DS125F1

PIN DESCRIPTIONS*

Clock Generator

XIN; XOUT - Crystal In; Crystal Out, Pins 4, 5.

A gate inside the chip is connected to these pins and can be used with a crystal to provide the

master clock for the device. Alternatively, an external (CMOS compatible) clock can be

supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the

device into a lower powered state (approximately 70% power reduction).

Serial Output I/O

CS - Chip Select, Pin 1.

This input allows an external device to access the serial port.

DRDY - Data Ready, Pin 16.

Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new

output word has been placed into the serial port. DRDY will return high after all data bits are

shifted out of the serial port or two master clock cycles before new data becomes available if

the CS pin is inactive (high).

SDATA - Serial Data Output, Pin 15.

SDATA is the output pin of the serial output port. Data from this pin will be output at a rate

determined by SCLK. Data is output MSB first and advances to the next data bit on the falling

edges of SCLK. SDATA will be in a high impedance state when not transmitting data.

SCLK - Serial Clock Input, Pin 14.

A clock signal on this pin determines the output rate of the data from the SDATA pin. This pin

must not be allowed to float.

CHIP SELECT CS DRDY DATA READY

CONVERT CONV SDATA SERIAL DATA OUTPUT

CALIBRATE CAL SCLK SERIAL CLOCK INPUT

CRYSTAL IN XIN VD+ PO SITIVE DIGITA L POWER

CRYSTAL OUT XOUT GND GROUND

BIPOLAR/UNIPOLAR BP/UP VA+ PO SITIVE ANALO G POWER

DIFFERENTIAL ANALOG INPUT AIN+ VREF- VOLTAGE REFERENCE INPUT

DIFFERENTIAL ANALOG INPUT AIN- VREF+ VOLTAGE REFERENCE INPUT

*Pinout appl ies to both PDIP and S OIC

CS5509

DS125F1 19

Control Input Pins

CAL - Calibrate, Pin 3.

When taken high the same time that the CONV pin is taken high the converter will perform a

self-calibration which includes calibration of the offset and gain scale factors in the converter.

CONV - Convert, Pin 2.

The CONV pin initiates a calibration cycle if it is taken from low to high while the CAL pin is

high, or it initiates a conversion if it is taken from low to high with the CAL pin low. If

CONV is held high (CAL low) the converter will do continuous conversions.

BP/UP - Bipolar/Unipolar, Pin 6.

The BP/UP pin selects the conversion mode of the converter. When high the converter will

convert bipolar input signals; when low it will convert unipolar input signals.

Measurement and Reference Inputs

AIN+, AIN- - Differential Analog Inputs, Pins 7, 8.

Analog differential inputs to the delta-sigma modulator.

VREF+, VREF- - Differential Voltage Reference Inputs, Pins 9, 10.

A differential voltage reference on these pins operates as the voltage reference for the

converter. The voltage between these pins can be any voltage between 1.0 and 3.6 volts.

Power Supply Connections

VA+ - Positive Analog Power, Pin 11.

Positive analog supply voltage. Nominally +5 volts.

VD+ - Positive Digital Power, Pin 13.

Positive digital supply voltage. Nominally +5 volts or +3.3 volts.

GND - Ground, Pin 12.

Ground.

CS5509

20 DS125F1

SPECIFICATION DEFINITIONS

Linearity Error

The deviation of a code from a straight line which connects the two endpoints of the A/D

Converter transfer function. One endpoint is located 1/2 LSB below the first code transition

and the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in

percent of full-scale.

Differential Nonlinearity

The deviation of a code’s width from the ideal width. Units in LSBs.

Full Scale Error

The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} - 3⁄2 LSB].

Units are in LSBs.

Unipolar Offset

The deviation of the first code transition from the ideal (1⁄2 LSB above the voltage on the AIN-

pin.) when in unipolar mode (BP/UP low). Units are in LSBs.

Bipolar Offset

The deviation of the mid-scale transition (011...111 to 100...000) from the ideal (1⁄2 LSB below

the voltage on the AIN- pin.) when in bipolar mode (BP/UP high). Units are in LSBs

CS5509

DS125F1 21

APPENDIX

The following companies provide 32.768 kHz crystals in many package varieties and temperature

ranges.

Fox Electronics

5570 Enterprise Parkway

Fort Meyers, FL 33905

(813) 693-0099

Micro Crystal Division / SMH

702 West Algonquin Road

Arlington Heights, IL 60005

(708) 806-1485

SaRonix

4010 Transport Street

Palo Alto, California 94303

(415) 856-6900

Statek

512 North Main

Orange, California 92668

(714) 639-7810

IQD Ltd.

North Street

Crewkerne

Somerset TA18 7AK

England

01460 77155

Mr. Pierre Hersberger

Microcrystal/DIV. ETA S.A.

Schild-Rust-Strasse 17

Grenchen CH-2540

Switzerland

065 53 05 57

Taiwan X’tal Corp.

5F. No. 16, Sec 2, Chung Yang S. RD.

Reitou, Taipei, Taiwan R. O. C.

Tel: 02-894-1202

Fax: 02-895-6207

Interquip Limited

24/F Million Fortune Industrial Centre

34-36 Chai Wan Kok Street, Tsuen Wan N T

Tel: 4135515

Fax: 4137053

S& T Enterprises, Ltd.

Rm 404 Blk B

Sea View Estate

North Point, Hong Kong

Tel: 5784921

Fax: 8073126

Mr. Darren Mcleod

Hy-Q International Pty. Ltd.

12 Rosella Road,

FRANKSON, 3199

Victoria, Australia

Tel: 61-3-783 9611

Fax: 61-3-783 9703

CS5509

22 DS125F1



Cirrus Logic, Inc. 1998

(All Rights Rese rved)

Cirrus Logic, Inc.

Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.crystal.com

CDB5509

Evaluation Board for the CS5509 A/D Converter

Features

Operation with on-board 32.768 kHz crystal

or off-board clock source

DIP Switch Selectable:

-BP/UP mode

On-board precision voltage reference

Access to all digital control pins

Description

The CDB5509 is a circuit board designed to provide

quick evaluation of the CS5509 A/D converter.

The board provides buffered digital signals, an on-board

precision voltage reference, o ptions for usi ng an external

clock, and a momentary swit ch to initiate calib ration.

ORDERING INFORMATION

CDB5509 Evaluat ion Board

AIN+

AIN-

+5V

GND

CS5509

CLKIN

VREF

MAR ‘95

DS125DB1

Introduction

The CDB5509 evaluation board provides a quick

means of testing the CS5509 A/D converter. The

CS5509 converter requires a minimal amount of

external circuitry. The evaluation board comes

configured with the A/D converter chip operat-

ing from a 32.768 kHz crystal and with an

off-chip precision 2.5 volt reference. The board

provides access to all of the digital interface pins

of the CS5509 chip.

Evaluation Board Overview

The board provides a complete means of making

the CS5509 A/D converter chip function. The

user must provide a means of taking the output

data from the board in serial format and using it

in his system.

Figure 1 illustrates the schematic for the board.

The board comes configured for the A/D con-

verter chip to operate from the 32.768 kHz

watch crystal. A BNC connector for an external

clock is provided on the board. To connect the

external BNC source to the converter chip, a cir-

cuit trace must be cut. Then a jumper must be

inserted in the proper holes to connect the XIN

pin of the converter to the input line from the

BNC. The BNC input is terminated with a 50Ω

resistor. Remove this resistor if driving from a

logic gate. See the schematic in Figure 1.

The board comes with the A/D converter VREF+

and VREF- pins hard-wired to the 2.5 volt

bandgap voltage reference IC on the board.

All of the control pins of the CS5509 are avail-

able at the J1 header connector. Buffer ICs U2

and U3 are used to buffer the converter for inter-

face to off-board circuits. The buffers are used

on the evaluation board only because the exact

loading and off-board circuitry is unknown.

Most applications will not require the buffer ICs

for proper operation.

To put the board in operation, select either bipo-

lar or unipolar mode with DIP switch S2. Then

press the CAL pushbutton after the board is

powered up. This initiates calibration of the con-

verter which is required before measurements

can be taken. With CONV high (S2-3 open) the

converter will convert continuously. Figure 3 il-

lustrates the CAB5509 adapter board. The

CAB5509 translates a CS5505 pinout to a

CS5509 pinout.

Figures 4 and 5 illustrate the evaluation board

layout while Figure 6 illustrates the component

placement (silkscreen) of the evaluation board.

CDB5509

24 DS125DB1

Figure 1. ADC Connections

U3C

R21

47k

VD+

U3D

810 9

TP14

11 12

VD+

R16

100k

TP13

U3B

U3A

VD+

C18

0.1

SCLKI

SCLKO

SDATA

DRDY

CONV

CAL

U2F8

1514

U2E 1211

U2D

10 9

U2C

U2B

U2A 3

R20

R19 R18

47k

R17

47k VD+

VD+

C17

0.1

TP12

TP11

TP7

TP8

TP9

TP10

100k

SCLK

DRDY

SDATA

C16

R22

10 +

R10 20k

U2 74HC4050

U3 74HC125

VD+

100k

VD+

100k

R25

100k

R24

100k

R23

100k

S2 A1

CONV

BP/UP

0.01

0.1

2LT1019

-2.5 V

0.1

External

VREF

25k

VA+

GND

VD+

XIN

XOUT

BP/UP

SCLK

SDATA

CAL

CONV

DRDY

VREF+

VREF-

C10

0.1

11 13

VD+

C70.1

C11

0.01

CAL

R11

100k

32.768

kHz

CLKIN

TP15

200

AIN+ 402 AIN+

R13

AIN-

TP6

402 C15

100k

R31

R12

R27

R26 C19

C20

10nF

CS5509

+5V

GND

F0.1

6.8V

AGND

DGND

AIN-

Note: Buffers not required for general applications.

CDB5509

DS125DB1 25

CS DRDY

CONV SDATA

CAL SCLK

XIN VD+

XOUT GND

BP/UP VA+

AIN+ VREF-

AIN- VREF+

Figure 2. CS5509 Pin Layout

116

1312

(Top View)

Figure 3. CA B5509 A dapter Board

CDB5509

26 DS125DB1

Figure 4. Top Ground Plane Layer (NOT TO SCALE)

CDB5509

DS125DB1 27

Figure 5. Bottom Trace Layer (NOT TO SCALE)

CDB5509

28 DS125DB1

Figure 6. Silk Screen Layer (NOT TO SCALE)

CDB5509

DS125DB1 29