1-Mbit (64K x 16) Static RAM
CY62126DV30
MoBL®
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-05230 Rev. *D Revised June 21, 2004
Features
• Very high speed: 55 and 70 ns
• Wide voltage ran ge: 2.2V to 3.6V
• Pin compatible with CY62126BV
• Ultra-low active power
— Typica l active current: 0.85 mA @ f = 1 MHz
— Typica l active current: 5 mA @ f = fMAX
• Ultra-low standby power
• Easy memory expansion with CE and OE featur es
• Automatic power-down when deselected
• Packages offered in a 48-ball FBGA and a 44-lead TSOP
Type II
Functional Description[1]
The CY62126DV30 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular te lephones. Th e device
also has an automatic power-down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected Chip
Enable (CE) HIGH. The input/output pins (I/O0 through I/O15)
are placed in a high-impedance state when: deselected Chip
Enable (CE) HIGH, outputs are disabled (OE HIGH), both Byte
High Enable and Byte Low Enable are disabled (BHE, BLE
HIGH) or during a Write operation (Chip Enable (CE) LOW and
Write Enable (WE) LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) LOW and Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0 through
I/Oh A15). If Byte High Enable (BHE) is LOW, then data from
I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A15).
Reading from the device is accomplished by taking Chip
Enable (CE) LOW and Output Enable (OE) LOW while forcing
the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is
LOW, then O7. If Byte High En able (BHE) is LOW, then data
from memory will appear on I/O8 to I/O15.
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
64K x 16
RAM Array I/O0–I/O7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12
A13
A14
A15
2048 x 512
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3I/O8–I/O15
CE
WE
BLE
BHE
A0
A1
A9
A10
CY62126DV30
MoBL®
Document #: 38-05230 Rev. *D Page 2 of 11
Pin Configurations[2,3]
Notes:
2. NC pins are not connected to the die.
3. E3 (DNU) can be left as NC or VSS to ensure proper operation. (Expansion Pins on FBGA Package: E4 - 2M, D3 - 4M, H1 - 8M, G2 - 16M, H6 - 32M).
WE
A11
A10
A6
A0
A3CE
I/O10
I/O8
I/O9
A4
A5
I/O11
I/O13
I/O12
I/O14
I/O15
VSS
A9
A8
OE
VSS
A7
I/O0
BHE
NC
A2
A1
BLE
VCC
I/O2
I/O1
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
FBGA (Top View)
NC
DNU
VCC
NC
WE
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top View
TSOP II (Forward)
12
13
41
44
43
42
16
15 29
30
VCC
A15
A14
A13
A12
NC
A4
A3
OE
VSS
A5
I/O15
A2
CE
I/O2
I/O0
I/O1
BHE
NC
A1
A0
18
17
20
19
I/O3
27
28
25
26
22
21 23
24 NC
VSS
I/O6
I/O4
I/O5
I/O7
A6
A7
BLE
VCC
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
CY62126DV30
MoBL®
Document #: 38-05230 Rev. *D Page 3 of 11
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground
Potential...........................................................−0.3V to 3.9V
DC Voltage Applied to Outputs
in High-Z S tate[4] ....................................−0.3V to VCC + 0.3V
DC Input Voltage[4] ................................−0.3V to VCC + 0.3V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ....................................................> 200 mA
Operating Range
Range Ambient Temperature (TA) VCC[5]
Industrial −40°C to +85°C 2.2V to 3.6V
Product Portfolio
Product VCC Range (V) Speed
(ns)
Power Dissipation
Operating, ICC (mA) Standby, ISB2 (µA)f = 1 MHz f = fMAX
Min. Typ. Max. Typ.[6] Max. Typ.[6] Max. Typ.[6] Max.
CY62126DV30L 2.2 3.0 3.6 55/70 0.85 1.5 510 1.5 5
CY62126DV30LL 55/70 0.85 1.5 510 1.5 4
DC Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
CY62126DV30-55/70
UnitMin. Typ.[6] Max.
VOH Output HIGH Voltage 2.2 < VCC < 2.7 IOH = −0.1 mA 2.0 V
2.7 < VCC < 3.6 IOH = −1.0 mA 2.4
VOL Output LOW Voltage 2.2 < VCC < 2.7 IOL = 0.1 mA 0.4 V
2.7 < VCC < 3.6 IOL = 2.1 mA 0.4
VIH Input HIGH Voltage 2.2 < VCC < 2.7 1.8 VCC + 0.3 V
2.7 < VCC < 3.6 2.2 VCC + 0.3
VIL Input LOW Voltage 2.2 < VCC < 2.7 −0.3 0.6 V
2.7 < VCC < 3.6 −0.3 0.8
IIX Input Leakage Current GND < VI < VCC −1+1 µA
IOZ Output Leakage Current GND < VO < VCC, Output Disabled −1+1 µA
ICC VCC Operating Supp ly
Current f = fMAX = 1/tRC VCC = 3.6V,
IOUT = 0 mA,
CMOS level
510 mA
f = 1 MHz 0.85 1.5
ISB1 Automatic CE Power-down
Current − CMOS Inputs CE > VCC − 0.2V,
VIN > VCC − 0.2V, VIN < 0.2V,
f = fMAX (Address and Data Only),
f = 0 (OE, WE, BHE and BLE)
L1.5 5µA
LL 1.5 4
ISB2 Automatic CE Power-down
Current − CMOS Inputs CE > VCC − 0.2V,
VIN > VCC − 0.2V or VIN < 0.2V,
f = 0, VCC = 3.6V
L1.5 5µA
LL 1.5 4
Notes:
4. VIL(min.) = −2.0V for pulse durations less than 20 ns., VIH(max.) = VCC + 0.75V for pulse durations less than 20 ns.
5. Full device operation requires line ar ramp of VCC from 0V to VCC(min) & VCC must be stable at VCC(min) for 500 µ s.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
CY62126DV30
MoBL®
Document #: 38-05230 Rev. *D Page 4 of 11
AC Test Loads and Waveforms
Capacitance[8]
Parameter Description Test Conditions Max. Unit
CIN Input Capacit ance TA = 25°C, f = 1 MHz
VCC = VCC(typ) 8pF
COUT Output Capacitance 8pF
Thermal Resistance
Parameter Description Test Conditions TSOP FBGA Unit
θJA Thermal Resistance (Junction to Ambient)[7] Still Air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board 55 76 °C/W
θJC Thermal Resistance (Junction to Case)[7] 12 11 °C/W
Data Retention Characteristics
Parameter Description Conditions Min. Typ.[6] Max. Unit
VDR VCC for Data Retention 1.5 V
ICCDR Data Retention Current VCC=1.5V, CE > VCC − 0.2V,
VIN > VCC − 0.2V or VIN < 0.2V L 4 µA
LL 3
tCDR[7] Chip Deselect to Data
Retention T ime 0ns
tR[8] Operation Recovery Time 100 µs
Notes:
7. Tested initially and after any design or proces changes that may affect these parameters.
8. Full device operation requires linear VCC ramp from VDR to VCC(min.) >100 µs.
VCC Typ
VCC
OUTPUT
R2
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
OUTPUT VTH
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Rise TIme: 1 V/ns Fall Time: 1 V/ns
Parameters 2.5V 3.0V Unit
R1 16600 1103 Ohms
R2 15400 1554 Ohms
RTH 8000 645 Ohms
VTH 1.2 1.75 Volts
CY62126DV30
MoBL®
Document #: 38-05230 Rev. *D Page 5 of 11
Data Retention Waveform
VCC(min)
VCC(min)
tCDR
VDR >1.5 V
DATA RETENTION MODE
tR
CE
VCC
Switching Characteristics (Over the Operating Range)[9]
Parameter Description
CY62126DV30-55 CY62126DV30-70
UnitMin. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 55 70 ns
tAA Address to Data Valid 55 70 ns
tOHA Data Hold from Address Change 10 10 ns
tACE CE LOW to Data Valid 55 70 ns
tDOE OE LOW to Data Valid 25 35 ns
tLZOE OE LOW to Low Z[10] 5 5 ns
tHZOE OE HIGH to High Z[10, 11] 20 25 ns
tLZCE CE LOW to Low Z[10] 10 10 ns
tHZCE CE HIGH to High Z[10, 11] 20 25 ns
tPU CE LOW to Power-up 0 0 ns
tPD CE HIGH to Power-down 55 70 ns
tDBE BLE/BHE LOW to Data Va lid 25 35 ns
tLZBE BLE/BHE LOW to Low Z[10] 5 5 ns
tHZBE BLE/BHE HIGH to High-Z[10, 11] 20 25 ns
Write Cycle[12]
tWC Write Cycle Time 55 70 ns
tSCE CE LOW to Write End 40 60 ns
tAW Address Set-up to Write End 40 60 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-up to Write Start 0 0 ns
tPWE WE Pulse Width 40 50 ns
tBW BLE/BHE LOW to Write End 40 60 ns
tSD Data Set-up to Write End 25 30 ns
tHD Data Ho l d from Write End 0 0 ns
tHZWE WE LOW to High Z[10, 11] 20 25 ns
tLZWE WE HIGH to Low Z[10] 10 5ns
Notes:
9. Test conditions assume signal tr ansition time of 1V/ ns or less, timing re ference levels of VCC(typ.)/2 , input pulse level s of 0 to VCC(typ.), and output loading of the
specified IOL.
10.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than t.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance st ate.
12.The internal Write time of the memory is define d by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signal.
CY62126DV30
MoBL®
Document #: 38-05230 Rev. *D Page 6 of 11
Switching Waveforms
Notes:
13.Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL.
14.WE is HIGH for Read cycle.
15.Address valid prior to or coincident with CE, BHE, BLE transition LOW.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
Read Cycle No. 1 (Address Transition Controlled)[13, 14]
Read Cycle No. 2 (OE Controlled)[14, 15]
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
DATA OUT HIGH IMPEDANCE IMPEDANCE
I
CC
I
SB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
CC
SUPPLY
CURRENT
t
HZBE
BHE/BLE t
LZOE
ADDRESS
t
DOE
t
LZOE
tDBE
CY62126DV30
MoBL®
Document #: 38-05230 Rev. *D Page 7 of 11
Write Cycle No. 1 (WE Controlled) [11, 12, 16, 17, 18]
Write Cycle No. 2 (CE Controlled) [11, 12, 16, 17, 18]
Notes:
16.Data I/O is high-impedance if OE = VIH.
17.If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
18.During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Switching Waveforms(continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
DATA I/O
ADDRESS
CE
WE
OE
tHZOE
DATAIN VALID
NOTE18
BHE/BLE tBW
tSCE
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 18
BHE/BLE tBW
tSA
CY62126DV30
MoBL®
Document #: 38-05230 Rev. *D Page 8 of 11
Write Cycle No. 3 (WE Controlled, OE LOW)[17, 18]
Write Cycle No. 4 (BHE-/BLE-controlled, OE LOW)[17, 18]
Switching Waveforms(continued)
DATAIN VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATAI/O NOTE 18
tBW
BHE/BLE
DATA I/O
ADDRESS
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
CE
WE
DATA
IN
VALID
NOTE 18
t
BW
BHE/BLE
tSCE
t
PWE
CY62126DV30
MoBL®
Document #: 38-05230 Rev. *D Page 9 of 11
Truth Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High Z Deselect/Power-Down Standby (ISB)
L X X H H High Z Output Disabled Active (ICC)
L H L L L Data Out (I/OO–I/O15)Read Active (ICC)
L H L H L Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z Read Active (ICC)
L H L L H Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z Read Active (ICC)
L H H L L High Z Output Disabled Active (ICC)
L H H H L High Z Output Disa bled Active (ICC)
L H H L H High Z Output Disa bled Active (ICC)
L L X L L Data In (I/OO–I/O15)Write Active (ICC)
L L X H L Data In (I/OO–I/O7);
I/O8–I/O15 in High Z Write Active (ICC)
L L X L H Data In (I/O8–I/O15);
I/O0–I/O7 in High Z Write Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
55 CY62126DV30L-55BVI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Industrial
CY62126DV30LL-55BVI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62126DV30L-55ZI Z44 44-Lead TSOP Type II
CY62126DV30LL-55ZI Z44 44-Lead TSOP Ty pe II
70 CY62126DV30L-70BVI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Industrial
CY62126DV30LL-70BVI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62126DV30L-70ZI Z44 44-Lead TSOP Type II
CY62126DV30LL-70ZI Z44 44-Lead TSOP Ty pe II
CY62126DV30
MoBL®
Document #: 38-05230 Rev. *D Page 10 of 11
© Cypress Semi con duct or Cor po rati on , 20 04 . The information contained he re i n is su bject to change without notice. Cypr ess S em i con duct or Corpo ration assu mes no resp onsib ility f or th e u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. F urthermore, Cyp ress does not a uthorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
MoBL is a registered tra demark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and
company names mentioned in this document are the trademarks of their respective holders.
Package Diagrams
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*B
44-pin TSOP II Z44
51-85087-*A
CY62126DV30
MoBL®
Document #: 38-05230 Rev. *D Page 11 of 11
Document History Page
Document Title: CY62126DV30 MoBL® 1- Mbit (64K x 16) Static RAM
Document Number: 38-05230
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 11768 9 08/27/02 JUI New Data Sheet
*A 127313 06/13/03 MPR Changed From Advanced Status to Preliminary.
Changed ISB2 to 5 µA (L), 4 µA (LL)
Changed ICCDR to 4 µA (L), 3 µA (LL)
Changed CIN from 6 pF to 8 pF
*B 128340 07/22/03 JUI Changed from Preliminary to Final
Add 70-ns speed, updated ordering information
*C 129002 0 8/29/03 CDY Changed ICC 1 MHz typ from 0.5 mA to 0.85 mA
*D 238050 See ECN AJU Fixed typo: Changed tDBE from 70 ns to 35 ns
