32 Gbps, Dual Channel, Advanced Linear Equalizer HMC6545 Data Sheet 25 VCC0 26 REGSEL0 27 REGSEL1 28 RST T/2 T/2 T/2 T/2 c0 c1 c2 cn 24 GND 23 OUTP0 AGC 22 OUTN0 INN0 3 LPF 20 GND SERIAL CONTROL REGISTERS 19 OUTP1 AGC INN1 7 LPF T/2 T/2 T/2 T/2 d0 d1 d2 dn 18 OUTN1 17 GND PACKAGE BASE GND 13393-001 VCC1 16 SVCC 15 COMPP1 11 VCC1 10 CAGC1 9 SCL 14 APPLICATIONS SDA 13 INP1 6 21 GND GND 5 COMPN1 12 GND 4 GND 8 40 Gbps/100 Gbps DQPSK direct detection receivers Short and long reach CFP2 and QSFP+ modules CEI-28G MR and CEI-25G LR 100 GE line cards 16 Gbps and 32 Gbps Fibre Channel Infiniband 14 Gbps FDR and 28 Gbps EDR rates Signal conditioning for backplane and line cards Broadband test and measurement equipment 29 COMPN0 HMC6545 GND 1 INP0 2 30 COMPP0 31 VCC0 FUNCTIONAL BLOCK DIAGRAM Supports data rates from dc up to 32 Gbps Protocol and data rate agnostic Low latency (<170 ps) Integrated AGC with differential sensitivity of <50 mV Up to 20 dB programmable multiple unit interval input equalization Extended chromatic and polarization mode dispersion tolerance Programmable differential output amplitude control of up to 600 mV Single 3.3 V supply eliminating external regulators Wide temperature range from -40C to +95C 5 mm x 5 mm, 32-lead LFCSP package 32 CAGC0 FEATURES Figure 1. GENERAL DESCRIPTION The HMC6545 is a low power, high performance, fully programmable, dual-channel, asynchronous advanced linear equalizer that operates at data rates of up to 32 Gbps. The HMC6545 is protocol and data rate agnostic, and it can operate on the transmit path to predistort a transmitted signal to invert channel distortion or on the receiver path to equalize the distorted and attenuated received signal. The HMC6545 is effective in dealing with chromatic and polarization mode dispersion and intersymbol interference (ISI) caused by a wide variety of transmission media (backplane or fiber) and channel lengths. The HMC6545 consists of an automatic gain control (AGC); dc offset correction circuitry; a 9-tap, 18 ps spaced feedforward equalizer (FFE); a summing node; and a linear programmable output driver. The input AGC linearly attenuates or amplifies the distorted input signal to generate a constant voltage at the Rev. B input of the FFE. The 9-tap FFE is programmed via 2-wire interface to generate wide range frequency responses that are precursor or postcursor in nature for compensating signal impairments. After FFE tap coefficients are summed at the summing node, the signal is received by a linear output driver. DC offset correction circuitry is controlled either automatically or manually via Forward Error Correction (FEC). All high speed differential inputs and outputs of the HMC6545 are current mode logic (CML) and terminated on chip with 50 to the positive supply, 3.3 V, and can be dc-coupled or ac-coupled. The inputs and outputs of the HMC6545 can be operated either differentially or single-ended. The low power, high performance, and feature rich HMC6545 is packaged in a 5 mm x 5 mm, 32-lead LFCSP package. The device uses a single 3.3 V supply, eliminating external regulators. The HMC6545 operates over a -40C to +95C temperature range. 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Technical Support www.analog.com HMC6545 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................8 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 11 Functional Block Diagram .............................................................. 1 Input Receiver ............................................................................. 11 General Description ......................................................................... 1 FFE Delay Line ........................................................................... 11 Revision History ............................................................................... 2 Output Driver ............................................................................. 12 Specifications..................................................................................... 3 2-Wire Serial Port....................................................................... 12 DC Electrical Characteristics ...................................................... 3 Register Map ................................................................................... 15 AC Electrical Characteristics ...................................................... 3 Register List Summary and Register Descriptions ................ 15 Absolute Maximum Ratings............................................................ 5 Evaluation Printed Circuit Board (PCB) ..................................... 21 ESD Caution .................................................................................. 5 Evaluation Kit Contents ............................................................ 21 Pin Configuration and Function Descriptions ............................. 6 Outline Dimensions ....................................................................... 23 Interface Schematics..................................................................... 7 Ordering Guide .......................................................................... 23 REVISION HISTORY 6/2016--Rev. A to Rev. B Changes to Table 6 .......................................................................... 12 Changes to Table 13 ........................................................................ 15 Changes to Figure 35 ...................................................................... 22 10/2015--Revision A: Initial Version Rev. B | Page 2 of 23 Data Sheet HMC6545 SPECIFICATIONS DC ELECTRICAL CHARACTERISTICS Unless otherwise noted, typical values at VCC = 3.3 V, TA = 25C. Table 1. Parameter POWER CONSUMPTION Supply Voltage Supply Current Power-Down Supply Current DC Offset Correction Automatic Manual CML INPUT PORT (INP0, INN0, INP1, INN1) Input Termination CML OUTPUT PORT (OUTP0, OUTN0, OUTP1, OUTN1) Output Termination Output Level High Output CMOS INPUT (SDA, SCL, RST, REGSEL0, REGSEL1) Input Voltage Level High Input Input Current Symbol Test Conditions/Comments VCC ICCMAX ICCMIN Single channel; all tap amplifiers active Single channel; single-tap amplifier active Min Typ Max Unit 3.00 3.30 130 93 17 3.45 150 V mA mA mA +60 +60 mV mV At maximum AGC gain -60 -60 RIN Differential input resistance 80 100 120 ROUT Single-ended output resistance 45 55 65 VCC - 0.5 V V 0.8 +100 V V A VOH VOL VCC VIH VIL IIL, IIH VCC - 1.3 VIL = 0 V or VIH = VCC -100 AC ELECTRICAL CHARACTERISTICS Unless otherwise noted, typical values at VCC = 3.3 V, TA = 25C. Table 2. Parameter INPUT Data Rate Range Input Equalization DIFFERENTIAL AMPLITUDE Input Output Linear AGC Operation Saturated AGC Operation AGC SETTLING TIME FFE Tap Delay Delay Depth Test Conditions/Comments Min Differential input range for linear AGC operation, THD < 5% DC 40 Typ Max Unit 32 880 Gbps mV p-p dB 1600 mV p-p 20 40 Input signal: PRBS 231 - 1 at 100 mV p-p THD < 5%; AGC = 2; all taps enabled, Tap 4 gain = 63, gain of all other taps = 0, predriver gain = 63 AGC = 7 All taps are enabled with maximum gain, predriver gain = 63, AGC = 7 No external capacitor Rev. B | Page 3 of 23 410 mV p-p 600 960 0.5 mV p-p mV p-p s 18 145 ps ps HMC6545 Parameter NOISE CHARACTERISTICS Channel to Channel Isolation Total Harmonic Distortion Output Driver Rise/Fall Time Additive RMS Jitter 1 LATENCY DIFFERENTIAL RETURN LOSS Input Output NUMBER OF TAPS 1 Data Sheet Test Conditions/Comments Min Up to 32 GHz AGC = 2, for differential input voltage 250 mV p-p 20% to 80% Input signal: 28 Gbps, 1010 pattern; all taps enabled, Tap 4 gain = 63, gain of all other taps = 0, predriver gain = 63; AGC = 2 Typ Max 30 Unit 0.4 dB % ps ps 170 ps 5 16 Up to 20 GHz -9 -8 dB dB 9 Additive rms jitter is calculated by JRMS,DUT = ((JTESTED)2 - (JSOURCE)2). Rev. B | Page 4 of 23 Data Sheet HMC6545 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VCC to GND All Pins to GND Operating Ambient Temperature Range Differential Peak-to-Peak Input Voltage Swing Maximum Input Voltage at CML Inputs Maximum Input Voltage at Digital Inputs (SDA, SCL, REGSEL1, REGSEL0, RST) Maximum Peak Reflow Temperature (MSL1)1 Maximum Junction Temperature Continuous Power Dissipation (TA = 85C, Derate 46.59 mW/C Above 85C) Thermal Resistance (Junction to EPAD) ESD Sensitivity, Human Body Model (HBM) 1 Rating -0.6 V to +3.6 V -0.3 V to VCC + 0.3 V -40C to +95C 1.6 V p-p VCC + 0.6 V VCC + 0.6 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 260C 125C 1.86 W 21.46C/W Class 1C See the Ordering Guide section. Rev. B | Page 5 of 23 HMC6545 Data Sheet 25 VCC0 26 REGSEL0 GND 1 24 GND INP0 2 23 OUTP0 INN0 3 22 OUTN0 HMC6545 GND 4 21 GND TOP VIEW (Not to Scale) GND 5 20 GND VCC1 16 SVCC 15 SCL 14 SDA 13 COMPN1 12 17 GND COMPP1 11 18 OUTN1 GND 8 VCC1 10 19 OUTP1 INN1 7 CAGC1 9 INP1 6 NOTES 1. EXPOSED PAD. EXPOSED PAD MUST BE CONNECTED TO RF/DC GROUND. PACKAGE BASE GND 13393-033 27 REGSEL1 28 RST 29 COMPN0 30 COMPP0 31 VCC0 32 CAGC0 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin Number 1, 4, 5, 8, 17, 20, 21, 24 2, 3 6, 7 9, 32 10, 16 11, 12 13 14 15 18, 19 22, 23 25, 31 29, 30 26, 27 28 Mnemonic GND INP0, INN0 INP1, INN1 CAGC1, CAGC0 VCC1 COMPP1, COMPN1 SDA SCL SVCC OUTN1, OUTP1 OUTN0, OUTP0 VCC0 COMPN0, COMPP0 REGSEL0, REGSEL1 RST EPAD Description Ground. This pin and the package base must be connected to RF and dc ground. Differential CML Inputs, Channel 0. Differential CML Inputs, Channel 1. External Capacitor for AGC Bandwidth. Power Supplies for Channel 1. External Capacitors to Cancel DC Offset, Channel 1. 2-Wire Digital Data. 2-Wire Digital Clock. Power Supply for Digital Circuitry and Bias. Differential CML Data Outputs, Channel 1. Differential CML Data Outputs, Channel 0. Power Supplies for Channel 0. External Capacitors to Cancel DC Offset, Channel 0. Default Coefficient Selection for Channel and 2-Wire Interface Device Address. Reset for 2-Wire Interface. Exposed Pad. The exposed pad must be connected to RF/dc ground. Rev. B | Page 6 of 23 Data Sheet HMC6545 INTERFACE SCHEMATICS VCC0, VCC1 VCC0, VCC1 13393-002 GND COMPN0, COMPN1 13393-005 COMPP0, COMPP1 Figure 6. COMPPx, COMPNx Interface Schematic Figure 3. GND Interface Schematic VCC0, VCC1 VCC0, VCC1 INP0, INP1 VCC0, VCC1 SDA/SCL 100 13393-003 13393-006 INN0, INN1 Figure 4. INPx, INNx Interface Schematic Figure 7. SDA, SCL Interface Schematic VCC0, VCC1 50 VCC0, VCC1 OUTP0, OUTP1 CAGC0, CAGC1 VCC0, VCC1 50 13393-007 13393-004 OUTN0, OUTN1 Figure 5. CAGCx Interface Schematic Figure 8. OUTPx, OUTNx Interface Schematic VCC0, VCC1 13393-008 REGSEL0, REGSEL1 Figure 9. REGSELx Interface Schematic Rev. B | Page 7 of 23 HMC6545 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 150 140 TA = 25C 140 130 3.00V 3.15V 3.30V 3.45V 120 120 IDD (mA) 130 110 110 +95C +25C -40C 100 100 90 90 0 1 2 3 4 5 6 7 8 9 ENABLED TAPS 80 13393-009 80 2 3 4 5 6 7 8 9 Figure 13. Supply Current vs. Enabled Taps Over Temperature 1.0 TA = 25C VCC = 3.3V AGC = 3 PREDRIVER GAIN = 63 250 1 ENABLED TAPS Figure 10. Supply Current (IDD) vs. Enabled Taps Over Supply Voltage 300 0 13393-012 IDD (mA) VCC = 3.3V TA = 25C AGC = 3 PREDRIVER GAIN = 63 0.8 0.6 LINEARITY (V/V) IDD (mA) 0.4 200 CHANNEL 0 CHANNEL 0 + CHANNEL 1 150 0.2 3.00V 3.15V 3.30V 3.45V 0 -0.2 -0.4 100 -0.6 ENABLED TAPS 0.8 63 56 49 42 35 28 21 7 TAP VALUE Figure 11. Supply Current (IDD) vs. Enabled Taps Over Enabled Channels 1.0 14 -1.0 0 9 -7 8 -14 7 -21 6 -28 5 -35 4 -42 3 -49 2 -56 1 -63 0 13393-010 50 13393-013 -0.8 Figure 14. Normalized Linearity vs. Tap Value Over Supply Voltage, Tap 4 Value Is Varied, While Others Are Enabled with No Gain 12 VCC = 3.3V AGC = 3 PREDRIVER GAIN = 63 10 0.6 TA = 25C AGC = 2 PREDRIVER GAIN = 63 8 0.2 THD (%) LINEARITY (V/V) 0.4 0 -0.2 +95C +25C -40C -0.4 3.15V 3.30V 3.45V 6 4 -0.6 63 56 49 42 35 28 0 25 13393-011 TAP VALUE 21 7 14 0 -7 -14 -21 -28 -35 -42 -49 -56 -63 -1.0 Figure 12. Normalized Linearity vs. Tap Value Over Temperature, Tap 4 Value Is Varied, While Others Are Enabled with No Gain 75 125 175 225 275 325 375 425 475 525 575 625 DIFFERENTIAL INPUT AMPLITUDE (mV p-p) 13393-014 2 -0.8 Figure 15. THD vs. Differential Input Amplitude Over Supply Voltage, Tap 4 Gain Is Set to +63, While Others are Enabled with No Gain Rev. B | Page 8 of 23 Data Sheet 12 HMC6545 12 VCC = 3.3V AGC = 2 PREDRIVER GAIN = 63 10 10 8 +95C +25C -40C 4 2 75 125 175 225 275 325 375 425 475 525 575 625 DIFFERENTIAL INPUT AMPLITUDE (mV p-p) Figure 16. THD vs. Differential Input Amplitude Over Temperature, Tap 4 Gain Is Set to Maximum Gain, While Others Are Enabled with No Gain 7 4 3 2 0 7 14 21 28 35 42 49 56 63 PREDRIVER GAIN Figure 17. THD vs. Predriver Gain, Tap 4 Gain Is Set to Maximum Gain, While Others Are Enabled with No Gain 20 700 600 500 400 AGC = 0 AGC = 4 AGC = 7 300 200 100 0 7 14 21 28 35 42 49 56 63 PREDRIVER GAIN SETTING Figure 20. Differential Output Amplitude vs. Predriver Gain Over AGC, Input Signal: Differential PRBS 231 - 1, 10 Gbps at 500 mV p-p 0 TA = 25C VCC = 3.3V 16 TA = 25C VCC = 3.3V AGC = 4 PREDRIVER GAIN = 7 TAP 0 = -3 TAP 1 = -8 TAP 2 = -4 TAP 3 = +63 TAP 4 = +63 TAP 5 = +57 TAP 6 = +18 TAP 7 = -41 TAP 8 = -35 800 0 13393-016 1 125 175 225 275 325 375 425 475 525 575 625 Figure 19. THD vs. Differential Input Amplitude Over AGC Value, Tap 4 Gain Is Set to Maximum Gain, While Others Are Enabled with No Gain DIFFERENTIAL OUTPUT AMPLITUDE (mV p-p) THD (%) 5 75 DIFFERENTIAL INPUT AMPLITUDE (mV p-p) 900 TA = 25C VCC = 3.3V AGC = 2 6 TA = 25C VCC = 3.3V PREDRIVER GAIN = 63 0 25 13393-015 0 25 TA = 25C VCC = 3.3V -5 INPUT RETURN LOSS (dB) 12 SMALL SIGNAL GAIN (dB) AGC = 2 AGC = 3 4 2 0 6 13393-019 6 13393-018 THD (%) THD (%) 8 8 4 TAP 0 TAP 1 TAP 2 TAP 3 TAP 4 TAP 5 TAP 6 TAP 7 TAP 8 0 -4 -8 -12 -10 -15 -20 -25 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 FREQUENCY (GHz) Figure 18. Small Signal Gain Over Taps, for S21 Line of Each Tap, Relevant Tap Is Set to Maximum Gain While Remaining Taps Are Enabled with No Gain Rev. B | Page 9 of 23 -30 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 FREQUENCY (GHz) Figure 21. Input Return Loss 13393-020 -20 13393-017 -16 HMC6545 Data Sheet 0 TAP 0 TAP 1 TAP 2 TAP 3 TAP 4 TA = 25C VCC = 3.3V -3 +63 -10 +4 -1 TAP 5 = TAP 6 = TAP 7 = TAP 8 = -1 -1 -1 -2 AGC = 4 PREDRIVER GAIN = 63 -10 -15 -25 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 FREQUENCY (GHz) -3 +63 -10 +4 -1 JITTER RMS JITTER p-p RISE TIME FALL TIME TAP 5 = TAP 6 = TAP 7 = TAP 8 = (F1) (F1) (F1) (F1) -1 -1 -1 -2 AGC = 4 PREDRIVER GAIN = 63 CURRENT 944 fS 5.444ps 16.22ps 16.22ps CH3 100mV/DIV MINIMUM 944 fS 5.333ps 18.22ps 16.00ps MAXIMUM 982 fS 5.444ps 18.44ps 18.67ps TIME 10ps/DIV TAP 0 TAP 1 TAP 2 TAP 3 TAP 4 TOTAL MEAS 94 94 94 94 DELAY 24.1475ns -3 +63 -10 +4 -1 JITTER RMS JITTER p-p RISE TIME FALL TIME TAP 5 = TAP 6 = TAP 7 = TAP 8 = (F1) (F1) (F1) (F1) CH3 100mV/DIV -1 -1 -1 -2 MINIMUM 1.025ps 5.333ps 10.00ps 16.44ps MAXIMUM 1.080ps 5.567ps 17.33ps 17.33ps TIME 10ps/DIV TAP 0 TAP 1 TAP 2 TAP 3 TAP 4 TOTAL MEAS 125 125 125 125 DELAY 24.1112ns MAXIMUM 4.014ps 4.889ps 16.67ps 16.67ps TIME 10ps/DIV -3 +63 -10 +4 -1 TAP 5 = TAP 6 = TAP 7 = TAP 8 = (F1) (F1) (F1) (F1) -1 -1 -1 -2 TOTAL MEAS 236 236 236 236 DELAY 24.2003ns = = = = = -3 +63 -10 +4 -1 JITTER RMS JITTER p-p RISE TIME FALL TIME MINIMUM 994 fS 5.333ps 16.07ps 16.44ps MAXIMUM 1.021ps 5.557ps 17.11ps 17.11ps TIME 10ps/DIV TAP 5 = TAP 6 = TAP 7 = TAP 8 = (F1) (F1) (F1) (F1) CH3 100mV/DIV Figure 24. Typical Output Waveform t 28 Gbps, PRBS 231 - 1 Input Data AGC = 4 PREDRIVER GAIN = 63 CURRENT 1.008ps 5.557ps 17.11ps 16.69ps CH3 100mV/DIV AGC = 4 PREDRIVER GAIN = 63 CURRENT 1.053ps 5.557ps 17.93ps 17.11ps MINIMUM 948 fS 4.000ps 16.22ps 17.78ps TOTAL MEAS 66 66 66 66 DELAY 24.1468ns Figure 26. Typical Output Waveform at 25.8 Gbps, PRBS 231 - 1 Input Data 13393-023 = = = = = = = = = = JITTER RMS JITTER p-p RISE TIME FALL TIME Figure 23. Typical Output Waveform at 22 Gbps, PRBS 231 - 1 Input Data, Input Signal = 300 mV p-p Differential TAP 0 TAP 1 TAP 2 TAP 3 TAP 4 CH3 100mV/DIV 13393-022 = = = = = CURRENT 914 fS 4.880ps 16.22ps 18.22ps Figure 25. Typical Output Waveform at 10 Gbps PRBS 231 - 1 Input Data Figure 22. Output Return Loss TAP 0 TAP 1 TAP 2 TAP 3 TAP 4 (F1) (F1) (F1) (F1) 13393-025 0 13393-021 -30 JITTER RMS JITTER p-p RISE TIME FALL TIME 13393-024 -20 -1 -1 -1 -2 AGC = 4 PREDRIVER GAIN = 63 CURRENT 960 fS 5.557ps 15.78ps 15.56ps MINIMUM 957 fS 5.333ps 15.56ps 15.56ps MAXIMUM 1.036ps 5.557ps 15.78ps 16.08ps TIME 10ps/DIV TOTAL MEAS 100 100 100 100 DELAY 24.0976ns 13393-026 OUTPUT RETURN LOSS (dB) -5 = = = = = Figure 27. Typical Output Waveform at 32 Gbps, PRBS 231 - 1 Input Data Rev. B | Page 10 of 23 Data Sheet HMC6545 THEORY OF OPERATION The HMC6545 advanced linear equalizer has two symmetrical channels, each containing an input AGC, a 9-tap delay chain with each delay tap connected to a variable tap amplifier, a summation node combining the outputs of the tap amplifiers, and an output driver. INPUT RECEIVER AGC The HMC6545 has an integrated AGC that linearly amplifies/ attenuates the input signal, generating a fixed voltage swing level for further processing in the FFE delay line. An input AGC is required both to supply a well defined voltage swing level to the FFE delay line and to control the internal and external (output) voltage swings because the signal path is linear. The AGC has a sensitivity level of 40 mV p-p differential. The HMC6545 processes the input signal linearly at up to a 600 mV p-p differential input voltage level. The AGC loop bandwidth and settling time can be changed using an external capacitor connected to the CAGC0/GND and CAGC1/GND nodes. An internal 2.5 pF capacitor at these nodes sets the default AGC settling time to 0.5 s. The evaluation board includes 1 nF capacitors for both channels. Internal and External Offset Correction Circuitry The input receiver has two modes of offset correction that can be configured by changing the offset settings register via the 2-wire interface: automatic offset correction and manual offset correction (all registers in Table 5 are identical to each other). Table 5. Offset Settings Registers Register Register 0x0A Register 0x2A Register 0x4A Register 0x6A Description Channel 0 Offset Settings, Array A register Channel 0 Offset Settings, Array B register Channel 1 Offset Settings, Array A register Channel 1 Offset Settings, Array B register By default, the input receiver is configured in the automatic offset correction mode, which can correct up to 60 mV of input referred dc offset at the worst case AGC gain (maximum AGC gain with a minimum input signal level). The input referred automatic offset correction range changes depending on the AGC gain and increases up to 180 mV for minimum AGC gain with a maximum signal level at the input of the receiver. Automatic offset correction loop bandwidth is externally set by a series RC network (for each channel, R1/C1 and R2/C2), and it is recommended to keep the component values as shown in the evaluation board schematic (see Figure 35). For Channel 1, Array A, automatic offset correction loop can be disabled by setting Register 0x4A, Bit 6 to 0, which enables the manual offset correction (set Register 0x0A for Channel 0, Array A; Register 0x2A for Channel 0, Array B; and Register 0x6A for Channel 1, Array B; see Table 5). Manual offset correction amount can be adjusted by configuring Register 0x4A, Bits[5:0], where Register 0x4A, Bit 5 defines the sign and Bits[4:0] define the magnitude of gain (see Table 48). Similar to automatic offset correction mode, manual offset correction dynamic range changes with the AGC gain with the total correction being 60 mV for maximum AGC gain, which corresponds to about 2 mV/step (5-bit control) adjustment resolution for maximum AGC gain. For minimum AGC gain, the correction dynamic range increases to 180 mV, and the minimum step for adjustment increases to 6 mV/step. FFE DELAY LINE The FFE delay line receives an input signal from the AGC (with a controlled magnitude), and this signal propagates along a delay line composed of eight delay elements, where each delay element has 18 ps nominal propagation. The delayed signals are then multiplied by programmable coefficients by the tap amplifiers and summed together. One of the taps near the center can be selected as the main tap. The taps that follow are called postcursor taps, and the taps that precede are called precursor taps. By combining different tap values, a wide variety of filter transfer functions can be created that can, for example, compensate for the gain or phase distortion of a lossy channel or the chromatic dispersion of an optical channel. Tap amplifier gains are controlled using the 2-wire interface with five bits of magnitude resolution with positive or negative polarity. To disable a coefficient, set the gain of the particular tap amplifier to 0 (positive gain sign, and 0 gain setting). In addition, the tap amplifier can be powered down to save power, but this may have an impact on the delay and gain of the remaining taps in the delay chain. See Table 14 to Table 22 and Table 38 to Table 46 for Array A tap amplifier settings for Channel 0 and Channel 1, respectively. For Array B tap amplifier settings, see Table 26 to Table 34 and Table 50 to Table 58 for Channel 0 and Channel 1, respectively. Each channel has two sets of tap coefficient register arrays (Channel 0, Array A; Channel 0, Array B; Channel 1, Array A; and Channel 1, Array B) that can be configured through the 2-wire interface. Register 0x00 to Register 0x08 set the tap coefficients of Channel 0, Array A. Register 0x20 to Register 0x28 set the tap coefficients of Channel 0, Array B. Register 0x40 to Register 0x48 set the tap coefficients of Channel 1, Array A. Register 0x60 to Register 0x68 set the tap coefficients of Channel 1, Array B. The REGSEL0 and REGSEL1 pins of the device set the default register array (A or B), determining the tap coefficients of a particular channel. For example, applying REGSEL0 = 0 activates Channel 0, Array A; and REGSEL1 = 0 activates Channel 1, Array A. Applying REGSEL0 = 1 activates Channel 0, Array B; and REGSEL1 = 1 activates Channel 1, Array B. Rev. B | Page 11 of 23 HMC6545 Data Sheet OUTPUT DRIVER 2-WIRE SERIAL PORT After the tap amplifier outputs are summed, the combined signal is received by a linear output driver. The output driver consists of two stages. The first stage is a predriver stage providing controllable signal amplification (6-bit resolution) using Register 0x09 (Channel 0, Array A), Register 0x29 (Channel 0, Array B), Register 0x49 (Channel 1, Array A), and Register 0x69 (Channel 1, Array B). Similar to the tap coefficient registers, each predriver has two registers that can be selected asynchronously by the REGSEL0 and REGSEL1 pins. The register values must be configured through the 2-wire interface prior to the register selection via the REGSEL0 and REGSEL1 pins. To access all of its internal registers, the HMC6545 uses a 2-wire interface, which consists of a serial data line (SDA) and a serial clock line (SCL). Both SDA and SCL are implemented with open-drain input/output pins and are connected to a positive supply voltage via pull-up resistors. See Table 7 to Table 10 for the predriver settings for Channel 0 and Channel 1. The final stage of the output driver is a 50 CML driver stage that provides the specified linearity (according to the THD specification) up to 600 mV p-p differential output swing. The linearity degrades at higher output swings. Typically, a microcontroller, a microprocessor or a digital signal processor acts as a master, controls the bus, and has the responsibility to generate the clock signal and device addresses. The HMC6545 functions as a slave device. The device address on the HMC6545 is 0x38 (default) and set by connecting the REGSEL0 and REGSEL1 pins to either VCC (Logic 1) or GND (Logic 0) and by writing 1 to Register 0x80, Bit 6. If Register 0x80, Bit 6 = 0 (default), the REGSEL0 and REGSEL1 pins select Array A or Array B. If Register 0x80, Bit 6 = 1, the REGSEL0 and REGSEL1 pins also determine the 2-wire interface device address according to Table 6. Table 6. 2-Wire Interface Device Address Setting REGSEL1 0 0 1 1 REGSEL0 0 1 0 1 Address Setting (Register 0x80, Bit 6 = 1) 0x38 (default) 0x3A 0x3C 0x3E Table 7. Register 0x09--Channel 0 Predriver Settings, Array A Register Bits [5:0] [7:6] Type R/W R/W Name Predriver gain Factory set Default 0x30 0b00 Minimum 000000 Maximum 111111 Description Channel 0 predriver gain Not used Maximum 111111 Description Channel 0 predriver gain Not used Maximum 111111 Description Channel 1 predriver gain Not used Maximum 111111 Description Channel 1 predriver gain Not used Table 8. Register 0x29--Channel 0 Predriver Settings, Array B Register Bits [5:0] [7:6] Type R/W R/W Name Predriver gain Factory set Default 0x3F 0b00 Minimum 000000 Table 9. Register 0x49--Channel 1 Predriver Settings, Array A Register Bits [5:0] [7:6] Type R/W R/W Name Predriver gain Factory set Default 0x30 0b00 Minimum 000000 Table 10. Register 0x69--Channel 1 Predriver Settings, Array B Register Bits [5:0] [7:6] Type R/W R/W Name Predriver gain Factory set Default 0x3F 0b00 Minimum 000000 Rev. B | Page 12 of 23 Data Sheet HMC6545 Protocol Table 11 lists the definitions and conditions occurring in a 2-wire data transfer. When all data communication is over for the current transfer cycle, the master indicates the end of data transfer by generating a stop condition. Figure 28 shows a representation of a complete communication cycle on the 2-wire interface. Data Transfer Formats Write Cycle The master generates a start condition to indicate the beginning of a new data transfer. In a write cycle, the master transmitter sends data to the slave receiver. The transfer direction is from master to slave and does not change (see Figure 29). The master generates a start condition followed by a 7-bit slave address and by the R/W bit set to 0. The slave with a matching address replies with an acknowledge. The master then transmits the first byte to the slave device. This first byte is an address of the internal registers of the slave. The slave device replies with an acknowledge bit. For a subsequent read cycle, the master generates a stop bit; otherwise, the master then transmits the next byte, which is a data byte to be stored in the internal slave register previously addressed. This data byte is followed by an acknowledge bit from the slave. This process can continue for multiple bytes, and the slave device increments its internal register address count as it receives subsequent bytes from the master. When all data transfer is over, the master generates a stop condition to end the cycle. The master then starts generating clock pulses on SCL and transmits the first byte on SDA. This first byte always consists of a 7-bit slave address followed by one bit that indicates the read/ write direction (R/W). The device on the bus with a matching address generates an acknowledge. The master continues generating more clock pulses on SCL and, depending on the value of the R/W bit, sends (write operation, R/W = 0) or receives (read operation, R/W = 1) data on SDA. In each case, the receiver must acknowledge the data sent by the transmitter. This sequence of 8-bit data followed by a 1-bit acknowledge can be repeated multiple times. Table 11. 2-Wire Data Transfer Terminology and Definitions Definition A start condition is always generated by the master and is defined as a high to low transition on the SDA line while SCL is high. The bus becomes busy after a start condition. A stop condition is always generated by the master and is defined as a low to high transition on the SDA line while SCL is high. The bus becomes free after the stop condition occurs. Every byte transmitted on SDA must be eight bits long and is transferred with the most significant bit (MSB) first. Each byte must be followed by an acknowledge bit. For data to be considered valid, the SDA line must be stable during the entire high period of its respective clock pulse. For each byte sent or received on the bus, the master generates an extra clock cycle that is used for acknowledgement, for a total of nine bits. The transmitter releases the SDA line, which is pulled high by the external resistor, and the receiver must pull down the SDA line and drive it low while SCL is high during this entire clock cycle to indicate acknowledgment. SDA is left high during this clock cycle to indicate a no acknowledge (NACK) situation, usually because the device addressed is unable to receive or transmit the data requested. Stop Byte Format Data Valid Condition Acknowledge SDA SCL MSB 1 START CONDITION 2 7 ADDRESS 8 9 1 2 R/W ACK 7 DATA 8 9 1 ACK 2 7 DATA 8 9 ACK STOP CONDITION 13393-027 Term Start START SLAVE ADDRESS R/W = 0 FROM MASTER TO SLAVE ACK ADDRESS BYTE ACK DATA BYTE FROM SLAVE TO MASTER Figure 29. Write Cycle Rev. B | Page 13 of 23 ACK DATA BYTE NACK STOP 13393-028 Figure 28. Complete Data Transfer HMC6545 Data Sheet that other device does not respond because there is no preceding start condition. Read Cycle In a read cycle, the master reads from the slave immediately after the first byte. The direction of data transfer changes between master and slave (see Figure 32). In this case, the R/W bit is set to 1 to indicate that the master reads data from the slave device. The address of the internal register from which the data is to come has been previously set in a precedent write cycle; otherwise, the slave device defaults to Address 0x00. This time, the slave device transmits all the data bytes and the master replies with an acknowledge bit. For the last byte read, the master replies with a no acknowledge bit to indicate to the slave that it must stop transmitting data. The master then generates a stop condition, and the cycle ends. In the HMC6545, regardless of whether there is a start condition, if the HMC6545 sees a bit stream that corresponds to its chip address, it then responds and causes unwanted results. There must be only one HMC6545 device on the 2-wire interface bus; otherwise, 2-wire interface bus multiplexers can be used to isolate the HMC6545 devices. See Figure 33 for an example design. Reset A low strobe signal must be sent to the RST pin to reset the registers to their default values. SDA and SCL must be high in the 2-wire interface bus before and after the rising edge. 2-Wire Interface Design Considerations The HMC6545 2-wire interface slave interface responds to any register address or data matching its chip address even when there is no preceding start condition. A 2-wire interface communication is defined as shown in Figure 30. ADDRESS BYTE START CHIP ADDRESS + READ DATA BYTE DATA BYTE STOP STOP RST 0.5s 0.5s 13393-031 CHIP ADDRESS + WRITE SCL 13393-034 START SDA Figure 30. 2-Wire Interface Communication 1.0s Coincidentally, the data or register address can be the same as the chip address of another device on the same bus. However, DATA BYTE ACK DATA BYTE ACK DATA BYTE FROM SLAVE TO MASTER Figure 32. Read Cycle 2-WIRE INTERFACE BUS MASTER 2-WIRE INTERFACE BUS DEMUX CONTROL 2-WIRE INTERFACE BUS HMC6545 HMC6545 OTHER VENDOR SLAVE1 OTHER VENDOR SLAVE2 Figure 33. Multiple HMC6545 Devices on 2-Wire Interface Bus Rev. B | Page 14 of 23 13393-030 FROM MASTER TO SLAVE ACK NACK STOP 13393-029 START SLAVE ADDRESS R/W = 1 Figure 31. Reset Registers Data Sheet HMC6545 REGISTER MAP REGISTER LIST SUMMARY AND REGISTER DESCRIPTIONS Global Register Global register bit order is different for read and write operations. Table 12. Register 0x80--Global Register, Write Operation Bit 7 6 Type W W W W W W Name Factory set 2-wire interface device address read Channel 1 enable Channel 0 enable Factory set Channel 1 reset 5 4 3 2 Default 0 0 1 1 1 1 1 W Channel 0 reset 1 0 W Global reset 1 Description Not used. 2-wire interface device address set. Writing 1 generates a 2-wire interface device address read command. Channel 1 enable. Writing 1 enables Channel 1. Channel 0 enable. Writing 1 enables Channel 0. Not used. Channel 1 soft reset. Writing 0 generates a soft reset, resetting all the registers in Channel 1 to their default states. Writing 1 resumes normal chip operation. Channel 0 soft reset. Writing 0 generates a soft reset, resetting all the registers in Channel 0 to their default states. Writing 1 resumes normal chip operation. Global soft reset. Writing 0 generates a soft reset, resetting all the registers to their default states. Writing 1 resumes normal chip operation. Table 13. Register 0x80--Global Register, Read Operation Bit 7 6 5 4 3 2 1 0 Type R R R R R R R R Name 2-wire interface device address, Bit 1 2-wire interface device address, Bit 0 Channel 1 enable Channel 0 enable Factory set Channel 1 reset Channel 0 reset Global reset Default 0 0 1 1 1 1 1 1 Description Bit 1 of device address Least significant bit of device address Channel 1 enable Channel 0 enable Not used Channel 1 reset Channel 0 reset Global reset Channel 0, Array A Register Set Table 14. Register 0x00--Channel 0, Tap 0 Settings, Array A Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 0 enable Tap 0 gain sign Tap 0 gain Default 1 1 0x00 Description Channel 0 Tap 0 enable. Channel 0 Tap 0 gain sign. 1 means positive, 0 means negative. Channel 0 Tap 0 gain. Table 15. Register 0x01--Channel 0, Tap 1 Settings, Array A Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 1 enable Tap 1 gain sign Tap 1 gain Default 1 1 0x00 Description Channel 0 Tap 1 enable. Channel 0 Tap 1 gain sign. 1 means positive, 0 means negative. Channel 0 Tap 1 gain. Table 16. Register 0x02--Channel 0, Tap 2 Settings, Array A Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 2 enable Tap 2 gain sign Tap 2 gain Default 1 1 0x00 Description Channel 0 Tap 2 enable. Channel 0 Tap 2 gain sign. 1 means positive, 0 means negative. Channel 0 Tap 2 gain. Rev. B | Page 15 of 23 HMC6545 Data Sheet Table 17. Register 0x03--Channel 0, Tap 3 Settings, Array A Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 3 enable Tap 3 gain sign Tap 3 gain Default 1 1 0x00 Description Channel 0 Tap 3 enable. Channel 0 Tap 3 gain sign. 1 means positive, 0 means negative. Channel 0 Tap 3 gain. Table 18. Register 0x04--Channel 0, Tap 4 Settings, Array A Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 4 enable Tap 4 gain sign Tap 4 gain Default 1 1 0x3F Description Channel 0 Tap 4 enable. Channel 0 Tap 4 gain sign. 1 means positive, 0 means negative. Channel 0 Tap 4 gain. Table 19. Register 0x05--Channel 0, Tap 5 Settings, Array A Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 5 enable Tap 5 gain sign Tap 5 gain Default 1 1 0x00 Description Channel 0 Tap 5 enable. Channel 0 Tap 5 gain sign. 1 means positive, 0 means negative. Channel 0 Tap 5 gain. Table 20. Register 0x06--Channel 0, Tap 6 Settings, Array A Register Bit [5:0] 6 7 Type R/W R/W R/W Name Tap 6 gain Tap 6 gain sign Tap 6 enable Default 0x00 1 1 Description Channel 0 Tap 6 gain. Channel 0 Tap 6 gain sign. 1 means positive, 0 means negative. Channel 0 Tap 6 enable. Table 21. Register 0x07--Channel 0, Tap 7 Settings, Array A Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 7 enable Tap 7 gain sign Tap 7 gain Default 1 1 0x00 Description Channel 0 Tap 7 enable. Channel 0 Tap 7 gain sign. 1 means positive, 0 means negative. Channel 0 Tap 7 gain. Table 22. Register 0x08--Channel 0, Tap 8 Settings, Array A Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 8 enable Tap 8 gain sign Tap 8 gain Default 1 1 0x00 Description Channel 0 Tap 8 enable. Channel 0 Tap 8 gain sign. 1 means positive, 0 means negative. Channel 0 Tap 8 gain. Table 23. Register 0x09--Channel 0 Predriver Settings, Array A Register Bit [7:6] [5:0] Type R/W R/W Name Factory set Predriver gain Default 0b00 0x30 Description Not used Channel 0 predriver gain Table 24. Register 0x0A--Channel 0 Offset Settings, Array A Register Bit 7 6 5 [4:0] Type R/W R/W R/W R/W Name Factory set Automatic offset enable Manual offset sign Manual offset gain Default 0 1 0 0x00 Description Not used Channel 0 automatic offset enable Channel 0 manual offset sign Channel 0 manual offset gain Table 25. Register 0x0B--Channel 0 Internal AGC Amplitude, Array A Register Bit [7:3] [2:0] Type R/W R/W Name Factory set Internal AGC amplitude Default 0x00 0b100 Rev. B | Page 16 of 23 Description Not used Internal AGC amplitude Data Sheet HMC6545 Channel 0, Array B Register Set Table 26. Register 0x20--Channel 0, Tap 0 Settings, Array B Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 0 enable Tap 0 gain sign Tap 0 gain Default 1 1 0x00 Description Channel 0 Tap 0 enable. Channel 0 Tap 0 gain sign. 1 means positive, 0 means negative. Channel 0 Tap 0 gain. Table 27. Register 0x21--Channel 0, Tap 1 Settings, Array B Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 1 enable Tap 1 gain sign Tap 1 gain Default 1 0 0x04 Description Channel 0 Tap 1 enable. Channel 0 Tap 1 gain sign. 1 means positive, 0 means negative. Channel 0 Tap 1 gain. Table 28. Register 0x22--Channel 0, Tap 2 Settings, Array B Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 2 enable Tap 2 gain sign Tap 2 gain Default 1 1 0x3F Description Channel 0 Tap 2 enable. Channel 0 Tap 2 gain sign. 1 means positive, 0 means negative. Channel 0 Tap 2 gain. Table 29. Register 0x23--Channel 0, Tap 3 Settings, Array B Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 3 enable Tap 3 gain sign Tap 3 gain Default 1 0 0x28 Description Channel 0 Tap 3 enable. Channel 0 Tap 3 gain sign. 1 means positive, 0 means negative. Channel 0 Tap 3 gain. Table 30. Register 0x24--Channel 0, Tap 4 Settings, Array B Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 4 enable Tap 4 gain sign Tap 4 gain Default 1 0 0x04 Description Channel 0 Tap 4 enable. Channel 0 Tap 4 gain sign. 1 means positive, 0 means negative. Channel 0 Tap 4 gain. Table 31. Register 0x25--Channel 0, Tap 5 Settings, Array B Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 5 enable Tap 5 gain sign Tap 5 gain Default 1 1 0x00 Description Channel 0 Tap 5 enable. Channel 0 Tap 5 gain sign. 1 means positive, 0 means negative. Channel 0 Tap 5 gain. Table 32. Register 0x26, Channel 0, Tap 6 Settings, Array B Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 6 enable Tap 6 gain sign Tap 6 gain Default 1 1 0x00 Description Channel 0 Tap 6 enable. Channel 0 Tap 6 gain sign. 1 means positive, 0 means negative. Channel 0 Tap 6 gain. Table 33. Register 0x27--Channel 0, Tap 7 Settings, Array B Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 7 enable Tap 7 gain sign Tap 7 gain Default 1 1 0x00 Description Channel 0 Tap 7 enable. Channel 0 Tap 7 gain sign. 1 means positive, 0 means negative. Channel 0 Tap 7 gain. Table 34. Register 0x28--Channel 0, Tap 8 Settings, Array B Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 8 enable Tap 8 gain sign Tap 8 gain Default 1 1 0x00 Description Channel 0 Tap 8 enable. Channel 0 Tap 8 gain sign. 1 means positive, 0 means negative. Channel 0 Tap 8 gain. Rev. B | Page 17 of 23 HMC6545 Data Sheet Table 35. Register 0x29--Channel 0 Predriver Settings, Array B Register Bit [7:6] [5:0] Type R/W R/W Name Factory set Predriver gain Default 0b00 0x3F Description Not used Channel 0 predriver gain Table 36. Register 0x2A--Channel 0 Offset Settings, Array B Register Bit 7 6 5 [4:0] Type R/W R/W R/W R/W Name Factory set Automatic offset enable Manual offset sign Manual offset gain Default 0 1 0 0x00 Description Not used Channel 0 automatic offset enable Channel 0 manual offset sign Channel 0 manual offset gain Table 37. Register 0x2B--Channel 0 Internal AGC Amplitude, Array B Register Bit [7:3] [2:0] Type R/W R/W Name Factory set Internal AGC amplitude Default 0x00 0b100 Description Not used Internal AGC amplitude Channel 1, Array A Register Set Table 38. Register 0x40--Channel 1, Tap 0 Settings, Array A Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 0 enable Tap 0 gain sign Tap 0 gain Default 1 1 0x00 Description Channel 1 Tap 0 enable. Channel 1 Tap 0 gain sign. 1 means positive, 0 means negative. Channel 1 Tap 0 gain. Table 39. Register 0x41--Channel 1, Tap 1 Settings, Array A Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 1 enable Tap 1 gain sign Tap 1 gain Default 1 1 0x00 Description Channel 1 Tap 1 enable. Channel 1 Tap 1 gain sign. 1 means positive, 0 means negative. Channel 1 Tap 1 gain. Table 40. Register 0x42--Channel 1, Tap 2 Settings, Array A Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 2 enable Tap 2 gain sign Tap 2 gain Default 1 1 0x00 Description Channel 1 Tap 2 enable. Channel 1 Tap 2 gain sign. 1 means positive, 0 means negative. Channel 1 Tap 2 gain. Table 41. Register 0x43--Channel 1, Tap 3 Settings, Array A Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 3 enable Tap 3 gain sign Tap 3 gain Default 1 1 0x00 Description Channel 1 Tap 3 enable. Channel 1 Tap 3 gain sign. 1 means positive, 0 means negative. Channel 1 Tap 3 gain. Table 42. Register 0x44--Channel 1, Tap 4 Settings, Array A Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 4 enable Tap 4 gain sign Tap 4 gain Default 1 1 0x1F Description Channel 1 Tap 4 enable. Channel 1 Tap 4 gain sign. 1 means positive, 0 means negative. Channel 1 Tap 4 gain. Table 43. Register 0x45--Channel 1, Tap 5 Settings, Array A Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 5 enable Tap 5 gain sign Tap 5 gain Default 1 1 0x00 Description Channel 1 Tap 5 enable. Channel 1 Tap 5 gain sign. 1 means positive, 0 means negative. Channel 1 Tap 5 gain. Rev. B | Page 18 of 23 Data Sheet HMC6545 Table 44. Register 0x46--Channel 1, Tap 6 Settings, Array A Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 6 enable Tap 6 gain sign Tap 6 gain Default 1 1 0x00 Description Channel 1 Tap 6 enable. Channel 1 Tap 6 gain sign. 1 means positive, 0 means negative. Channel 1 Tap 6 gain. Table 45. Register 0x47--Channel 1, Tap 7 Settings, Array A Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 7 enable Tap 7 gain sign Tap 7 gain Default 1 1 0x00 Description Channel 1 Tap 7 enable. Channel 1 Tap 7 gain sign. 1 means positive, 0 means negative. Channel 1 Tap 7 gain. Table 46. Register 0x48--Channel 1, Tap 8 Settings, Array A Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 8 enable Tap 8 gain sign Tap 8 gain Default 1 1 0x00 Description Channel 1 Tap 8 enable. Channel 1 Tap 8 gain sign. 1 means positive, 0 means negative. Channel 1 Tap 8 gain. Table 47. Register 0x49--Channel 1 Predriver Settings, Array A Register Bit [7:6] [5:0] Type R/W R/W Name Factory set Predriver gain Default 0b00 0x30 Description Not used Channel 1 predriver gain Table 48. Register 0x4A--Channel 1 Offset Settings, Array A Register Bit 7 6 5 [4:0] Type R/W R/W R/W R/W Name Factory set Automatic offset enable Manual offset sign Manual offset gain Default 0 1 0 0x00 Description Not used Channel 0 automatic offset enable Channel 0 manual offset sign Channel 0 manual offset gain Table 49. Register 0x4B--Channel 1 Internal AGC Amplitude, Array A Register Bit [7:3] [2:0] Type R/W R/W Name Factory set Internal AGC amplitude Default 0x00 0b100 Description Not used Internal AGC amplitude Channel 1, Array B Register Set Table 50. Register 0x60--Channel 1, Tap 0 Settings, Array B Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 0 enable Tap 0 gain sign Tap 0 gain Default 1 1 0x00 Description Channel 1 Tap 0 enable. Channel 1 Tap 0 gain sign. 1 means positive, 0 means negative. Channel 1 Tap 0 gain. Table 51. Register 0x61--Channel 1, Tap 1 Settings, Array B Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 1 enable Tap 1 gain sign Tap 1 gain Default 1 0 0x04 Description Channel 1 Tap 1 enable. Channel 1 Tap 1 gain sign. 1 means positive, 0 means negative. Channel 1 Tap 1 gain. Table 52. Register 0x62--Channel 1, Tap 2 Settings, Array B Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 2 enable Tap 2 gain sign Tap 2 gain Default 1 1 0x3F Description Channel 1 Tap 2 enable. Channel 1 Tap 2 gain sign. 1 means positive, 0 means negative. Channel 1 Tap 2 gain. Rev. B | Page 19 of 23 HMC6545 Data Sheet Table 53. Register 0x63--Channel 1, Tap 3 Settings, Array B Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 3 enable Tap 3 gain sign Tap 3 gain Default 1 0 0x28 Description Channel 1 Tap 3 enable. Channel 1 Tap 3 gain sign. 1 means positive, 0 means negative. Channel 1 Tap 3 gain. Table 54. Register 0x64--Channel 1, Tap 4 Settings, Array B Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 4 enable Tap 4 gain sign Tap 4 gain Default 1 0 0x04 Description Channel 1 Tap 4 enable. Channel 1 Tap 4 gain sign. 1 means positive, 0 means negative. Channel 1 Tap 4 gain. Table 55. Register 0x65--Channel 1, Tap 5 Settings, Array B Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 5 enable Tap 5 gain sign Tap 5 gain Default 1 1 0x00 Description Channel 1 Tap 5 enable. Channel 1 Tap 5 gain sign. 1 means positive, 0 means negative. Channel 1 Tap 5 gain. Table 56. Register 0x66--Channel 1, Tap 6 Settings, Array B Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 6 enable Tap 6 gain sign Tap 6 gain Default 1 1 0x00 Description Channel 1 Tap 6 enable. Channel 1 Tap 6 gain sign. 1 means positive, 0 means negative. Channel 1 Tap 6 gain. Table 57. Register 0x67--Channel 1, Tap 7 Settings, Array B Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 7 enable Tap 7 gain sign Tap 7 gain Default 1 1 0x00 Description Channel 1 Tap 7 enable. Channel 1 Tap 7 gain sign. 1 means positive, 0 means negative. Channel 1 Tap 7 gain. Table 58. Register 0x68--Channel 1, Tap 8 Settings, Array B Register Bit 7 6 [5:0] Type R/W R/W R/W Name Tap 8 Enable Tap 8 Gain Sign Tap 8 Gain Default 1 1 0x00 Description Channel 1 Tap 8 enable. Channel 1 Tap 8 gain sign. 1 means positive, 0 means negative. Channel 1 Tap 8 gain. Table 59. Register 0x69--Channel 1 Predriver Settings, Array B Register Bit [7:6] [5:0] Type R/W R/W Name Factory set Predriver gain Default 0b00 0x3F Description Not used Channel 1 predriver gain Table 60. Register 0x6A--Channel 1 Offset Settings, Array B Register Bit 7 6 5 [4:0] Type R/W R/W R/W R/W Name Factory set Automatic offset enable Manual offset sign Manual offset gain Default 0 1 0 0x00 Description Not used Channel 1 automatic offset enable Channel 1 manual offset sign Channel 1 manual offset gain Table 61. Register 0x6B--Channel 1 Internal AGC Amplitude, Array B Register Bit [7:3] [2:0] Type R/W R/W Name Factory set Internal AGC amplitude Default 0x00 0b100 Rev. B | Page 20 of 23 Description Not used Internal AGC amplitude Data Sheet HMC6545 EVALUATION PRINTED CIRCUIT BOARD (PCB) J5 J6 J7 J8 SCL +5V C29 GND TP2 C28 C26 TP1 U2 C25 OUTN0 C15 C23 C24 R8 C33 C27 OUTP0 U7 C16 R24 R23 GND C17 R22 C37 R15 U11 C34 C36 40 C18 J10 R16 R17 R12 21 VCC1 R18 VCC0 TP7 C30 +3.3V 3.3V TP6 TP5 TP4 SDA OUTN1 OUTP1 SVCC U4 J9 TP3 20 1 GND SW1 C13 U5 INP0 C14 C20 U6 C19 INN1 INP1 INN0 R13 R11 R14 R10 TP8 VDD1 J1 J2 J3 J4 13393-032 U1 Figure 34. PCB EVALUATION KIT CONTENTS The HMC6545 evaluation PCB kit, EKIT01-HMC6545LP5, includes the following components: The CD-ROM contains user software, an evaluation PCB schematic, and a user manual. To order the evaluation kit, see the Ordering Guide section. 6-foot USB 2.0, Type A male to Type B male cable User software CD-ROM Rev. B | Page 21 of 23 HMC6545 Data Sheet SVCC R1 C1 1k 1nF C22 INN0 J2 C14 INP1 J3 C20 100nF K_SRI-NS INN1 J4 U1 HMC6545 C15 C16 OUTP0 K_SRI-NS OUTP1 VCC1 C17 R2 1k 3.3k C2 1nF 1.69k C4 100pF C3 100nF K_SRI-NS 1. RF TRACES ARE 50 IMPEDANCE: INP0/INP1, INN0/INN1, OUTP0/OUTP1, OUTN0/OUTN1. 2. RF DIFFERENTIAL PAIRS ARE MATCHED LENGTH: INP0/INP1, INN0/INN1, OUTP0/OUTP1, OUTN0/OUTN1. SVCC 100nF PLACE CAPS & L CLOSE TO SVCC PIN ON U1 TP7 K_SRI-NS L3 SVCC C12 100pF 27nH C11 100nF R19 3.3V 0 SCL SDA TP5 C5 100pF 100nF NOTES: R5 TP6 PLACE CAPS CLOSE TO VCC1 PIN 10 ON U1 PLACE CAPS CLOSE TO VCC0 PIN 31 ON U1 C6 100pF J7 K_SRI-NS OUTN1 J8 R6 27nH J11 THRU CAL 100nF PLACE C21 CLOSE TO CAGCB PIN VCC0 C39 THRU_CAL_RFN K_SRI-NS J5 K_SRI-NS OUTN0 J6 100nF C18 1nF L2 100nF 100nF 100nF K_SRI-NS C41 K_SRI-NS 24 GND 23 OUTP0 22 OUTN0 21 GND 20 GND 19 OUTP1 18 OUTN1 17 GND C21 C19 THRU_CAL_RFP 100nF 9 10 11 12 13 14 15 16 K_SRI-NS K_SRI-NS TSM-102-01-L-DV CAGCB VCC1 COMPPB COMPNB SDA SCL SVCC VCC1 100nF J12 100nF R21 0 PLACE CAPS & L CLOSE TO VCC0 PIN 25 ON U1 L1 3.3V VCC1 27nH C10 100pF C9 100pF C8 100pF C7 100pF R20 PLACE CAPS & L CLOSE TO VCC1 PIN 16 ON U1 Figure 35. Evaluation Board Schematic Rev. B | Page 22 of 23 3.3V 0 13393-035 K_SRI-NS C38 J14 1 3 J13 1 GND 2 INP0 3 INN0 4 GND 5 GND 6 INP1 7 INN1 8 GND 100nF J9 CAGCA 32 VCC0 31 COMPPA 30 COMPNA 29 RST 28 RGSEL1 27 RGSEL0 26 VCC0 25 INP0 J1 C13 VCC0 10k R3 C40 2 4 RST PLACE C22 CLOSE TO CAGCA PIN 1nF 10k R4 RGSEL1 RGSEL0 Data Sheet HMC6545 OUTLINE DIMENSIONS PIN 1 INDICATOR 0.30 0.25 0.18 1 24 0.50 BSC 3.80 3.65 SQ 3.50 EXPOSED PAD 17 0.45 0.40 0.35 TOP VIEW 1.00 0.90 0.80 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF PKG-000000 SEATING PLANE PIN 1 INDICATOR 32 25 9 BOTTOM VIEW 3.50 REF 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-4. 03-04-2015-A 5.10 5.00 SQ 4.90 Figure 36.32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm x 5 mm Body and 0.90 mm Package Height (HCP-32-1) Dimensions shown in millimeters ORDERING GUIDE Model HMC6545LP5E Temperature Range -40C to +95C Lead Finish 100% matte Sn MSL Rating1 MSL1 Package Description 32-Lead LFCSP Package Option HCP-32-1 HMC6545LP5ETR -40C to +95C 100% matte Sn MSL1 32-Lead LFCSP HCP-32-1 EKIT01-HMC6545LP5 1 2 Evaluation Kit See the Absolute Maximum Ratings section for additional details. XXXX is the four-digit lot number. (c)2015-2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13393-0-6/16(B) Rev. B | Page 23 of 23 Branding2 H 6545 XXXX H 6545 XXXX