CD54HCT393F3A96 - Texas Instruments

Data sheet acquired from Harris Semiconductor

SCHS186A

Features

• Fully Static Operation

• Buffered Inputs

• Common Reset

• Negative-Edge Clocking

• Typical fMAX = 60 MHz at VCC = 5V, CL = 15pF,

TA = 25oC

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating T emperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at

VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il≤1µA at VOL, VOH

Description

The ’HC393 and ’HCT393 are 4-stage ripple-carry binary

counters. All counter stages are master-slave ﬂip-ﬂops. The

state of the stage advances one count on the negative

transition of each clock pulse; a high voltage level on the MR

line resets all counters to their zero state. All inputs and

outputs are buffered.

Pinout

CD54HC393, CD54HCT393

(CERDIP)

CD74HC393, CD74HCT393

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER TEMP. RANGE

(oC) PACKAGE

CD54HC393F3A -55 to 125 14 Ld CERDIP

CD74HC393E -55 to 125 14 Ld PDIP

CD74HC393M -55 to 125 14 Ld SOIC

CD54HCT393F -55 to 125 14 Ld CERDIP

CD54HCT393F3A -55 to 125 14 Ld CERDIP

CD74HCT393E -55 to 125 14 Ld PDIP

CD74HCT393M -55 to 125 14 Ld SOIC

NOTES:

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

2. Waferor diefor thispart numberis availablewhich meetsall elec-

trical specifications. Please contact your local TI sales office or

customer service for ordering information.

1CP

1MR

1Q0

1Q1

1Q2

1Q3

GND

VCC

2CP

2MR

2Q0

2Q1

2Q2

2Q3

September 1997 - Revised May 2000

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC393,

CD54/74HCT393

High Speed CMOS Logic

Dual 4-Stage Binary Counter

[ /Title

(

CD74

C393

D74

CT39

)

Sub-

ect

(

High

peed

MOS

Functional Diagram

GND = 7

VCC = 14

1Q2

61Q3

1Q1

41Q0

2Q2

82Q3

2Q1

10 2Q0

BINARY

1CP

2CP

COUNTER

1MR 2

2MR

TRUTH TABLE

CP COUNT

OUTPUTS

Q0Q1Q2Q3

0LLLL

1HLLL

2LHLL

3HHLL

4LLHL

5HLHL

6LHHL

7HHHL

8LLLH

9HLLH

10LHLH

11 H H L H

12 L L H H

13 H L H H

14LHHH

15HHHH

CP COUNT MR OUTPUT

↑L No Change

↓L Count

X H L L L L

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,

↑ = Transition from Low to High Level, ↓= Transition from High to Low.

CD54/74HC393, CD54/74HCT393

Logic Diagram

1(13)

2(12)

Q0Q1Q2Q3

3(11) 4(10) 5(9) 6(8)

R R R

ΦΦΦ

Φ Φ Φ

CD54/74HC393, CD54/74HCT393

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, IIK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, IOK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, IO

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input

Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

Low Level Input

Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V

6 - - 1.8 - 1.8 - 1.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output

Voltage

TTL Loads

- - ---- - - -V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

- - ---- - - -V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC or

GND -6--±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 0 6 - - 8 - 80 - 160 µA

CD54/74HC393, CD54/74HCT393

HCT TYPES

High Level Input

Voltage VIH - - 4.5 to

5.5 2--2 - 2 - V

Low Level Input

Voltage VIL - - 4.5 to

5.5 - - 0.8 - 0.8 - 0.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V

High Level Output

Voltage

TTL Loads

-4 4.5 3.98 - - 3.84 - 3.7 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

4 4.5 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC and

GND 0 5.5 - - ±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 0 5.5 - - 8 - 80 - 160 µA

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

∆ICC VCC

-2.1 - 4.5 to

5.5 - 100 360 - 450 - 490 µA

NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) speciﬁcation is 1.8mA.

DC Electrical Speciﬁcations (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

nCP 0.4

nMR 1

NOTE: Unit Load is ∆ICC limit speciﬁed in DC Electrical Table, e.g.,

360µA max at 25oC.

Prerequisite for Switching Speciﬁcations

PARAMETER SYMBOL VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HC TYPES

Maximum Clock

Frequency fMAX 26--5-4-ns

4.5 30 - - 24 - 20 - ns

6 35- -28-24-ns

Clock Pulse Width tW2 80 - - 100 - 120 - ns

4.5 16 - - 20 - 24 - ns

6 14- -17-20-ns

Reset Recovery Time tREC 25--5-5-ns

4.5 5 - - 5 - 5 - ns

65--5-5-ns

CD54/74HC393, CD54/74HCT393

Reset Pulse Width tW2 80 - - 100 - 120 - ns

4.5 16 - - 20 - 24 - ns

6 14- -17-20-ns

HCT TYPES

Maximum Clock

Frequency fMAX 4.5 27 - - 22 - 18 - MHz

Clock Pulse Width tW4.5 19 - - 24 - 29 - ns

Reset Recovery Time tREC 4.5 5 - - 5 - 5 - ns

Reset Pulse Width tW4.5 16 - - 20 - 24 - ns

Switching Speciﬁcations Input tr, tf = 6ns

PARAMETER SYMBOL TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HC TYPES

Propagation Delay Time

(Figure 1) tPLH,

tPHL CL= 50pF 2 - - 45 - 55 - 70 ns

Qn to Qn + 1 4.5 - - 9 - 11 - 14 ns

CL=15pF 5 - 4 - - - - - ns

CL= 50pF 6 - - 8 - 9 - 12 ns

nCP to nQ0tPLH,

tPHL CL= 50pF 2 - - 150 - 190 - 225 ns

4.5 - - 30 - 38 - 59 ns

CL=15pF 5 - 12 - - - - - ns

CL= 50pF 6 - - 26 - 33 - 50 ns

nCP to nQ1tPLH,

tPHL CL= 50pF 2 - - 190 - 245 - 295 ns

4.5 - - 38 - 49 - 59 ns

6 - - 33 - 42 - 50 ns

nCP to nQ2tPLH,

tPHL CL= 50pF 2 - - 240 - 300 - 360 ns

4.5 - - 48 - 60 - 72 ns

6 - - 41 - 51 - 61 ns

nCP to nQ3tPLH,

tPHL CL= 50pF 2 - - 285 - 355 - 430 ns

4.5 - 57 - 71 - 86 ns

6 - - 48 - 60 - 73 ns

MR to QntPLH,

tPHL CL= 50pF 2 - - 135 - 170 - 205 ns

4.5 - - 27 - 34 - 41 ns

CL=15pF 5 - 11 - - - - - ns

CL= 50pF 6 - - 23 - 29 - 35 ns

Output Transition Time

(Figure 1) tTLH,t

THL CL= 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Input Capacitance CIN CL= 50pF - - - 10 - 10 - 10 pF

Power Dissipation Capacitance

(Notes 4, 5) CPD CL=15pF 5 - 20 - - - - - pF

Prerequisite for Switching Speciﬁcations (Continued)

PARAMETER SYMBOL VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

CD54/74HC393, CD54/74HCT393

HCT TYPES

Propagation Delay Time

(Figure 1) tPLH,

tPHL CL= 50pF 4.5 - - 12 - 15 - 18 ns

Qn to Qn + 1 CL=15pF 5 - 4 - - - - - ns

nCP to nQ0tPLH,

tPHL CL= 50pF 4.5 - - 32 - 40 - 48 ns

CL=15pF 5 - 13 - - - - - ns

nCP to nQ1tPLH,

tPHL CL= 50pF 4.5 - - 44 - 55 - 66 ns

nCP to nQ2tPLH,

tPHL CL= 50pF 4.5 - - 50 - 63 - 75 ns

nCP to nQ3tPLH,

tPHL CL= 50pF 4.5 - - 62 - 78 - 93 ns

MR to QntPLH,

tPHL CL= 50pF 4.5 - - 32 - 40 - 48 ns

CL=15pF 5 - 13 - - - - - ns

Output Transition tTLH,t

THL CL= 50pF 4.5 - - 15 - 19 - 22 ns

Input Capacitance CIN CL=15pF - - - 10 - 10 - 10 pF

Power Dissipation Capacitance

(Notes 4, 5) CPD CL=15pF 5 - 21 - - - - - pF

NOTES:

4. CPD is used to determine the dynamic power consumption, per stage.

5. PD = VCC2 fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

Switching Speciﬁcations Input tr, tf = 6ns (Continued)

PARAMETER SYMBOL TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

tPHL tPLH

tTHL tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns tf = 6ns

90%

tPHL tPLH

tTHL tTLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

tr = 6ns tf = 6ns

90%

CD54/74HC393, CD54/74HCT393

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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

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