Élan™SC520 Microcontroller Data Sheet 31
PRELIMINARY
The ROM/Flash controller:
■Reduces system cost by gluelessly interfacing
static m emo ry with up t o thr ee ROM/Flas h chi p s e-
lects
■Suppo rts execute -in- pl ac e (XIP) opera tin g sy st ems
for applications that require ex ecuting out of ROM or
Flash memory instead of DRAM
■Supports high-performance page-mode devices
Flexible Address-Mapping Hardware
In addition to the memory management unit (MMU)
within the Am5x86 CPU core, the ÉlanSC520 micro-
controller provides 16 Programmable Address Region
(PAR) registers that enable flexible placement of mem-
or y (SDRAM, ROM, Flash, SRAM, etc.) and peripher-
als into the two address spaces of the Am5x86 CPU
(memor y a ddress s pace and I/ O ad dress sp ace). The
PAR hardware allows designers to flexibly configure
both addre ss spaces and p lace memor y and/or exter-
nal per ipheral s, as required by the applicat ion. The in-
ternal memory-mapped configuration registers space
can also be remapped to accommodate system re-
quireme nts. PAR registers also al low c ontrol of impor-
tant attributes, such as cacheability, write protection,
and code execution protection for memory resources.
Easy-to-Use GP Bus Inte rface
The ÉlanSC520 microcontroller includes a simple gen-
eral-purpose bus (GP bus) that provides programma-
ble bus timing and allows the connection of 8/16-bit
peri pheral devices and mem or y to the ÉlanSC520 m i-
crocontroller. The GP bus operates at 33 MHz, which
offers good performance at a very low interface cost.
The ÉlanSC520 microcontroller provides up to eight
chip selects for external GP bus devices such as off-
the-shelf I/O peripherals, custom ASICs, and SRAM or
NVRAM. The GP bus interface supports programma-
ble timing and dynam ic bus widt h and c ycle stre tchin g
to accommodate a wide variety of standard peripher-
als, such as UART s, 10-Mbit LAN co ntroller ch ips an d
serial communications controllers. Up to four external
DMA channels provide fly-by DMA transfers between
perip hera l de vic es on t he GP b us and sy stem S DRAM.
Internally, the GP bus is used to provide a complement
of integrated peripherals, such as a DMA controller,
programmable interr upt co ntrol ler, timer s, and UA RTs,
as described in “Integrated Peripherals” on page 31.
These inter nal peripherals are designed to operate at
the full clock rate of the GP bus. The internal peripher-
als can also be configured to operate in PC/AT-compat-
ible configuration, but are generally not restricted to
this config urati on .
The ÉlanSC520 microcontroller provides a wa y to view
accesses to the internal peripherals on the external GP
bus for debugging purposes.
Clock Generation
The ÉlanSC520 microcontroller offers user-config-
urable CPU core clock speed operation at 100 or 133
MHz f or diff erent power/performance points depending
on the applicat ion .
Not all ÉlanSC520 microcontroller devices suppor t all
CPU clock rates. The maximum supported clock rate
for a device is indicat ed by the par t number pri nted on
the package. The clocking circuitry can be pro-
grammed to run the device at higher than the rated
speeds. However, if an ÉlanSC520 microcontroller is
programmed to run at a higher clock speed than that for
which it is rated, th en erroneous ope rati on can result,
and physical damage to the device may occur.
The ÉlanSC520 microcontroller includes on-chip oscilla-
tors and PLLs, as well as most of the required PLL loop
filter components. The ÉlanSC520 microcontroller re-
quires two standard crystals, one for 32.768 kHz and
one for 33 MHz. All the clocks required inside the
ÉlanSC520 microcontroller are generated from these
crystals. The ÉlanSC520 microcontroller also supplies
the clocks for the SDRAM and PCI bus; however, exter-
nal clock bu ffering may be require d in som e syst ems .
Note: The ÉlanSC5 20 micr ocontro ller sup por ts either
a 33.000-MHz or 33.333-MHz crystal. In this docu-
ment, the ge neric ter m “33 MHz” refers to the system
clock derived from whichever 33-MHz crystal fre-
quency is being used in the system.
Integrated Peripherals
The ÉlanSC520 microcontroller is a highly integrated
single-chip CPU with a set of integrated peripherals
that are a superset of common PC/AT peripherals, plus
a set of memor y- mapped p eriphe rals that enh ance its
usability in various applications.
■A programmable interr upt controller (PIC) that pro-
vides the capability to prioritize 22 interrupt levels,
up to 15 o f these being exter nal sources. The PIC
can be programmed to operate in PC/AT-compati-
ble mode, but also contains extended features, in-
cluding support for more sources and flexible
routing that allows any interrupt request to be
steered to a ny P IC in put. In ter r upt req uests c an b e
programmed to generate either non-maskable in-
terrupt (NMI) or maskable interrupt requests.
■An integrate d DMA contr oller is i nclu ded for trans-
ferring data between SDRAM and GP bus peripher-
als. The GP-DMA controller operates in single-cycle
(fly-by) mode for more efficient transfers. The GP-
DMA controller can be programmed for PC/AT com-
patibility, but also contains enhanced features:
– A double buffer-chaining mode provides a more
efficient software interface
– Extended address and transfer counts
– Flexib l e routing of DMA channels