MIC2591B-5YTQ - Micrel Semiconductor, Inc.

August 2004 1 M9999-082004

MIC2591B Micrel

MIC2591B

Dual-Slot PCI Express Hot-Plug Controller

General Description

The MIC2591B is a dual-slot power controller supporting the

power distribution requirements for Peripheral Component

Interconnect Express (PCI Express) Hot-Plug compliant sys-

tems incorporating the Intelligent Platform Management In-

terface (IPMI) Specification v1.0. The MIC2591B provides

complete power control support for two PCI Express slots,

including the 3.3VAUX defined by the PCI Express stan-

dards. Support for 12V, 3.3V, and 3.3VAUX supplies is

provided including programmable constant-current inrush

limiting, voltage supervision, programmable current limit, and

circuit breaker functions. These features provide compre-

hensive system protection and fault isolation. The MIC2591B

also incorporates an SMBus interface via which complete

status of each slot is provided. Data such as voltage and

current from each supply of each slot can be obtained for IPMI

sensor records in addition to the power status of each slot.

All support documentation can be found on Micrel’s web

site at www.micrel.com.

Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

Features

• Supports two independent PCI Express slots

• SMBus interface for slot power control and status

• Voltage-tolerant I/O for compatibility with SMBus 2.0

systems

• 12V, 3.3V, and 3.3VAUX supplies supported per PCI

Express Specification v1.0a

• On-chip circuitry for data collection of each rail output

voltage and output current for both slots

- Integral analog multiplexer and 8-bit ∆Σ ADC

- Compliant to the Intelligent Platform Management

Interface (IPMI) Specification v1.0

- Conversion results available via an SMBus interface

• Programmable inrush current limiting

• Active current regulation controls inrush current

• Electronic circuit breaker for each supply to each slot

• High accuracies for both circuit breaker trip points and

nuisance trip prevention timers

• Dual level fault detection for quick fault response without

nuisance tripping

• Thermal isolation between circuitry for Slot A and Slot B

• Two General Purpose Input pins suitable for interface to

logic and switches.

Applications

• PCI Express v1.0a hot-plug power control

Ordering Information

Part Number 12V and 3V 3.3VAUX Package

Standard Pb-Free Fast-Trip Thresholds Current Limit

MIC2591B – 2BTQ MIC2591B – 2YTQ 100mV 0.375A 48 Pin TQFP

MIC2591B – 3BTQ* MIC2591B – 3YTQ* 150mV 0.375A 48 Pin TQFP

MIC2591B – 5BTQ* MIC2591B – 5YTQ* Disabled 0.375A 48 Pin TQFP

* Contact factory for availability

MIC2591B Micrel

August 2004 2 M9999-082004

Typical Application

System

Power

Supply

PCI Express Connector

+12V

+3.3V

VSTBY

VSTBYBVSTBYA VAUXA

12VINA

12VSENSEA

3VINA

3VSENSEA

12VINB

12VSENSEB

3VINB

3VSENSEB

12VGATEA

12VOUTA

3VGATEA

3VOUTA

3VGATEB

3VOUTB

VAUXB

GND

ONB

ONA

GPI_B0

GPI_A0

/FORCE_ONB

/FORCE_ONA

AUXENB

AUXENA

/INT

SCL

SDA

12VGATEB

12VOUTB

RFILTER[A&B]

CFILTERA

CFILTERB

MIC2591B

22nF *R

12VGATEA

15Ω

Si4435DY

Si4420DY

GATE

22nF

MILLER

6800pF

15Ω

SENSE

0.020Ω

PCI

Express

Bus

3.3AUX

375mA

3.3V

3.0A

12V

2.1A (x4/x8)

SENSE

0.020Ω

22nF *R

12VGATEB

15Ω

Si4435DY

MILLER

6800pF

SENSE

0.013Ω

Si4420DY

GATE

22nF

3VGATEB

SENSE

0.013Ω

PCI Express Connector

PCI

Express

Bus

3.3AUX

375mA

3.3V

3.0A

12V

2.1A (x4/x8)

* Values for R

12VGATE[A/B]

and R

3VGATE[A/B]

may vary

depending upon the CGS of the external MOSFETs.

These components are not required for MIC2591B

operation but can be implemented for GATE output

slew rate control (application specific)

• Bold lines indicate high current paths

11 26

15Ω

3VGATEA

0.1µF 0.1µF

0.1µF

/FAULTB

/FAULTA

/PWRGDB

/PWRGDA

ONB

ONA

AUXENB

AUXENA

/INT

SCL

SDA

110kΩ

Hot-Plug

Controller

SMBus I/O Management

Controller

STBY

10k x 3

10k x 4

SDA

SCL

/INT

SMBus

Base

Address

GPI_B0

100k 100k100k100k

GPI_A0

STBY

/FORCE_ONB

/FORCE_ONA

/FAULTB

/FAULTA

/PWRGDB

/PWRGDA

STBY

10k x 4

IREF

23.2k

August 2004 3 M9999-082004

MIC2591B Micrel

Pin Configuration

48-Pin TQFP

GND

3VOUTA

VAUXA

3VGATEA

3VSENSEA

RFILTER[A&B]

/FAULTA

CFILTERA

12VGATEA

GPI_A0

12VINA

/PWRGDA

12VSENSEA

13 14 15 16 17 18 19 20

/FORCE_ONA

12VOUTA

VSTBYA

3VINA

3VOUTB

VAUXB

3VGATEB

3VSENSEB

21 22 23 24

/FAULTB

CFILTERB

12VGATEB

IREF

12VINB

/PWRGDB

12VSENSEB

/FORCE_ONB

12VOUTB

VSTBYB

3VINB

ONA

AUXENA

GND

SCL

SDA

ONB

AUXENB

48 47 46 45 44 43 42 41

GPI_B0

/INT

40 39 38 37

Hot-Plug

Control

Interface

Slot A

Interface

Slot B

Interface

MIC2591B Micrel

August 2004 4 M9999-082004

Pin Description

Pin Number Pin Name Pin Function

5 12VINA 12V Supply Power and Sense Inputs: Two pins are provided for Kelvin

32 12VINB connection (one for each slot). Pin 5 is the (+) Kelvin-sense connection to

the supply side of the sense resistor for 12V Slot A. Pin 32 is the (+) Kelvin-

sense connection to the supply side of the sense resistor for 12V Slot B.

These two pins must ultimately connect to each other as close as possible at

the MIC2591B controller in order to eliminate any IR drop between these

pins. An undervoltage lockout circuit (UVLO) prevents the switches from

turning on while this input is less than its lockout threshold.

12 3VINA 3.3V Supply Power and Sense Inputs: Two pins are provided for

25 3VINB connection (one for each slot). Pin 12 is the (+) Kelvin-sense connection to

the supply side of the sense resistor for 3V Slot A. Pin 25 is the (+) Kelvin-

sense connection to the supply side of the sense resistor for 3V Slot B.

These two pins must ultimately connect to each other as close as possible at

the MIC2591B controller in order to eliminate any IR drop between these

pins. An undervoltage lockout circuit (UVLO) prevents the switches from

turning on while this input is less than its lockout threshold.

16 3VOUTA 3.3V Power-Good Sense Inputs: Connect to 3.3V[A/B] outputs (i.e., the

21 3VOUTB source terminal of the external power MOSFET). Used to monitor the 3.3V

output voltages for Power-is-Good status.

10 12VOUTA 12V Power-Good Sense Inputs: Connect to 12V[A/B] outputs (i.e., the drain

27 12VOUTB terminal of the external power MOSFET). Used to monitor the12V output

voltages for Power-is-Good status.

8 12VSENSEA 12V Circuit Breaker Sense Inputs: The current limit thresholds are set

29 12VSENSEB by connecting sense resistors between these pins and 12VIN[A/B]. When

the current limit threshold of IR = 50mV is reached, the 12VGATE[A/B] pin

is modulated to maintain a constant voltage across the sense resistor and

therefore a constant current into the load. If the 50mV threshold is exceeded

for tFLT, the circuit breaker is tripped and the GATE pin for the affected

supply’s external MOSFET is immediately pulled high.

13 3VSENSEA 3V Circuit Breaker Sense Inputs: The current limit thresholds are set by

24 3VSENSEB connecting sense resistors between these pins and 3VIN[A/B]. When the

current limit threshold of IR = 50mV is reached, the 3VGATE[A/B] pin is

modulated to maintain a constant voltage across the sense resistor and

therefore a constant current into the load. If the 50mV threshold is exceeded

for tFLT, the circuit breaker is tripped and the GATE pin for the affected

supply’s external MOSFET is immediately pulled low.

3 12VGATEA 12V Gate Drive Outputs: Each pin connects to the gate of an external

34 12VGATEB P-Channel MOSFET. During power-up, the CGATE and the CGS of the

MOSFETs are connected to a 25µA current sink. This controls the value of

dv/dt seen at the source of the MOSFETs.

During current limit events, the voltage at this pin is adjusted to maintain

constant current through the switch for a period of tFLT. Whenever an

overcurrent, thermal shutdown, or input undervoltage fault condition occurs,

the GATE pin for the affected slot is immediately brought high. These pins

are charged by an internal current source during power-down.

14 3VGATEA 3V Gate Drive Outputs: Each pin connects to the gate of an external

23 3VGATEB N-Channel MOSFET. During power-up, the CGATE and the CGS of the

MOSFETs are connected to a 25µA current source. This controls the value

of dv/dt seen at the source of the MOSFETs, and hence the current flowing

into the load capacitance.

During current limit events, the voltage at this pin is adjusted to maintain

constant current through the switch for a period of tFLT. Whenever an

overcurrent, thermal shutdown, or input undervoltage fault condition occurs,

the GATE pin for the affected slot is immediately brought low. During power-

down, these pins are discharged by an internal current source.

33 IREF A resistor connected between this pin and GND sets the ADC current

measurement gain for the VAUX[A/B] outputs. This resistor must be

23.2kΩ±1%.

August 2004 5 M9999-082004

MIC2591B Micrel

Pin Description (continued)

Pin Number Pin Name Pin Function

11 VSTBYA 3.3V Standby Input Voltage: Required to support PCI Express VAUX output.

26 VSTBYB Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]

to ensure that the chip is accessible during standby modes. A UVLO circuit

prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO

threshold. Both pins must be connected together at the MIC2591B controller.

15 VAUXA 3.3VAUX Outputs to PCI Express Card Slots: These outputs connect

22 VAUXB the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal

400mΩ MOSFETs. These outputs are current limited and protected against

short-circuit faults.

44 ONA Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA

43 ONB and MAINB (+3.3V and +12V) outputs. Taking ON[A/B] low after a fault

resets the +12V and/or +3.3V fault latches for the affected slot. Tie these

pins to GND if using SMI power control. Also, see pin description for

/FAULTA and /FAULTB.

45 AUXENA Enable Inputs: Rising-edge triggered. Used to enable or disable the

42 AUXENB VAUX[A/B] outputs. Taking AUXEN[A/B] low after a fault resets the respec-

tive slot’s Aux Output Fault Latch. Tie these pins to GND if using SMI power

control. Also, see pin description for /FAULTA and /FAULTB.

2 CFILTERA Overcurrent Timers: Capacitors connected between these

35 CFILTERB pins and GND set the duration of tFLT. tFLT is the amount of time for which a

slot remains in current limit before its circuit breaker is tripped.

6 /PWRGDA Power-is-Good Outputs: Open-drain, active-low. Asserted when a slot has

31 /PWRGDB been commanded to turn on and has successfully begun delivering power

to its respective +12V, +3.3V, and VAUX outputs. Each pin requires an

external pull-up resistor to VSTBY.

1 /FAULTA Fault Outputs: Open-drain, active-low. Asserted whenever the

36 /FAULTB circuit breaker trips due to a fault condition (overcurrent, input undervoltage,

overtemperature). Each pin requires an external pull-up resistor to VSTBY.

Bringing the slot’s ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B]

was asserted in response to a fault condition on one of the slot’s MAIN

outputs (+12V or +3.3V).

/FAULT[A/B] is reset by bringing the slot’s AUXEN[A/B] pin low if

/FAULT[A/B] was asserted in response to a fault condition on the slot’s

VAUX output. If a fault condition occurred on both the MAIN and VAUX

outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be

brought low to deassert the /FAULT[A/B] output.

9 /FORCE_ONA Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B]

28 /FORCE_ONB input will turn on all three of the respective slot’s outputs (+12V, +3.3V, and

VAUX), while specifically defeating all protections on those supplies. This

explcitly includes all overcurrent and short circuit protections, and on-chip

thermal protection for the VAUX[A/B] supplies. Additionally included are the

UVLO protections for the +3.3V and +12V main supplies. The

/FORCE_ON[A/B] pins do not disable UVLO protection for the VAUX[A/B]

supplies. These input pins are intended for diagnostic purposes only.

Asserting /FORCE_ON[A/B] will cause the respective slot’s /PWRGD[A/B]

and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus

There is a pair of register bits, accessible via the SMBus, which can be set

to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B]

pins -- See CNTRL[A/B] Register Bit D[2].

4 GPI_A0 General Purpose Inputs: The states of these two inputs are available by

38 GPI_B0 reading the Common Status Register, Bits [4:5]. If not used, connect each

pin to GND.

MIC2591B Micrel

August 2004 6 M9999-082004

Pin Description (continued)

Pin Number Pin Name Pin Function

39 A2 SMBus Address Select Pins: Connect to ground or leave open in order to

40 A1 program device SMBus base address. These inputs have internal pull-up

41 A0 resistors to VSTBY[A/B].

48 SDA SMBus Data: Bidirectional SMBus data line.

47 SCL SMBus Clock: Input.

37 /INT Interrupt Output: Open-drain, active-low. Asserted whenever a power fault

is detected if the INTMSK bit (CS Register Bit D[3]) is a logical "0". This

output is cleared by performing an "echo reset" to the appropriate fault bit(s)

in the STAT[A/B] and/or CS registers. This pin requires an external pull-up

resistor to VSTBY.

17 GND 2 Pins, IC Ground Connections: Tie directly to the system’s analog GND

46 plane directly at the device.

20 RFILTER[A&B] Connecting this pin to GND through a 110kΩ, 1% resistor will provide a

significant improvement in timeout duration accuracy for slow overcurrent

faults on Slot A and Slot B. If left floating (NC), overcurrent timeout duration

accuracy is determined by the specification for VFILTER and IFILTER. Please

see the “Circuit Breaker Function” text in the “Functional Description” section

for more detail.

7 NC Reserved: Make no external connections to these pins.

August 2004 7 M9999-082004

MIC2591B Micrel

Absolute Maximum Ratings(1)

Supply Voltages

12VIN[A/B] ................................................................................ 14V

3VIN[A/B], VSTBY[A/B] ............................................... 7V

Any Logic Pin ........................ –0.5V (min) to 3.6V (max)

Output Current (/FAULT[A/B], /INT, SDA).................. 10mA

Power Dissipation .................................... Internally Limited

Lead Temperature

(IR Reflow, Peak Temperature) .......... 240°C +0°C/–5°C

Storage Temperature ............................... –65°C to +150°C

ESD Rating(3)

Human Body Model ................................................... 2kV

Machine Model ........................................................ 200V

Operating Ratings(2)

Supply Voltages

12VIN[A/B] .............................................. 11.0V to 13.0V

3VIN[A/B] .................................................... 3.0V to 3.6V

VSTBY[A/B] ................................................. 3.0V to 3.6V

Ambient Temperature (TA) ............................ 0°C to + 70°C

Junction Temperature (TJ) ........................................ 125°C

Package Thermal Resistance

TQFP (θJA) ....................................................... 56.5°C/W

Electrical Characteristics(4)

12VIN[A/B] = 12V, 3VIN[A/B] = 3.3V, VSTBY[A/B] = 3.3V, TA = 25°C, unless otherwise noted. Bold indicates specification applies over the

full operating temperature range from 0°C to +70°C.

Symbol Parameter Condition Min Typ Max Units

Power Control and Logic Sections

ICC12 Supply Current 2.5 5mA

ICC3.3 0.5 1mA

ICCSTBY 2.5 5mA

Undervoltage Lockout Thresholds

VUVLO(12V) 12VIN[A/B] 12VIN[A/B] increasing 8910 V

VUVLO(3V) 3VIN[A/B] 3VIN[A/B] increasing 2.2 2.5 2.75 V

VUVLO(STBY) VSTBY[A/B] VSTBY[A/B] increasing 2.8 2.9 3.0 V

VHYSUV Undervoltage Lockout Hysteresis 180 mV

12VIN, 3VIN

VHYSSTBY Undervoltage Lockout Hysteresis 50 mV

VSTBY[A/B]

Power-Good Undervoltage Thresholds

VUVTH(12V) 12VOUT[A/B] 12VOUT[A/B] decreasing 10.2 10.5 10.8 V

VUVTH(3V) 3VOUT[A/B] 3VOUT[A/B] decreasing 2.7 2.8 2.9 V

VUVTH(VAUX) VAUX[A/B] VAUX[A/B] decreasing 2.7 2.8 2.9 V

VHYSPG Power-Good Detect Hysteresis 30 mV

VGATE(12V) 12VGATE Voltage 0 1.5 V

IGATE(12VSINK) 12VGATE Sink Current Start Cycle 15 25 35 µA

GATE(12VPULLUP)

12VGATE Pull-up Current (Fault Off) Any fault condition –20 mA

(VDD –VGATE) = 2.5V

VGATE(3V) 3VGATE Voltage

12V

–1.5

12VIN V

GATE(3VCHARGE)

3VGATE Charge Current Start Cycle 15 25 35 µA

IGATE(3VSINK) 3VGATE Sink Current (Fault Off) Any fault condition 40 mA

VGATE = 2.5V

CFILTER[A/B] Overcurrent Delay Time, Pin 20 (RFILTER[A&B]) Floating or NC

VFILTER CFILTER[A/B] Threshold Voltage 1.20 1.25 1.30 V

IFILTER CFILTER[A/B] Charging Current V12VIN – V12VSENSE > VTHILIMIT

Delay ms C F V (V)

FILTER FILTER

FILTER

() ()

()

=µ×

µ×103

and/or

1.80 2.5 5.0 µA

Notes:

1. Exceeding measurements given within the “Absolute Maximum Ratings” section may damage the device.

2. The device is not guaranteed to function outside of the measurements given in the “Operating Ratings" section.

3. Devices are ESD sensitive. Employ proper handling precautions. The human body model is 1.5kΩ in series with 100pF.

4. Specification for packaged product only.

V3VIN – V3VSENSE > VTHILIMIT

MIC2591B Micrel

August 2004 8 M9999-082004

Electrical Characteristics (continued)(5)

Symbol Parameter Condition Min Typ Max Units

CFILTER Overcurrent DelayTime, Pin 20 grounded through RFILTER[A&B] = 110 kΩ, 1%

SF CFILTER Overcurrent Delay V12VIN – V12VSENSE > VTHILIMIT

Scaling Factor and/or 4.4 55.6

Delay(ms) = CFILTER(µF) V3VIN –V3VSENSE > VTHILIMIT

× RFILTER(kΩ) × SF

VTHILIMIT Current Limit Threshold Voltages

12V[A/B] supplies V12VIN – V12VSENSE 45 50 55 mV

3.3V[A/B] supplies V3VIN – V3VSENSE 45 50 55 mV

VTHFAST 12VOUT[A/B] and 3VOUT[A/B] V12VIN – V12VSENSE MIC2591B-2BTQ 90 100 110 mV

Fast-Trip Threshold Voltages V3VIN – V3VSENSE MIC2591B-3BTQ 135 150 165 mV

MIC2591B-5BTQ Disabled

I12VSENSE[A/B] 12VSENSE[A/B] Input current 0.35 µA

I3VSENSE[A/B] 3VSENSE[A/B] Input current 0.35 µA

VIL LOW-Level Input Voltage –0.5 0.8 V

ON[A/B], AUXEN[A/B], GPI_[A0/B0],

/FORCE_ON[A/B]

VOL Output LOW Voltage IOL = 3mA 0.4 V

/FAULT[A/B], /PWRGD[A/B],

/INT, SDA

VIH HIGH-Level Input Voltage 2.1 3.6 V

ON[A/B], AUXEN[A/B], GPI_[A0/B0],

/FORCE_ON[A/B], A[0-2], SCL, SDA

PULLUP(A0 - A2)

Internal Pull-ups from A[0-2] to V

STBY[A/B]

40 kΩ

ILKG,OFF(12VIN[A/B])

12VIN[A/B] Input leakage current VSTBY = VSTBY[A/B] = +3.3V, 1 µA

12VIN[A/B] = OFF; 3VIN[A/B] = OFF

LKG,OFF(3VIN[A/B])

3VIN[A/B] Input leakage current VSTBY = VSTBY[A/B] = +3.3V, 1 µA

3VIN[A/B] = OFF; 12VIN[A/B] = OFF

IIL Input Leakage Current ±5µA

SCL, ON[A/B], AUXEN[A/B],

/FORCE_ON[A/B]

ILKG(OFF) Off-State Leakage Current GPI_[A0/B0]: ILKG for these two pins ±5µA

/FAULT[A/B], /PWRGD[A/B], measured with VAUX OFF

/INT, SDA, GPI_[A0/B0]

TOV Overtemperature Shutdown and Reset TJ increasing, each slot(6) 140 °C

Thresholds, with overcurrent on slot TJ decreasing, each slot(6) 130 °C

Overtemperature Shutdown and TJ increasing, both slots(6) 160 °C

Reset Thresholds, all other conditions TJ decreasing, both slots(6) 150 °C

(all outputs will latch OFF)

RDS(AUX) Output MOSFET Resistance IDS = 375mA, TJ = 125°C400 mΩ

VAUX[A/B] MOSFET

VOFF(VAUX) Off-State Output Offset Voltage VAUX[A/B] = Off, TJ = 125°C50 mV

VAUX[A/B]

Notes:

5. Specification for packaged product only.

6. Parameters guaranteed by design. Not 100% production tested.

August 2004 9 M9999-082004

MIC2591B Micrel

Electrical Characteristics (continued)(7)

Symbol Parameter Condition Min Typ Max Units

IAUX(THRESH) Auxiliary Output Current Limit Current which must be drawn from 0.84 A

Threshold (Figure 4) VAUX to register as a fault

ISC(TRAN) Maximum Transient Short Circuit VAUX Enabled, then Grounded

Current

MAX

STBY[A/B]

DS(AUX)

ILIM(AUX) Regulated Current after Transient From end of ISC(TRAN) to CFILTER time-out 0.375 0.7 1.35 A

Output Discharge Resistance

RDIS(12V) 12VOUT[A/B] 12VOUT[A/B] = 6.0V 1600 Ω

RDIS(3V) 3VOUT[A/B] 3VOUT[A/B] = 1.65V 150 Ω

RDIS(VAUX) 3VAUX[A/B] 3VAUX[A/B] = 1.65V 430 Ω

tOFF(12V) 12V Current Limit Response Time MIC2591B-2BTQ 1 2.0 µs

(Figure 2) CGATE = 25pF

VIN –VSENSE = 140mV

tOFF(3V) 3.3V Current Limit Response Time MIC2591B-2BTQ 1 2.0 µs

(Figure 3) CGATE = 25pF

VIN –VSENSE = 140mV(8)

tSC(TRAN) VAUX[A/B] Current Limit Response VAUX[A/B] = 0V, VSTBYA = VSTBYB = +3.3V 2.5 5µs

Time (Figure 5)

PROP(12VFAULT)

Delay from 12V[A/B] Overcurrent MIC2591B-2BTQ 1 µs

Limit to /FAULT output CFILTER = 0

VIN –VSENSE = 140mV(8)

PROP(3VFAULT)

Delay from 3V[A/B] Overcurrent MIC2591B-2BTQ 1 µs

Limit to /FAULT[A/B] Output CFILTER = 0

VIN –VSENSE = 140mV(8)

PROP(VAUXFAULT)

Delay from VAUX[A/B] Overcurrent MIC2591B-2BTQ 1 µs

limit to /FAULT[A/B] output

CFILTER = 0

VAUX Output Grounded(8)

tWON[A/B], AUXEN[A/B] Pulse Width Note 8 100 ns

tPOR MIC2591B Power-On Reset Time Note 8 250 µs

after VSTBY[A/B] becomes valid

SMBus Timing

t1SCL (clock) period Figure 1 2.5 µs

t2Data In setup time to SCL HIGH Figure 1 100 ns

t3Data Out stable after SCL LOW Figure 1 300 ns

t4Data LOW setup time to SCL LOW Start condition, Figure 1 100 ns

t5Data HIGH hold time after SCL HIGH Stop condition, Figure 1 100 ns

Notes:

7. Specification for packaged product only.

8. Parameters guaranteed by design. Not 100% production tested.

MIC2591B Micrel

August 2004 10 M9999-082004

Electrical Characteristics (continued)(9)

Symbol Parameter Condition Min Typ Max Units

8-Bit Analog to Digital Converter

Max_Error Total unadjusted error for:

Voltage, All Outputs –5 +5 % F.S.

Current, 3VOUT[A/B] and Measured as voltage across –5 +5 % F.S.

12VOUT[A/B] corresponding external RSENSE

Current, VAUX[A/B] 23.2kΩ resistor from IREF (Pin 33) to GND ±5 % F.S.

tCONV Conversion time 60 100 ms

Resolution Specifications

VAUXA Full Scale Voltage 4.00 V

VAUXB LSB of Voltage 15.62 mV

Full Scale Current 375 mA

LSB of Current 1.47 mA

x4/x8 Values

3VOUTA Full Scale Voltage External RSENSE = 13.0mΩ3.85 V

3VOUTB LSB of Voltage 15.0 mV

Full Scale Current 4.23 A

LSB of Current 16.5 mA

12VOUTA Full Scale Voltage External RSENSE = 20.0mΩ13.8 V

12VOUTB LSB of Voltage 53.9 mV

Full Scale Current 2.75 A

LSB of Current 10.7 mA

x16 Values

3VOUTA Full Scale Voltage External RSENSE = 13.0mΩ3.85 V

3VOUTB LSB of Voltage 15.0 mV

Full Scale Current 4.23 A

LSB of Current 16.5 mA

12VOUTA Full Scale Voltage External RSENSE = 10.0mΩ13.8 V

12VOUTB LSB of Voltage 53.9 mV

Full Scale Current 5.5 A

LSB of Current 21.5 mA

Notes:

9. Specification for packaged product only.

August 2004 11 M9999-082004

MIC2591B Micrel

Timing Diagrams

SCL

SDA

Data In

SDA

Data Out

Figure 1. SMBus Timing

12VGATE

VTHFAST

VTHILIMIT

tOFF(12V)

VIN – VSENSE

Figure 2. 12V Current Limit Response Timing

3VGATE

THFAST

THILIMIT

OFF(3V)

– V

SENSE

OV t

Figure 3. 3V Current Limit Response Timing

IOUT(AUX) IOUT(AUX)

ILIM(AUX)

Must Trip

May Not Trip

IAUX(THRESH)

Figure 4. VAUX Current Limit Threshold

OUT(AUX)

SC(TRAN)

LIM(AUX)

SC(TRAN)

Figure 5. VAUX Current Limit Response Timing

MIC2591B Micrel

August 2004 12 M9999-082004

Function Block Diagram

Logic Circuits

VAUX

PWRGD

Thermal

Shutdown

ON/OFF

VAUX Charge

Pump &

MOSFET

VAUX

Overcurrent

Bandgap

Reference

3VIN[A/B]

VREF

MUX &

12 Channel, 8-bit

A/D Converter

VAUX

FULL-SCALE

CURRENT

REFERENCE

DIGITAL CORE/SERIAL INTERFACE

12VIN[A/B]

VREF

12VBIAS

Power-on

Reset

250µs

UVLO

12V

UVLO

ON/OFF

50mV

100mV*

VSTBY(REF)

Current Mirror

RFILTER[A&B]

OPEN PIN

DETECTOR

VREF

IREF

VSTBY(REF)

40kΩ × 3

12VGATE[A/B]

VAUX[A/B]

3VGATE[A/B]

/PWRGD[A/B]

/FAULT[A/B]

3VOUT[A/B]

12VPWRGD

3VPWRGD

12VOUT[A/B]

/INT

IREF

A0A1A2SDASCL

GND

GPI_[A0/B0]

/FORCE_ON[A/B]

RFILTER[A&B]

CFILTER[A/B]

3VIN[A/B]

3VSENSE[A/B]

12VIN[A/B]

12VSENSE[A/B]

ON[A/B] AUX[A/B] VSTBY[A/B]

VSTBY

UVLO

* MIC2591B-3BTQ fast threshold is 150mV

MIC2591B-5BTQ fast threshold is disabled

Contact factory for availabilty

Overcurrent Detection

MIC2591B Block Diagram

August 2004 13 M9999-082004

MIC2591B Micrel

Figure 6. Input Pin Configuration for Disabling HPI/SMI Control

Functional Description

Hot Swap Insertion

When circuit boards are inserted into systems carrying live

supply voltages (“hot-plugged”), high inrush currents often

result due to the charging of bulk capacitance that resides

across the circuit board’s supply pins. This transient inrush

current can cause the system’s supply voltages to tempo-

rarily go out of regulation, causing data loss or system

lock-up. In more extreme cases, the transients occurring

during a hot-plug event may cause permanent damage to

connectors or on-board components.

The MIC2591B addresses these issues by limiting the inrush

currents to the load (PCI Express Board), and thereby con-

trolling the rate at which the load’s circuits turn-on. In addition

to this inrush current control, the MIC2591B offers input and

output voltage supervisory functions and current limiting to

provide robust protection for both the system and circuit

board.

System Interface

The MIC2591B employs two system interfaces: the hardware

Hot-Plug Interface (HPI) and the System Management Inter-

face (SMI). The HPI includes ON[A/B], AUXEN[A/B], as well

as /FAULT[A/B]; the SMI consists of SDA, SCL, and /INT,

whose signals conform to the levels and timing of the SMBus

specification. The MIC2591B can be operated exclusively

from the SMI, or can employ the HPl for power control while

continuing to use the SMI for access to all but the power

control registers.

In addition to the basic power control features of the MIC2591B

accessible by the HPI, the SMI also gives the host access to

the following information from the part:

• Output voltage and current from each supply.

• Fault conditions occurring on each supply.

• GPI_[A0/B0] pin status.

When using the System Management Interface for power

control, do not use the Hot-Plug Interface. Conversely, when

using the Hot-Plug Interface for power control, do not execute

power control commands over the System Management

Interface bus (all other register accesses via the SMI bus

remain permissible while in the HPI control mode). When

utilizing the SMI exclusively, the HPI input pins (ON[A/B],

AUXEN[A/B], and /FORCE_ON[A/B] should be configured

as shown below in Figure 6 (Disabling HPI when SMI control

is used). This configuration safeguards the power slots in the

event that the SMBus communication link is disconnected for

any reason.

Additionally, when utilizing the HPI exclusively, the SMBus

(or SMI) will be inactive if the input pins (SDA, SCL, A0, A1,

and A2) are configured as shown in Figure 6 below (Disabling

SMI when HPI Control is used).

Power-On Reset and Power Cycling

The MIC2591B utilizes VSTBY[A/B] as the main supply input

source. VSTBY[A/B] is required for proper operation of the

MIC2591B’s SMBus and registers and must be applied at all

times. A Power-On Reset (POR) cycle is initiated after

VSTBY[A/B] rises above its UVLO threshold and remains

valid at that voltage for 250µs. All internal registers are

cleared after POR. If VSTBY[A/B] is recycled, the MIC2591B

enters a new power-on-reset cycle. VSTBY must be the first

supply input applied followed by the MAIN supply inputs of

12VIN and 3VIN. The SMBus is ready for access at the end of

the POR cycle (250µs after VSTBY[A/B] is valid). During

tPOR, all outputs remain off. In most applications, the total

POR interval will consist of the time required to charge the

VSTBY input (bypass) capacitance to the UVLO threshold plus

the internal tPOR. The following equation is used to approxi-

mate the total POR interval:

I(A)

POR_TOTAL

STBY ( F) x ULVO(STBY)

CHARGE(STBY)

POR

() ()µ=

(

)

⎡

⎣

⎢

⎤

⎦

⎥

⎧

⎨

⎪

⎩

⎪

⎫

⎬

⎪

⎭

⎪

+µ

µ−

where CSTBY is the VSTBY input bulk bypass capacitance and

ICHARGE(STBY) is the current supplied by the VSTBY source to

charge the capacitance.

Power-Up Cycle

Enabling the GATE output

When a slot's MAIN supplies are off, the 12VGATE pin is held

high with an internal pull-up. Similarly, the 3VGATE pin is

internally held low. When the MAIN supplies of the MIC2591B

are enabled by asserting ON[A/B], the 3VGATE[A/B] and

12VGATE[A/B] pins are each connected to a constant cur-

rent supply. These supplies are each nominally 25µA. For a

slot’s 3VGATE pin, this is a current source; for the 12VGATE

pin, this is a current sink.

MIC2591B

/INT

SDA

SCL

STBY

100k

Disabling SMI when

HPI Control is used

Disabling HPI when

SMI Control is used

100k

INT

/FORCE_ONB

100k 100k

/FORCE_ONA

AUXENA

AUXENB

ONA

ONB

MIC2591B

MIC2591B Micrel

August 2004 14 M9999-082004

Inrush Current and Load Dominated Start-up

The expected maximum inrush current can be calculated by

using the following equation:

INRUSH I C

C25 A C

GATE LOAD

GATE

LOAD

GATE

≅×≅µ×

where ⎪IGATE⎪ is the GATE pin current, IGATE(3VCHARGE)

or IGATE(12VSINK), CLOAD is the load capacitance, and

CGATE is the total GATE capacitance (CISS of the external

MOSFET and any external capacitance connected from

the GATE output pin to the GATE reference – GND or

source).

For the 3.3V outputs and 12V outputs (if no external 12VGATE

output capacitors are implemented), the following equation is

used to determine the output slew rate.

dV dt I

OUT

LIM 3V 12V

LOAD 3V 12V

(/ )

Consequently, the overcurrent timer delay must be pro-

grammed to exceed the time it will take to charge the output

load to the input rail voltage level.

MAIN Outputs (Start-up Delay and Slew-Rate Control)

The 3.3V outputs act as source followers. In this mode of

operation,VSOURCE = [VGATE – VTH(ON)] until the associated

output reaches 3.3V. The voltage on the gate of the MOSFET

will then continue to rise until it reaches 12V, which ensures

minimum RDS(ON). Note that a delay exists between the ON

command to a slot and the appearance of voltage at the slot’s

3.3V output. This delay is the time required to charge the

3VGATE output up to the threshold voltage of the external

MOSFET (typically about 3V).

3VDLY

GATE GS(TH)

GATE(3VCHARGE)

(

)

The source (output) side of the external MOSFET will reach

the drain voltage in a time given by:

3V(SOURCE_DRAIN) 3VDLY

LOAD DRAIN

LIM(3V)

(

)

For the 12V outputs, each MOSFET is configured as a Miller

integrator (by virtue of CMILLER, which is connected between

the MOSFET’s gate and drain). In this configuration, the

feedback action from drain to gate of the MOSFET causes the

voltage at the drain of the MOSFET to slew in a linear fashion

at a rate which satisfies the following equation:

dv / dt(12V) I

GATE

MILLER

=−⎛

⎝

⎜

⎞

⎠

⎟

A delay exists between the ON command to a slot and the

appearance of voltage at the slot’s 12V output. For a slot’s

12V output, that delay is given by the time required for the

capacitor from the gate of the MOSFET to its source (typically

five times the value of CMILLER) to charge to the threshold

voltage of the MOSFET (typically about 3V). In this instance,

the delay before the output voltage starts ramping can be

approximated by:

VDLY

GATE(TOTAL) GS(TH)

GATE

12 ≅

(

)

where CGATE(TOTAL) is the sum of the CGS of the external

MOSFET, any external capacitance from the GATE output of

the MIC2591B to the source of the MOSFET, and CMILLER

(external, if used).

Table 1 approximates the output slew-rate for various values

of CGATE when start-up is dominated by GATE capacitance

(external CGATE from GATE pin to ground plus CGS of the

external MOSFET for the 3.3V rail; CMILLER for the 12V rail).

| IGATE | = 25µA

CGATE or CMILLER dv/dt (load)

0.01µF* 2.5V/ms

0.022µF* 1.136V/ms

0.047µF 0.532 V/ms

0.1µF 0.250V/ms

* Values in this range will be affected by the internal parasitic

capacitances of the MOSFETs used, and should be verified

experimentally.

Table 1. 3.3V and 12V Output Slew-Rate Selection for

Gate Capacitance Dominated Start-up

Power-Down Cycle

When a slot is turned off, resistors internal to the MIC2591B

are connected to each of the outputs to provide a discharge

path for capacitors connected to the part’s outputs. The

nominal output discharge resistance values for each rail are

found in the “Electrical Characteristics” table.

Standby Mode

Standby mode is entered when one or more of the MAIN

supply inputs (12VIN and/or 3VIN) is below its respective

UVLO threshold or OFF. The MIC2591B also supplies

3.3V auxiliary outputs (VAUX[A/B]), satisfying PCI Express

specifications. These outputs are fed via the VSTBY[A/B]

input pins and controlled by the AUXEN[A/B] input pins or

via their respective bits in the Control Registers. These

outputs are independent of the MAIN outputs (12VIN[A/B]

and 3VIN[A/B]). Should the MAIN supply inputs move

below their respective UVLO thresholds, VAUX[A/B] will

still function as long as VSTBY[A/B] is present. Prior to

standby mode, ONA and ONB (or the Control Registers'

MAINA and MAINB bits) inputs should be deasserted or

the MIC2591B will assert /FAULT[A/B] and /INT (if inter-

rupts are enabled) output signals, if an undervoltage

condition on the MAIN supply inputs is detected.

Circuit Breaker Function

The MIC2591B provides an electronic circuit breaker function

that protects against excessive loads, such as short circuits,

at each supply. When the current from one or more of a slot’s

MAIN outputs exceeds the current limit threshold

(ILIM = 50mV/RSENSE) for a duration greater than tFLT, the

circuit breaker is tripped and both MAIN supplies (all outputs

except VAUX[A/B]) are shut off. Should the load current

cause a MAIN output’s VSENSE to exceed VTHFAST, the

outputs are immediately shut off with no delay. Undervoltage

August 2004 15 M9999-082004

MIC2591B Micrel

VSTBY

4.99 k

/PWRGD[A/B]

AUXEN[A/B](1)

ON[A/B]

(1)

FORCE_ON[A/B]

(1)

External pin

(2)

CNTRL[A/B] Register Bit D[0]

(3)

Internal flag

(4)

CNTRL[A/B] Register Bit D[1]

(5)

CNTRL[A/B] Register Bit D[2]

MAIN[A/B]

(4)

VAUX[A/B]

(2)

3VAUX_UV[A/B]

(3)

FORCE_EN[A/B]

(5)

12VOUT_UV[A/B]

(3)

3VOUT_UV[A/B]

(3)

Figure 7. /PWRGD[A/B] Logic Diagram

conditions on the MAIN supply inputs also trip the circuit

breaker, but only when the MAIN outputs are enabled (to

signal a supply input brown-out condition).

The VAUX[A/B] outputs have a different circuit-breaker func-

tion. The VAUX[A/B] circuit breakers do not incorporate a

fast-trip detector, instead they regulate the output current into

a fault to avoid exceeding their operating current limit. The

circuit breaker will trip due to an overcurrent on VAUX[A/B]

when the fault timer expires. This use of the tFLT timer

prevents the circuit breaker from tripping prematurely due to

brief current transients.

Following a fault condition, the outputs can be turned on

again via the ON inputs (if the fault occurred on one of the

MAIN outputs), via the AUXEN inputs (if the fault occurred on

the AUX outputs), or by cycling both ON and AUXEN (if faults

occurred on both the MAIN and AUX outputs). A fault condi-

tion can alternatively be cleared under SMI control of the

ENABLE bits in the CNTRL[A/B] registers (see Register Bits

D[1:0]). When the circuit breaker trips, /FAULT[A/B] will be

asserted if the outputs were enabled through the Hot-Plug

Interface inputs. At the same time, /INT will be asserted

(unless interrupts are masked). Note that /INT is deasserted

by writing a Logic 1 back into the respective fault bit position(s)

in the STAT[A/B] register or the Common Status Register.

The response time (tFLT) of the MIC2591B’s primary overcur-

rent detector is set by external capacitors at the CFILTER[A/B]

pins to GND. For Slot A, CFILTER[A] is located at Pin 2; for

Slot B, CFILTER[B] is located at Pin 35. For a given response

time, the value for CFILTER[A/B] is given by:

tmsIA

VV10

FILTER[A/B]

FLT A B FILTER

FILTER 3

() () ()

()

[/]

µ= ×µ

where tFLT[A/B] is the desired response time and quantities

IFILTER and VFILTER are specified in the MIC2591B’s “Electri-

cal Characteristics” table.

For applications that require a more accurate response time

for a given CFILTER[A/B] tolerance, the MIC2591B employs a

patent-pending technique that improves response time accu-

racy by more than a factor of two. A

110kΩ, 1% resistor connected from the MIC2591B’s

RFILTER[A&B] pin (Pin 20) to GND can be used. In this case,

the value for CFILTER[A/B] for a desired response time (tFLT) is

given by:

tms

RkSF

FILTER[A/B] FLT

FILTER[A/B]

() ()

()

µ= Ω×

where tFLT is the desired response time, RFILTER[A&B] is

110kΩ, and “SF” is the CFILTER[A/B] response time “Scaling

Factor” in the “Electrical Characteristics” table.

Thermal Shutdown

The internal VAUX[A/B] MOSFETs are protected against

damage not only by current limiting, but by dual-mode over-

temperature protection as well. Each slot controller on the

MIC2591B is thermally isolated from the other. Should an

overcurrent condition raise the junction temperature of one

slot’s controller and pass elements to 140°C, all of the outputs

for that slot (including VAUX) will be shut off and the slot’s

/FAULT output will be asserted. The other slot’s operating

MIC2591B Micrel

August 2004 16 M9999-082004

condition will remain unaffected. However, should the

MIC2591B’s die temperature exceed 160°C, both slots (all

outputs, including VAUXA and VAUXB) will be shut off,

whether or not a current limit condition exists. A 160°C

overtemperature condition additionally sets the overtem-

perature bit (OT_INT) in the Common Status Register.

/PWRGD[A/B] Outputs

The MIC2591B has two /PWRGD outputs, one for each slot.

These are open-drain, active-low outputs that require an

external pull-up resistor to VSTBY. Each output is asserted

when a slot has been enabled and has successfully begun

delivering power to its respective +12V, +3.3V, and VAUX

outputs. An equivalent logic diagram for /PWRGD[A/B] is

shown in Figure 7.

/FORCE_ON[A/B] Inputs

These level-sensitive, active-low inputs are provided to facili-

tate designing systems using the MIC2591B. Asserting

/FORCE_ON[A/B] will turn on all three of the respective slot’s

outputs (+12V, +3.3V, and VAUX), while specifically defeat-

ing all protections for those outputs. This explicitly includes all

overcurrent and short circuit protections, and on-chip thermal

protection for the VAUX outputs. Additionally, asserting a

slot’s /FORCE_ON[A/B] input will disable all of its input and

output UVLO protections, with the sole exception of that

asserting either or both of the /FORCE_ON[A/B] inputs will

not disable the VSTBY[A/B] input UVLO.

Asserting /FORCE_ON[A/B] will cause the respective slot’s

/PWRGD[A/B] and /FAULT[A/B] outputs to enter their open-

drain state. Additionally, there are two SMBus accessible

be set to disable the corresponding slot’s /FORCE_ON[A/B]

pins. This allows system software to prevent these hardware

overrides from being inadvertently activated during normal

use. If not used, each pin should be connected to VSTBY using

an external pull-up resistor. See Figure 6 for details.

General Purpose Input (GPI) Pins

Two pins on the MIC2591B are available for use as GPI pins.

The logic state of each of these pins can be determined by

polling Bits [4:5] of Common Status Register. Both of these

inputs are compliant to 3.3V. If unused, connect each

GPI_[A0/B0] pin to GND.

A/D Converter

The MIC2591B has an internal 12-channel, 8-bit A/D con-

verter that monitors the output voltage and current of each

supply. This information is available via the System Manage-

ment Interface. While the information is particularly intended

for use by systems that support the IPMI 1.0 standard, it may

be used for any other desired purpose. A 23.2kΩ external

resistor must be connected from the IREF pin to ground to set

the A/D Converter's Full-Scale current reference for the

VAUX[A/B] internal MOSFETs.

Hot-Plug Interface (HPI)

Once the input supplies are above their respective UVLO

thresholds, the Hot-Plug Interface can be utilized for power

control by enabling the control input pins (AUXEN[A/B] and

ON[A/B]) for each slot. In order for the MIC2591B to switch on

the VAUX supply for either slot, the AUXEN[A/B] control must

be enabled after the power-on-reset delay, tPOR (typically,

250µs), has elapsed. The timing response diagram of Figure

8 illustrates a Hot-Plug Interface operation where an overcur-

rent fault is detected by the MIC2591B controller after initiat-

ing a power-up sequence. The MAIN (+12V & +3.3V) and

VAUX[A/B] supply rails, /FAULT, /PWRGD and /INT output

responses for both AUX and MAIN are shown in the figure.

System Management Interface (SMI)

The MIC2591B’s System Management Interface uses the

Read_Byte and Write_Byte subset of the SMBus protocols to

communicate with its host via the System Management

Interface bus. The /INT output signals the controlling proces-

sor that one or more events need attention, if an interrupt-

driven architecture is used. Note that the MIC2591B does not

participate in the SMBus Alert Response Address (ARA)

portion of the SMBus protocol.

Fault Reporting and Interrupt Generation

SMI-only Control Applications

In applications where the MIC2591B is controlled only by the

SMI, ON[A/B] and AUXEN[A/B] are connected to GND and

the /FORCE_ON[A/B] pins are connected to VSTBY as shown

in Figure 6. In this case, the MIC2591B’s /FAULT[A/B]

outputs and STAT[A/B] Register Bit D[7] (FAULT[A/B]) are

not activated as fault status is determined by polling STAT[A/B]

registers are asserted after power-on-reset when:

• Either or both CNTRL[A/B] Register Bits D[1:0] are

asserted, AND

• 12VIN[A/B], 3VIN[A/B], or VSTBY[A/B] input volt-

age is lower than its respective ULVO threshold,

• The fast OC circuit breaker[A/B] has tripped, OR

• The slow OC circuit breaker[A/B] has tripped AND

its filter timeout has expired, OR

• The slow OC circuit breaker[A/B] has tripped AND

Slot[A/B] die temperature > 140°C, OR

• The MIC2591B’s global die temperature > 160°C

To clear any one or all STAT[A/B] Register Bits D[4], D[2],

D[0] and/or CS Register Bits D[2], D[1] once asserted, a

software subroutine can perform an “echo reset” where a

Logical “1” is written back to those register bit locations that

have indicated a fault. This method of “echo reset” allows

data to be retained in the STAT[A/B] and/or CS registers until

such time as the system is prepared to operate on that data.

The MIC2591B can operate in interrupt mode or polled mode.

For interrupt-mode operation, the open-drain, active-LOW

/INT output signal is activated after power-on-reset if the

INTMSK bit (CS Register Bit D[3]) has been reset to Logical

“0”. Once activated, the /INT output is asserted by any one of

the fault conditions listed above and deasserted when one or

all STAT[A/B] Register Bits D[4], D[2], D[0] and/or CS Regis-

ter Bits D[2], D[1] are reset upon the execution of an SMBus

“echo reset” WRITE_BYTE cycle. For polled-mode opera-

tion, the INTMSK bit should be set to Logical “1,” thereby

inhibiting /INT output pin operation.

August 2004 17 M9999-082004

MIC2591B Micrel

S1000

A2 A1 A0

0A000000XXA

D4D5D6 D3 D2 D1 D0D7

MIC2591B Device Address

DATA

CLK

Command Byte to MIC2591B Data Byte to MIC2591B

START STOP

R/W = WRITE ACKNOWLEDGE ACKNOWLEDGE ACKNOWLEDGE

Master to device transfer,

i.e., DATA driven by master.

Device to master transfer,

i.e., DATA driven by device.

Figure 9. WRITE_BYTE Protocol

S1000A2A1A0 A2A1A00A000000XXAS1 0 100

D4D5D6 D3 D2 D1 D0

/A P

MIC2591B Device Address

DATA

CLK

Command Byte to MIC2591B MIC2591B Device Address Data Read From MIC2591B

START START STOP

R/W = WRITE R/W = READACKNOWLEDGE ACKNOWLEDGE ACKNOWLEDGE NOT ACKNOWLEDGE

Master to device transfer,

i.e., DATA driven by master.

Device to master transfer,

i.e., DATA driven by device.

Figure 10. READ_BYTE Protocol

S1000

A2 A1 A0

D4D5D6 D3 D2 D1 D0D7

/A P

MIC2591B Device Address

DATA

CLK

Byte Read from MIC2591B

START STOP

R/W = READ ACKNOWLEDGE NOT ACKNOWLEDGE

Master to device transfer,

i.e., DATA driven by master.

Device to master transfer,

i.e., DATA driven by device.

Figure 11. RECEIVE_BYTE Protocol

/INT*

/FAULT_[A/B]

3VOUT[A/B]

AUX_OUT[A/B]

VAUX_OUT[A/B]

AUXEN[A/B]

LIM(3V)

STEADY-STATE

ON[A/B]

+3.3V

tPOR

VSTBY

UVLO

tFLT

LIM(AUX)

STEADY-STATE

* /INT de-asserted by software

12VOUT[A/B]

/PWRGD_[A/B]

Figure 8. Hot-Plug Interface Operation

MIC2591B Micrel

August 2004 18 M9999-082004

For those SMI-control applications where the

/FORCE_ON[A/B] inputs are needed for diagnostic pur-

poses, the /FORCE_ON[A/B] inputs must be enabled; that is,

CNTRL[A/B] Register Bit D[2] should read Logical “0.” Once

/FORCE_ON[A/B] inputs are asserted, all output voltages

are present with all circuit protection features disabled, in-

cluding overtemperature protection on VAUX[A/B] outputs.

To inhibit /FORCE_ON[A/B] operation, a Logical “1” shall be

written to the CNTRL[A/B] Register Bit D[2] location(s).

HPI-only Control Applications

In applications where the MIC2591B is controlled only by the

HPI, SMBus signals SCL, SDA, and /INT signals are con-

nected to VSTBY as shown in Figure 6. In this configuration,

the MIC2591B’s /FAULT[A/B] outputs are activated after

power-on-reset and become asserted when:

Either or both external ON[A/B] and AUXEN[A/B] input sig-

nals are asserted, AND

• 12VIN[A/B], 3VIN[A/B], or VSTBY[A/B] input volt-

age is lower than its respective ULVO threshold,

• The fast OC circuit breaker[A/B] has tripped, OR

• The slow OC circuit breaker[A/B] has tripped AND

its filter timeout[A/B] has expired, OR

• The slow OC circuit breaker[A/B] has tripped AND

Slot[A/B] die temperature > 140°C, OR

• The MIC2591B’s global die temperature > 160°C

In order to clear /FAULT[A/B] outputs once asserted, either or

both ON[A/B] and AUXEN[A/B] input signals must be

deasserted. Please see /FAULT[A/B] pin description for

additional information.

If the /FORCE_ON[A/B] inputs are used for diagnostic pur-

poses, both /FAULT[A/B] and /PWRGD[A/B] outputs are

deasserted once /FORCE_ON[A/B] inputs are asserted.

Serial Port Operation

The MIC2591B uses standard SMBus Write_Byte and

Read_Byte operations for communication with its host. The

SMBus Write_Byte operation involves sending the device’s

target address, with the R/W bit (LSB) set to the low (write)

state, followed by a command byte and a data byte. The

SMBus Read_Byte operation is similar, but is a composite

write and read operation: the host first sends the device’s

target address followed by the command byte, as in a write

operation. A new “Start” bit must then be sent to the MIC2591B,

followed by a repeat of the device address with the R/W bit set

to the high (read) state. The data to be read from the part may

then be clocked out. There is one exception to this rule: If the

location latched in the pointer register from the last write

operation is known to be correct (i.e., points to the desired

procedure may be used. To perform a Receive_Byte opera-

tion, the host sends an address byte to select the target

MIC2591B, with the R/W bit set to the high (read) state, and

then retrieves the data byte. Figures 9 through 11 show the

formats for these data read and data write procedures.

The Command Register is eight bits (one byte) wide. This

byte carries the address of the MIC2591B’s register to be

operated upon. The command byte values corresponding to

the various MIC2591B register addresses are shown in Table

2. Command byte values other than 0000 0XXXb = 00h - 07h

are reserved and should not be used.

MIC2591B SMBus Address Configuration

The MIC2591B responds to its own unique SMBus address,

which is assigned using A2, A1, and A0. These represent the

3 LSBs of its 7-bit address, as shown in Table 3. These

address bits are assigned only during power up of the

VSTBY[A/B] supply input. These address bits allow up to

eight MIC2591B devices in a single system. These pins are

either grounded or left unconnected to specify a logical 0 or

logical 1, respectively. A pin designated as a logical 1 may

also be pulled up to VSTBY.

MIC2591B Register Set and Programmer’s Model

Target Register Command Byte Value Power-On

Default

Label Description Read Write

RESULT ADC Conversion Result Register 00hna xxh

ADC_CNTRL ADC Control Register 01h01h00h

CNTRLA Control Register Slot A 02h02h00h

CNTRLB Control Register Slot B 03h03h00h

STATA Slot A Status 04h04h00h

STATB Slot B Status 05h05h00h

CS Common Status Register 06h06hxxxx 0000b

Reserved Reserved / Do Not Use 07h - FFh07h - FFhUndefined

Table 2. MIC2591B Register Addresses

Inputs MIC2591B Device Address

A2 A1 A0 Binary Hex

0 0 0 1000 000X*b80h

0 0 1 1000 001Xb82h

0 1 0 1000 010Xb84h

0 1 1 1000 011Xb86h

1 0 0 1000 100Xb88h

1 0 1 1000 101Xb8Ah

1 1 0 1000 110Xb8Ch

1 1 1 1000 111Xb8Eh

* Where X = '1' for READ and '0' for WRITE

Table 3. MIC2591B SMBus Addressing

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MIC2591B Micrel

Detailed Register Descriptions

Converter Result Register (RESULT)

8-Bits, Read-Only

Conversion Result Register (RESULT)

D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

read-only read-only read-only read-only read-only read-only read-only read-only

Voltage or Current Data from ADC

Bit Function Operation

D[7:0] Measured data from ADC read-only

Power-Up Default Value: xxxx xxxxb = xxh

Read Command Byte: 0000 0000b = 00h

ADC Control Register (ADC_CNTRL)

8-Bits, Read/Write

ADC Control Register (ADC_CNTRL)

D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

read-only read-only read-only read/write read/write read/write read/write read/write

BUSY Reserved Reserved SEL PAR Supply Select

SUP[2:0]

Bit(s) Function Operation

BUSY ADC status 0 = ADC quiescent, 1 = ADC busy

D[6] Reserved Always read as zero

D[5] Reserved Always read as zero

SEL A/D Slot Select Specifies slot for A/D conversion

0 = Slot A, 1 = Slot B

PAR Parameter control bit for ADC conversion 1 = Voltage, 0 = Current

SUP[2:0] Supply select for ADC conversion 000 = No conversion

001 = +3.3V supply

010 = Undefined - Do Not Use

011 = +12V supply

100 = Undefined - Do Not Use

101 = VAUX supply

Power-Up Default Value: 0000 0000b = 00h

Command_Byte Value (R/W): 0000 0001b = 01h

To operate the ADC, the ADC_CNTRL register must be

accessed with the following parameters:

• Selection of which slot will provide the parameter

to be measured (Register Bit D[4])

• Choice of whether voltage or current is to be

reported (Register Bit D[3])

• Selection of the which supply that is to be moni-

tored (Register Bit D[2:0])

Note that this data may all be contained within one write to the

ADC_CNTRL register.

Software must then poll the BUSY bit (D[7]) until it is zero, or

wait for a period of 100ms. At the end of that time, the

RESULT register will contain the results of the conversion.

After reading the RESULT register, a new conversion may be

started.

MIC2591B Micrel

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Control Register, Slot A (CNTRLA)

8-Bits, Read/Write

Control Register, Slot A (CNTRLA)

D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

read-only read-only read only read only read-only read/write read/write read/write

AUXAPG MAINAPG Reserved Reserved Reserved /FORCE_A MAINA VAUXA

ENABLE

Bit(s) Function Operation

AUXAPG AUX output power-good status, Slot A 1 = Power-is-Good

(VAUXA Output is above its UVLO threshold)

MAINAPG MAIN output power-good status, Slot A 1 = Power-is-Good

(MAINA Outputs are above their UVLO

thresholds)

D[5] Reserved Always read as zero

D[4] Reserved Always read as zero

D[3] Reserved Always read as zero

/FORCE_A Allows or inhibits the operation of the /FORCE_ONA 0 = /FORCE_ONA is enabled

ENABLE input pin 1 = /FORCE_ONA is disabled

MAINA MAIN enable control, Slot A 0 = Off, 1 = On

VAUXA VAUX enable control, Slot A 0 = Off, 1 = On

Power-Up Default Value: 0000 0000b = 00h

Read Command_Byte Value (R/W): 0000 0010b = 02h

The power-up default value is 00h. Slot is disabled upon power-up, i.e., all supply outputs are off.

Notes:

1. The state of the /PWRGDA pin is the logical AND of the values of the AUXAPG and the MAINAPG bits, except when /FORCE_ONA is asserted. If

/FORCE_ONA is asserted (the pin is pulled low), and /FORCE_AENABLE is set to a logic zero, the /PWRGDA pin will be unconditionally forced to

its open-drain (“Power Not Good”) state.

2. The values of the MAINAPG and AUXAPG register bits are

not

affected by /FORCE_ONA, but will instead continue to read as high if power is

“Good,” and as low if the conditions which indicate that power is good are not met.

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MIC2591B Micrel

Control Register, Slot B (CNTRLB)

8-Bits, Read/Write

Control Register, Slot B (CNTRLB)

D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

read-only read-only read only read only read-only read/write read/write read/write

AUXBPG MAINBPG Reserved Reserved Reserved /FORCE_B MAINB VAUXB

ENABLE

Bit(s) Function Operation

AUXBPG AUX output power-good status, Slot B 1 = Power-is-Good

(VAUXB Output is above its UVLO threshold)

MAINBPG MAIN output power-good status, Slot B 1 = Power-is-Good

(MAINB Outputs are above their UVLO

thresholds)

D[5] Reserved Always read as zero

D[4] Reserved Always read as zero

D[3] Reserved Always read as zero

/FORCE_B Allows or inhibits the operation of the /FORCE_ONB 0 = /FORCE_ONB is enabled

ENABLE input pin 1 = /FORCE_ONB is disabled

MAINB MAIN enable control, Slot B 0 = Off, 1 = On

VAUXB VAUX enable control, Slot B 0 = Off, 1 = On

Power-Up Default Value: 0000 0000b = 00h

Command_Byte Value (R/W): 0000 0011b = 03h

The power-up default value is 00h. Slot is disabled upon power-up, i.e., all supply outputs are off.

Notes:

1. The state of the /PWRGDB pin is the logical AND of the values of the AUXBPG and the MAINBPG bits, except when /FORCE_ONB is asserted. If /

FORCE_ONB is asserted (the pin is pulled low), and /FORCE_BENABLE is set to a logic zero, the /PWRGDB pin will be unconditionally forced to

its open-drain (“Power Not Good”) state.

2. The values of the MAINBPG and AUXBPG register bits are

not

affected by /FORCE_ONB, but will instead continue to read as high if power is

“Good,” and as low if the conditions which indicate that power is good are not met.

MIC2591B Micrel

August 2004 22 M9999-082004

Status Register Slot A (STATA)

8-Bits, Read-Only

Status Register, Slot A (STATA)

D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

read-only read-only read-only read/write read-only read/write read-only read/write

FAULTA MAINA VAUXA VAUXAF Reserved 12VAF Reserved 3VAF

Bit(s) Function Operation

FAULTA FAULT Status - Slot A 1 = Fault pin asserted

(/FAULTA pin is LOW)

0 = Fault pin deasserted

(/FAULTA pin is HIGH)

See Notes 1, 2, and 3.

MAINA MAIN Enable Status - Slot A Represents the actual state (on/off) of the

two Main Power outputs for Slot A

(+12V and +3.3V)

1 = Main Power ON

0 = Main Power OFF

VAUXA VAUX Enable Status - Slot A Represents the actual state (on/off) of the

Auxiliary Power output for Slot A

1 = AUX Power ON

0 = AUX Power OFF

VAUXAF Overcurrent Fault: VAUXA supply 1 = Fault 0 = No fault

D[3] Reserved Always read as zero

12VAF Overcurrent Fault: +12V supply 1 = Fault 0 = No fault

D[1] Reserved Always read as zero

3VAF Overcurrent Fault: 3.3V supply 1 = Fault 0 = No fault

Power-Up Default Value: 0000 0000b = 00h

Command_Byte Value (R/W): 0000 0100b = 04h

The power-up default value is 00h. Both slots are disabled upon power-up, i.e., all supply outputs are off. In response to an

overcurrent fault condition, writing a logical 1 back into the active (or set) bit position will clear the bit and deassert /INT. The

status of the /FAULTA pin is not affected by reading the Status Register or by clearing active status bits.

Notes:

1. If FAULTA has been set by an overcurrent condition on one or more of the MAIN outputs, the ONA input must go LOW to reset FAULTA.

If FAULTA has been set by a VAUXA overcurrent event, the AUXENA input must go LOW to reset FAULTA.

If an overcurrent has occurred on both a MAIN output and the VAUX output of slot A, both ONA and AUXENA of the slot must go low to reset

FAULTA.

2. Neither the FAULTA bits nor the /FAULTA pins are active when the MIC2591B power paths are controlled by the System Management Interface.

When using SMI power path control, AUXENA and ONA pins for that slot must be tied to GND.

3. If /FORCE_ONA is asserted (low), the /FAULTA pin will be unconditionally forced to its open-drain state. Note, though, that the value in the

FAULTA register bit is not affected by /FORCE_ONA, but will instead continue to read as a high if no faults are present on Slot A, and as a low if

any fault conditions exist which would disable Slot A if /FORCE_ONA was not asserted.

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MIC2591B Micrel

Status Register Slot B (STATB)

8-Bits, Read-Only

Status Register, Slot B (STATB)

D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

read-only read-only read-only read/write read-only read/write read-only read/write

FAULTB MAINB VAUXB VAUXBF Reserved 12VBF Reserved 3VBF

Bit(s) Function Operation

FAULTB FAULT Pin Status - Slot B 1 = Fault pin asserted

(/FAULTB pin is LOW)

0 = Fault pin deasserted

(/FAULTB pin is HIGH)

See Notes 1, 2, and 3.

MAINB MAIN Enable Status - Slot B Represents the actual state (on/off) of the

four Main Power outputs for Slot B

(+12V and +3.3V)

1 = MAIN Power ON

0 = MAIN Power OFF

VAUXB VAUX Enable Status - Slot B Represents the actual state (on/off) of the

Auxiliary Power output for Slot B

1 = AUX Power ON

0 = AUX Power OFF

VAUXBF Overcurrent Fault: VAUXB supply 1 = Fault 0 = No fault

D[3] Reserved Always read as zero

12VBF Overcurrent Fault: +12V supply 1 = Fault 0 = No fault

D[1] Reserved Always read as zero

3VBF Overcurrent Fault: 3.3V supply 1 = Fault 0 = No fault

Power-Up Default Value: 0000 0000b = 00h

Command_Byte Value (R/W): 0000 0101b = 05h

The power-up default value is 00h. Both slots are disabled upon power-up, i.e., all supply outputs are off. In response to an

overcurrent fault condition, writing a logical 1 back into the active (or set) bit position will clear the bit and deassert /INT. The

status of the /FAULTB pin is not affected by reading the Status Register or by clearing active status bits.

Notes:

1. If FAULTB has been set by an overcurrent condition on one or more of the MAIN outputs, the ONB input must go LOW to reset FAULTB.

If FAULTB has been set by a VAUXB overcurrent event, the AUXENB input must go LOW to reset FAULTB.

If an overcurrent has occurred on both a MAIN output and the VAUX output of slot B, both ONB and AUXENB of the slot must go low to reset

FAULTB.

2. Neither the FAULTB bits nor the /FAULTB pins are active when the MIC2591B power paths are controlled by the System Management Interface.

When using SMI power path control, the AUXENB and ONB pins for that slot must be tied to GND.

3:. If /FORCE_ONB is asserted (low), the /FAULTB pin will be unconditionally forced to its open-drain state. Note, though, that the value in the

FAULTB register bit is not affected by /FORCE_ONB, but will instead continue to read as a high if no faults are present on Slot B, and as a low if

any fault conditions exist which would disable Slot B if /FORCE_ONB was not asserted.

MIC2591B Micrel

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Common Status Register (CS)

8-Bits, Read/Write

Common Status Register (CS)

D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

read-write read-write read-only read-only read-write read-write read-write read-only

Reserved Reserved GPI_B0 GPI_A0 INTMSK UV_INT OT_INT Reserved

Bit(s) Function Operation

D[7] Reserved Always read as zero

D[6] Reserved Always read as zero

GPI_B0 General Purpose Input 0, Slot B State of GPI_B0 pin

GPI_A0 General Purpose Input 0, Slot A State of GPI_A0 pin

INTMSK Interrupt Mask 0 = /INT generation is enabled

1 = /INT generation is disabled. The

MIC2591B does not participate in the SMBus

Alert Response Address (ARA) protocol

UV_INT Undervoltage Interrupt 0 = No UVLO fault

1 = UVLO fault

Set whenever a circuit breaker fault condition

occurs as a result of an undervoltage lockout

condition on one of the main supply inputs.

This bit is only set if a UVLO condition occurs

while the ON[A/B] pin is asserted or the

MAIN[A/B] control bits are set

OT_INT Overtemperature Interrupt 0 = Die Temp < 160°C.

1 = Fault: Die Temp > 160°C.

Set if a fault occurs as a result of the

MIC2591B’s die temperature exceeding

160°C

D[0] Reserved Undefined

Power-Up Default Value: 00000000b = 00h

Command_Byte Value (R/W): 00000110b = 06h

To reset the OT_INT and UV_INT fault bits, a logical 1 must be written back to these bits.

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MIC2591B Micrel

Package Information

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TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.

Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

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