Dual High Speed,
Low Noise Op Amp
Data Sheet
AD8022
Rev. C
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FEATURES
Low power amplifiers provide low noise and low distortion,
ideal for xDSL modem receiver
Wide supply range: +5 V, ±2.5 V to ±12 V voltage supply
Low power consumption: 4.0 mA/Amp
Voltage feedback
Ease of Use
Lower total noise (insignificant input current noise
contribution compared to current feedback amps)
Low noise and distortion
2.5 nV/√Hz voltage noise @ 100 kHz
1.2 pA/√Hz current noise
MTPR < −66 dBc (G = +7)
SFDR 110 dB @ 200 kHz
High speed
130 MHz bandwidth (−3 dB), G = +1
Settling time to 0.1%, 68 ns
50 V/μs slew rate
High output swing: ±10.1 V on ±12 V supply
Low offset voltage, 1.5 mV typical
APPLICATIONS
Receiver for ADSL, VDSL, HDSL, and proprietary
xDSL systems
Low noise instrumentation front end
Ultrasound preamps
Active filters
16-bit ADC buffers
FUNCTIONAL BLOCK DIAGRAM
AD8022
1
2
3
4
8
7
6
5
O
UT1
–IN1
+IN1
–V
S
+V
S
OUT2
–IN2
+IN2
01053-001
–
+
–
+
Figure 1.
GENERAL DESCRIPTIONS
The AD8022 consists of two low noise, high speed, voltage
feedback amplifiers. Each amplifier consumes only 4.0 mA of
quiescent current, yet has only 2.5 nV/√Hz of voltage noise.
These dual amplifiers provide wideband, low distortion
performance, with high output current optimized for stability
when driving capacitive loads. Manufactured on ADI’s high
voltage generation of XFCB bipolar process, the AD8022
operates on a wide range of supply voltages. The AD8022 is
available in both an 8-lead MSOP and an 8-lead SOIC. Fast over
voltage recovery and wide bandwidth make the AD8022 ideal as
the receive channel front end to an ADSL, VDSL, or proprietary
xDSL transceiver design.
In an xDSL line interface circuit, the AD8022’s op amps can be
configured as the differential receiver from the line transformer
or as independent active filters.
FREQUENCY (Hz)
(pA/ Hz, nV/ Hz)
100
10
1
10 10M1M100k10k1k100
01053-002
i
N
(pA/ Hz)
e
N
(nV/ Hz)
Figure 2. Current and Voltage Noise vs. Frequency
AD8022 Data Sheet
Rev. C | Page 2 of 16
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Maximum Power Dissipation ..................................................... 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 12
Applications..................................................................................... 13
DMT Modulation and Multitone Power Ratio (MTPR)....... 13
Channel Capacity and SNR....................................................... 13
Power Supply and Decoupling.................................................. 13
Layout Considerations............................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
8/11—Rev. B to Rev. C
Changes to Figure 40 ......................................................................14
Updated Outline Dimensions........................................................16
Changes to Ordering Guide...........................................................16
5/05—Rev. A to Rev. B
Changes to Format.............................................................Universal
Deleted Evaluation Boards Section.............................................. 14
Deleted Generating DMT Section................................................ 14
Changes to Ordering Guide.......................................................... 16
Updated Outline Dimensions....................................................... 16
9/02—Rev. 0 to Rev. A
Changes to Features ..........................................................................1
Changes to Applications...................................................................1
Changes to Product Description.....................................................1
Changes to Functional Block Diagram ..........................................1
Changes to Figure 1...........................................................................1
Changes to Specifications Table......................................................2
Edits to TPCs 1, 2, 3, 6 ......................................................................5
New TPCs 7, 8....................................................................................6
Edits to TPCs 16, 17, 18....................................................................7
Edits to TPC 19..................................................................................8
Edits to TPC 28..................................................................................9
Edits to Figure 3...............................................................................11
Edits to Figure 6...............................................................................14
Updated Outline Dimensions........................................................16
Data Sheet AD8022
Rev. C | Page 3 of 16
SPECIFICATIONS
At 25°C, VS = ±12 V, RL = 500 Ω, G = +1, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth VOUT = 50 mV p-p 110 130 MHz
Bandwidth for 0.1 dB Flatness VOUT = 50 mV p-p 25 MHz
Large Signal Bandwidth1 V
OUT = 4 V p-p 4 MHz
Slew Rate VOUT = 2 V p-p, G = +2 40 50 V/μs
Rise and Fall Time VOUT = 2 V p-p, G = +2 30 ns
Settling Time 0.1% VOUT = 2 V p-p 62 ns
Overdrive Recovery Time VOUT = 150% of max output
voltage, G = +2
200 ns
NOISE/DISTORTION PERFORMANCE
Distortion VOUT = 2 V p-p
Second Harmonic fC = 1 MHz −95 dBc
Third Harmonic fC = 1 MHz −100 dBc
Multitone Input Power Ratio2 G = +7 differential
26 kHz to 132 kHz −67.2 dBc
144 kHz to 1.1 MHz −66 dBc
Voltage Noise (RTI) f = 100 kHz 2.5 nV/√Hz
Input Current Noise f = 100 kHz 1.2 pA/√Hz
DC PERFORMANCE
Input Offset Voltage −1.5 ±6 mV
T
MIN to TMAX ±7.25 mV
Input Offset Current ±120 nA
Input Bias Current 2.5 5.0 μA
T
MIN to TMAX ±7.5 μA
Open-Loop Gain 72 dB
INPUT CHARACTERISTICS
Input Resistance (Differential) 20 kΩ
Input Capacitance 0.7 pF
Input Common-Mode Voltage Range −11.25 to +11.75 V
Common-Mode Rejection Ratio VCM = ±3 V 98 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 500 Ω ±10.1 V
R
L = 2 kΩ ±10.6 V
Linear Output Current G = +1, RL = 150 Ω, dc error = 1% ±55 mA
Short-Circuit Output Current 100 mA
Capacitive Load Drive RS = 0 Ω, <3 dB of peaking 75 pF
POWER SUPPLY
Operating Range +4.5 ±13.0 V
Quiescent Current 4.0 5.5 mA/Amp
T
MIN to TMAX 6.1 mA/Amp
Power Supply Rejection Ratio VS = ±5V to ±12 V 80 dB
OPERATING TEMPERATURE RANGE −40 +85 °C
1 FPBW = Slew Rate/(2π VPEAK).
2 Multitone testing performed with 800 mV rms across a 500 Ω load at Point A and Point B on the circuit of Figure 23.
AD8022 Data Sheet
Rev. C | Page 4 of 16
At 25°C, VS = ±2.5 V, RL = 500 Ω, G = +1, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth VOUT = 50 mV p-p 100 120 MHz
Bandwidth for 0.1 dB Flatness VOUT = 50 mV p-p 22 MHz
Large Signal Bandwidth1 V
OUT = 3 V p-p 4 MHz
Slew Rate VOUT = 2 V p-p, G = +2 30 42 V/μs
Rise and Fall Time VOUT = 2 V p-p, G = +2 40 ns
Settling Time 0.1% VOUT = 2 V p-p 75 ns
Overdrive Recovery Time VOUT = 150% of max output
voltage, G = +2
225 ns
NOISE/DISTORTION PERFORMANCE
Distortion VOUT = 2 V p-p
Second Harmonic fC = 1 MHz −77.5 dBc
Third Harmonic fC = 1 MHz −94 dBc
Multitone Input Power Ratio2 G = +7 differential, VS = ±6 V
26 kHz to 132 kHz −69 dBc
144 kHz to 1.1 MHz −66.7 dBc
Voltage Noise (RTI) f = 100 kHz 2.3 nV/√Hz
Input Current Noise f = 100 kHz 1 pA/√Hz
DC PERFORMANCE
Input Offset Voltage −0.8 ±5.0 mV
T
MIN to TMAX ±6.25 mV
Input Offset Current ±65 nA
Input Bias Current 2.0 5.0 μA
T
MIN to TMAX 7.5 μA
Open-Loop Gain 64 dB
INPUT CHARACTERISTICS
Input Resistance (Differential) 20 kΩ
Input Capacitance 0.7 pF
Input Common-Mode Voltage Range −1.83 to +2.0 V
Common-Mode Rejection Ratio VCM = ±2.5 V, VS = ±5.0 V 98 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 500 Ω −1.38 to +1.48 V
Linear Output Current G = +1, RL = 100 Ω, dc error = 1% ±32 mA
Short-Circuit Output Current 80 mA
Capacitive Load Drive RS = 0 Ω, <3 dB of peaking 75 pF
POWER SUPPLY
Operating Range +4.5 ±13.0 V
Quiescent Current 3.5 4.25 mA/Amp
T
MIN to TMAX 4.4 mA/Amp
Power Supply Rejection Ratio ∆VS = ±1 V 86 dB
OPERATING TEMPERATURE RANGE −40 +85 °C
1 FPBW = Slew Rate/(2 π VPEAK).
2 Multitone testing performed with 800 mV rms across a 500 Ω load at Point A and Point B on the circuit of Figure 23.
Data Sheet AD8022
Rev. C | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage (+VS to −VS) 26.4 V
Internal Power Dissipation1
8-Lead SOIC (R) 1.6 W
8-Lead MSOP (RM) 1.2 W
Input Voltage (Common Mode) ±VS
Differential Input Voltage ±0.8 V
Output Short-Circuit Duration Observe Power Derating Curves
Storage Temperature Range −65°C to +125°C
Operating Temperature Range
(A Grade)
−40°C to +85°C
Lead Temperature Range
(Soldering 10 sec)
300°C
1 Specification is for the device in free air:
8-Lead SOIC: θJA = 160°C/W.
8-Lead MSOP: θJA = 200°C/W.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8022 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit may cause a shift in
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
175°C for an extended period can result in device failure.
While the AD8022 is internally short-circuit protected, this may
not be sufficient to guarantee that the maximum junction
temperature (150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the
maximum power derating curves.
AMBIENT TEMPERATURE (°C)
MAXIMUM POWER DISSIPATION (W)
2.0
1.5
1.0
0.5
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
01053-003
T
J
= 150°C
8-LEAD SOIC PACKAGE
8-LEAD MSOP
Figure 3. Maximum Power Dissipation vs. Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8022 Data Sheet
Rev. C | Page 6 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (MHz)
(dB)
5
2
1
3
4
0
–5
–4
–3
–2
–1
0.1 1 10 100 500
01053-004
R
F
50Ω
50Ω
50Ω
V
IN
V
OUT
R
F
= 715Ω
R
F
= 0Ω
R
F
= 402Ω
Figure 4. Frequency Response vs. RF, G = +1, VS = ±12 V, VIN = 63 mV p-p
FREQUENCY (Hz)
(dB)
0.4
0.1
0
0.2
0.3
–0.1
–0.6
–0.5
–0.4
–0.3
–0.2
100k 1M 10M 100M
01053-005
G = +2
R
L
= 500Ω
±12V
±5.0V
±2.5V
Figure 5. Fine-Scale Gain Flatness vs. Frequency, G = +2
FREQUENCY (Hz)
(dB)
0.4
0.1
0
0.2
0.3
–0.1
–0.6
–0.5
–0.4
–0.3
–0.2
100k 1M 10M 100M
01053-006
G = +2
R
L
= 500Ω
±12V
±5.0V
±2.5V
Figure 6. Fine-Scale Gain Flatness vs. Frequency, G = +1
FREQUENCY (MHz)
(dB)
5
2
1
3
4
0
–5
–4
–3
–2
–1
0.1 1 10 100 500
01053-007
402Ω
453Ω
56.2Ω
50Ω
V
IN
V
OUT
V
IN
= 0.05V p-p
V
IN
= 0.2V p-p
V
IN
= 2.0V p-p
V
IN
= 0.8V p-p
V
IN
= 0.4V p-p
Figure 7. Frequency Response vs. Signal Level, VS = ±12 V, G = +1
FREQUENCY (kHz)
FREQUENCY RESPONCE (dB)
5
2
1
3
4
0
–5
–4
–3
–2
–1
0.1 1 10 100 500
01053-008
453Ω
715Ω715Ω
56.2Ω
50Ω
V
IN
V
OUT
R
S
C
L
50pF
30pF
0pF
Figure 8. Frequency Response vs. Capacitive Load; CL = 0 pF and 50 pF; RS = 0 Ω
SUPPLY VOLTAGE (±V)
FREQUENCY (MHz)
140
80
60
100
120
40
0
20
0 2 4 6 8 10 12 14
01053-009
G = +1, R
F
= 402Ω
G = +2, R
F
= 715Ω
Figure 9. Bandwidth vs. Supply, RL = 500 Ω, VIN = 200 mV p-p
Data Sheet AD8022
Rev. C | Page 7 of 16
FREQUENCY (Hz)
GAIN (dB)
80
30
60
50
70
40
0
20
10
–10
5k 10k 100k 10M1M 100M 500M
01053-010
Figure 10. Open-Loop Gain vs. Frequency
FREQUENCY (Hz)
FREQUENCY (Degrees)
0
180
–180
5k 10k 100k 10M1M 100M 500M
01053-011
Figure 11. Open-Loop Phase vs. Frequency
01053-012
OUTPUT
INPUT
100mV
100mV
100ns
100
90
10
0%
Figure 12. Noninverting Small Signal Pulse Response,
RL = 500 Ω, VS = ±12 V, G = +1, RF = 0 Ω
01053-013
OUTPUT
INPUT
100mV
100mV
100ns
100
90
10
0%
Figure 13. Noninverting Small Signal Pulse Response,
RL = 500 Ω, VS = ±2.5 V, G = +1, RF = 0 Ω
01053-014
OUTPUT
INPUT
2.00V
2.00V
100ns
100
90
10
0%
Figure 14. Noninverting Large Signal Pulse Response,
RL = 500 Ω, VS = ±12 V, G = +1, RF = 0 Ω
01053-015
OUTPUT
INPUT
1.00V
1.00V
100ns
100
90
10
0%
Figure 15. Noninverting Large Signal Pulse Response,
RL = 500 Ω, VS = ±2.5 V, G = +1, RF = 0 Ω
AD8022 Data Sheet
Rev. C | Page 8 of 16
TIME (ns)
SETTLING ERROR (%)
0.4
0.2
0.1
0.3
0
–0.4
–0.3
–0.2
–0.1
0 20 40 60 80 100 120
01053-016
+0.1%
–0.1%
Figure 16. Settling Time to 0.1%, VS = ±12 V,
Step Size = 2 V p-p, G = +2, RL = 500 Ω
TIME (ns)
SETTLING ERROR (%)
0.4
0.2
0.1
0.3
0
–0.4
–0.3
–0.2
–0.1
0 20 40 60 80 100 120
01053-017
+0.1%
–0.1%
Figure 17. Settling Time to 0.1%, VS = ±2.5 V, Step Size = 2 V p-p,
G = +2, RL = 500 Ω
SUPPLY VOLTAGE (V)
SLEW RATE (V/μs)
70
50
40
60
30
0
10
20
2.5 4.5 6.5 8.5 10.5 12.5
01053-018
NEGATIVE EDGE
POSITIVE EDGE
Figure 18. Slew Rate vs. Supply Voltage, G = +2
FREQUENCY (Hz)
HARMONIC DISTORTION (dB)
–50
–60
–70
–80
–90
–130
–120
–110
–100
1k 10k 100k 1M 10M
01053-019
3RD
2ND
Figure 19. Distortion vs. Frequency, VS = ±12 V, RL = 500 Ω,
RF = 0 Ω, VOUT = 2 V p-p, G = +1
FREQUENCY (Hz)
HARMONIC DISTORTION (dB)
–50
–60
–70
–80
–90
–130
–120
–110
–100
1k 10k 100k 1M 10M
01053-020
3RD
2ND
Figure 20. Distortion vs. Frequency, VS = ±2.5 V,
RL = 500 Ω, RF = 0 Ω, VOUT = 2 V p-p, G = +1
OUTPUT VOLTAGE (V p-p)
HARMONIC DISTORTION (dBc)
–20
–30
–40
–50
–60
–120
–100
–90
–80
–70
0 5 10 15 20
01053-021
3RD
2ND
Figure 21. Distortion vs. Output Voltage, VS = ±12 V,
G = +2, f = 1 MHz, RL = 500 Ω, RF = 715 Ω
Data Sheet AD8022
Rev. C | Page 9 of 16
OUTPUT VOLTAGE (V p-p)
HARMONIC DISTORTION (dBc)
0
–20
–40
–60
–120
–100
–80
0 1.50.5 1.0 2.0 2.5 3.0
01053-022
3RD
2ND
Figure 22. Distortion vs. Output Voltage, VS = ±2.5 V,
G = +1, f = 1 MHz, RL = 500 Ω, RF = 0 Ω
+V
–V
AD8022
1/2
AD8022
1/2
2
50Ω
715Ω
715Ω
500Ω
01053-023
Figure 23. Multitone Power Ratio Test Circuit
FREQUENCY (kHz)
10dB/DIV (dBc)
549.3 559.3558.3557.3556.3555.3554.3553.3552.3551.3550.3
01053-024
–66.0dBc
Figure 24. Multitone Power Ratio: VS = ±12 V, RL = 500 Ω,
Full Rate ADSL (DMT), Downstream
FREQUENCY (kHz)
10dB/DIV (dBc)
102.4 103.4 104.4 105.4 106.4 107.4 108.4 109.4 112.4111.4110.4
01053-025
–67.2dBc
Figure 25. Multitone Power Ratio: VS = ±12 V, RL = 500 Ω,
Full Rate ADSL (DMT), Upstream
FREQUENCY (kHz)
10dB/DIV (dBc)
549.3 559.3558.3557.3556.3555.3554.3553.3552.3551.3550.3
01053-026
–66.7dBc
Figure 26. Multitone Power Ratio: VS = ±6 V, RL = 500 Ω,
Full Rate ADSL (DMT), Downstream
FREQUENCY (kHz)
10dB/DIV (dBc)
102.4 103.4 104.4 105.4 106.4 107.4 108.4 109.4 112.4111.4110.4
01053-027
–69.0dBc
Figure 27. Multitone Power Ratio: VS = ±6 V, RL = 500 Ω,
Full Rate ADSL (DMT), Upstream
AD8022 Data Sheet
Rev. C | Page 10 of 16
TEMPERATURE (
°
C)
VOLTAGE OFFSET (mV)
0
–0.5
–1.0
–1.5
–2.5
–2.0
–60 –40 –20 140120100806040200
01053-028
V
S
= ±2.5V
SIDE B
SIDE A
SIDE B
SIDE A
V
S
= +12V
Figure 28. Voltage Offset vs. Temperature
TEMPERATURE (
°
C)
BIAS CURRENT (
μ
A)
4.5
4.0
3.5
3.0
0
2.5
2.0
1.5
1.0
0.5
–60 –40 –20 140120100806040200
01053-029
V
S
= ±12V
V
S
= ±2.5V
Figure 29. Bias Current vs. Temperature
V
CM
(V)
V
OS
(mV)
4
3
2
1
–4
0
–1
–2
–3
–12.5 –10.0 –7.5 –5.0 –2.5 12.510.07.55.02.50
01053-030
V
S
= ±12V
V
OUT
V
IN
1k
Ω
1k
Ω
1k
Ω
500
Ω
1k
Ω
V
S
= ±2.5V
Figure 30. Voltage Offset vs. Input Common-Mode Voltage
FREQUENCY Hz)
CMRR (dB)
–50
–100
–60
–70
–80
–90
1k 10k 1M100k
01053-031
1k
Ω
1k
Ω
50
Ω
1k
Ω
56.7
Ω
1k
Ω
Figure 31. CMRR vs. Frequency
TEMPERATURE (
°
C)
TOTAL SUPPLY CURRENT (mA)
8.5
8.0
7.5
7.0
5.0
6.5
6.0
5.5
–50 150100500
01053-032
V
S
= ±12V
V
S
= ±2.5V
Figure 32. Total Supply Current vs. Temperature
FREQUENCY (Hz)
POWER SUPPLY REJECTION (dB)
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
10k 100M10M1M100k
01053-033
+PSRR
–PSRR
Figure 33. Power Supply Rejection vs. Frequency VS = ±12 V
Data Sheet AD8022
Rev. C | Page 11 of 16
FREQUENCY (Hz)
POWER SUPPLY REJECTION (dB)
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
10k 100M10M1M100k
01053-034
+PSRR
–PSRR
Figure 34. Power Supply Rejection vs. Frequency VS = ±2.5 V
FREQUENCY (Hz)
CROSSTALK (dB)
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
10k 100M10M1M100k
01053-035
SIDE A OUT
SIDE B OUT
Figure 35. Output-to-Output Crosstalk vs. Frequency, VS = ±12 V
FREQUENCY (Hz)
CROSSTALK (dB)
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
100k 100M10M1M
01053-036
SIDE A OUT
SIDE B OUT
Figure 36. Output-to-Output Crosstalk vs. Frequency, VS = ±2.5 V
FREQUENCY (Hz)
OUTPUT IMPEDANCE (
Ω
)
100
0.0316
0.1
0.316
1
3.16
10
31
30k 500M100M10M1M100k
01053-037
Figure 37. Output Impedance vs. Frequency, VS = ±12 V
AD8022 Data Sheet
Rev. C | Page 12 of 16
THEORY OF OPERATION
The AD8022 is a voltage-feedback op amp designed especially
for ADSL or other applications requiring very low voltage and
current noise along with low supply current, low distortion, and
ease of use.
The AD8022 is fabricated on Analog Devices’ proprietary
eXtra-Fast Complementary Bipolar (XFCB) process, which
enables the construction of PNP and NPN transistors with
similar fTs in the 4 GHz region. The process is dielectrically
isolated to eliminate the parasitic and latch-up problems caused
by junction isolation. These features enable the construction of
high frequency, low distortion amplifiers with low supply
currents.
+
V
S
–VS
15Ω
15Ω
OUTPUT
+IN
–IN
7.5pF
600μA
01053-038
Figure 38. Simplified Schematic
As shown in Figure 38, the AD8022 input stage consists of an
NPN differential pair in which each transistor operates a
300 μA collector current. This gives the input devices a high
transconductance and therefore gives the AD8022 a low input
noise of 2.5 nV/√Hz @ 100 kHz. The input stage drives a folded
cascode that consists of a pair of PNP transistors. These PNPs
then drive a current mirror that provides a differential input to
single-ended output conversion. The output stage provides a
high current gain of 10,000 so that the AD8022 can maintain a
high dc open-loop gain, even into low load impedances.
Data Sheet AD8022
Rev. C | Page 13 of 16
5
APPLICATIONS
The low noise AD8022 dual xDSL receiver amplifier is
specifically designed for the dual differential receiver amplifier
function within xDSL transceiver hybrids, as well as other low
noise amplifier applications. The AD8022 can be used in
receiving modulated signals including discrete multitone
(DMT) on either end of the subscriber loop. Communication
systems designers can be challenged when designing an xDSL
modem transceiver hybrid capable of receiving the smallest
signals embedded in noise that inherently exists on twisted-pair
phone lines. Noise sources include near-end crosstalk (NEXT),
far-end crosstalk (FEXT), background, and impulse noise, all of
which are fed, to some degree, into the receiver front end. Based
on a Bellcore noise survey, the background noise level for
typical twisted-pair telephone loops is −140 dBm/√Hz or
31 nV/√Hz. It is therefore important to minimize the noise
added by the receiver amplifiers to preserve as much signal-to-
noise ratio (SNR) as possible. With careful transceiver hybrid
design, using the AD8022 dual, low noise, receiver amplifier to
maintain power density levels lower than −140 dBm/√Hz in
ADSL modems is easily achieved.
DMT MODULATION AND MULTITONE POWER
RATIO (MTPR)
ADSL systems rely on discrete multitone DMT modulation to
carry digital data over phone lines. DMT modulation appears in
the frequency domain as power contained in several individual
frequency subbands, sometimes referred to as tones or bins,
each of which is uniformly separated in frequency. (See Figure 24
to Figure 27 for MTPR results while the AD8022 receives DMT
driving 800 mV rms across a 500 Ω differential load.) A
uniquely encoded quadrature amplitude modulation (QAM)
signal occurs at the center frequency of each subband or tone.
Difficulties exist when decoding these subbands if a QAM
signal from one subband is corrupted by the QAM signal(s)
from other subbands, regardless of whether the corruption
comes from an adjacent subband or harmonics of other
subbands. Conventional methods of expressing the output
signal integrity of line receivers, such as spurious-free dynamic
range (SFDR), single tone harmonic distortion (THD), two-
tone intermodulation distortion (IMD), and third-order
intercept (IP3), become significantly less meaningful when
amplifiers are required to process DMT and other heavily
modulated waveforms. A typical xDSL downstream DMT signal
can contain as many as 256 carriers (subbands or tones) of
QAM signals. MTPR is the relative difference between the
measured power in a typical subband (at one tone or carrier) vs.
the power at another subband specifically selected to contain no
QAM data.
In other words, a selected subband (or tone) remains open or
void of intentional power (without a QAM signal) yielding an
empty frequency bin. MTPR, sometimes referred to as the
empty bin test, is typically expressed in dBc, similar to
expressing the relative difference between single tone
fundamentals and second or third harmonic distortion
components. Measurements of MTPR are typically made at the
output of the receiver directly across the differential load. Other
components aside, the receiver function of an ADSL transceiver
hybrid is affected by the turns ratio of the selected transformers
within the hybrid design. Since a transformer reflects the
secondary voltage back to the primary side by the inverse of the
turns ratio, 1/N, increasing the turns ratio on the secondary side
reduces the voltage across the primary side inputs of the
differential receiver. Increasing the turns ratio of the
transformers can inadvertently cause a reduction of the SNR by
reducing the received signal strength.
CHANNEL CAPACITY AND SNR
The efficiency of an ADSL system in delivering the digital data
embedded in the DMT signals can be compromised when the
noise power of the transmission system increases. Figure 39
shows the relationship between SNR and the relative maximum
number of bits per tone or subband while maintaining a bit
error rate at 10–7 errors per second.
BITS/TONE
SNR (dB)
60
0
10
20
30
40
50
01105
01053-039
Figure 39. ADSL DMT SNR vs. Bits/Tone
POWER SUPPLY AND DECOUPLING
The AD8022 should be powered with a good quality (that is,
low noise) dual supply of ±12 V for the best overall
performance. The AD8022 circuit also functions at voltages
lower than ±12 V. Careful attention must be paid to decoupling
the power supply pins. A pair of 10 μF capacitors located in
near proximity to the AD8022 is required to provide good
decoupling for lower frequency signals. In addition, 0.1 μF
decoupling capacitors should be located as close to each of the
power supply pins as is physically possible.
AD8022 Data Sheet
Rev. C | Page 14 of 16
+
A
VDD
B3
TP4
AGND
B4
TP19
TP5
TP18
C4
10µF
+
A
VEE
B5
TP6
C5
10µF
+
DVDD
B1
TP3
DGND
B2
TP2
C3
10µF
A
+
A
VCC
B6
TP7
C6
10µF
C7
1µF
C8
0.1µF
C9
0.1µF
AA
AVEE
AVCC
0.1µF
0.1µF
1µF
A
A
A
249Ω
A
A
A A A
A
A
249Ω
750Ω
750Ω
226Ω
10kΩ49.9Ω
A
AD8022
AD8022
AA
J4
OUT2
C13
22pF
1µF
A
10kΩ49.9Ω
AA
J3
OUT1
C12
22pF
DIFFERENTIAL
DMT OUTPUTS
4
2
8
6
12
10
16
14
22
20
18
26
24
30
28
34
36
38
40
32
3
1
7
5
11
9
15
13
15
16
13
14
11
12
9
10
2
1
4
3
6
5
8
7
C1
C19
C25
C2
C27
C26
C29
C27
21
19
17
25
23
29
27
33
35
37
39
31
2
1
4
3
6
5
8
7
11
10
9
13
12
14
27
28
25
26
23
24
21
22
18
19
20
16
17
15
DVDD
CLOCK
NC
DCOM
COMP2
AVDD
IOUTB
IOUTA
FS ADJ
COMP1
ACOM
REFLO
REFIO
SLEEP
DB12
DB13
DB10
DB11
DB8
DB9
DB6
DB7
DB3
DB4
DB5
DB1
DB2
DB0
P1
TO TEK
AWG
2021
1
2345678910
R1
98765432
R2
1
2345678910
R5
DVDD
1
2345678910
R7
DVDD
1
2345678910
R3
16 PIN DIP
RES PK
15
16
13
14
11
12
9
10
2
1
4
3
6
5
8
7
C31
C30
C33
C32
C35
C34
C36
16 PIN DIP
RES PK
10
1
98765432
R2
10
11
98765432
R6
10
DVDD
1
98765432
R6
10
DVDD
U1
AD9754
CT1
EXTCLK
J1
PDIN
J2
CLK
JP1
A
123
B
TP1
R15
49.9Ω
AVDD
AVDD TP8
OUT1
OUT2
TP12
TP11
JP2
AVDD
AVDD
TP10
JP4
TP14
TP9
TP13
R17
49.9Ω
1
2
3
C11
0.1µF
C10
0.1µF
R16
2kΩ
R
20kΩ
01053-040
Figure 40. DMT Signal Generator Schematic
Data Sheet AD8022
Rev. C | Page 15 of 16
+V
IN
–V
IN
+V
OUT
–V
OUT
191Ω
1%
191Ω
1%
243Ω
1%
243Ω
1%
249Ω
1%
422Ω
1%
249Ω
1%
COMMON-
MODE
VOLTAGE
SIGNAL C
M
LEVEL
8200pF
10%
8200pF
10%
6800pF
5% NPO
6800pF
5% NPO
0.1μF
50V
5%
NPO
0.1μF
16V
10%
X7R
AD8022
12V
3
2
8
1
AD8022
6
5
4
7
01053-041
Figure 41. Differential Input Sallen-Key Filter
Using AD8022 on Single Supply, +12 V
FREQUENCY (Hz)
(dB)
7.5
–42.5
–37.5
–32.5
–27.5
–22.5
–17.5
–12.5
–7.5
–2.5
2.5
10k 10M1M100k
01053-042
Figure 42. Frequency Response of Sallen-Key Filter
LAYOUT CONSIDERATIONS
As is the case with all high speed amplifiers, careful attention to
printed circuit board layout details prevent associated board
parasitics from becoming problematic. Proper RF design
technique is mandatory. The PCB should have a ground plane
covering all unused portions of the component side of the
board to provide a low impedance return path. Removing the
ground plane from the area near the input signal lines reduces
stray capacitance. Chip capacitors should be used for supply
bypassing. One end of the capacitor should be connected to the
ground plane, and the other should be connected no more than
1/8 inch away from each supply pin. An additional large
(0.47 μF to 10 μF) tantalum capacitor should be connected in
parallel, although not necessarily as close, in order to supply
current for fast, large signal changes at the AD8022 output.
Signal lines connecting the feedback and gain resistors should
be as short as possible, minimizing the inductance and stray
capacitance associated with these traces. Locate termination
resistors and loads as close as possible to the input(s) and
output, respectively. Adhere to stripline design techniques for
long signal traces (greater than about 1 inch). Following these
generic guidelines improves the performance of the AD8022 in
all applications.
AD8022 Data Sheet
Rev. C | Page 16 of 16
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 43. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)—Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 44. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)—Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD8022AR −40°C to +85°C 8-Lead SOIC_N R-8
AD8022ARZ −40°C to +85°C 8-Lead SOIC_N R-8
AD8022ARZ-REEL −40°C to +85°C 8-Lead SOIC_N R-8
AD8022ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
AD8022ARMZ −40°C to +85°C 8-Lead MSOP RM-8
AD8022ARMZ-REEL −40°C to +85°C 8-Lead MSOP RM-8
AD8022ARMZ-REEL7 −40°C to +85°C 8-Lead MSOP RM-8
AD8022ARM-EBZ Evaluation Board
AD8022AR-EBZ Evaluation Board
1 Z = RoHS Compliant Part.
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D01053-0-8/11(C)
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