Datasheet RL78/L1A R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 RENESAS MCU Integrated LCD controller/driver, 12-bit resolution A/D Converter, 12-bit resolution D/A Converter, Operational amplifier, Internal reference voltage for A/D and D/A converters. True Low Power Platform (as low as 70.8 A/MHz, and 0.68 A in Halt mode( RTC2 + LVD)), 1.8 V to 3.6 V operation, 48 to 128 Kbyte Flash, 33 DMIPS at 24 MHz, for All LCD Based Applications. 1. OUTLINE 1.1 Features Ultra-low power consumption technology * VDD = single power supply voltage of 1.8 to 3.6 V * HALT mode * STOP mode * SNOOZE mode Timers * 16-bit timer: * 8-bit timer: * 12-bit interval timer: * Real-time clock 2: RL78 CPU core * CISC architecture with 3-stage pipeline * Minimum instruction execution time: Can be changed from high speed (0.04167 s: @ 24 MHz operation with high-speed on-chip oscillator clock) to ultra-low speed (30.5 s: @ 32.768 kHz operation with subsystem clock) * Multiply/divide and multiply/accumulate instructions are supported. * Address space: 1 MB * General-purpose registers: (8-bit register 8) 4 banks * On-chip RAM: 5.5 KB * Watchdog timer: Code flash memory * Code flash memory: 48 to 128 KB * Block size: 1 KB * Prohibition of block erase and rewriting (security function) * On-chip debug function * Self-programming (with boot swap function/flash shield window function) Data flash memory * Data flash memory: 8 KB * Background operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory. * Number of rewrites: 1,000,000 times (TYP.) * Voltage of rewrites: VDD = 1.8 to 3.6 V High-speed on-chip oscillator * Select from 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz * High accuracy: 1.0% (VDD = 1.8 to 3.6 V, TA = -20 to +85 C) Operating ambient temperature * TA = -40 to +85 C (A: Consumer applications) Power management and reset function * On-chip power-on-reset (POR) circuit * On-chip voltage detector (LVD) (Select interrupt and reset from 10 levels) Data transfer controller (DTC) * Transfer modes: Normal transfer mode, repeat transfer mode, block transfer mode * Activation sources: Activated by interrupt sources (30 sources). * Chain transfer function Event link controller (ELC) * Event signals of 22 types can be linked to the specified peripheral function. Serial interfaces * CSI/CSI (SPI supported): * UART: * I2C/simplified I2C: 4 channels 4 channels 5 channels R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 8 channels 2 channels 1 channel 1 channel (calendar for 99 years, alarm function, and clock correction function) 1 channel (operable with the dedicated low-speed on-chip oscillator) LCD controller/driver * Internal voltage boosting method, capacitor split method, and external resistance division method are switchable. * Segment signal output: 32 (28) to 45 (41) Note 1 * Common signal output: 4 (8) Note 1 A/D converter * 12-bit resolution A/D converter (1.8 V AVDD VDD 3.6 V) * Analog input: 10 to 14 channels * Internal reference voltage (TYP. 1.45 V) and temperature sensor Note 2 D/A converter * 12-bit resolution D/A converter (1.8 V AVDD VDD 3.6 V) * Analog output: 2 channels * Output voltage: 0.35 V to AVDD - 0.47 V Voltage reference * The output voltage can be selected from among 1.5 V (typ.), 1.8 V (typ.), 2.048 V (typ.), and 2.5 V (typ.). * Can be used as the internal reference voltage for A/D and D/A converters. Comparator * 1 channel * Operating modes: Comparator high-speed mode, comparator lowspeed mode, window mode * The external reference voltage or internal reference voltage can be selected as the reference voltage. Operational amplifier * General-purpose operational amplifier: * Rail-to-rail operational amplifier with analog MUX: 1 channel 2 channels I/O ports * I/O ports: 59 to 79 (N-ch open drain I/O [withstand voltage of 6 V]: 2) * Can be set to N-ch open drain, TTL input buffer, and on-chip pull-up resistor * On-chip key interrupt function * On-chip clock output/buzzer output controller Others * On-chip BCD (binary-coded decimal) correction circuit Note 1. The number in parentheses indicates the number of signal outputs when 8 coms are used. Note 2. Selectable only in HS (high-speed main) mode. Note 3. The functions mounted depend on the product. See 1.6 Outline of Functions. Page 1 of 80 RL78/L1A 1. OUTLINE ROM, RAM capacities Products with USB Flash ROM Data Flash RAM 128 KB 8 KB 96 KB RL78/L1A 80 pins 100 pins 5.5 KB -- R5F11MPG 8 KB 5.5 KB R5F11MMF R5F11MPF 64 KB 8 KB 5.5 KB R5F11MME R5F11MPE 48 KB 8 KB 5.5 KB R5F11MMD -- R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 2 of 80 RL78/L1A 1.2 1. OUTLINE Ordering Information Pin Count 80 pins Package 80-pin plastic LFQFP Fields of Application A (12 12 mm, 0.5 mm pitch) 100 pins 100-pin plastic LFQFP (14 14 mm, 0.5 mm pitch) Orderable Part Number R5F11MMDAFB#30, R5F11MMEAFB#30, R5F111MFAFB#30 R5F11MMDAFB#50, R5F11MMEAFB#50, R5F11MMFAFB#50 A R5F11MPEAFB#30, R5F11MPFAFB#30, R5F11MPGAFB#30 R5F11MPEAFB#50, R5F11MPFAFB#50, R5F11MPGAFB#50 Figure 1 - 1 Part Number, Memory Size, and Package of RL78/L1A Part No. R 5 F 1 1 M P E A x x x F B # 3 0 Packaging specification: #30: Tray #50: Embossed Tape Package type: FB: LFQFP, 0.50 mm pitch ROM number (Omitted with blank products) Fields of application: A: Consumer applications, TA = -40 to +85 C ROM capacity: D: 48 KB E: 64 KB F: 96 KB G: 128 KB Pin count: M: 80-pin P: 100-pin RL78/L1A Group 11M: RL78/L1A Memory type: F: Flash memory Renesas MCU Renesas semiconductor product Caution Orderable part numbers are current as of when this manual was published. Please make sure to refer to the relevant product page on the Renesas website for the latest part numbers. R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 3 of 80 RL78/L1A 1.3 1. OUTLINE Pin Configuration (Top View) 1.3.1 80-pin products COM4/SEG0 COM5/SEG1 COM6/SEG2 COM7/SEG3 P50/TI02/TO02/INTP6/SEG4 P51/TI04/TO04/SEG5 P52/TI03/TO03/SEG6 P07/TI05/TO05/SEG40 COM0 COM1 COM2 COM3 P14/INTP7/PCLBUZ0/SCK20/SCL20/SEG29 P00/SCK30/SCL30/SEG33 P01/SI30/RxD3/SDA30/SEG34 P02/SO30/TxD3/(PCLBUZ0)/SEG35 P03/TI00/TO00/INTP1/SEG36 P04/INTP2/SEG37 P05/TI06/TO06/SEG38 P06/INTP5/SEG39 * 80-pin plastic LFQFP (fine pitch) (12 12 mm, 0.5 mm pitch) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P81/AMP0OPD/TXD2/SO20/SEG43 P80/AMP1OPD/RXD2/SI20/SDA20/SEG44 P27/ANI13/MUX00 P26/ANI12/MUX01 P23/AMP0AMP0O P21/ANI09/AMP0+ P20/ANO0 P143/ANI08 P142/ANI07 P141/ANI06 P140/ANI05 P107/ANI04/MUX10 P106/ANI03/MUX11 P103/AMP1AMP1O P101/ANI00/AMP1+ P100/ANO1 AVDD AVSS 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 RL78/L1A Top View 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P70/KR7/SEG12 P71/KR6/SEG13 P72/KR5/SEG14 P73/KR4/SEG15 P74/KR3/SEG16 P75/KR2/SEG17 P76/KR1/SEG18 P77/TI07/TO07/KR0/SEG19 P30/INTP3/RTC1HZ/SEG20 P31/TI01/TO01/SEG21 P32/INTP4/SEG22 P35/SCK10/SCL10/SEG25/VCOUT0 P36/PCLBUZ1/RxD1/SI10/SDA10/SEG26 P37/TxD1/SO10/SEG27 P125/VL3/(TI06)/(TO06)/(INTP7) VL4 VL2 VL1 P126/CAPL/(TI05)/(TO05)/(INTP6) P127/CAPH/(TI04)/(TO04)/(INTP5) P150/AMP2+ AMP2O P152/AMP2P153/AMP2OPD P154/AVREFM AVREFP/VREFOUT P44/SI00/RxD0/SDA00/TOOLRxD/(PCLBUZ1)/IVREF0 P43/SO00/TxD00/(TI00)/(TO00)/TOOLTxD/(INTP0)/IVCMP0 P40/TOOL0/(TI01)/(TO01)/SCK00/SCL00 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0/(SSI00)/ADTRG P122/X2/EXCLK P121/X1 REGC VSS VDD P60/SCLA0/(TI02)/(TO02)/(INTP3)/SSI00 P61/SDAA0/(TI03)/(TO03)/(INTP4) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 4 of 80 RL78/L1A 1.3.2 1. OUTLINE 100-pin products P51/TI04/TO04/SEG5 P52/TI03/TO03/SEG6 P12/TxD2/SO20/SEG41 P13/SEG28 P14/INTP7/PCLBUZ0/SCK20/SCL20/SEG29 P15/SEG30 P16/SEG31 P17/SEG32 P00/SCK30/SCL30/SEG33 P01/SI30/RxD3/SDA30/SEG34 P02/SO30/TxD3/(PCLBUZ0)/SEG35 P03/TI00/TO00/INTP1/SEG36 P04/INTP2/SEG37 P05/TI06/TO06/SEG38 P06/INTP5/SEG39 P07/TI05/TO05/SEG40 COM0 COM1 COM2 COM3 COM4/SEG0 COM5/SEG1 COM6/SEG2 COM7/SEG3 P50/TI02/TO02/INTP6/SEG4 * 100-pin plastic LFQFP (fine pitch) (14 14 mm, 0.5 mm pitch) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 RL78/L1A Top View 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P53/SEG7 P54/SEG8 P55/SEG9 P56/SEG10 P57/SEG11 P70/KR7/SEG12 P71/KR6/SEG13 P72/KR5/SEG14 P73/KR4/SEG15 P74/KR3/SEG16 P75/KR2/SEG17 P76/KR1/SEG18 P77/TI07/TO07/KR0/SEG19 P30/INTP3/RTC1HZ/SEG20 P31/TI01/TO01/SEG21 P32/INTP4/SEG22 P33/SEG23 P34/SEG24 P35/SCK10/SCL10/SEG25/(VCOUT0) P36/PCLBUZ1/RxD1/SI10/SDA10/SEG26 P37/TxD1/SO10/SEG27 P125/VL3/(TI06)/(TO06)/(INTP7) VL4 VL2 VL1 P150/AMP2+ AMP2O P152/AMP2P153/AMP2OPD P154/AVREFM AVREFP/VREFOUT P130 P44/SI00/RxD0/SDA00/TOOLRxD/(PCLBUZ1)/IVREF0 P43/SO00/TxD00/(TI00)/(TO00)/TOOLTxD/(INTP0)/IVCMP0 P42/(INTP1)/VCOUT0 P41/SCK00/SCL00/(INTP2) P40/TOOL0/(TI01)/(TO01)/(SCK00/SCL00) RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0/(SSI00)/ADTRG P122/X2/EXCLK P121/X1 REGC VSS VDD P60/SCLA0/(TI02)/(TO02)/(INTP3)/SSI00 P61/SDAA0/(TI03)/(TO03)/(INTP4) P127/CAPH/(TI04)/(TO04)/(INTP5) P126/CAPL/(TI05)/(TO05)/(INTP6) P11/RxD2/SI20/SDA20/SEG42 P81/AMP0OPD/(TxD2/SO20)/SEG43 P80/AMP1OPD/(RxD2/SI20/SDA20)/SEG44 P27/ANI13/MUX00 P26/ANI12/MUX01 P25/ANI11/MUX02 P24/ANI10/MUX03 P23/AMP0AMP0O P21/ANI09/AMP0+ P20/ANO0 P143/ANI08 P142/ANI07 P141/ANI06 P140/ANI05 P107/ANI04/MUX10 P106/ANI03/MUX11 P105/ANI02/MUX12 P104/ANI01/MUX13 P103/AMP1AMP1O P101/ANI00/AMP1+ P100/ANO1 AVDD AVSS Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 5 of 80 RL78/L1A 1.4 1. OUTLINE Pin Identification AMP0+ to AMP2+ : OP AMP + Input AMP0- to AMP2+ : OP AMP - Input AMP0O to AMP2+ : OP AMP Output REGC : Regulator Capacitance AMP0OPD to : Low Resistance Switch RESET : Reset RTC1HZ : Real-time Clock Correction RxD0 to RxD3 : Receive Data : Serial Clock Input/Output AMP2OPD PCLBUZ0, PCLBUZ1 : Programmable Clock Output/ Buzzer Output ADTRG : A/D External Trigger Input ANI0 to ANI14 : Analog Input SCK00, SCK10, SCK20, ANO0, ANO1 : Analog Output SCK30 AVDD : Analog Power Supply SCLA0 AVREFM : Analog Reference Voltage SCL00, SCL10, SCL20, SCL30 : Serial Clock Output AVREFP : Analog Reference Voltage Minus Plus AVSS : Analog Ground SDAA0, SDA00, SDA10, : Serial Clock Input/Output : Serial Data Input/Output SDA20, SDA30 SEG0 to SEG55 : LCD Segment Output SI00, SI10, SI20, SI30 : Serial Data Input CAPH, CAPL : Capacitor for LCD SO00, SO10, SO20, SO30 : Serial Data Output COM0 to COM7 : LCD Common Output SSI00 : Slave Select Input EXCLK : External Clock Input TI00 to TI07 : Timer Input TO00 to TO07 : Timer Output TOOL0 : Data Input/Output for Tool TOOLRxD, TOOLTxD : Data Input/Output for (Main System Clock) EXCLKS : External Clock Input (Sub System Clock) INTP0 to INTP7 : External Interrupt Input IVCMP0 : Comparator Input External Device TxD0 to TxD3 : Transmit Data IVREF0 : Comparator Reference Input VCOUT0 : Comparator Output KR0 to KR7 : Key Return VDD : Power Supply MUX00 to MUX03, : OP AMP output analog MUX VL1 to VL4 : LCD Power Supply VREFOUT : Analog Reference Voltage MUX10 to MUX13 switch P00 to P07 : Port 0 P11 to P17 : Port 1 VSS : Ground P20, P21 P23 to P27 : Port 2 X1, X2 : Crystal Oscillator P30 to P37 : Port 3 P40 to P44 : Port 4 P50 to P57 : Port 5 P60, P61 : Port 6 P70 to P77 : Port 7 P80, P81 : Port 8 P100, P101 : Port 10 Output (Main System Clock) XT1, XT2 : Crystal Oscillator (Subsystem Clock) P103 to P107 P121 to P127 : Port 12 P130, P137 : Port 13 P140 to P143 : Port 14 P150, P152 to P154 : Port 15 R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 6 of 80 RL78/L1A 1.5 1. OUTLINE Block Diagram 1.5.1 80-pin products TIMER ARRAY UNIT0 (8 ch) TI00/TO00 10 ANI00, ANI03 to ANI09, ANI12, ANI13 PORT 0 ch 0 ANI14 TI01/TO01 ch 1 8 P00 to P07 1/2AVDD PORT 1 A/D CONVERTER P14 ADTRG TI02/TO02 ch 2 TI03/TO03 ch 3 TI04/TO04 ch 4 TI05/TO05 ch 5 TI06/TO06 ch 6 TI07/TO07 ch 7 8-BIT INTERVAL TIMER AVREFP/VREFOUT AVREFM CODE FLASH MEMORY DATA FLASH MEMORY RL78 CPU CORE MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR DATA TRANSFER CONTROL 12- BIT INTERVAL TIMER REAL-TIME CLOCK RTC1HZ SERIAL ARRAY UNIT0 (4 ch) RxD0 TxD0 RxD1 TxD1 UART0 P20, P21, P23, P26, P27 PORT 3 6 P30 to P32, P35 to P37 PORT 4 3 P40, P43, P44 PORT 5 3 P50 to P52 PORT 6 2 P60, P61 PORT 7 8 P70 to P77 PORT 8 2 P80, P81 PORT 10 5 P100, P101, P103, P106, P107 RAM ch 01 WINDOW WATCHDOG TIMER 5 INT ch 00 LOW-SPEED ON-CHIP OSCILLATOR PORT 2 PORT 12 P125 to P127 P121 to P124 PORT 13 AVDD, AVSS, TOOLRxD, VDD VSS TOOLTxD SDAA0 SERIAL INTERFACE IICA0 P137 PORT 14 4 P140 to P143 PORT 15 4 P150, P152 to P154 KEY RETURN 8 KR0 to KR7 SCLA0 COMPARATOR (1 ch) POWER ON RESET/ VOLTAGE DETECTOR VCOUT0 IVCMP0 IVREF0 COMPARATOR0 POR/LVD CONTROL UART1 RESET CONTROL SCK00 SI00 SO00 SSI00 CSI00 (SPI) SCK10 SI10 SO10 SCL00 SDA00 CSI10 OP AMP (3 ch) ON-CHIP DEBUG AMP0+ AMP0AMP0O AMP0OPD OP AMP 0 2 LRSW0 MUX00, MUX01 IIC10 AMP1+ AMP1AMP1O AMP1OPD OP AMP 1 2 SERIAL ARRAY UNIT1 (4 ch) SYSTEM CONTROL INTERRUPT CONTROL UART2 RxD3 TxD3 UART3 D/A CONVERTER CSI20 CRC SCK20 SI20 SO20 SCK30 SI30 SO30 SCL20 SDA20 CSI30 IIC20 SCL30 SDA30 IIC30 SEG0 to SEG6, SEG12 to SEG22, SEG25 to SEG27, SEG29, SEG33 to SEG40, SEG43, SEG44 32 COM0 to COM7 8 LCD CONTROLLER/ DRIVER XT1 XT2/EXCLKS VOLTAGE REGULATOR RxD2 TxD2 OP AMP 2 RESET X1 X2/EXCLK LRSW1 MUX10, MUX11 AMP2+ AMP2- AMP2OPD AMP2O TOOL0 HIGH-SPEED ON-CHIP OSCILLATOR IIC00 SCL10 SDA10 VL1 to VL4 CAPH CAPL 3 4 LRSW2 REGC 8 ANO0 ANO1 BUZZER OUTPUT CLOCK OUTPUT CONTROL INTP0 to INTP7 2 PCLBUZ0, PCLBUZ1 EVENT LINK CONTROLLER BCD ADJUSTMENT RAM SPACE FOR LCD DATA R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 7 of 80 RL78/L1A 1. OUTLINE 1.5.2 100-pin products TIMER ARRAY UNIT0 (8 ch) TI00/TO00 14 ch 0 ANI14 TI01/TO01 ch 1 A/D CONVERTER PORT 0 8 P00 to P07 PORT 1 7 P11 to P17 PORT 2 7 P20, P21 P23 to P27 PORT 3 8 P30 to P37 PORT 4 5 P40 to P44 PORT 5 8 P50 to P57 PORT 6 2 P60, P61 ANI00 to ANI13 1/2AVDD ADTRG AVREFP/VREFOUT TI02/TO02 ch 2 TI03/TO03 ch 3 TI04/TO04 ch 4 TI05/TO05 ch 5 TI06/TO06 ch 6 TI07/TO07 ch 7 8-BIT INTERVAL TIMER AVREFM CODE FLASH MEMORY DATA FLASH MEMORY INT RL78 CPU CORE MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR PORT 7 8 P70 to P77 DATA TRANSFER CONTROL PORT 8 2 P80, P81 RAM PORT 10 7 P100, P101, P103 to P107 ch 00 PORT 12 ch 01 3 P125 to P127 4 P121 to P124 P130 P137 PORT 13 LOW-SPEED ON-CHIP OSCILLATOR WINDOW WATCHDOG TIMER AVDD, AVSS, TOOLRxD, VDD VSS TOOLTxD 12- BIT INTERVAL TIMER REAL-TIME CLOCK RTC1HZ SERIAL ARRAY UNIT0 (4 ch) RxD0 TxD0 RxD1 TxD1 SDAA0 SERIAL INTERFACE IICA0 VCOUT0 IVCMP0 IVREF0 COMPARATOR0 SCK10 SI10 SO10 SCL00 SDA00 CSI10 AMP0+ AMP0AMP0O OP AMP 0 4 SERIAL ARRAY UNIT1 (4 ch) RxD3 TxD3 UART3 SCK20 SI20 SO20 SCK30 SI30 SO30 SCL20 SDA20 KEY RETURN 8 KR0 to KR7 POR/LVD CONTROL TOOL0 4 OP AMP 2 SYSTEM CONTROL AMP0OPD LRSW0 RESET X1 X2/EXCLK HIGH-SPEED ON-CHIP OSCILLATOR XT1 XT2/EXCLKS VOLTAGE REGULATOR AMP1OPD INTERRUPT CONTROL MUX10 to MUX13 AMP2+ AMP2AMP2O REGC LRSW1 8 ANO0 D/A CONVERTER AMP2OPD INTP0 to INTP7 ANO1 LRSW2 CRC CSI20 BUZZER OUTPUT SCL30 SDA30 CSI30 CLOCK OUTPUT CONTROL IIC20 EVENT LINK CONTROLLER 2 PCLBUZ0, PCLBUZ1 IIC30 BCD ADJUSTMENT SEG0 to SEG44 45 COM0 to COM7 8 VL1 to VL4 CAPH CAPL P150, P152 to P154 MUX00 to MUX03 AMP1+ AMP1AMP1O OP AMP 1 UART2 4 ON-CHIP DEBUG IIC10 RxD2 TxD2 PORT 15 RESET CONTROL OP AMP (3 ch) IIC00 SCL10 SDA10 P140 to P143 POWER ON RESET/ VOLTAGE DETECTOR COMPARATOR (1 ch) UART0 CSI00 (SPI) 4 SCLA0 UART1 SCK00 SI00 SO00 SSI00 PORT 14 LCD CONTROLLER/ DRIVER RAM SPACE FOR LCD DATA R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 8 of 80 RL78/L1A 1.6 1. OUTLINE Outline of Functions [80-pin, 100-pin products] (1/2) 80-pin 100-pin R5F11MMx (x = D to F) R5F11MPx (x = E to G) Code flash memory (KB) 48 to 96 64 to 128 Data flash memory (KB) 8 8 5.5 5.5 Item RAM (KB) Memory space Main system clock 1 MB High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) High-speed on-chip HS (high-speed main) operation mode: 1 to 24 MHz (VDD = 2.7 to 3.6 V), oscillator clock HS (high-speed main) operation mode: 1 to 16 MHz (VDD = 2.4 to 3.6 V), 1 to 20 MHz: VDD = 2.7 to 3.6 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V LS (low-speed main) operation mode: 1 to 8 MHz (VDD = 1.8 to 3.6 V) Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) Low-speed on-chip oscillator clock 15 kHz (TYP.): VDD = 1.8 to 3.6 V General-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) Minimum instruction execution time 0.04167 s (High-speed on-chip oscillator clock: fHOCO = fIH = 24 MHz operation) 32.768 kHz (TYP.): VDD = 1.8 to 3.6 V 0.05 s (High-speed system clock: fMX = 20 MHz operation) 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation) Instruction set I/O port * * * * * Data transfer (8/16 bits) Adder and subtractor/logical operation (8/16 bits) Multiplication (8 bits 8 bits, 16 bits 16 bits), Division (16 bits 16 bits, 32 bits 32 bits) Multiplication and Accumulation (16 bits 16 bits + 32 bits) Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. Total 59 79 CMOS I/O 52 71 CMOS input 5 5 CMOS output 0 1 2 2 N-ch open-drain I/O (6 V tolerance) Timer 16-bit timer TAU 8 channels (Timer outputs: 8, PWM outputs: 7 Note) 8-bit or 16-bit interval 2 channels (8 bits) / 1 channel (16 bits) timer Watchdog timer 1 channel 12-bit interval timer 1 channel Real-time clock 2 1 channel RTC output 1 1 Hz (subsystem clock: fSUB = 32.768 kHz) Note The number of outputs varies, depending on the setting of channels in use and the number of the master. R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 9 of 80 RL78/L1A 1. OUTLINE (2/2) Item 80-pin 100-pin R5F11MMx (x = D to F) R5F11MPx (x = E to G) 2 2 Clock output/buzzer output * 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) * 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 12-bit resolution A/D converter 10 channels 12-bit resolution D/A converter 2 channels VREFOUT (voltage reference) 2 channels 2.5 V/2.048 V/1.8 V/1.5 V Operational amplifier AMPnO with analog MUX switch 3 channels 3 channels 2 channels (2 in-out/channel) 2 channels (4 in-out/channel) 1 channel 1 channel Comparator Serial interface 14 channels * CSI (SPI supported): 1 channel/UART (LIN-bus supported): 1 channel/simplified I2C: 1 channel * CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel * CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel * CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel I2C bus LCD controller/driver 1 channel 1 channel Internal voltage boosting method, capacitor split method, and external resistance division method are switchable. Segment signal output 32 (28) Note 1 Common signal output 45 (41) Note 1 4 (8) Note 1 Data transfer controller (DTC) Event link controller (ELC) 30 sources 30 sources Event input: 22, Event trigger output: 8 Event input: 22, Event trigger output: 8 Vectored interrupt Internal 31 31 sources External 9 9 8 8 Key interrupt Reset * * * * Reset by RESET pin Internal reset by watchdog timer Internal reset by power-on-reset Internal reset by voltage detector * Internal reset by illegal instruction execution Note 2 * Internal reset by RAM parity error * Internal reset by illegal-memory access Power-on-reset circuit * Power-on-reset: 1.51 0.04 V * Power-down-reset: 1.50 0.04 V Voltage detector * Rising edge: 1.88 V to 3.13 V (10 stages) * Falling edge: 1.84 V to 3.06 V (10 stages) On-chip debug function Provided Power supply voltage VDD = 1.8 to 3.6 V Operating ambient temperature TA = -40 to +85 C (A: Consumer applications) Note 1. Note 2. The number in parentheses indicates the number of signal outputs when 8 coms are used. The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug emulator. R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 10 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) This chapter describes the electrical specifications for the products A: Consumer applications (TA = -40 to +85 C). Caution 1. The RL78 microcontroller has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. Caution 2. The pins mounted depend on the product. Refer to 2.1 Port Function to 2.2.1 With functions for each product in the RL78/L1A User's Manual. R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 11 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) 2.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Symbols Conditions VDD AVDD REGC pin input voltage (1/3) VIREGC AVDD VDD REGC Ratings Unit -0.5 to +6.5 V -0.5 to +4.6 V -0.3 to +2.8 V and -0.3 to VDD + 0.3 Note 1 Input voltage VI1 P00 to P07, P11 to P17, P30 to P37, P40 to P44, -0.3 to VDD + 0.3 Note 2 V P50 to P57, P70 to P77, P80, P81, P125 to P127, P137, EXCLK, EXCLKS, RESET VI2 P60, P61 (N-ch open-drain) VI4 IVCMP0 VI5 P20, P21, P23 to P27, P100, P101, P103 to -0.3 to +6.5 V -0.7 to VDD + 0.7 V -0.3 to AVDD + 0.3 Note 3 V -0.3 to VDD + 0.3 Note 2 V -0.3 to AVDD + 0.3 Note 3 V -0.3 to AVDD + 0.3 V P107, P140 to P143, P150, P152 to P154 Output voltage VO1 P00 to P07, P11 to P17, P30 to P37, P40 to P44, P50 to P57, P60, P61, P70 to P77, P80, P81, P125 to P127,P130 Analog input voltage VO2 P20, P21, P23 to P27, P100, P101, P103 to P107, P140 to P143, P150, P152 to P154 VAI1 ANI0 to ANI13 and AVREF(+) + 0.3 Note 1. Note 2. Note 3. Note 4. Caution Notes 2, 4 Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. Must be 6.5 V or lower. Must be 4.6 V or lower. Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. Remark 2. AVREF (+): + side reference voltage of the A/D converter. Remark 3. VSS: Reference voltage R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 12 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) Absolute Maximum Ratings (TA = 25C) Parameter LCD voltage Note 1. Note 2. Caution (2/3) Symbols Conditions Ratings Unit VLI1 VL1 input voltage Note 1 -0.3 to +2.8 V VLI2 VL2 input voltage Note 1 -0.3 to +6.5 V VLI3 VL3 input voltage Note 1 -0.3 to +6.5 V VLI4 VL4 input voltage Note 1 -0.3 to +6.5 V VLI5 CAPL, CAPH input voltage Note 1 -0.3 to +6.5 V VLO1 VL1 output voltage -0.3 to +2.8 V VLO2 VL2 output voltage -0.3 to +6.5 V VLO3 VL3 output voltage -0.3 to +6.5 V VLO4 VL4 output voltage -0.3 to +6.5 V VLO5 CAPL, CAPH output voltage -0.3 to +6.5 VLO6 COM0 to COM7 External resistance division method SEG0 to SEG44 output voltage Capacitor split method Internal voltage boosting method V -0.3 to VDD + 0.3 Note 2 V -0.3 to VDD + 0.3 Note 2 V -0.3 to VLI4 + 0.3 Note 2 V This value only indicates the absolute maximum ratings when applying voltage to the VL1, VL2, VL3, and VL4 pins; it does not mean that applying voltage to these pins is recommended. When using the internal voltage boosting method or capacitance split method, connect these pins to VSS via a capacitor (0.47 30%) and connect a capacitor (0.47 30%) between the CAPL and CAPH pins. Must be 6.5 V or lower. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 13 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) Absolute Maximum Ratings (TA = 25C) Parameter Output current, high (3/3) Symbols IOH1 IOH2 Conditions Ratings Unit -40 mA Total of all P40 to P44 -70 mA pins -100 mA -170 mA P00 to P07, P11 to P17, P30 to P37, P50 to P57, P70 to P77, P80, P81, P125 to P127, P130 Per pin P20, P21, P23 to P27, P100, P101, P103 to P107, -0.1 mA -1.6 Note mA Per pin 40 mA Total of all P40 to P44 70 mA pins 170 mA 100 mA 0.4 mA Per pin Total of all P140 to P143, P150, P152 to P154 pins Output current, low IOL1 P00 to P07, P11 to P17, P30 to P37, P50 to P57, P60, P61, P70 to P77, P80, P81, P125 to P127, P130 IOL2 Per pin P20, P21, P23 to P27, P100, P101, P103 to P107, Total of all P140 to P143, P150, P152 to P154 6.4 mA Note pins Operating ambient temperature TA Storage temperature Tstg Note Caution In normal operation mode -40 to +85 C -65 to +150 C In flash memory programming mode Do not exceed the rated values when outputting the current simultaneously 16 pins at maximum. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 14 of 80 RL78/L1A 2.2 2.2.1 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) Oscillator Characteristics X1 and XT1 oscillator characteristics (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V) Parameter Resonator Conditions MIN. MAX. Unit X1 clock oscillation frequency (fX) Ceramic resonator/crystal resonator 2.7 V VDD 3.6 V 1.0 20.0 MHz 2.4 V VDD < 2.7 V 1.0 16.0 1.8 V VDD < 2.4 V 1.0 8.0 Note XT1 clock oscillation frequency Crystal resonator 32 TYP. 32.768 35 kHz (fXT) Note Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark When using the X1 and XT1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/L1A User's Manual. R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 15 of 80 RL78/L1A 2.2.2 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) On-chip oscillator characteristics (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V) Oscillators High-speed on-chip oscillator clock fre- Symbol fHOCO quency Notes 1, 2 High-speed on-chip oscillator clock frequency accuracy Low-speed on-chip oscillator clock fre- Conditions MIN. TYP. MAX. Unit 2.7 V VDD 3.6 V 1 24 MHz 2.4 V VDD 3.6 V 1 16 MHz 1.8 V VDD 3.6 V 1 8 MHz +1.0 % -20 to +85C 1.8 V VDD 3.6 V -1.0 -40 to -20C 1.8 V VDD 3.6 V -1.5 +1.5 15 fIL % kHz quency Low-speed on-chip oscillator clock fre- -15 +15 % quency accuracy Note 1. High-speed on-chip oscillator frequency is selected with bits 0 to 4 of the option byte (000C2H/010C2H) and bits 0 to 2 of Note 2. the HOCODIV register. This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time. R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 16 of 80 RL78/L1A 2.3 2.3.1 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) DC Characteristics Pin characteristics (TA = -40 to +85 C, 1.8 V AVDD VDD 3.6 V, AVSS = VSS = 0 V) Items Output current, high Symbol Note 1 IOH1 MAX. Unit Per pin for P00 to P07, P11 to P17, Conditions MIN. TYP. -10.0 mA P30 to P37, P40 to P44, P50 to P57, P70 to P77, P80, P81, P125 to P127, Note 2 P130 Total of P00 to P07, P11 to P17, P30 to P37, P40 to P44, P50 to P57, P70 to P77, P80, P81, P125 to P127, P130 2.7 V AVDD VDD -15.0 mA -7.0 mA -0.1 mA 3.6 V 1.8 V AVDD VDD < 2.7 V (When duty = 70% Note 3) IOH2 Per pin for P20, P21, P23 to P27, P100, P101, P103 to P107, P140 to P143, P150, P152 to P154 Total of P20, P21, P23 to P27, P100, P101, P103 to P107, P140 to P143, 1.8 V AVDD VDD 3.6 V 1.8 V AVDD VDD 3.6 V Note 2 -1.6 mA P150, P152 to P154 (When duty = 70% Note 3) Note 1. Note 2. Note 3. Value of current at which the device operation is guaranteed even if the current flows from the VDD pin(IOH1), AVDD pin(IOH2) to an output pin. However, do not exceed the total current value. Specification under conditions where the duty factor is 70%. The output current value that has changed the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). * Total output current of pins = (IOH 0.7)/(n 0.01) <Example> Where n = 50% and IOH = -10.0 mA Total output current of pins = (-10.0 0.7)/(50 0.01) = -14.0 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution P00-P02, P11, P12, P14, P35-P37, P40, P41, P43, P44, P80, P81 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 17 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (TA = -40 to +85 C, 1.8 V AVDD VDD 3.6 V, AVSS = VSS = 0 V) Items Output current, low Note 1 Symbol IOL1 Conditions MIN. TYP. MAX. Unit Per pin for P00 to P07, P11 to P17, 20.0 mA P30 to P37, P40 to P44, P50 to P57, P70 to P77, P80, P81, P125 to P127, Note 2 P130 Per pin for P60 and P61 15.0 mA Note 2 Total of P40 to P44 (When duty = 70% Note 3) Total of P00 to P07, P11 to P17, P30 to P37, P50 to P57, P60, P61, P70 to P77, P80, P81, P125 to P127, P130 2.7 V AVDD VDD 15.0 mA 1.8 V AVDD VDD < 2.7 V 9.0 mA 2.7 V AVDD VDD 3.6 V 35.0 mA 1.8 V AVDD VDD < 2.7 V 20.0 mA 50.0 mA 0.4 mA 3.6 V (When duty = 70% Note 3) Total of all pins (When duty = 70% Note 3) IOL2 Per pin for P20, P21, P23 to P27, P100, P101, P103 to P107, P140 to P143, P150, P152 to P154 1.8 V AVDD VDD 3.6 V Total of P20, P21, P23 to P27, P100, P101, P103 to P107, P140 to P143, 1.8 V AVDD VDD 3.6 V Note 2 6.4 mA P150, P152 to P154 (When duty = 70% Note 3) Note 1. Value of current at which the device operation is guaranteed even if the current flows from an output pin to the VSS pin Note 2. However, do not exceed the total current value. Specification under conditions where the duty factor is 70%. The output current value that has changed the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). * Total output current of pins = (IOL 0.7)/(n 0.01) <Example> Where n = 50% and IOL = 10.0 mA Total output current of pins = (10.0 0.7)/(50 0.01) = 14.0 mA (IOL1), AVSS pin (IOL2). Note 3. However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 18 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (TA = -40 to +85 C, 1.8 V AVDD VDD 3.6 V, AVSS = VSS = 0 V) Items Input voltage, high Symbol Conditions MIN. TYP. MAX. Unit VIH1 Port P00 to P07, P11 to P17, P30 to P37, P40 to P44, P50 to P57, P70 to P77, P80 to P81, P125 to P127 Normal input buffer 0.8 VDD VDD V VIH2 For TTL mode supported ports TTL input buffer 3.3 V VDD 3.6 V 2.0 VDD V TTL input buffer 1.8 V VDD < 3.3 V 1.50 VDD V 0.7 AVDD AVDD V VIH3 P20, P21, P23 to P27, P100, P101, P103 to P107, P140 to P143, P150, P152 to P154 P60, P61 0.7 VDD 6.0 V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8 VDD VDD V VIL1 Port P00 to P07, P11 to P17, P30 to Normal input buffer 0 0.2 VDD V TTL input buffer 3.3 V VDD 3.6 V 0 0.5 V TTL input buffer 1.8 V VDD < 3.3 V 0 0.32 V VIH4 Input voltage, low P37, P40 to P44, P50 to P57, P70 to P77, P80 to P81, P125 to P127 VIL2 Caution For TTL mode supported ports VIL3 P20, P21, P23 to P27, P100, P101, P103 to P107, P140 to P143, P150, P152 to P154 0 0.3 AVDD V VIL4 P60, P61 0 0.3 VDD V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2 VDD V The maximum value of VIH of pins P00 to P02, P11, P12, P14, P35 to P37, P40, P41. P43, P44, P80, P81 is VDD, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 19 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (TA = -40 to +85 C, 1.8 V AVDD VDD 3.6 V, AVSS = VSS = 0 V) Items Output voltage, high Symbol VOH1 Conditions MIN. P00 to P07, P11 to P17, P30 to P37, 2.7 V AVDD VDD P40 to P44, P50 to P57, P70 to P77, P80, P81, P125 to P127, P130 3.6 V, TYP. MAX. Unit VDD - 0.6 V VDD - 0.5 V AVDD - 0.5 V IOH = -2.0 mA 1.8 V AVDD VDD 3.6 V, IOH = -1.5 mA VOH2 Output voltage, low VOL1 VOL2 VOL3 Caution P20, P21, P23 to P27, P100, P101, 1.8 V AVDD VDD P103 to P107, P140 to P143, P150, P152 to P154 3.6 V, IOH = -100 A P00 to P07, P11 to P17, P30 to P37, 2.7 V AVDD VDD P40 to P44, P50 to P57, P70 to P77, P80, P81, P125 to P127, P130 3.6 V, P20, P21, P23 to P27, P100, P101, P103 to P107, P140 to P143, P150, P152 to P154 P60, P61 0.6 V 2.7 V AVDD VDD 3.6 V, IOL = 1.5 mA 0.4 V 1.8 V AVDD VDD 3.6 V, IOL = 0.6 mA 0.4 V 1.8 V AVDD VDD 0.4 V 2.7 V AVDD VDD 3.6 V, IOL = 3.0 mA 0.4 V 1.8 V AVDD VDD 3.6 V, IOL = 2.0 mA 0.4 V IOL = 3.0 mA 3.6 V, IOL = 400 A P00 to P02, P11, P12, P14, P35 to P37, P40, P41. P43, P44, P80, P81 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 20 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (TA = -40 to +85 C, 1.8 V AVDD VDD 3.6 V, AVSS = VSS = 0 V) Items Symbol Input leakage ILIH1 Conditions P00 to P07, P11 to P17, P30 to P37, MIN. TYP. MAX. Unit 1 A 1 A 10 A VI = AVDD 1 A VI = VSS -1 A VI = VSS In input port or external clock input -1 A In resonator connection -10 A -1 A k VI = VDD P40 to P44, P50 to P57, P60, P61, P70 to P77, P80, P81, P125 to P127, current, high P137,_RESET ILIH3 P121 to P124 (X1, X2, EXCLK, XT1, VI = VDD In input port or exter- XT2, EXCLKS) nal clock input In resonator connection ILIH4 P20, P21, P23 to P27, P100, P101, P103 to P107, P140 to P143, P150, P152 to P154 Input leakage current, low ILIL1 P00 to P07, P11 to P17, P30 to P37, P40 to P44, P50 to P57, P60, P61, P70 to P77, P80, P81, P125 to P127, P137,_RESET ILIL3 ILIL4 P121 to P124 (X1, X2, EXCLK, XT1, XT2, EXCLKS) P20, P21, P23 to P27, P100, P101, VI = AVSS P103 to P107, P140 to P143, P150, P152 to P154 On-chip pull-up resistance RU1 RU2 Remark P00 to P07, P11 to P17, P30 to P37, P50 to P57, P70 to P77, P80, P81, P125 to P127 VI = VSS 2.4 V VDD 3.6 V 10 20 100 1.8 V VDD < 2.4 V 10 30 100 P40 to P44 VI = VSS 10 20 100 k Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 21 of 80 RL78/L1A 2.3.2 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) Supply current characteristics (TA = -40 to +85 C, 1.8 V AVDD VDD 3.6 V, VSS = 0 V) Parameter Supply current Note 1 Symbol IDD1 (1/2) Conditions Operating HS fIH = 24 MHz Note 3 mode (high-speed main) MIN. TYP. MAX. Basic operation VDD = 3.6 V 1.7 VDD = 3.0 V 1.7 Normal operation VDD = 3.6 V 3.6 6.1 VDD = 3.0 V 3.6 6.1 Normal operation VDD = 3.6 V 2.7 4.7 VDD = 3.0 V 2.7 4.7 Normal operation VDD = 3.6 V 1.2 2.1 VDD = 3.0 V 1.2 2.1 HS fMX = 20 MHz Note 2, (high-speed main) VDD = 3.6 V mode Note 5 fMX = 20 MHz Note 2, VDD = 3.0 V Normal operation Square wave input 3.0 5.1 Resonator connection 3.2 5.2 Normal operation Square wave input 2.9 5.1 Resonator connection 3.2 5.2 fMX = 16 MHz Note 2, VDD = 3.6 V Normal operation Square wave input 2.5 4.4 Resonator connection 2.7 4.5 fMX = 16 MHz Note 2, VDD = 3.0 V Normal operation Square wave input 2.5 4.4 Resonator connection 2.7 4.5 fMX = 10 MHz Note 2, VDD = 3.6 V Normal operation Square wave input 1.9 3.0 Resonator connection 1.9 3.0 fMX = 10 MHz Note 2, VDD = 3.0 V Normal operation Square wave input 1.9 3.0 Resonator connection 1.9 3.0 fMX = 8 MHz Note 2, VDD = 3.6 V Normal operation Square wave input 1.1 2.0 Resonator connection 1.1 2.0 fMX = 8 MHz Note 2, VDD = 3.0 V Normal operation Square wave input 1.1 2.0 Resonator connection 1.1 2.0 fSUB = 32.768 kHz Note 4 TA = -40C Normal operation Square wave input 4.0 5.4 Resonator connection 4.3 5.4 fSUB = 32.768 kHzNote 4 TA = +25C Normal operation Square wave input 4.0 5.4 Resonator connection 4.3 5.4 fSUB = 32.768 kHzNote 4 TA = +50C Normal operation Square wave input 4.1 7.1 Resonator connection 4.4 7.1 fSUB = 32.768 kHzNote 4 TA = +70C Normal operation Square wave input 4.3 8.7 Resonator connection 4.7 8.7 fSUB = 32.768 kHzNote 4 TA = +85C Normal operation Square wave input 4.7 12.0 Resonator connection 5.2 12.0 mode Note 5 fIH = 16 MHz Note 3 LS (low-speed main) fIH = 8 MHz Note 3 mode Note 5 LS (low-speed main) mode Note 5 Subsystem clock operation Unit mA mA mA mA A (Notes and Remarks are listed on the next page.) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 22 of 80 RL78/L1A Note 1. Note 2. Note 3. Note 4. Note 5. 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD, or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the LCD controller/driver, A/D converter, D/A converter, rail to rail OPA(with analog MUX), General-purpose OPA, voltage reference, low-resistance switch, comparator, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. When high-speed on-chip oscillator and subsystem clock are stopped. When high-speed system clock and subsystem clock are stopped. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). However, not including the current flowing into the real-time clock 2, 12-bit interval timer, 8-bit interval timer, and watchdog timer. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 3.6 V@1 MHz to 24 MHz 2.4 V VDD 3.6 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V VDD 3.6 V@1 MHz to 8 MHz Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Frequency when the high-speed on-chip oscillator (24 MHz max.) Remark 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C Remark 2. fIH: R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 23 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (TA = -40 to +85 C, 1.8 V AVDD VDD 3.6 V, VSS = 0 V) Parameter Symbol Conditions Supply current IDD2 HALT mode Note 2 (2/2) MIN. HS (high-speed main) fIH = 24 MHz Note 4 mode Note 7 Note 1 0.42 1.83 1.38 0.39 1.38 VDD = 3.0 V 0.25 0.71 mode Note 7 VDD = 2.0 V 0.25 0.71 HS (high-speed main) fMX = 20 MHz Note 3, VDD = 3.6 V mode Note 7 Square wave input 0.26 1.55 Resonator connection 0.4 1.68 fMX = 20 MHz Note 3, VDD = 3.0 V Square wave input 0.25 1.55 Resonator connection 0.4 1.68 Square wave input 0.23 1.22 Resonator connection 0.36 1.39 Square wave input 0.22 1.22 Resonator connection 0.35 1.39 0.82 fIH = 8 MHz Note 4 Note 3, fMX = 16 MHz Note 3, VDD = 3.0 V fMX = 10 MHz VDD = 3.0 V Note 3, fMX = 10 MHz Note 3, VDD = 2.0 V LS (low-speed main) mode Note 7 fMX = 8 MHz VDD = 3.0 V Note 3, Square wave input 0.18 Resonator connection 0.28 0.90 Square wave input 0.18 0.81 Resonator connection 0.28 0.89 Square wave input 0.09 0.51 Resonator connection 0.15 0.56 Square wave input 0.10 0.52 Resonator connection 0.15 0.57 Square wave input 0.32 0.75 Resonator connection 0.51 0.83 fSUB = 32.768 kHz Note 5 Square wave input TA = +25C Resonator connection 0.41 0.83 0.62 1.00 Square wave input 0.52 1.17 Resonator connection 0.75 1.36 fSUB = 32.768 kHz Note 5 Square wave input TA = +70C Resonator connection 0.82 1.97 1.08 2.16 Square wave input 1.38 3.37 Resonator connection 1.62 3.56 TA = -40C 0.16 0.51 TA = +25C 0.22 0.51 TA = +50C 0.27 1.10 TA = +70C 0.37 1.90 TA = +85C 0.6 3.30 fMX = 8 MHz Note 3, VDD = 2.0 V Subsystem clock operation fSUB = 32.768 kHz TA = -40C fSUB = 32.768 kHz TA = +50C fSUB = 32.768 kHz TA = +85C Note 8 mA VDD = 3.0 V 0.39 fMX = 16 MHz VDD = 3.6 V Note 6 Unit 1.83 VDD = 5.0 V LS (low-speed main) STOP mode MAX. 0.42 VDD = 3.0 V fIH = 16 MHz Note 4 IDD3 TYP. VDD = 3.6 V Note 5 Note 5 Note 5 mA mA mA A A (Notes and Remarks are listed on the next page.) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 24 of 80 RL78/L1A Note 1. 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the LCD controller/driver, A/D converter, D/A converter, ail to rail OPA(with analog MUX), General-purpose OPA, voltage reference, low-resistance switch, comparator, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Note 8. and the current flowing during data flash rewrite. During HALT instruction execution by flash memory. When high-speed on-chip oscillator and subsystem clock are stopped. When high-speed system clock and subsystem clock are stopped. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the real-time clock 2 is included. However, not including the current flowing into the 12-bit interval timer, 8-bit interval timer, and watchdog timer. Not including the current flowing into the real-time clock 2, 12-bit interval timer, 8-bit interval timer, and watchdog timer. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 3.6 V@1 MHz to 24 MHz 2.4 V VDD 3.6 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V VDD 3.6 V@1 MHz to 8 MHz Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Frequency when the high-speed on-chip oscillator (24 MHz max.) Remark 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C Remark 2. fIH: R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 25 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (TA = -40 to +85 C, 1.8 V AVDD VDD 3.6 V, VSS = 0 V) Parameter Low-speed on-chip oscillator operating current RTC2 operating current 12-bit interval timer operating current Symbol Conditions IRTC MIN. TYP. MAX. Unit 0.20 A fSUB = 32.768 kHz 0.02 A fSUB = 32.768 kHz 0.02 A 8-bit counter mode 2-channel operation 0.12 A 16-bit counter mode operation 0.10 A A IFIL Note 1 Notes 1, 3 ITMKA Notes 1, 2, 4 8-bit interval timer operating current Notes 1, 20 fSUB = 32.768 kHz Watchdog timer operating current IWDT fIL = 15 kHz 0.22 Notes 1, 5 A/D converter operating current AVDD = 3.0 V, when conversion at maximum speed 0.7 1.7 mA Notes 6, 7 40 80 A 40 80 ITMRT IADC A/D converter AVREF(+) current IAVREF Note 8 AVDD = 3.0 V, HVSEL[1:0] = 00B Note 7 Internal reference voltage (1.45 V) current IADREF Temperature sensor operating current ITMPS Note 1 D/A converter operating current D/A converter AVREF(+) current Comparator operating current AVDD = 3.0 V, HVSEL[1:0] = 01B 85 A 85 A Notes 1, 9 IDAC Per D/A converter channel 0.4 0.8 mA AVREFP = 3.0 V, REF[2:0] = 110B, Per channel 35 80 A VDD = 3.6 V, Regulator output voltage = 2.1 V Window mode 7.0 A Comparator high-speed mode 2.6 A Comparator low-speed mode 1.2 A VDD = 3.6 V, Regulator output voltage = 1.8 V Window mode 4.10 A Comparator high-speed mode 1.5 A Comparator low-speed mode 0.9 A Notes 7, 11 IDAREF Note 10 ICMP Notes 1, 12 General-purpose IAMP1 operational ampli- Notes 7, 19 fier operating current (for 1 unit) AVDD = 3.0 Rail to rail operational amplifier operating current (for 1 unit) IAMP2 AVDD = 3.0 LVD operating current ILVI Self-programming operating current Note 10 Notes 7, 19 2 4 A High-speed mode 140 280 A Low-power consumption mode 10 16 A High-speed mode 210 350 A Low-power consumption mode A 0.06 Notes 1, 13 IFSP 2.0 12.2 mA 2.0 12.2 mA 0.70 0.84 mA 40 A Notes 1, 14 BGO operating current IBGO SNOOZE operating current ISNOZ Note 1 CSI/UART operation Voltage reference IVREF AVDD = VDD = 3.0 V Notes 1, 15 R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 26 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (TA = -40 to +85 C, 1.8 V AVDD VDD 3.6 V, VSS = 0 V) Parameter LCD operating current Symbol ILCD1 Notes 17, 18 ILCD2 Note 17 ILCD3 Note 17 Conditions MIN. TYP. MAX. Unit External resistance division method fLCD = fSUB LCD clock = 128 Hz 1/3 bias VDD = 3.6 V, 4-time slice VL4 = 3.6 V 0.14 A Internal voltage boosting method fLCD = fSUB LCD clock = 128 Hz 1/3 bias 4-time slice VDD = 3.0 V, VL4 = 3.0 V (VLCD = 04H) 0.61 A Capacitor split method fLCD = fSUB LCD clock = 128 Hz 1/3 bias 4-time slice VDD = 3.0 V, VL4 = 3.0 V 0.12 A (Notes and Remarks are listed on the next page.) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 27 of 80 RL78/L1A Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Note 8. Note 9. Note 10. Note 11. Note 12. Note 13. Note 14. Note 15. Note 16. Note 17. Note 18. Note 19. Note 20. 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) Current flowing to VDD. When high speed on-chip oscillator and high-speed system clock are stopped. Current flowing only to the real-time clock 2 (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IRTC, when the real-time clock 2 operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock 2. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and ITMKA, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the 12-bit interval timer. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates in STOP mode. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC, IAVREF, IADREF when the A/D converter operates in an operation mode or the HALT mode. Current flowing to the AVDD. Current flowing from the reference voltage source of A/D converter. Operation current flowing to the internal reference voltage. Current flowing to the AVREFP. Current flowing only to the D/A converter. The current value of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IDA when the D/A converter operates in an operation mode or the HALT mode. Current flowing only to the comparator circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ICMP when the comparator circuit operates in the Operating, HALT or STOP mode. Current flowing only to the LVD circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVI when the LVD circuit operates in the Operating, HALT or STOP mode. Current flowing only during self-programming. Current flowing only during data flash rewrite. For shift time to the SNOOZE mode, see 24.3.3 SNOOZE mode in the RL78/L1A User's Manual.RL78 microcontrollers Current flowing only to the LCD controller/driver (VDD pin). The current value of the RL78 microcontrollers is the sum of the LCD operating current (ILCD1, ILCD2 or ILCD3) to the supply current (IDD1, or IDD2) when the LCD controller/driver operates in an operation mode or HALT mode. Not including the current that flows through the LCD panel. Not including the current that flows through the external divider resistor divider resistor. Current flowing only to the operational amplifier. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IAMP when the operational amplifier operates in the operating mode, HALT mode, or STOP mode. Current flowing only to the 8-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT, when the 8-bit interval timer operates in the operating mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 3. fCLK: CPU/peripheral hardware clock frequency Remark 4. Temperature condition of the TYP. value is TA = 25C R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 28 of 80 RL78/L1A 2.4 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) AC Characteristics 2.4.1 Basic operation (TA = -40 to +85 C, 1.8 V AVDD VDD 3.6 V, VSS = 0 V) Items Symbol Conditions imum instruction exe- Main system clock (fMAIN) cution time) operation Instruction cycle (min- TCY MAX. Unit HS (high-speed main) 2.7 V VDD 3.6 V 0.0417 MIN. TYP. 1 s mode 2.4 V VDD < 2.7 V 0.0625 1 s LS (low-speed main) 1.8 V VDD 3.6 V 0.125 1 s mode Subsystem clock (fSUB) operation 1.8 V VDD 3.6 V 28.5 31.3 s In the self- HS (high-speed main) 2.7 V VDD 3.6 V 0.0417 1 s program- mode 2.4 V VDD < 2.7 V 0.0625 1 s LS (low-speed main) 1.8 V VDD 3.6 V 0.125 1 s 2.7 V VDD 3.6 V 1.0 20.0 MHz 2.4 V VDD < 2.7 V 1.0 16.0 MHz 1.8 V VDD < 2.7 V 1.0 8.0 MHz 32 35 kHz ming mode 30.5 mode External main system fEX EXCLK clock frequency External main system clock input high-level width, low-level width fEXT EXCLKS tEXH, tEXL EXCLK tEXHS, tEXLS tTIH, tTIL TI00 to TI07 Timer output frequency fTO fPCL 24 ns 2.4 V VDD < 2.7 V 30 ns 1.8 V VDD < 2.7 V 60 ns 13.7 s 1/fMCK + 10 ns EXCLKS Timer input high-level width, low-level width Buzzer output frequency 2.7 V VDD 3.6 V TO00 to TO07 PCLBUZ0, PCLBUZ1 HS (high-speed main) mode 2.7 V VDD 3.6 V 8 MHz 2.4 V VDD < 2.7 V 8 MHz LS (low-speed main) mode 1.8 V VDD 3.6 V 4 MHz HS (high-speed main) mode 2.7 V VDD 3.6 V 8 MHz 2.4 V VDD < 2.7 V 8 MHz LS (low-speed main) mode 1.8 V VDD 3.6 V 4 MHz Interrupt input highlevel width, low-level width tINTH, tINTL INTP0 to INTP7 1.8 V VDD 3.6 V 1 s Key interrupt input low-level width tKR KR0 to KR7 1.8 V VDD 3.6 V 250 ns RESET low-level width tRSL RESET 10 s Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0), n: Channel number (n = 0 to 7)) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 29 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) 10 1.0 Cycle time TCY [s] When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.1 0.0625 0.05 0.0417 0.01 0 1.0 2.0 3.0 4.0 2.4 2.7 3.6 5.0 6.0 Supply voltage VDD [V] R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 30 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) TCY vs VDD (LS (low-speed main) mode) 10 When the high-speed on-chip oscillator clock is selected Cycle time TCY [s] 1.0 During self programming When high-speed system clock is selected 0.125 0.1 0.01 0 1.0 2.0 1.8 4.0 3.0 5.0 6.0 3.6 Supply voltage VDD [V] R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 31 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL External System Clock Timing 1/fEX 1/fEXS tEXL tEXLS tEXH tEXHS EXCLK/EXCLKS TI/TO Timing tTIL tTIH TI00 to TI07 1/fTO TO00 to TO07 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP7 R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 32 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) Key Interrupt Input Timing tKR KR0 to KR7 RESET Input Timing tRSL RESET R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 33 of 80 RL78/L1A 2.5 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) Peripheral Functions Characteristics AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL 2.5.1 Serial array unit (1) During communication at same potential (UART mode) (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V) Parameter Transfer rate Note 1 Symbol Conditions HS (high-speed main) Mode MIN. 2.7 V VDD 3.6 V MAX. LS (low-speed main) Mode MIN. MAX. Unit fMCK/6 Note 2 fMCK/6 bps 4.0 1.3 Mbps fMCK/6 Note 2 fMCK/6 bps 2.6 1.3 Mbps -- fMCK/6 Note 2 bps -- 1.3 Mbps Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 2.4 V VDD 3.6 V Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 1.8 V VDD 3.6 V Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 Note 1. Transfer rate in the SNOOZE mode is 4800 bps only. Note 2. The following conditions are required for low voltage interface. 2.4 V VDD < 2.7 V: MAX. 2.6 Mbps 1.8 V VDD < 2.4 V: MAX. 1.3 Mbps Note 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V VDD 3.6 V) LS (low-speed main) mode: 8 MHz (1.8 V VDD 3.6 V) 16 MHz (2.4 V VDD 3.6 V) Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 34 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) UART mode connection diagram (during communication at same potential) TxDq Rx RL78 microcontroller User's device RxDq Tx UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Remark 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3, 4, 8) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 35 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = -40 to +85 C, 2.7 V VDD 3.6 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time tKCY1 tKCY1 fCLK/2 SCKp high-/low-level width tKL1 SIp setup time (to SCKp) Note 1 SIp hold time (from SCKp) Note 2 2.7 V VDD 3.6 V MAX. LS (low-speed main) Mode MIN. Unit MAX. 167 250 ns 2.7 V VDD 3.6 V tKCY1/2 - 10 tKCY1/2 - 50 ns tSIK1 2.7 V VDD 3.6 V 33 110 ns tKSI1 2.7 V VDD 3.6 V 10 Delay time from SCKp to SOp out- tKSO1 C = 20 pF Note 4 10 10 ns 10 ns put Note 3 Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using Note 1. Note 2. Note 3. port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 4) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 36 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time tKCY1 tKCY1 fCLK/4 SIp setup time (to SCKp) Note 1 SIp hold time (from SCKp) Note 2 tSIK1 tKSI1 Delay time from SCKp to SOp out- tKSO1 MAX. MIN. Unit MAX. 2.7 V VDD 3.6 V 167 500 ns 2.4 V VDD 3.6 V 250 500 ns 1.8 V VDD 3.6 V tKH1, tKL1 SCKp high-/low-level width LS (low-speed main) Mode -- 500 ns 2.7 V VDD 3.6 V tKCY1/2 - 18 tKCY1/2 - 50 ns 2.4 V VDD 3.6 V tKCY1/2 - 38 tKCY1/2 - 50 ns 1.8 V VDD 3.6 V -- tKCY1/2 - 50 ns 2.7 V VDD 3.6 V 44 110 ns 2.4 V VDD 3.6 V 75 110 ns 1.8 V VDD 3.6 V -- 110 ns 2.4 V VDD 3.6 V 19 19 ns 1.8 V VDD 3.6 V -- C = 30 pF Note 4 put Note 3 19 ns 2.7 V VDD 3.6 V 25 50 ns 2.4 V VDD 3.6 V 25 50 ns 1.8 V VDD 3.6 V -- 50 ns Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using Note 1. Note 2. Note 3. port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 10, 20, 30), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0, 1, 3, 4, 8) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 37 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. tKCY2 SCKp cycle time Note 5 SCKp high-/low-level width tKH2, tKL2 SIp setup time (to SCKp) Note 1 SIp hold time (from SCKp) Note 2 tSIK2 tKSI2 2.7 V VDD 3.6 V tKSO2 Note 2. Note 3. Note 4. Note 5. Caution MIN. Unit MAX. fMCK 16 MHz 8/fMCK -- ns 6/fMCK 6/fMCK ns 2.4 V VDD 3.6 V 6/fMCK and 500 6/fMCK and 500 ns 1.8 V VDD 3.6 V -- 6/fMCK and 750 ns 2.7 V VDD 3.6 V tKCY2/2 - 8 tKCY2/2 - 8 ns 1.8 V VDD 3.6 V -- tKCY2/2 - 18 ns 2.7 V VDD 3.6 V 1/fMCK + 20 1/fMCK + 30 ns 2.4 V VDD 3.6 V 1/fMCK + 30 1/fMCK + 30 ns 1.8 V VDD 3.6 V -- 1/fMCK + 30 ns 2.4 V VDD 3.6 V 1/fMCK + 31 1/fMCK + 31 ns C = 30 pF Note 4 -- 1/fMCK + 31 ns 2.7 V VDD 3.6 V 2/fMCK + 44 2/fMCK + 110 ns 2.4 V VDD 3.6 V 2/fMCK + 75 2/fMCK + 110 ns 1.8 V VDD 3.6 V -- 2/fMCK + 110 ns output Note 3 Note 1. MAX. fMCK 16 MHz 1.8 V VDD 3.6 V Delay time from SCKp to SOp LS (low-speed main) Mode When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SCKp and SOp output lines. The maximum transfer rate when using the SNOOZE mode is 1 Mbps. Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 10, 20, 30), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0, 1, 3, 4, 8) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 38 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) CSI mode connection diagram (during communication at same potential) SCKp RL78 microcontroller SIp SOp SCK SO User's device SI Remark 1. p: CSI number (p = 00, 10, 20, 30) Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 39 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1, 2 tKH1, 2 tKL1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 Output data SOp CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Output data Remark 1. p: CSI number (p = 00, 10, 20, 30) Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 40 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (5) During communication at same potential (simplified I2C mode) (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCLr clock frequency Hold time when SCLr = "L" Hold time when SCLr = "H" Data setup time (reception) Data hold time (transmission) Note 1. Note 2. Caution fSCL tLOW tHIGH tSU: DAT tHD: DAT MAX. LS (low-speed main) Mode MIN. Unit MAX. 2.7 V VDD 3.6 V, Cb = 50 pF, Rb = 2.7 k 1000 Note 1 400 Note 1 kHz 1.8 V VDD 3.6 V, Cb = 100 pF, Rb = 3 k 400 Note 1 400 Note 1 kHz 1.8 V VDD 2.7 V, Cb = 100 pF, Rb = 5 k 300 Note 1 300 Note 1 kHz 2.7 V VDD 3.6 V, Cb = 50 pF, Rb = 2.7 k 475 1150 ns 1.8 V VDD 3.6 V, Cb = 100 pF, Rb = 3 k 1150 1150 ns 1.8 V VDD 2.7 V, Cb = 100 pF, Rb = 5 k 1550 1550 ns 2.7 V VDD 3.6 V, Cb = 50 pF, Rb = 2.7 k 475 1150 ns 1.8 V VDD 3.6 V, Cb = 100 pF, Rb = 3 k 1150 1150 ns 1.8 V VDD 2.7 V, Cb = 100 pF, Rb = 5 k 1550 1550 ns 2.7 V VDD 3.6 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 85 1/fMCK + 145 ns Note 2 Note 2 1.8 V VDD 3.6 V, Cb = 100 pF, Rb = 3 k 1/fMCK + 145 1/fMCK + 145 Note 2 Note 2 1.8 V VDD 2.7 V, Cb = 100 pF, Rb = 5 k 1/fMCK + 230 1/fMCK + 230 Note 2 Note 2 2.7 V VDD 3.6 V, Cb = 50 pF, Rb = 2.7 k 0 305 0 305 ns 1.8 V VDD 3.6 V, Cb = 100 pF, Rb = 3 k 0 355 0 355 ns 1.8 V VDD 2.7 V, Cb = 100 pF, Rb = 5 k 0 405 0 405 ns ns ns The value must also be equal to or less than fMCK/4. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh). R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 41 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) Simplified I2C mode connection diagram (during communication at same potential) VDD Rb SDAr SDA RL78 microcontroller User's device SCLr SCL Simplified I2C mode serial transfer timing (during communication at same potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD: DAT tSU: DAT Remark 1. Rb[]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SCLr, SDAr) load capacitance Remark 2. r: IIC number (r = 00, 10, 20, 30), g: PIM number (g = 0, 1, 3, 4, 8), h: POM number (h = 0 to 3) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00 to 03, 10 to 13) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 42 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (6) Communication at different potential (1.8 V, 2.5 V) (UART mode) (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V)(1/2) Parameter Symbol Conditions HS (high-speed main) Mode MIN. Transfer rate reception Notes 1, 2 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V MAX. LS (low-speed main) Mode MIN. Unit MAX. fMCK/6 Note 1 fMCK/6 Note 1 bps 4.0 1.3 Mbps bps Theoretical value of the maximum transfer rate fMCK = fCLK Note 4 1.8 V VDD 3.3 V, 1.6 V Vb 2.0 V fMCK/6 fMCK/6 Notes 1, 2, 3 Notes 1, 2, 3 4.0 1.3 Theoretical value of the maximum transfer rate Mbps fMCK = fCLK Note 4 Note 1. Note 2. Note 3. Note 4. Caution Transfer rate in the SNOOZE mode is 4,800 bps only. Use it with VDD Vb. The following conditions are required for low voltage interface. MAX. 2.6 Mbps 2.4 V VDD 2.7 V: MAX. 1.3 Mbps 1.8 V VDD 2.4 V: The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V VDD 3.6 V) 16 MHz (2.4 V VDD 3.6 V) LS (low-speed main) mode: 8 MHz (1.8 V VDD 3.6 V) Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3, 4, 8) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 43 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (6) Communication at different potential (1.8 V, 2.5 V) (UART mode) (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V)(2/2) Parameter Transfer rate Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode MIN. MIN. transmission 2.7 V VDD 3.6 V, MAX. Unit MAX. Note 1 Note 1 bps 1.2 Note 2 1.2 Note 2 Mbps Notes 3, 4 Notes 3, 4 bps 0.43 Note 5 0.43 Note 5 Mbps 2.3 V Vb 2.7 V Note 2 Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V 1.8 V VDD 3.3 V, 1.6 V Vb 2.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V Note 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V VDD 3.6 V and 2.3 V Vb 2.7 V 1 Maximum transfer rate = 2.0 {-Cb Rb In (1 )} 3 Vb 1 Transfer rate 2 [bps] - {-Cb Rb In (1 - 2.0 )} Vb 100 [%] Baud rate error (theoretical value) = ( 1 Transfer rate ) Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. Note 2. Note 3. Note 4. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. Use it with VDD Vb. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V VDD < 3.3 V and 1.6 V Vb 2.0 V 1 Maximum transfer rate = [bps] 1.5 )} 3 {-Cb Rb In (1 Vb 1 Transfer rate 2 - {-Cb Rb In (1 - 1.5 )} Vb 100 [%] Baud rate error (theoretical value) = ( 1 Transfer rate ) Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. Note 5. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 44 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) UART mode connection diagram (during communication at different potential) Vb Rb TxDq Rx RL78 microcontroller User's device RxDq Tx UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remark 1. Rb[]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3, 4, 8) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 45 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (7) Communication at different potential (2.5 V) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = -40 to +85 C, 2.7 V VDD 3.6 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time tKCY1 tKCY1 2/fCLK 2.7 V VDD 3.6 V, MAX. LS (low-speed main) Mode MIN. Unit MAX. 300 1150 ns tKCY1/2 - 120 tKCY1/2 - 120 ns tKCY1/2 - 10 tKCY1/2 - 50 ns 121 479 ns 10 10 ns 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 1.4 k SCKp high-level width tKH1 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SCKp low-level width tKL1 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 1.4 k SIp setup time tSIK1 (to SCKp) Note 1 SIp hold time 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k tKSI1 (from SCKp) Note 1 Delay time from SCKp to SOp output tKSO1 to SOp output 130 ns tSIK1 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k 33 110 ns tKSI1 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k 10 10 ns tKSO1 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k (from SCKp) Note 2 Delay time from SCKp 130 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 1.4 k (to SCKp) Note 2 SIp hold time 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 1.4 k Note 1 SIp setup time 2.7 V VDD 3.6 V, Note 2 10 10 ns Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin Note 1. and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 4) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 46 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (8) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V)(1/2) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time SCKp high-level width SCKp low-level width tKCY1 tKH1 tKL1 tKCY1 4/fCLK MAX. LS (low-speed main) Mode MIN. Unit MAX. 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 500 Note 1150 ns 1.8 V VDD 3.3 V, 1.6 V Vb 1.8 V, Cb = 30 pF, Rb = 5.5 k 1150 Note 1150 ns 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k tKCY1/2 - 170 tKCY1/2 - 170 ns 1.8 V VDD 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k tKCY1/2 - 458 tKCY1/2 - 458 ns 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k tKCY1/2 - 18 tKCY1/2 - 50 ns 1.8 V VDD 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k tKCY1/2 - 50 tKCY1/2 - 50 ns Note Use it with VDD Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the page after the next page.) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 47 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (8) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V)(2/2) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SIp setup time tSIK1 (to SCKp) Note 1 SIp hold time tKSI1 (from SCKp) Note 1 Delay time from SCKp to SOp tKSO1 output Note 1 SIp setup time tSIK1 (to SCKp) Note 2 SIp hold time tKSI1 (from SCKp) Note 2 Delay time from SCKp tKSO1 to SOp output Note 2 MAX. LS (low-speed main) Mode MIN. Unit MAX. 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 177 479 ns 1.8 V VDD 3.3 V, 1.6 V Vb 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 479 479 ns 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 19 19 ns 1.8 V VDD 3.3 V, 1.6 V Vb 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 19 19 ns 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 195 195 ns 1.8 V VDD 3.3 V, 1.6 V Vb 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 483 483 ns 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 44 110 ns 1.8 V VDD 3.3 V, 1.6 V Vb 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 110 110 ns 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 19 19 ns 1.8 V VDD 3.3 V, 1.6 V Vb 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 19 19 ns 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 25 25 ns 1.8 V VDD 3.3 V, 1.6 V Vb 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 25 25 ns Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Use it with VDD Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin Note 1. Note 2. and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 48 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) CSI mode connection diagram (during communication at different potential) <Master> Vb Vb Rb SCKp RL78 microcontroller Rb SCK SIp SO SOp SI User's device Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 10, 20, 30), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0, 1, 3, 4, 8) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02, 10, 12) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 49 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1 tKL1 tKH1 SCKp tSIK1 tKSI1 Input data SIp tKSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1 tKH1 tKL1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp Remark Output data p: CSI number (p = 00, 10, 20, 30), m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), g: PIM and POM number (g = 0, 1, 3, 4, 8) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 50 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (9) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time Note 1 SCKp high-/low-level width SIp setup time tKCY2 tKH2, tKL2 tSIK2 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V 20 MHz < fMCK 24 MHz ns 16 MHz < fMCK 20 MHz 14/fMCK -- ns 8 MHz < fMCK 16 MHz 12/fMCK -- ns 4 MHz < fMCK 8 MHz 8/fMCK 16/fMCK ns fMCK 4 MHz 6/fMCK 10/fMCK ns 1.8 V VDD < 3.3 V, 20 MHz < fMCK 24 MHz 36/fMCK -- ns 1.6 V Vb 2.0 V Note 2 16 MHz < fMCK 20 MHz 32/fMCK -- ns 8 MHz < fMCK 16 MHz 26/fMCK -- ns 4 MHz < fMCK 8 MHz 16/fMCK 16/fMCK ns fMCK 4 MHz 10/fMCK 10/fMCK ns 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V tKCY2/2 - 18 tKCY2/2 - 50 ns 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 tKCY2/2 - 50 tKCY2/2 - 50 ns 2.7 V VDD 3.6 V 1/fMCK + 20 1/fMCK + 30 ns 1.8 V VDD < 3.3 V 1/fMCK + 30 1/fMCK + 30 ns 1/fMCK + 31 1/fMCK + 31 ns tKSI2 tKSO2 to SOp output Note 5 Note 1. Note 2. Note 3. Note 4. Note 5. Caution Unit MAX. -- (from SCKp) Note 4 Delay time from SCKp MIN. 16/fMCK (to SCKp) Note 3 SIp hold time MAX. LS (low-speed main) Mode 2.7 V VDD 3.6 V, 2.3 V Vb 2.7 V Cb = 30 pF, Rb = 2.7 k 2/fMCK + 214 2/fMCK + 573 ns 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 Cb = 30 pF, Rb = 5.5 k 2/fMCK + 573 2/fMCK + 573 ns Transfer rate in the SNOOZE mode: MAX. 1 Mbps Use it with VDD Vb. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 51 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) CSI mode connection diagram (during communication at different potential) <Slave> Vb Rb SCKp RL78 microcontroller SCK SIp SO SOp SI User's device Remark 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 10, 20, 30), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0, 1, 3, 4, 8) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02, 10, 12)) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 52 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 SCKp tSIK2 tKSI2 Input data SIp tKSO2 SOp Output data CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKH2 tKL2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 SOp Remark Output data p: CSI number (p = 00, 10, 20, 30), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0, 1, 3, 4, 8) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 53 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (10) Communication at different potential (1.8 V, 2.5 V) (simplified I2C mode) (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V) Parameter SCLr clock frequency Hold time when SCLr = "L" Hold time when SCLr = "H" Data setup time (reception) Data hold time (transmission) Symbol fSCL tLOW tHIGH tSU:DAT tHD:DAT Conditions HS (high-speed main) Mode MIN. MAX. LS (low-speed main) Mode MIN. MAX. Unit 2.7 V VDD 3.6 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 1000 Note 1 300 Note 1 kHz 2.7 V VDD 3.6 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 400 Note 1 300 Note 1 kHz 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 400 Note 1 300 Note 1 kHz 2.7 V VDD 3.6 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 475 1550 ns 2.7 V VDD < 3.6 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 1150 1550 ns 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 1550 1550 ns 2.7 V VDD 3.6 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 200 610 ns 2.7 V VDD 3.6 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 600 610 ns 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 610 610 ns 2.7 V VDD 3.6 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 135 1/fMCK + 190 ns Note 3 Note 3 2.7 V VDD 3.6 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 1/fMCK + 190 1/fMCK + 190 Note 3 Note 3 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 1/fMCK + 190 1/fMCK + 190 Note 3 Note 3 ns ns 2.7 V VDD 3.6 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 0 305 0 305 ns 2.7 V VDD 3.6 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 0 355 0 355 ns 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 0 405 0 405 ns Note 1. The value must also be equal to or less than fMCK/4. Note 2. Use it with VDD Vb. Note 3. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 54 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) Simplified I2C mode connection diagram (during communication at different potential) Vb Vb Rb Rb SDAr SDA RL78 microcontroller User's device SCLr SCL Simplified I2C mode serial transfer timing (during communication at different potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD: DAT tSU: DAT Remark 1. Rb[]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage Remark 2. r: IIC number (r = 00, 10, 20, 30), g: PIM, POM number (g = 0, 1, 3, 4, 8) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 02, 10, 12) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 55 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) 2.5.2 Serial interface IICA (1) I2C standard mode (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V) Parameter SCLA0 clock frequency Symbol fSCL Setup time of restart condi- tSU: STA tion Hold time Note 1 tHD: STA Conditions Standard mode: fCLK 1 MHz HS (high-speed main) Mode tLOW Hold time when SCLA0 = "H" tHIGH Data setup time (reception) tSU: DAT Data hold time (transmis- MAX. MIN. MAX. 2.7 V VDD 3.6 V 0 100 0 100 kHz 1.8 V VDD 3.6 V -- -- 0 100 kHz 2.7 V VDD 3.6 V 4.7 1.8 V VDD 3.6 V 2.7 V VDD 3.6 V -- 4.0 tHD: DAT 2.7 V VDD 3.6 V -- 4.7 1.8 V VDD 3.6 V 2.7 V VDD 3.6 V -- 2.7 V VDD 3.6 V 2.7 V VDD 3.6 V Setup time of stop condition tSU: STO Bus-free time tBUF 2.7 V VDD 3.6 V 2.7 V VDD 3.6 V 4.0 s 4.0 s 4.7 s 4.7 s s s 250 ns -- 250 ns 3.45 -- 4.0 1.8 V VDD 3.6 V 1.8 V VDD 3.6 V s 4.0 0 1.8 V VDD 3.6 V s 4.7 4.0 250 1.8 V VDD 3.6 V 4.7 -- 4.0 1.8 V VDD 3.6 V sion) Note 2 Unit MIN. 1.8 V VDD 3.6 V Hold time when SCLA0 = "L" LS (low-speed main) Mode -- 4.7 -- 0 3.45 s 0 3.45 s 4.0 s 4.0 s 4.7 s 4.7 s Note 1. The first clock pulse is generated after this period when the start/restart condition is detected. Note 2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 k R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 56 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (2) I2C fast mode (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V) Parameter SCLA0 clock frequency Symbol fSCL Conditions Fast mode: fCLK 3.5 MHz 2.7 V VDD 3.6 V 1.8 V VDD 3.6 V Setup time of restart con- tSU: STA dition 2.7 V VDD 3.6 V Hold time Note 1 tHD: STA 2.7 V VDD 3.6 V Hold time when SCLA0 = "L" tLOW 2.7 V VDD 3.6 V Hold time when SCLA0 = "H" tHIGH 2.7 V VDD 3.6 V Data setup time (reception) tSU: DAT 2.7 V VDD 3.6 V Data hold time (transmis- tHD: DAT 2.7 V VDD 3.6 V HS (high-speed main) Mode MAX. MIN. MAX. 0 400 0 400 kHz 0 400 0 400 kHz 0.6 1.8 V VDD 3.6 V -- 0.6 -- 1.3 1.8 V VDD 3.6 V -- 0.6 1.8 V VDD 3.6 V -- 100 1.8 V VDD 3.6 V -- 0 1.8 V VDD 3.6 V Setup time of stop condition tSU: STO 2.7 V VDD 3.6 V Bus-free time tBUF 2.7 V VDD 3.6 V -- -- 1.3 -- 0.6 s 0.6 s 0.6 s 0.6 s 1.3 s 1.3 s 0.6 s 0.6 s 100 ns 100 0.9 0.6 1.8 V VDD 3.6 V 1.8 V VDD 3.6 V Unit MIN. 1.8 V VDD 3.6 V sion) Note 2 LS (low-speed main) Mode ns 0 0.9 s 0 0.9 s 0.6 s 0.6 s 1.3 s 1.3 s Note 1. The first clock pulse is generated after this period when the start/restart condition is detected. Note 2. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode: Cb = 320 pF, Rb = 1.1 k R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 57 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (3) I2C fast mode plus (TA = -40 to +85 C, 2.7 V VDD 3.6 V, VSS = 0 V) Parameter Symbol HS (high-speed main) Mode Conditions 2.7 V VDD 3.6 V SCLA0 clock frequency fSCL Fast mode plus: fCLK 10 MHz Setup time of restart condition tSU: STA 2.7 V VDD 3.6 V Hold time Note 1 tHD: STA Hold time when SCLA0 = "L" MIN. MAX. 0 1000 LS (low-speed main) Mode MIN. Unit MAX. -- kHz 0.26 -- s 2.7 V VDD 3.6 V 0.26 -- s tLOW 2.7 V VDD 3.6 V 0.5 -- s Hold time when SCLA0 = "H" tHIGH 2.7 V VDD 3.6 V 0.26 -- s Data setup time (reception) tSU: DAT 2.7 V VDD 3.6 V 50 -- ns Data hold time (transmis- tHD: DAT 2.7 V VDD 3.6 V 0 -- s Setup time of stop condition tSU: STO 2.7 V VDD 3.6 V 0.26 -- s Bus-free time tBUF 2.7 V VDD 3.6 V 0.5 -- s 0.45 sion) Note 2 Note 1. The first clock pulse is generated after this period when the start/restart condition is detected. Note 2. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode plus: Cb = 120 pF, Rb = 1.1 k IICA serial transfer timing tLOW SCLn tHD: DAT tHD: STA tHIGH tSU: STA tHD: STA tSU: STO tSU: DAT SDAn tBUF Stop condition Start condition R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Restart condition Stop condition Page 58 of 80 RL78/L1A 2.6 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) Analog Characteristics 2.6.1 A/D converter characteristics TA = -40 to +85C, 1.8 V AVREFP AVDD VDD 3.6 V, VSS = AVSS = 0 V, reference voltage(+) = AVREFP, reference voltage(-) = AVREFM = 0 V MIN TYP MAX Unit Resolution Parameter RES Symbol Conditions 12 bit Analog capacitance Cs 15 pF Analog input Rs 2.5 k resistance Frequency fCLK High-speed mode Normal mode Conversion time Tconv 2.7 V AVREFP AVDD VDD 3.6 V 1 24 MHz 2.4 V AVREFP AVDD VDD 3.6 V 1 16 MHz 2.7 V AVREFP AVDD VDD 3.6 V 1 24 MHz 2.4 V AVREFP AVDD VDD 3.6 V 1 16 MHz 1.8 V AVREFP AVDD VDD 3.6 V 1 8 MHz 3 s 4.5 s 3.4 s 5.1 s 10.1 s 1.25 5.0 LSB 1.25 5.0 LSB High-speed mode 2.7 V AVREFP AVDD VDD 3.6 V ADCSR.ADHSC = 0 Permissible signal source impedance ADSSTRn = 28H max = 0.3 k ADCLK = 24 MHz 2.4 V AVREFP AVDD VDD 3.6 V Permissible signal source impedance max = 1.3 k ADCLK = 16 MHz Normal mode 2.7 V AVREFP AVDD VDD 3.6 V ADCSR.ADHSC = 1 Permissible signal source impedance ADSSTRn = 28H max = 1.1 k ADCLK = 24 MHz 2.4 V AVREFP AVDD VDD 3.6 V Permissible signal source impedance max = 2.2 k ADCLK = 16 MHz 1.8 V AVREFP AVDD VDD 3.6 V Permissible signal source impedance max = 5 k ADCLK = 8 MHz Overall error AINL High-speed mode 2.7 V AVREFP AVDD VDD 3.6 V ADCSR.ADHSC = 0 2.4 V AVREFP AVDD VDD 3.6 V ADSSTRn = 28 H Normal mode 2.7 V AVREFP AVDD VDD 3.6 V 1.25 5.0 LSB ADCSR.ADHSC = 1 2.4 V AVREFP AVDD VDD 3.6 V 1.25 5.0 LSB 1.8 V AVREFP AVDD VDD 3.6 V 3.0 8.0 LSB High-speed mode 2.7 V AVREFP AVDD VDD 3.6 V 0.5 4.5 LSB ADCSR.ADHSC = 0 2.4 V AVREFP AVDD VDD 3.6 V 0.5 4.5 LSB ADSSTRn = 28H Zero-scale error EZS ADSSTRn = 28H Normal mode 2.7 V AVREFP AVDD VDD 3.6 V 0.5 4.5 LSB ADCSR.ADHSC = 1 2.4 V AVREFP AVDD VDD 3.6 V 0.5 4.5 LSB 1.8 V AVREFP AVDD VDD 3.6 V 1 7.5 LSB ADSSTRn = 28H R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 59 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) Parameter Full-scale error Symbol EFS Conditions High-speed mode 2.7 V AVREFP AVDD VDD 3.6 V ADCSR.ADHSC = 0 2.4 V AVREFP AVDD VDD 3.6 V ADSSTRn = 28H DLE error Unit 0.75 4.5 LSB 0.75 4.5 LSB 2.7 V AVREFP AVDD VDD 3.6 V 0.75 4.5 LSB 2.4 V AVREFP AVDD VDD 3.6 V 0.75 4.5 LSB 1.8 V AVREFP AVDD VDD 3.6 V 1.5 7.5 LSB High-speed mode 2.7 V AVREFP AVDD VDD 3.6 V 1.0 LSB ADCSR.ADHSC = 0 2.4 V AVREFP AVDD VDD 3.6 V 1.0 LSB Normal mode 2.7 V AVREFP AVDD VDD 3.6 V 1.0 LSB ADCSR.ADHSC = 1 2.4 V AVREFP AVDD VDD 3.6 V 1.0 LSB 1.8 V AVREFP AVDD VDD 3.6 V 1.0 LSB High-speed mode 2.7 V AVREFP AVDD VDD 3.6 V 1.0 3.0 LSB ADCSR.ADHSC = 0 2.4 V AVREFP AVDD VDD 3.6 V 1.0 4.5 LSB ADSSTRn = 28H ILE MAX ADCSR.ADHSC = 1 ADSSTRn = 28H Integral linearity error TYP Normal mode ADSSTRn = 28H Differential linearity MIN ADSSTRn = 28H Normal mode 2.7 V AVREFP AVDD VDD 3.6 V 1.0 3.0 LSB ADCSR.ADHSC =1 2.4 V AVREFP AVDD VDD 3.6 V 1.0 3.0 LSB 1.8 V AVREFP AVDD VDD 3.6 V 1.0 3.0 LSB ADSSTRn = 28H The characteristics above only apply when pins other than those of the A/D converter are not in use. The overall error includes the quantization error. Each of the offset error, full-scale error, DNL differential non-linearity error, and INL integral non-linearity error does not include the quantization error. Note [Reference value for design (not guaranteed)] We can provide the design reference values for the A/D converter. Note, however, that these values are not guaranteed and can only be used as a reference when using this function. See below for details. TA = 0 to +50C, 2.0 V AVREFP AVDD VDD 3.6 V, VSS = AVSS = 0 V, reference voltage(+) = AVREFP, reference voltage(-) = AVREFM = 0 V Parameter Symbol Conditions MIN TYP MAX Unit Resolution RES Note 3 bit Analog capacitance Cs Note 3 pF Analog input Rs Note 3 k 2.7 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 MHz 2.4 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 MHz 2.7 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 MHz 2.4 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 MHz 2.0 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 MHz resistance Frequency fCLK High-speed mode Normal mode R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 60 of 80 RL78/L1A Parameter Conversion time 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) Symbol Tconv Conditions High-speed mode 2.7 V AVREFP AVDD VDD 3.6 V ADCSR.ADHSC = 0 Permissible signal source impedance ADSSTRn = 28H max = 0.3 k MIN TYP MAX Unit Note 3 s Note 3 s Note 3 s Note 3 s Note 3 s ADCLK = 24 MHz 2.4 V AVREFP AVDD VDD 3.6 V Permissible signal source impedance max = 1.3 k ADCLK = 16 MHz Normal mode 2.7 V AVREFP AVDD VDD 3.6 V ADCSR.ADHSC = 1 Permissible signal source impedance ADSSTRn = 28H max = 1.1 k ADCLK = 24 MHz 2.4 V AVREFP AVDD VDD 3.6 V Permissible signal source impedance max = 2.2 k ADCLK = 16 MHz 2.0 V AVREFP AVDD VDD 3.6 V Permissible signal source impedance max = 5 k ADCLK = 8 MHz Overall error AINL High-speed mode 2.7 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 LSB ADCSR.ADHSC = 0 2.4 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 LSB Normal mode 2.7 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 LSB ADCSR.ADHSC = 1 2.4 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 LSB 2.0 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 LSB High-speed mode 2.7 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 LSB ADCSR.ADHSC = 0 2.4 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 LSB Normal mode 2.7 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 LSB ADCSR.ADHSC = 1 2.4 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 LSB 2.0 V AVREFP AVDD VDD 3.6 V Note 3 4.5 LSB High-speed mode 2.7 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 LSB ADCSR.ADHSC = 0 2.4 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 LSB Normal mode 2.7 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 LSB ADCSR.ADHSC = 1 2.4 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 LSB ADSSTRn = 28H ADSSTRn = 28H Zero-scale error EZS Note 1, Note 2 ADSSTRn = 28H ADSSTRn = 28H Full-scale error EFS Note 1, Note 2 ADSSTRn = 28H ADSSTRn = 28H Differential linearity DLE error 2.0 V AVREFP AVDD VDD 3.6 V Note 3 4.5 LSB High-speed mode 2.7 V AVREFP AVDD VDD 3.6 V Note 3 LSB ADCSR.ADHSC = 0 2.4 V AVREFP AVDD VDD 3.6 V Note 3 LSB Normal mode 2.7 V AVREFP AVDD VDD 3.6 V Note 3 LSB ADCSR.ADHSC = 1 2.4 V AVREFP AVDD VDD 3.6 V Note 3 LSB 2.0 V AVREFP AVDD VDD 3.6 V Note 3 LSB High-speed mode 2.7 V AVREFP AVDD VDD 3 .6 V Note 3 Note 3 LSB ADCSR.ADHSC = 0 2.4 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 LSB Normal mode 2.7 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 LSB ADCSR.ADHSC = 1 2.4 V AVREFP AVDD VDD 3.6 V Note 3 Note 3 LSB 2.0 V AVREFP AVDD VDD 3.6 V Note 3 --Note 3 LSB ADSSTRn = 28H ADSSTRn = 28H Integral linearity error ILE ADSSTRn = 28H ADSSTRn = 28H R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 61 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) Note The characteristics above only apply when pins other than those of the A/D converter are not in use. The overall error includes the quantization error. Each of the offset error, full-scale error, DNL differential non-linearity error, and INL integral non-linearity error does not include the quantization error. Note 1. MAX. value is the average value 3 at normalized distribution. Note 2. These values are the results of characteristic evaluation. Note 3. The reference value is not available. 2.6.2 Temperature sensor, internal reference voltage output characteristics (TA = -40 to +85 C, 2.4 V VDD 3.6 V, VSS = 0 V), HS (high-speed main) mode Parameter Symbol Temperature sensor output voltage VTMPS25 Conditions TYP. 1.38 1.45 TA = +25C Internal reference voltage VBGR Temperature coefficient FVTMPS Temperature sensor output voltage that depends on the temperature Operation stabilization wait time tAMP 2.4 V VDD 3.6 V R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 MIN. MAX. Unit 1.5 V 1.05 -3.6 5 V mV/C s Page 62 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) 2.6.3 D/A converter characteristics (1) When reference voltage = AVREFP, AVREFM (TA = -40 to +85 C, 1.8 V AVREFP AVDD VDD 3.6 V, VSS = AVSS = 0 V) Parameter Symbol Resolution RES Load resistance R0 Load capacitance C0 Output voltage range Tout Differential linearity error DNL Integral linearity error AINL Zero-scale error Full-scale error Conditions MIN. TYP. MAX. 12 Unit bit k 30 50 pF AVDD 0.47 V 0.5 1.0 LSB 0.4 8.0 LSB EZS 20 mV EFS 20 mV 30 s MAX. Unit 12 bit Output resistance RO Conversion time tcon 0.35 5 (2) When reference voltage = AVDD, AVSS (TA = -40 to +85 C, 1.8 V AVDD VDD 3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. Resolution RES Load resistance R0 Load capacitance C0 50 pF Output voltage range Tout AVDD 0.47 V Differential linearity error DNL 0.5 2.0 LSB Integral linearity error AINL 0.4 8.0 LSB k 30 0.35 Zero-scale error EZS 30 mV Full-scale error EFS 30 mV Output resistance RO Conversion time tcon R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 5 30 s Page 63 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) 2.6.4 Comparator (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V) Parameter Input voltage range Symbol Conditions Ivref Ivcmp Output delay td MIN. TYP. MAX. Unit 0 VDD - 1.4 V -0.3 VDD + 0.3 V High-speed comparator mode, Input slew rate > 50 mV/s standard mode 1.2 s High-speed comparator mode, window mode 2.0 s 5.0 s VDD = 3.0 V Low-speed comparator mode, standard mode 3 High-electric-potential judgment voltage VTW+ High-speed comparator mode, window mode 0.76 VDD V Low-electric-potential judgment voltage VTW- High-speed comparator mode, window mode 0.24 VDD V Operation stabilization tCMP wait time Internal reference VBGR s 100 1.38 1.45 1.50 V voltage Note Note Not usable in LS (low-speed main) mode, sub-clock operation, or STOP mode. R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 64 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) 2.6.5 Rail to rail Operational amplifier characteristics (TA = -40 to +85 C, 2.2 V AVDD VDD 3.6 V, AVSS = VSS = 0 V) Parameter Circuit current Symbol Conditions MIN TYP MAX Unit Icc1 Low-power consumption mode 10 16 A Icc2 High-speed mode 210 350 A Common mode input Vicm1 Low-power consumption mode 0.1 AVDD-0.1 V range Vicm2 High-speed mode 0.1 AVDD-0.1 V Output voltage range Vo1 Low-power consumption mode 0.1 AVDD-0.1 V Vo2 High-speed mode 0.1 AVDD-0.1 V Fioff Low-power consumption mode -10 10 mV High-speed mode -5 5 mV 120 dB 0.06 MHz Input offset voltage Open gain Av Gain-bandwidth (GB) GBW1 Low-power consumption mode product GBW2 High-speed mode 1 MHz Phase margin PM CL = 22 pF 50 deg Gain margin GM CL = 20 pF 10 dB Equivalent input noise Vnoise1 f = 1 kHz Low-power 900 nV/Hz Power supply reduction Vnoise2 f = 10 kHz consumption mode 450 nV/Hz Vnoise3 f = 1 kHz High-speed mode 80 nV/Hz Vnoise4 f = 2 kHz 50 nV/Hz 90 dB 90 dB 110 300 s 5 14 s 100 300 s 4 14 s 0.01 0.04 V/s 0.3 0.7 V/s PSRR ratio Common mode signal CMPR reduction ratio Operation stabilization Tturn1 CL = 20 pF wait time Settling time Low-power consumption mode Tturn2 CL = 20 pF High-speed mode Tset1 CL = 20 pF Low-power consumption mode Slew rate Tset2 CL = 20 pF High-speed mode Tselw1 CL = 20 pF Low-power consumption mode Load current Tselw2 CL = 20 pF Iload1 Low-power consumption mode -110 110 A Iload2 High-speed mode -110 110 A 22 pF 1 k Load capacitance CL Analog MUX ON Ron resistance R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 One channel High-speed mode Page 65 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) [Reference value for design (not guaranteed)] We can provide the design reference values for the rail-to-rail operational amplifier. Note, however, that these values are not guaranteed and can only be used as a reference when using this function. See below for details. (TA = 0 to 50C, 2.0 V AVDD VDD 3.6 V, AVSS = VSS = 0 V) Parameter Circuit current Symbol Conditions MIN TYP MAX Unit Icc1 Low-power consumption mode Note 3 Note 3 A Icc2 High-speed mode Note 3 Note 3 A Common mode input Vicm1 Low-power consumption mode Note 3 Note 3 V range Vicm2 High-speed mode Note 3 Note 3 V Output voltage range Vo1 Low-power consumption mode Note 3 Note 3 V Vo2 High-speed mode Note 3 Note 3 V Fioff Low-power consumption mode -7 7 mV High-speed mode Note 3 Note 3 mV Note 3 Note 3 dB Input offset voltage Note 1, Note 2 Open gain Av Gain-bandwidth (GB) GBW1 Low-power consumption mode Note 3 MHz product GBW2 High-speed mode Note 3 MHz Phase margin PM CL = 22 pF Note 3 deg Gain margin GM CL = 20 pF Note 3 dB Equivalent input noise Vnoise1 f = 1 kHz Low-power Note 3 nV/Hz Vnoise2 f = 10 kHz consumption mode Note 3 nV/Hz Vnoise3 f = 1 kHz High-speed mode Note 3 nV/Hz Vnoise4 f = 2 kHz Power supply reduction Note 3 nV/Hz PSRR Note 3 dB CMPR Note 3 dB Note 3 Note 3 s ratio Common mode signal reduction ratio Operation stabilization Tstd1 CL = 20 pF wait time Low-power consumption mode Settling time Tstd2 CL = 20 pF High-speed mode Note 3 Note 3 s Tset1 CL = 20 pF Low-power Note 3 Note 3 s consumption mode Slew rate Tset2 CL = 20 pF High-speed mode Note 3 Note 3 s Tselw1 CL = 20 pF Low-power Note 3 Note 3 V/s Tselw2 CL = 20 pF Note 3 Note 3 V/s Iload1 Low-power consumption mode Note 3 Note 3 A Iload2 High-speed mode Note 3 Note 3 A Note 3 pF Note 3 k consumption mode Load current Load capacitance CL Analog MUX ON Ron High-speed mode One channel resistance Note 1. MAX. value is the average value 3 at normalized distribution. Note 2. These values are the results of characteristic evaluation. Note 3. The reference value is not available. R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 66 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) 2.6.6 General purpose Operational amplifier characteristics (TA = -40 to +85 C, 1.8 V AVDD VDD 3.6 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 2 4 A Circuit current lCC1 Low-power consumption mode lCC2 High-speed mode 280 A Common mode input range Vicm1 Low-power consumption mode 0.2 AVDD-0.5 V Vicm2 High-speed mode 0.3 AVDD-0.6 V Output voltage range Vo1 Low-power consumption mode 0.1 AVDD-0.1 V Vo2 High-speed mode 0.1 AVDD-0.1 V Input offset voltage Fioff 3 -10 +10 mV Open gain AV Gain-bandwidth (GB) product GBW1 Low-power consumption mode GBW2 High-speed mode Phase margin PM CL = 20 pF 50 deg Gain margin GM CL = 20 pF 10 dB Equivalent input noise Vnoise1 f = 1 kHz 140 60 120 dB 0.04 MHz 1.7 MHz nV/Hz Vnoise2 f = 10 kHz Low-power consumption mode 200 nV/Hz Vnoise3 f = 1 kHz High-speed mode 90 nV/Hz Vnoise4 f = 2 kHz 70 nV/Hz Power supply reduction ratio PSRP 90 dB Common mode signal reduction ratio CMPR 90 dB Operation stabilization wait time Tstd1 CL = 20 pF Low-power consumption mode 650 s Tstd2 CL = 20 pF High-speed mode 13 s Settling time Tset1 CL = 20 pF Low-power consumption mode 750 s Tset2 CL = 20 pF High-speed mode Slew rate Tselw1 CL = 20 pF Low-power consumption mode 0.02 V/s Tselw2 CL = 20 pF High-speed mode 1.1 V/s Load current lload1 Low-power consumption mode -100 100 A lload2 High-speed mode -100 100 A Load capacitance CL 20 pF R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 230 13 s Page 67 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) 2.6.7 Voltage reference (TA = -40 to +85 C, 1.8 V AVDD VDD 3.6 V, AVSS = VSS = 0 V) Parameter Reference voltage output Symbol Conditions MIN. TYP. MAX. Unit VREF1 VSEL = 00, 2.65 V AVDD 3.6V 2.425 2.5 2.575 V VREF2 VSEL = 01, 2.2 V AVDD 3.6V 1.987 2.048 2.109 V VREF3 VSEL = 10, 2.0 V AVDD 3.6V 1.746 1.8 1.854 V VREF4 VSEL = 11, 1.8 V AVDD 3.6V 1.455 1.5 1.545 V 50 ms 200 A Settling time From power-on to AVDD set Load current of ILoad the VREFOUT pin Note 1. Connect AVREFP/AVREFOUT pins to the ground via a tantalum capacitor (capacity: 10 F 30%, ESR: 2 (max.), ESL: 10 nH (max.)) and a ceramic capacitor (capacity: 0.1 F 30%, ESR: 2 (max.), ESL: 10nH (max.)). Note 2. The values specified in the Reference voltage output column apply when a load is stable. These values cannot be guaranteed when the load is variable. Note 3. Total load current, including the load current when VREFOUT is in use for the on-chip A/D converter and D/A converter reference potential. When VREFOUT is in use for the on-chip A/D converter load reference, the maximum load current is 55 A. When VREFOUT is in use for the on-chip D/A converter (channel 1), the maximum load current is 55 A. R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 68 of 80 RL78/L1A 2.6.8 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) POR circuit characteristics (TA = -40 to +85 C, VSS = 0 V) Parameter Symbol Detection voltage Minimum pulse width VPOR Note 2 Conditions Power supply rise time MIN. TYP. MAX. Unit 1.47 1.51 1.55 V 1.46 1.50 1.54 V VPDR Power supply fall TPW1 Other than STOP/SUB HALT/SUB RUN 300 s TPW2 STOP/SUB HALT/SUB RUN 300 s timeNote 1 Note 1. If the power supply voltage falls while the voltage detector is off, be sure to either shift to STOP mode or execute a reset by using the voltage detector or external reset pin before the power supply voltage falls below the minimum operating voltage specified in 2.4 AC Characteristics. Note 2. Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). TPW1 TPW2 VDD VPOR VPDR 0.7 V 2.6.9 1/2 AVDD voltage output LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = -40 to +85 C, 1.8 V AVDD VDD 3.6 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. Output voltage accuracy -4.0 Sampling time for the corresponding channel 20.0 R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 TYP. MAX. Unit +4.0 s Page 69 of 80 RL78/L1A 2.6.10 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = -40 to +85 C, VPDR VDD 3.6 V, VSS = 0 V) Parameter Detection voltage Supply voltage level Symbol VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VLVD8 VLVD9 VLVD10 VLVD11 Minimum pulse width Conditions TYP. MAX. Unit Power supply rise time 3.07 3.13 3.19 V Power supply fall time 3.00 3.06 3.12 V Power supply rise time 2.96 3.02 3.08 V Power supply fall time 2.90 2.96 3.02 V Power supply rise time 2.86 2.92 2.97 V Power supply fall time 2.80 2.86 2.91 V Power supply rise time 2.76 2.81 2.87 V Power supply fall time 2.70 2.75 2.81 V Power supply rise time 2.66 2.71 2.76 V Power supply fall time 2.60 2.65 2.70 V Power supply rise time 2.56 2.61 2.66 V Power supply fall time 2.50 2.55 2.60 V Power supply rise time 2.45 2.50 2.55 V Power supply fall time 2.40 2.45 2.50 V Power supply rise time 2.05 2.09 2.13 V Power supply fall time 2.00 2.04 2.08 V Power supply rise time 1.94 1.98 2.02 V Power supply fall time 1.90 1.94 1.98 V Power supply rise time 1.84 1.88 1.91 V Power supply fall time 1.80 1.84 1.87 V tLW s 300 Detection delay time Caution MIN. 300 s Set the detection voltage (VLVD) to be within the operating voltage range. The operating voltage range depends on the setting of the user option byte (000C2H/010C2H). The following shows the operating voltage range. HS (high-speed main) mode: VDD = 2.7 to 3.6 V @ 1 MHz to 24 MHz VDD = 2.4 to 3.6 V @ 1 MHz to 16 MHz LS (low-speed main) mode: R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 VDD = 1.8 to 3.6 V @ 1 MHz to 8 MHz Page 70 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) LVD Detection Voltage of Interrupt & Reset Mode (TA = -40 to +85 C, VPDR VDD 3.6 V, VSS = 0 V) Parameter Symbol Interrupt and reset mode Conditions VLVDB0 VLVDB1 LVIS0, LVIS1 = 1, 0 VLVDB2 LVIS0, LVIS1 = 0, 1 VLVDB3 LVIS0, LVIS1 = 0, 0 VLVDC0 TYP. MAX. Unit 1.80 1.84 1.87 V Rising release reset voltage 1.94 1.98 2.02 V Falling interrupt voltage 1.90 1.94 1.98 V Rising release reset voltage 2.05 2.09 2.13 V Falling interrupt voltage 2.00 2.04 2.08 V Rising release reset voltage 3.07 3.13 3.19 V Falling interrupt voltage 3.00 3.06 3.12 V VPOC0, VPOC1, VPOC2 = 0, 1, 0, falling reset voltage: 2.4 V VLVDC1 LVIS0, LVIS1 = 1, 0 VLVDC2 LVIS0, LVIS1 = 0, 1 VLVDD0 2.40 2.45 2.50 V Rising release reset voltage 2.56 2.61 2.66 V Falling interrupt voltage 2.50 2.55 2.60 V Rising release reset voltage 2.66 2.71 2.76 V Falling interrupt voltage 2.60 2.65 2.70 V 2.70 2.75 2.81 V Rising release reset voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V Rising release reset voltage 2.96 3.02 3.08 V Falling interrupt voltage 2.90 2.96 3.02 V VPOC0, VPOC1, VPOC2 = 0, 1, 1, falling reset voltage: 2.7 V VLVDD1 LVIS0, LVIS1 = 1, 0 VLVDD2 2.6.11 MIN. VPOC0, VPOC1, VPOC2 = 0, 0, 1, falling reset voltage: 1.8 V LVIS0, LVIS1 = 0, 1 Low-resistance switch TA = -40 to + 85C, 1.8 V AVDD VDD 3.6 V, AVSS = VSS = 0 V Parameter ON resistance 1 Symbo Ron1 Conditions AMP0OPD, AMP1OPD Load current < 0.1 mA ON resistance 2 Ron2 AMP2OPD Load current < 0.1 mA Load current Icas MIN TYP MAX 16 50 Unit 10 30 0.1 mA [Reference value for design (not guaranteed)] We can provide the design reference values for the low-resistance switch. Note, however, that these values are not guaranteed and can only be used as a reference when using this function. See below for details. TA = 0 to + 50C, 2.0 V AVDD VDD 3.6 V, AVSS = VSS = 0 V Parameter ON resistance 1 Note 1, Note 2 Symbol Ron1 Conditions AMP0OPD, AMP1OPD Load current < 0.1 mA ON resistance 2 Note 1, Note 2 Ron2 AMP2OPD Load current < 0.1 mA Load current Icas Note 1. MAX. value is the average value 3 at normalized distribution. Note 2. These values are the results of characteristic evaluation. Note 3. The reference value is not available. R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 MIN TYP MAX Note 3 26 Note 3 15 Note 3 Unit mA Page 71 of 80 RL78/L1A 2.7 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) Power supply voltage rising slope characteristics (TA = -40 to +85 C, VSS = 0 V) Parameter Power supply voltage rising slope Caution Conditions SVDD MIN. TYP. MAX. Unit 54 V/ms Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating voltage range shown in 2.4 AC Characteristics. R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 72 of 80 RL78/L1A 2.8 2.8.1 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) LCD Characteristics Resistance division method (1) Static display mode (TA = -40 to +85 C, VL4 (MIN.) VDD 3.6 V, VSS = 0 V) Parameter LCD drive voltage Symbol Conditions VL4 MIN. TYP. 2.0 MAX. Unit VDD V MAX. Unit VDD V MAX. Unit VDD V (2) 1/2 bias method, 1/4 bias method (TA = -40 to +85 C, VL4 (MIN.) VDD 3.6 V, VSS = 0 V) Parameter LCD drive voltage Symbol Conditions VL4 MIN. TYP. 2.7 (3) 1/3 bias method (TA = -40 to +85 C, VL4 (MIN.) VDD 3.6 V, VSS = 0 V) Parameter LCD drive voltage Symbol VL4 R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Conditions MIN. 2.5 TYP. Page 73 of 80 RL78/L1A 2.8.2 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) Internal voltage boosting method (1) 1/3 bias method (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V) Parameter LCD output voltage variation range Symbol VL1 Conditions C1 to C4 Note 1 = 0.47 F Note 2 MIN. TYP. MAX. Unit VLCD = 04H 0.90 1.00 1.08 V VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.33 V VLCD = 0AH 1.20 1.30 1.38 V VLCD = 0BH 1.25 1.35 1.43 V VLCD = 0CH 1.30 1.40 1.48 V VLCD = 0DH 1.35 1.45 1.53 V VLCD = 0EH 1.40 1.50 1.58 V VLCD = 0FH 1.45 1.55 1.63 V VLCD = 10H 1.50 1.60 1.68 V VLCD = 11H 1.55 1.65 1.73 V VLCD = 12H 1.60 1.70 1.78 V VLCD = 13H 1.65 1.75 1.83 V = 0.47 F 2 VL1 - 0.1 2 VL1 2 VL1 V C1 to C4 Note 1 = 0.47 F 3 VL1 - 0.15 3 VL1 3 VL1 V Doubler output voltage VL2 C1 to C4 Tripler output voltage VL4 Reference voltage setup time Note 2 tVWAIT1 Voltage boost wait time Note 3 tVWAIT2 Note 1. Note 1 C1 to C4 Note 1 = 0.47F 5 ms 500 ms This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = 0.47 F30% Note 2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits of the LCDM0 register to 01B) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). Note 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 74 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) (2) 1/4 bias method (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V) Parameter Symbol LCD output voltage variation range VL1 Conditions C1 to C5 Note 1 = 0.47 F Doubler output voltage VL2 Tripler output voltage VL3 Quadruply output voltage VL4 Reference voltage setup time Voltage boost wait time Note 1. Note 2 Note 3 Note 2 MIN. TYP. MAX. Unit VLCD = 04H 0.90 1.00 1.08 V VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.33 V VLCD = 0AH 1.20 1.30 1.38 V C1 to C5 Note 1 = 0.47 F 2 VL1 - 0.08 2 VL1 2 VL1 V C1 to C5 Note 1 = 0.47 F 3 VL1 - 0.12 3 VL1 3 VL1 V C1 to C5 Note 1 = 0.47 F 4 VL1 - 0.16 4 VL1 4 VL1 V C1 to C5 Note 1 tVWAIT1 tVWAIT2 = 0.47F 5 ms 500 ms This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL3 and GND C5: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = C5 = 0.47 F30% Note 2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits of the LCDM0 register to 01B) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). Note 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 75 of 80 RL78/L1A 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) 2.8.3 Capacitor split method (1) 1/3 bias method (TA = -40 to +85 C, 2.2 V VDD 3.6 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit VL4 voltage VL4 C1 to C4 = 0.47 F Note 2 VL2 voltage VL2 C1 to C4 = 0.47 F Note 2 2/3 VL4 - 0.1 2/3 VL4 2/3 VL4 + 0.1 V VL1 voltage VL1 C1 to C4 = 0.47 F Note 2 1/3 VL4 - 0.1 1/3 VL4 1/3 VL4 + 0.1 V Capacitor split wait time Note 1 tVWAIT VDD V 100 ms Note 1. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1). Note 2. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = 0.47 F30% R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 76 of 80 RL78/L1A 2.9 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) RAM data retention characteristics (TA = -40 to +85 C, VSS = 0 V) Parameter Symbol Data retention supply voltage VDDDR Conditions MIN. TYP. MAX. Unit 3.6 V 1.46 Note The value depends on the POR detection voltage. When the voltage drops, the RAM data is retained before a POR reset Note is effected, but RAM data is not retained when a POR reset is effected. Operation mode STOP mode RAM Data retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 2.10 Flash Memory Programming Characteristics (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V) Parameter Symbol Conditions MIN. System clock frequency fCLK 2.4 V VDD 3.6 V Number of code flash rewrites Cerwr Retained for 20 years TA = 85C Number of data flash rewrites Retained for 1 year TA = 25C Notes 1, 2, 3 Retained for 5 years TA = 85C 100,000 Retained for 20 years TA = 85C 10,000 TYP. MAX. 1 Notes 1, 2, 3 24 Unit MHz Times 1,000 1,000,000 Note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. Note 2. When using flash memory programmer and Renesas Electronics self programming library Note 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. 2.11 Dedicated Flash Memory Programmer Communication (UART) (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V) Parameter Transfer rate R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Symbol Conditions During serial programming MIN. 115,200 TYP. MAX. Unit 1,000,000 bps Page 77 of 80 RL78/L1A 2.12 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C) Timing Specs for Switching Modes (TA = -40 to +85 C, 1.8 V VDD 3.6 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 100 ms How long from when an external reset ends until the initial communication settings are specified tSUINIT POR and LVD reset must end before the external reset ends. How long from when the TOOL0 pin is placed at the low level until an external reset ends tSU POR and LVD reset must end before the external reset ends. 10 s Time to hold the TOOL0 pin at the low level after an external reset is released (excluding the processing time of the firmware to control the flash memory) tHD POR and LVD reset must end before the external reset ends. 1 ms <1> <2> <3> <4> RESET 723 s + tHD 00H reception processing (TOOLRxD, TOOLTxD mode) time TOOL0 tSU tSUINIT <1> The low level is input to the TOOL0 pin. <2> The external reset ends (POR and LVD reset must end before the external reset ends.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the resets end. tSU: How long from when the TOOL0 pin is placed at the low level until an external reset ends tHD: Time to hold the TOOL0 pin at the low level after an external reset is released (excluding the processing time of the firmware to control the flash memory) R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 Page 78 of 80 RL78/L1A 3. PACKAGE DRAWINGS 3. PACKAGE DRAWINGS 3.1 80-pin products R5F11MMDAFB, R5F11MMEAFB, R5F11MMFAFB JEITA Package Code P-LFQFP80-12x12-0.50 RENESAS Code PLQP0080KB-A Previous Code 80P6Q-A MASS[Typ.] 0.5g HD *1 D 60 41 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 40 61 bp E c *2 HE c1 b1 Reference Dimension in Millimeters Symbol ZE Terminal cross section 80 21 1 20 ZD Index mark F bp c A *3 A1 y S e A2 S L x L1 Detail F R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Min Nom Max 11.9 12.0 12.1 11.9 12.0 12.1 1.4 13.8 14.0 14.2 13.8 14.0 14.2 1.7 0.1 0.2 0 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0 10 0.5 0.08 0.08 1.25 1.25 0.3 0.5 0.7 1.0 Page 79 of 80 RL78/L1A 3. PACKAGE DRAWINGS 3.2 100-pin products R5F11MPEAFB, R5F11MPFAFB, R5F11MPGAFB JEITA Package Code P-LFQFP100-14x14-0.50 RENESAS Code PLQP0100KB-A Previous Code 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6g HD *1 D 51 75 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 50 76 bp c1 Reference Symbol c E *2 HE b1 D E A2 HD HE A A1 bp b1 c c1 26 1 ZE Terminal cross section 100 25 Index mark ZD F y S e *3 bp A1 c A A2 S L x L1 Detail F R01DS0280EJ0100 Rev. 1.00 Aug 12, 2016 e x y ZD ZE L L1 Dimension in Millimeters Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0 8 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0 Page 80 of 80 REVISION HISTORY Rev. Date 1.00 Aug 12, 2016 RL78/L1A Datasheet Description Page -- Summary First Edition issued SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, Inc. All trademarks and registered trademarks are the property of their respective owners. C-1 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics 3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or 5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product. the product's quality grade, as indicated below. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc. Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics. 6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products. 11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. California Eastern Laboratories, Inc. 4590 Patrick Henry Drive, Santa Clara, California 95054-1817, U.S.A. Tel: +1-408-919-2500, Fax: +1-408-988-0279 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K Tel: +44-1628-585-100, Fax: +44-1628-585-900 Renesas Electronics Europe GmbH Arcadiastrasse 10, 40472 Dusseldorf, Germany Tel: +49-211-6503-0, Fax: +49-211-6503-1327 Renesas Electronics (China) Co., Ltd. Room 1709, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100191, P.R.China Tel: +86-10-8235-1155, Fax: +86-10-8235-7679 Renesas Electronics (Shanghai) Co., Ltd. Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, P. R. China 200333 Tel: +86-21-2226-0888, Fax: +86-21-2226-0999 Renesas Electronics Hong Kong Limited Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong Tel: +852-2265-6688, Fax: +852 2886-9022 Renesas Electronics Taiwan Co., Ltd. 13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan Tel: +886-2-8175-9600, Fax: +886 2-8175-9670 Renesas Electronics Singapore Pte. Ltd. 80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949 Tel: +65-6213-0200, Fax: +65-6213-0300 Renesas Electronics Malaysia Sdn.Bhd. Unit 1207, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics India Pvt. Ltd. No.777C, 100 Feet Road, HAL II Stage, Indiranagar, Bangalore, India Tel: +91-80-67208700, Fax: +91-80-67208777 Renesas Electronics Korea Co., Ltd. 12F., 234 Teheran-ro, Gangnam-Gu, Seoul, 135-080, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 (c) 2016 Renesas Electronics Corporation. All rights reserved. Colophon 5.0