Am27C800 8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) ROM Compatible CMOS EPROM DISTINCTIVE CHARACTERISTICS M Fast access time ~~ 120 ns @ Low power consumption 100 pA maximum CMOS standby current M Industry standard pinout: ROM compatible 42-pin DIP, PDIP and 44-pin LCC and PLCC packages provide easy upgrade to 16 Mbits GENERAL DESCRIPTION The Am27C800 is an 8 Mbit ultraviolet erasable pro- grammable read-only memory that is functionally and pinout compatible with 8 Mbit masked ROMs. Under control of the BYTE input, the memory can be config- ured as either a 1 Mbit by 8-bit memory or a 512K by 16-bit memory. It operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. Products are available in windowed ceramic packages as well as plastic one time programmable (OTP) packages. Typically, any byte can be accessed in less than 120 ns, allowing operation with high-performance microproces- sors without any WAIT states. The Am27C800 offers OE Output Enable __ Chip Enable BYTE/Vpp and CE/PGM P ic AB Y Decoder A0-A18 Address Inputs X Decoder cr Advanced Micro Devices @ Single +5 V power supply @ +10% power supply tolerance standard on most speeds @ 100% Flashrite programming Typical programming time of less than 1 minute @ Latch-up protected to 100 mA from 1 V to Veco +1V @ High noise immunity separate Output Enable (OE) and Chip Enable (CE) controls, thus eliminating bus contention in a multiple bus microprocessor system. AMD's CMOS process technology provides high speed, low power, and high noise immunity. Typical power con- sumption is only 150 mW in active mode, and 100 pW in standby mode. All signals are TTL levels, including programming sig- nals. Bit locations may be programmed singly, in blocks, or at random. The Am27C800 supports AMD's Flash- rite programming algorithm (100 ys pulses) resulting in typical programming times of less than 1 minute. Data Outputs DQo-DQ15 Garr iar Output Buffers 8,388,608-Bit Cell Matrix 15452B-1 Publication# 15452 Rev.B Amendment/0 Issue Date: July 1993 This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. 2-157cl AMD PRELIMINARY PRODUCT SELECTOR GUIDE Family Part No. Am27C800 Ordering Part No: Voc +5% -125 -255 Voc + 10% -120 -150 -200 -250 Max Access Time (ns) 120 150 200 250 CE (E) Access Time (ns) 120 150 200 250 OE (G) Access Time (ns) 50 65 75 100 CONNECTION DIAGRAM Top View DIP PLCC/LCC VS Aig (_]1 421 ] Nc wc? a eg ReEeseseeesz a7 C43 4of] Ag oom ma marae rr, A6 (_]4 3977] A10 6 5 4 3 2 1 44 43 42 41 40 ) As (C15 38,7] Att a4 [7 e go [] A12 A4 (J6 37[] A12 A3 [8 ag] A13 A3 [_17 36[7] A13 A2 [Jo 371] A14 A2 [_]8 35 {7} A14 At []10 36[] Ais ai (J 34777 A15 Ao (}11 36[] A16 Ao [Jo 331] ate CE(E)/PGM (P) [] 12 34[] BYTE/Vre PGM(P)/GE(E) (711 3217] BYTEWpee Ves 13 33f] Vss Vss [_} 12 3117] Vss e Qt oe oe C13 30[] pais/aB dao [15 31 pas [Jie 30[] Da14 Dao [7}14 29{7) paz pat [17 20[] Das pas [J15 2817] para 18 19 20 21 22 23 24 25 26 27 28 pa1 [-J16 271] pas TDI easo8-3 26 S82f<S637re sage sge pag (17 [J pais SS 595285555 paz (-Jis 2517] pas a 98 a7 8 pais [_]19 2417) pai2 pas [_}20 231] pa DQ11 Cl 21 22 | Veco Note: 15452B-2 1. JEDEC nomenclature is in parenthesis. PIN DESIGNATIONS LOGIC SYMBOL AB = Address Input (BYTE Mode) >] AB A0-A18 = Address Inputs 18 BYTE/Vpp = Byte/Word Switch or Program AO-A18 16 Supply Voltage DQo-DQ15 cP CE (E)/PGM (P) = Chip Enable CE (E)/PGM (P) 3 DQo-DQ15 = Data Inputs/Outputs or NC = No Internal Connection ] OF (G) OE (G = Output Enable In V Vo Be Volt ne BYTEWer = U oltage oe ce Supply 9 15452B-4 Vss = Ground 2-158 Am27C800PRELIMINARY AMD &\ ORDERING INFORMATION EPROM Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27C800 -120 D c B Lt OPTIONAL PROCESSING Blank = Standard processing B = Burn-in TEMPERATURE RANGE C = Commercial (0C to +70C) I Industrial (40C to +85C) E = Extended Commercial (55C to +125C) PACKAGE TYPE D = 42-Pin Ceramic DIP (CDV042) L = 44-Pin Leadless Chip Carrier (CLV044) SPEED OPTION See Product Selector Guide and Valid Combinations ___ DEVICE NUMBER/DESCRIPTION Am27C800 8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) CMOS EPROM Valid Combinations Valid Combinations AM27C800-120 Valid Combinations list configurations planned to be supported in volume for this device. Consult the lo- AM27C800-125] DC, DCB, DI, DIB, cal AMD sales office to confirm availability of specific AM27C800-150} DE, DEB, LC, LCB, valid combinations and to check on newly released AM27C800-200 LI, LIB, LE, LEB combinations. AM27C800-255 Am27C800 2-159cl AMD PRELIMINARY ORDERING INFORMATION OTP Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27C800 1 P Cc i OPTIONAL PROCESSING Blank = Standard processing TEMPERATURE RANGE C = Commercial (0C to +70C) | = Industrial (-40C to +80C) PACKAGE TYPE P = 42-Pin Plastic DIP (PD 042) J = 44-Pin Rectangular Plastic Leaded Chip Carrier (PL 044) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am27C800 8 Megabit (1,048,566 x 8-Bit/524,288 x 16-Bit) CMOS OTP EPROM Valid Combinations AM27C800-150 AM27C800-155 AM27C800-200 AM27C800-255 PC, JC, PI, Jl Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the lo- cal AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. 2-160 Am27C800PRELIMINARY amp &\ ORDERING INFORMATION Military APL Products AMD products tor Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883 requirements. The order number (Valid Combination) is formed by a combination of: AM27C800 15: o /B X A L_ LEAD FINISH A = Hot Solder Dip PACKAGE TYPE X = 42-Pin Ceramic DIP (CD 044) U = 44-Pin Rectangular Ceramic Leadless Chip Carrier (CL 044) DEVICE CLASS /B = Class B SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER Am27C800 8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) CMOS EPROM Valid Combinations Valid Combinations AM27C800-150 Valid Combinations list configurations planned to ; be supported in volume for this device. Consult AM27C800-200 (BUA, IBXA the local AMD saies office to confirm availability of AM27C800-250 specific valid combinations and to check on newly released combinations. Group A Tests Group A tests consist of Subgroups 1, 2, 3, 7, 8, 9, 10, 11. Am27C800 2-161at AMD FUNCTIONAL DESCRIPTION Erasing the Am27C800 In order to clear all locations of their programmed con- tents, it is necessary to expose the Am27C800 to an ultraviolet light source. A dosage of 15 W seconds/cm? is required to completely erase an AM27C800. This dos- age can be obtained by exposure to an ultraviolet lamp wavelength of 2,537 Awith intensity of 12,000 W/ cm? for 15 to 20 minutes. The Am27C800 should be di- rectly under and about one inch from the source and all filters should be removed from the UV light source prior to erasure. it is important to note that the Am27C800 and similar devices will erase with light sources having wavelengths shorter than 4000 A. Although erasure times will be much longer than with UV sources at 2,537A, exposure to fluorescent light and sunlight will eventually erase the Am27C800 and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package window should be covered by an opaque /abel or substance. Programming the Am27C800 Upon delivery or after each erasure the Am27C800 has all 8,388,608 bits in the ONE or HIGH state. ZEROs are loaded into the Am27C800 through the procedure of programming. The programming mode is entered when 12.75 V + 0.25 V is applied to the Vep pin, CE/PGM is at Vi, and OE is at Vin. For programming, the data to be programmedis applied 16 bits in parallel to the data output pins. The Flashrite algorithm reduces programming time by using 100 Us programming pulses and by giving each addresss only as many pulses as is necessary in order to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies or the maximum is reached. This process is re- peated while sequencing through each address of the Am27C800. This part of the algorithm is done at Vcc = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After the final ad- dress is completed, the entire EPROM memory is veri- fied at Vcc = Vep = 5.25 V. Please refer to Section 6.0 for programming flow chart and characteristics. Program Inhibit Programming of multiple Am27C800s in parallel with different data is also easily accomplished. Except for CE/PGM, all like inputs of the parallel Am27C800 may be common. A TTL low-level program pulse applied to PRELIMINARY an Am27C800 CE/PGM input with Vpp = 12.75 V + 0.25 V, and OE HIGH will program that Am27C800. A high-level CE/PGM input inhibits the other Am27C800 devices from being programmed. Program Verify Averify should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE at Vi_, CE/PGM at Vin and Vep between 12.5 V and 13.0 V. Auto Select Mode The auto select mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C + 5C ambient temperature range that is required when programming the Am27C800. To activate this mode, the programming equipment must force 12.0 V + 0.5 V on address line A9 of the Am27C800. Two identifier bytes may then be se- quenced from the device outputs by toggling address line AO from Vit to Vin. All other address lines must be held at Vi. during auto select mode. Byte 0 (AO = Vi_) represents the manufacturer code, and Byte 1 (AO = Vin), the device identifier code. For the Am27C800, these two identifier bytes are given in the Mode Select table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. Read Mode The Am27C800 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE/PGM) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tacc ) is equal to the delay from CE/PGM to output (tce). Data is available at the outputs toe after the falling edge of OE, assuming that CE/PGM has been LOW and addresses have been stable for at least tacc -toe. Byte Mode The user has the option of reading data in either 16-bit words or 8-bit bytes under control of the BYTE input. With the BYTE input HIGH, inputs A18A0 will address 512K words of 16-bit data. When the BYTE input is LOW, AB functions as the least significant address input and 1 Mbyte of data can be accessed. The 8 bits of data will appear on DQ7DQ0. 2-162 Am27C800PRELIMINARY Standby Mode The Am27C800 has a CMOS standby mode which re- duces the maximum Vcc current to 100 pA. It is placed in CMOS-standby when CE/PGM is at Vcc + 0.3 V. The Am27C800 also has a TTL-standby mode which re- duces the maximum Vcc current to 1.0 mA. Itis placed in TTL-standby when CE/PGNM is at Vin. When in standby mode, the outputs are in a high-impedance state, inde- pendent of the OE input. Output OR-Tieing To accommodate multiple memory connections, a two- line control function is provided to allow for: m Low memory power dissipation m@ Assurance that output bus contention will not occur It is recommended that CE/PGM be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line fromthe system control AMD cl bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particu- lar memory device. System Applications During the switch between active and standby condi- tions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the out- put capacitance loading of the device. At a minimum, a 0.1 uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between Vcc and Vss to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive ef- fects of the printed circuit board traces on EPROM ar- rays, a 4.7 WF bulk electrolytic capacitor should be used between Vcc and Vss for each eight devices. The loca- tion of the capacitor should be close to where the power supply is connected to the array. MODE SELECT TABLE Mode Pins CE/PGM OE Ao AQ BYTE/Vpp Outputs Read Vit Vit x xX x Dout Output Disable VIL VIH X X Xx Hi-Z Standby (TTL) Vix X X X X Hi-Z Standby (CMOS) Veo + 0.3 V X X X X Hi-Z Program VIL Vin X X Vpp DIN Program Verify Vin Vit X X Vpp DouT Program Inhibit Vin VIH X X Vpp Hi-Z Auto Select Manufacturer Code Vit Vit VIL Vu X 01H (Note 3) Device Code Vit Vit VIH VH X 1AH Notes: 1. Va=120V+05V X = Either Vi or Vi. 2. 3, Al-A8 = A10-A18 = Vi, AB= X 4 . See DC Programming Characteristics for Vep voltage during programming. Am27C800 2-163cl AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature OTP Products ............... 65C to +125C All Other Products ............ ~65C to +150C Ambient Temperature with Power Applied ............. 55C to +125C Voltage with Respect To Vss All pins except A9,Vpp Vcc (Note 1) ............0.. -0.6 V to Vcc + 0.6 V AQ and Vpp (Note 2) ......... 0.6 V to +13.5V Voc woe eee eee -0.6 Vto +7.0V Notes: 1. During transitions, the inputs may overshoot Vss to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input may overshoot to Vcc + 2.0 V for periods of up to 20ns. 2. During transitions, A9 and Vpp may overshoot Vss to -2.0 V for periods of up to 20 ns. A9 and Vep must not exceed 13.5 V for any period of time. Stresses above those listed under Absolute Maximum Rat- ings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for ex- tended periods may affect device reliability. PRELIMINARY OPERATING RANGES Commercial (C) Devices Case Temperature (Tc).......... 0C to +70C Industrial (I) Devices Case Temperature (Tc)........ 40C to +85C Extended Commercial (E) Devices Case Temperature (Tc)....... 55C to +125C Military (M) Devices Case Temperature (Tc)....... 55C to +125C Supply Read Voltages Voc for Am27C800-XX5 ..... +4.75 V to +5.25 V Voce for AM27C800-XX0 ..... +4.50 V to +5.50 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. 2-164 Am27C800PRELIMINARY AMD cl DC CHARACTERISTICS over operating range unless otherwise specified. (Notes 1, 2 and 4) (for APL Products, Group A, Subgroups 1, 2, 3, 6 and 7 are tested unless otherwise noted) Parameter Symbol Parameter Description Test Conditions Min Max Unit VoH Output HIGH Voltage loH = 400 pA 2.4 Vv VoL Output LOW Voltage lo. = 2.1 mA 0.45 Vv VIH Input HIGH Voltage 2.0 Vcc + 0.5 Vv VIL Input LOW Voltage -0.5 +0.8 Vv lu Input Load Current VIN = 0 V to +Vcc 1.0 pA ILo Output Leakage Current VouT = 0 V to +Vcc 5.0 HA icc Vcc Active Current CE = ViL, f = 5 MHz, C/l Devices 50 mA (Note 3) louT = 0 mA E/M Devices 60 Icc2 Vcc TTL Standby Current | CE = VIH 1.0 mA loca Vcc CMOS Standby Current | CE = Vcc + 0.3 V 100 pA IPP Vep Current During Read CE = OE = Vi, Vpp = Vcc 100 pA Notes: 1, Vec must be applied simultaneously or before Vpp, and removed simultaneously or after Vpp. Icc1 is tested with OE/Vpp = Vix to simulate open outputs. 2. Caution: The Am27C800 must not be removed from (or inserted into) a socket when Vcc or Vpp is applied. 3. 4 . Minimum DC Input Voltage is -0.5 V. During transitions, the inputs may overshoot to -2.0 V for periods less than 20 ns. Maximum DC Voltage on output pins is Vcc + 0.5 V, which may overshoot to Vcc + 2.0 V for periods less than 20 ns. 40 40 LL Lo ~ 35 am = 3>-PN 6 | g PS 5 < A 5 < PS E 30 O 30 Ss Ze i Ze IN a LL 2 DN A 25 D 25 a 20 20 1 2 3 4 5 6 7 8 9 10 ~75-50 -25 0 25 50 75 100 125 150 Frequency in MHz Temperature in C Figure 1. Typical Supply Current Figure 2. Typical Supply Current vs. Frequency vs. Temperature Vcc = 5.5 V, T = 25C Vcc = 5.5 V, f= 5 MHz 15452B-5 15452B-6 Am27C800 2-1651 amp PRELIMINARY CAPACITANCE Parameter Test CDV042 CLV044 PD 042 PL 044 Symbol Parameter Description | Conditions Typ | Max | Typ | Max | Typ | Max | Typ | Max | Unit CIN Input Capacitance VIN =0 10 18 10 18 10 18 10 18 pF CouT Output Capacitance VouT = 0 10 18 10 18 10 18 10 18 pF Notes: 1. This parameter is only sampled and not 100% tested. 2 Ta =+25C, f= 1 MHz SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified (Notes 1, 3 and 4) (for APL Products, Group A, Subgroups 9, 10 and 11 are tested unless otherwise noted) Am27C800 Parameter -125 -255 JEDEC | Standard] Description Test Conditions -120 -150 -200 -250 Unit tavav tacc | Address to _ Min - - - - Output Delay CE = OE = VIL ns Max 120 150 200 250 tELQV tCE Chip Enable to SE-V Min - _ - - ns OE = Output Delay I" Max 120 150 200 250 tGLav toe Output Enable to SE2 Vi. Min - - - - - = ns Output Delay Max 50 55 60 60 tEHQz, tDF one Enable OR Min 0 0 0 0 or Output Enable ns taHaz | (Note 2) HIGH, whichever Max 40 40 40 60 comes first, to Output Float taxax toH =| Output Hold from Min 0 0 0 0 ns Addresses, CE, or OE, whichever - - ~ -_ occurred first Max Notes: 1. Vcc must be applied simultaneously or before Vpp, and removed simultaneously or after Vpp. This parameter is only sampled and not 100% tested. 2 3. Caution: The Am27C800 must not be removed from (or inserted into) a socket or board when Vpp or Vcc is applied. 4 . Output Load: 1 TTL gate and Cy = 100 pF Input Rise and Fall Times: 20 ns Input Pulse Levels: 0.45 V to 2.4 V Timing Measurement Reference Level: Inputs: 0.8 Vand 2.0 V Outputs: 0.8 V and 2.0 V 2-166 Am27C800PRELIMINARY AMD &\ SWITCHING TEST CIRCUIT Device 2.7 kQ Und WA 5.0V va 7 CL Diodes = IN3064 6.2 kQ2 or Equivalent = = = 15452B-7 Ct = 100 pF including jig capacitance SWITCHING TEST WAVEFORM 2.4V 2.0V 2.0V > Test Points < . 0.8 V 0.8 V 0.45 V Input Output 15452B-8 AC Testing: Inputs are driven at 2.4 V for a logic 1 and 0.45 for a logic "0. Input pulse rise and fall times are < 20 ns. Am27C800 2-167cl AMD PRELIMINARY KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must Be Will Be Steady Steady May Will Be Change Changing from H to L from H to L May Will Be Change Changing from L to H from L to H Dont Care, Changing, Any Change State Permitted Unknown Does Not Center Apply Line is High Impedance Ott State KS000010 SWITCHING WAVEFORMS 2 | | Addresses x 2.0 Addresses Valid 2.0 k 0.45 0.8 0.8 ________] y- CE/PGM V -_ tce - fC OE \ | _ {DF taco Ed | (Note 2) __-} tOH . Note 1) . High Z ( 7 High Z Output {( ( q Valid Output by) _ Notes: 1545 1. OE/Vep may be delayed up to tacc to after the falling edge of the addresses without impact on tacc. 2. tpF is specified from OE or CE, whichever occurs first. 2B-9 2-168 Am27C800