This is information on a product in full production.
October 2012 Doc ID 13317 Rev 8 1/42
1
RHF1401
Rad-hard 14-bit 30 Msps A/D converter
Datasheet − production data
Features
■Qml-V qualified, smd 5962-06260
■Rad hard: 300 kRad(Si) TID
■Failure immune (SEFI) and latch-up immune
(SEL) up to 120 MeV-cm2/mg at 2.7 V and
125° C
■Hermetic package
■Tested at Fs = 20 Msps
■Low power: 85 mW at 20 Msps
■Optimized for 2 Vpp differential input
■High linearity and dynamic performances
■2.5 V/3.3 V compatible digital I/O
■Internal reference voltage with external
reference option
Applications
■Digital communication satellites
■Space data acquisition systems
■Aerospace instrumentation
■Nuclear and high-energy physics
Description
The RHF1401 is a 14-bit analog-to-digital
converter that uses pure (ELDRS-free) CMOS
0.25 µm technology combining high performance,
radiation robustness and very low power
consumption.
The RHF1401 is based on a pipeline structure
and digital error correction to provide excellent
static linearity. Specifically designed to optimize
power consumption, the device only dissipates
85 mW at 20 Msps, while maintaining a high level
of performance. The device also integrates a
proprietary track-and-hold structure to ensure a
large effective resolution bandwidth.
Voltage references are integrated in the circuit to
simplify the design and minimize external
components. A tri-state capability is available on
the outputs to allow common bus sharing. A data-
ready signal, which is raised when the data is
valid on the output, can be used for
synchronization purposes.
The RHF1401 has an operating temperature
range of -55° C to +125° C and is available in a
small 48-pin ceramic SO-48 package.
Ceramic SO-48 package
The upper metallic lid is not electrically connected to any
pins, nor to the IC die inside the package.
Table 1. Device summary
Order code SMD pin Quality
level Package Lead
finish Mass EPPL(1) Temp range
RHF1401KSO1 - Engineering
model SO-48 Gold 1.1 g Yes -55 °C to +125 °C
RHF1401KSO-01V 5962F0626001VXC QMLV-Flight
1. EPPL = ESA preferred part list
www.st.com
Contents RHF1401
2/42 Doc ID 13317 Rev 8
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 Equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . . . . 12
2.2 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Electrical characteristics (after 300 kRad) . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4 Results for differential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5 Results for single ended input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 User manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1 Optimizing the power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2 Driving the analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.1 Differential mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.2 Single-ended mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3 Reference connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3.1 Internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3.2 External voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.5.1 Digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.5.2 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.5.3 Digital output load considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.6 PCB layout precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4 Definitions of specified parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.1 Static parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2 Dynamic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
RHF1401 Contents
Doc ID 13317 Rev 8 3/42
6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
List of tables RHF1401
4/42 Doc ID 13317 Rev 8
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. External reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Static accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 10. Digital inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 11. Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 12. Differential mode output codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 13. Single-ended mode output codes with Vinb = INCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 14. RHF1401 operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 15. Ceramic SO-48 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 16. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
RHF1401 List of figures
Doc ID 13317 Rev 8 5/42
List of figures
Figure 1. RHF1401 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Output buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Data format input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Reference mode control input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Output enable input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. VREFP and INCM input/output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10. VREFM input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11. Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Differential configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. ENOB vs. input frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. SINAD vs. input frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 15. THD vs. input frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16. SNR vs. input frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 17. SFDR vs. input frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 18. Consumption vs. input frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 19. ENOB vs. sampling frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 20. SINAD vs. sampling frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 21. THD vs. sampling frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 22. SNR vs. sampling frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 23. SFDR vs. sampling frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 24. Power consumption vs. sampling frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 25. ENOB vs. VREFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 26. SINAD vs. VREFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27. SNR vs. VREFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 28. THD vs. VREFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 29. ENOB vs. sine clock, diff. input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 30. Clock threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 31. ENOB vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 32. Power consumption vs. temp.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 33. DNL, differential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 34. INL, differential input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 35. Single-ended input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 36. ENOB vs. Fin, single-ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 37. SINAD vs. Fin, single-ended. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 38. THD vs. Fin, single-ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 39. SNR vs. Fin, single-ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 40. SFDR vs. Fin, single-ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 41. Power consumption vs. Fin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 42. ENOB vs. Vin, Fin 1 kHz, Vrefp = 0.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 43. ENOB vs Vin, Fin = 2 MHz, Vrefp = 0.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 44. ENOB vs. Vin, Fin 1 kHz, Vrefp = 1.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 45. ENOB vs Vin, Fin = 2 MHz, Vrefp = 1.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 46. ENOB vs. Vin, Fin 1 kHz, Vrefp = 1.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 47. ENOB vs Vin, Fin = 2 MHz, Vrefp = 1.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 48. ENOB vs. Vin, Fin 1 kHz, Vrefp = 1.4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
List of figures RHF1401
6/42 Doc ID 13317 Rev 8
Figure 49. ENOB vs Vin, Fin = 2 MHz, Vrefp = 1.4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 50. Rpol values vs. Fs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 51. Power consumption values vs. Fs with internal references disabled . . . . . . . . . . . . . . . . . 26
Figure 52. Equivalent VIN - VINB (differential input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 53. 2 Vpp differential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 54. Differential implementation using a balun. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 55. Optimized single-ended configuration (DC coupling), external REFP . . . . . . . . . . . . . . . . 29
Figure 56. AC-coupling single-ended input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 57. AC-coupling single-ended input configuration for low frequencies . . . . . . . . . . . . . . . . . . . 30
Figure 58. Internal voltage reference setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 59. External voltage reference setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 60. Example with zeners. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 61. Clock input schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 62. Output buffer fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 63. Output buffer rise time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 64. Ceramic SO-48 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
RHF1401 Description
Doc ID 13317 Rev 8 7/42
1 Description
1.1 Block diagram
Figure 1. RHF1401 block diagram
AM04556
VIN
INCM
VINB
CLK
GND
OR
D13
D0
DR
OEB
DFSB
VREFM
IPOL
GNDA
VREFP
stage
1
stage
2
stage
n
Digital data correction
Buers
Internal
VREFP
Sequencer-phase shifting
Timing
VCCBI VCCBE
REFMODE
Internal
INCM
Biasing
current
setup
Description RHF1401
8/42 Doc ID 13317 Rev 8
1.2 Pin connections
Figure 2. pin connections (top view)
GNDBI
GNDBE
VCCBE
NC
NC
OR
(MSB)D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
(LSB)D0
DR
VCCBE
GNDBE
VCCBI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DGND
DGND
CLK
DGND
DVCC
DVCC
AVCC
AVCC
AGND
INCM
AGND
VINB
AGND
VIN
AGND
VREFM
VREFP
IPOL
AGND
AVCC
AVCC
DFSB
OEB
REFMODE
RHF1401 Description
Doc ID 13317 Rev 8 9/42
1.3 Pin descriptions
Table 2. Pin descriptions
Pin Name Description Observations Pin Name Description Observations
1 GNDBI Digital buffer ground 0 V 25 REFMODE Ref. mode control input 2.5 V/3.3 V CMOS
input
2 GNDBE Digital buffer ground 0 V 26 OEB Output enable input 2.5 V/3.3 V CMOS
input
3VCCBE
Digital buffer power
supply 2.5 V/3.3 V 27 DFSB Data format select input 2.5 V/3.3 V CMOS
input
4NC Not connected to the
dice 28 AVCC Analog power supply 2.5 V
5NC Not connected to the
dice 29 AVCC Analog power supply 2.5 V
6 OR Out of range output CMOS output
(2.5 V/3.3 V) 30 AGND Analog ground 0 V
7 D13(MSB) Most significant bit
output CMOS output
(2.5 V/3.3 V) 31 IPOL Analog bias current input
8 D12 Digital output CMOS output
(2.5 V/3.3 V) 32 VREFP Top voltage reference Can be external or
internal
9 D11 Digital output CMOS output
(2.5 V/3.3 V) 33 VREFM Bottom voltage reference 0 V
10 D10 Digital output CMOS output
(2.5 V/3.3 V) 34 AGND Analog ground 0 V
11 D9 Digital output CMOS output
(2.5 V/3.3 V) 35 VIN Analog input 1 Vpp
12 D8 Digital output CMOS output
(2.5 V/3.3 V) 36 AGND Analog ground 0 V
13 D7 Digital output CMOS output
(2.5 V/3.3 V) 37 VINB Inverted analog input 1 Vpp
14 D6 Digital output CMOS output
(2.5 V/3.3 V) 38 AGND Analog ground 0 V
15 D5 Digital output CMOS output
(2.5 V/3.3 V) 39 INCM Input common mode Can be external or
internal
16 D4 Digital output CMOS output
(2.5 V/3.3 V) 40 AGND Analog ground 0 V
17 D3 Digital output CMOS output
(2.5V /3.3 V) 41 AVCC Analog power supply 2.5 V
18 D2 Digital output CMOS output
(2.5 V/3.3 V) 42 AVCC Analog power supply 2.5 V
19 D1 Digital output CMOS output
(2.5 V/3.3 V) 43 DVCC Digital power supply 2.5 V
20 D0(LSB) Digital output LSB CMOS output
(2.5 V/3.3 V) 44 DVCC Digital power supply 2.5 V
21 DR Data ready output(1) CMOS output
(2.5 V/3.3 V) 45 DGND Digital ground 0 V
22 VCCBE Digital buffer power
supply 2.5 V/3.3 V 46 CLK Clock input 2.5 V compatible
CMOS input
23 GNDBE Digital buffer ground 0 V 47 DGND Digital ground 0 V
24 VCCBI Digital buffer power
supply 2.5 V 48 DGND Digital ground 0 V
1. See load considerations in Section 2.2: Timing characteristics.
Description RHF1401
10/42 Doc ID 13317 Rev 8
1.4 Equivalent circuits
Figure 3. Analog inputs Figure 4. Output buffers
AM04557
VIN or VINB
(pad)
AVCC
AGND
7 pF
AM04558
D0 …D13
7 pF
(pad)
VCCBE
GNDBE
GNDBE
OEB
Data
VCCBE
Figure 5. Clock input Figure 6. Data format input
AM04559
CLK
7 pF
(pad)
DVCC
DGND
AM04560
DFSB
7 pF
(pad)
VCCBE
GNDBE
Figure 7. Reference mode control input Figure 8. Output enable input
AM04562
OEB
7 pF
(pad)
VCCBE
GNDBE
RHF1401 Description
Doc ID 13317 Rev 8 11/42
Figure 9. VREFP and INCM input/output
Figure 10. VREFM input
AM04563
VREFP
7 pF
(pad)
AVCC
AGND
INCM
7 pF
(pad)
AVCC
AGND
REFMODE REFMODE
AM04564
VREFM
AVCC
AGND
7 pF
(pad)
High input impedance
Electrical characteristics RHF1401
12/42 Doc ID 13317 Rev 8
2 Electrical characteristics
2.1 Absolute maximum ratings and operating conditions
Table 3. Absolute maximum ratings
Symbol Parameter Values Unit
AVCC Analog supply voltage 3.3 V
DVCC Digital supply voltage 3.3 V
VCCBI Digital buffer supply voltage 3.3 V
VCCBE Digital buffer supply voltage 3.6 V
VIN
VINB Analog inputs: bottom limit −> top limit -0.6 V −> AVCC+0.6 V V
VREFP
VINCM External references: bottom limit −> top limit -0.6 V −> AVCC+0.6 V V
IDout Digital output current -100 to 100 mA
Tstg Storage temperature -65 to +150 °C
Rthjc Thermal resistance junction to case 22 °C/W
Rthja Thermal resistance junction to ambient 125 °C/W
ESD HBM (human body model)(1)
1. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a
1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations
while the other pins are floating.
2kV
Table 4. Operating conditions
Symbol Parameter Min Typ Max Unit
AVCC Analog supply voltage 2.3 2.5 2.7 V
DVCC Digital supply voltage 2.3 2.5 2.7 V
VCCBI Digital internal buffer supply 2.3 2.5 2.7 V
VCCBE Digital output buffer supply 2.3 2.5 3.4 V
VREFP Forced top voltage reference 0.7 1 1.4 V
VREFM Bottom external reference voltage 0 0 0.5 V
VINCM Forced common mode voltage 0.2 0.5 1.1 V
VIN
or VINB
Max. voltage versus GND 1 1.6(1)
1. See Figure 25. for differential input and Figure 42. to Figure 49. for single-ended.
V
Min. voltage versus GND -0.2 GND V
DFSB
Digital inputs 0 VCCBE VREFMODE
OEB
RHF1401 Electrical characteristics
Doc ID 13317 Rev 8 13/42
2.2 Timing characteristics
Figure 11. Timing diagram
The input signal is sampled on the rising edge of the clock while the digital outputs are
synchronized on the falling edge of the clock. The duty cycles on DR and CLK are the same.
The rising and falling edges of the OR pin are synchronized with the falling edge of the DR
pin.
Table 5. Timing characteristics
Symbol Parameter Test conditions Min Typ Max Unit
DC Clock duty cycle Fs = 20 Msps 45 50 65 %
Tod Data output delay (fall of
clock to data valid) (1)
1. As per Figure 11.
10 pF load capacitance 5 7.5 13 ns
Tpd Data pipeline delay(2)
2. If the duty cycle does not equal 50%: Tpd = 7 cycles + CLK pulse width.
Duty cycle = 50% 7.5 7.5 7.5 cycles
Ton Falling edge of OEB to
digital output valid data 1ns
Toff Rising edge of OEB to
digital output tri-state 1ns
TrD Data rising time 10 pF load capacitance 6 ns
TfD Data falling time 10 pF load capacitance 3 ns
N-2
N-1
NN+1
N+2
N+3
N+4
N+5 N+6
N+7
N+8
N-8N-7 N-6 NN-5 N -4 N+1N-3N-1
HZ state
Analog
input
CLK
OEB
Data
output
DR
Toff Ton
Tpd + Tod
Tod
AM06120
OR
Tod
Electrical characteristics RHF1401
14/42 Doc ID 13317 Rev 8
2.3 Electrical characteristics (after 300 kRad)
Unless otherwise specified, the test conditions in the following tables are:
AVCC = DVCC = VCCBI =VCCBE = 2.5 V, Fs=20 Msps, FIN= 15 MHz, VIN at -1 dBFS,
VREFP = 1 V, INCM = 0.5 V, VREFM = 0 V, Tamb = 25 °C.
Table 6. Analog inputs
Symbol Parameter Test conditions Min Typ Max Unit
VIN-VINB Full-scale reference voltage
(FS)(1)
1. See Section 4: Definitions of specified parameters for more information.
VREFP = 1 V
(forced)
VREFM = 0 V
2V
pp
CIN Input capacitance 7 pF
ZIN Input impedance Fs = 20 Msps 3.3 kΩ
ERB Effective resolution bandwidth(1) 70 MHz
Table 7. Internal reference voltage
Symbol Parameter Test conditions Min Typ Max Unit
Rout Output resistance of internal
reference
REFMODE = 0
internal reference
on
30 Ω
REFMODE = 1
internal reference
off
7.5 kΩ
VREFP Top internal reference voltage REFMODE = 0 0.76 0.84 0.95 V
VINCM Input common mode voltage REFMODE = 0 0.40 0.44 0.50 V
Table 8. External reference voltage(1)
1. See Figure 59.& Figure 60
Symbol Parameter Test conditions Min Typ Max Unit
VREFP Forced top reference voltage REFMODE = 1 0.7 1.4 V
VREFM Forced bottom ref voltage REFMODE = 1 0 0.5 V
VINCM Forced common mode voltage REFMODE = 1 0.2 1.1 V
Table 9. Static accuracy
Symbol Parameter Test conditions Min Typ Max Unit
DNL Differential non-linearity(1)
1. See Figure 33 and Section 4 for more information. This parameter is not tested.
Fin = 1.5 Msps
Vin at +1 dBFS
Fs = 1.5 Msps
±0.4 LSB
INL Integral non-linearity(2)
2. See Figure 34 and Section 4 for more information. This parameter is not tested.
±3 LSB
Monotonicity and no missing
codes Guaranteed
RHF1401 Electrical characteristics
Doc ID 13317 Rev 8 15/42
Higher values of SNR, SINAD and ENOB can be obtained by increasing the full-scale range
of the analog input if the sampling frequency allows it.
Table 10. Digital inputs and outputs
Symbol Parameter Test conditions Min Typ Max Unit
Clock input
CT Clock threshold DVCC = 2.5 V 1.25 V
CA Square clock amplitude
(DC component = 1.25 V) DVCC = 2.5 V 0.8 2.5 Vpp
Digital inputs
VIL Logic "0" voltage VCCBE = 2.5 V 0 0.25 x
VCCBE V
VIH Logic "1" voltage VCCBE = 2.5 V 0.75 x
VCCBE VCCBE V
Digital outputs
VOL Logic "0" voltage IOL = -10 µA 0 0.25 V
VOH Logic "1" voltage IOH = 10 µA VCCBE
-0.25 V
IOZ High impedance leakage
current OEB set to VIH -15 15 µA
CLOutput load capacitance High CLK
frequencies 15 pF
Table 11. Dynamic characteristics
Symbol Parameter Test conditions Min Typ Max Unit
SFDR Spurious free dynamic range
Fin = 15 MHz
Fs = 20 Msps
Vin at -1 dBFS
internal references
CL = 6 pF
70 91 dBFS
SNR Signal to noise ratio 66 70 dB
THD Total harmonic distortion 70 86 dB
SINAD Signal to noise and distortion
ratio 65 70 dB
ENOB Effective number of bits 10.6 11.5 bits
Electrical characteristics RHF1401
16/42 Doc ID 13317 Rev 8
2.4 Results for differential input
Setup
●AVCC = DVCC = VCCBI = VCCBE = 2.5V
●VREFP = 1 V
●VREFM = 0 V
●INCM = VREFP/2
●REFMODE = 1 (internal references are disabled)
●Vin = full scale - 0.3 dB
●Tamb = 25C°
●A square clock is applied
Unless other test conditions are specified.
Figure 12. Differential configuration
Cf is a filter capacitor to cut the HF noise. Its value is 10 nF for input frequencies equal to or
below 20 kHz. The value of the capacitor is divided by two when the input frequency is
multiplied by 2.
AM04565
Dierential
input signal
VIN
VINB
INCM
REFM
REFP
Ground
External 1V
External
2.5 V
VCCBE
VCCBI
AVCC
DVCC
VOCM
GENERATOR
V
OC
M
G
ENERAT
O
R
C
f
RHF1401 Electrical characteristics
Doc ID 13317 Rev 8 17/42
Figure 13. ENOB vs. input frequency Figure 14. SINAD vs. input frequency
10.8
11.2
11.6
12
ENOB (bits)
Fs =
10 ksps
100 ksps
1 Msps
10
10.4
10E +0 100E +0 1E +3 10E +3 100E +3 1E +6 10E +6 100E +6
Input frequency
10 Msps
30 Msps
-70
-68
-66
-64
-62
-60
S INAD (dB )
Fs =
10 ksps
100 ksps
1 Msps
10 Msps
30 Msps
-76
-74
-72
1E +1 1E +2 1E +3 1E +4 1E +5 1E +6 1E +7 1E +8
Input frequency
Figure 15. THD vs. input frequency Figure 16. SNR vs. input frequency
-80
-75
-70
-65
-60
THD (dB)
Fs =
10 ksps
100 ksps
1 Msps
10 Msps
30 Msps
-90
-85
1E +1 1E +2 1E +3 1E +4 1E +5 1E +6 1E +7 1E +8
Input frequency
66
68
70
72
74
76
SNR (dB)
Fs =
10 ksps
100 ksps
1M
60
62
64
1E +1 1E +2 1E+3 1E+4 1E +5 1E +6 1E+7 1E+8
Input frequency
1
M
sps
10 Msps
30 Msps
Figure 17. SFDR vs. input frequency Figure 18. Consumption vs. input frequency
70
75
80
85
90
SFDR (dB)
Fs =
10 ksps
100 ksps
1 Msps
60
65
1E +1 1E +2 1E +3 1E +4 1E +5 1E +6 1E +7 1E +8
Input frequency
10 Msps
30 Msps
60
70
80
90
100
110
120
w
er cons umption (mW)
Fs =
10 ksps
100 ksps
1 Msps
10 Msps
30 Msps
30
40
50
1E +1 1E +2 1E +3 1E +4 1E +5 1E +6 1E +7 1E +8
Po
Input frequency
Electrical characteristics RHF1401
18/42 Doc ID 13317 Rev 8
Figure 19. ENOB vs. sampling frequency Figure 20. SINAD vs. sampling frequency
11
11.5
12
ENOB (bits)
Fin =
10 Hz
1 kHz
50 kHz
10
10.5
1E +4 1E +5 1E +6 1E+7 1E+8
S ampling frequency
50
kHz
2 MHz
10 MHz
-70
-68
-66
-64
-62
-60
SINAD (dB)
Fin =
10 Hz
1 kHz
50 kHz
2 MHz
10 MHz
-74
-72
1E +4 1E +5 1E +6 1E +7 1E +8
Sampling frequency
Figure 21. THD vs. sampling frequency Figure 22. SNR vs. sampling frequency
-80
-75
-70
-65
-60
THD (dB)
Fin =
10 Hz
1 kHz
50 kHz
2 MHz
10 MHz
-90
-85
1E +4 1E +5 1E +6 1E +7 1E +8
S ampling frequency
66
68
70
72
74
76
SNR (dB)
Fin =
10 Hz
1 kHz
50 kHz
60
62
64
1E +4 1E +5 1E +6 1E +7 1E +8
S ampling frequency
50
kHz
2 MHz
10 MHz
Figure 23. SFDR vs. sampling frequency Figure 24. Power consumption vs. sampling
frequency
70
75
80
85
90
SFDR (dB)
Fin =
10 Hz
1 kHz
50 kH
60
65
1E +4 1E +5 1E +6 1E +7 1E +8
S ampling frequency
50
kH
z
2 MHz
10 MHz
80
100
120
140
160
180
o
wer cons umption (mW)
Fin =
10 Hz
1 kHz
50 kHz
2 MHz
10 MHz
20
40
60
1E +4 1E +5 1E +6 1E +7 1E +8
P
o
S ampling frequency
RHF1401 Electrical characteristics
Doc ID 13317 Rev 8 19/42
Figure 25. ENOB vs. VREFP Figure 26. SINAD vs. VREFP
10.5
11
11.5
12
12.5
ENOB (bits)
Fs =
10 ksps
100 ksps
1Msps
9.5
10
0.8 0.9 1 1.1 1.2 1.3 1.4
External Vrefp (V)
1
Msps
10 Msps
20 Msps
25 Msps
30 Msps
35 Msps
-70
-65
-60
-55
-50
SINAD (dB)
Fs =
10 ksps
100 ksps
1 Msps
10 Msps
20 Msps
25 Msps
30 Msps
35 Msps
-80
-75
0.8 0.9 1 1.1 1.2 1.3 1.4
External Vrefp (V)
Figure 27. SNR vs. VREFP Figure 28. THD vs. VREFP
65
70
75
80
SNR (dB)
Fs =
10 ksps
100 ksps
1 Msps
55
60
0.8 0.9 1 1.1 1.2 1.3 1.4
External Vrefp (V)
10 Msps
20 Msps
25 Msps
30 Msps
35 Msps
-75
-70
-65
-60
-55
-50
THD (dB)
Fs =
10 ksps
100 ksps
1 Msps
10 Msps
20 Msps
25 Msps
30 Msps
35 Msps
-90
-85
-80
0.8 0.9 1 1.1 1.2 1.3 1.4
External Vrefp (V)
Figure 29. ENOB vs. sine clock, diff. input Figure 30. Clock threshold vs. temperature
11
11.5
12
ENOB (bits)
Fin =
10 Hz
1 kHz
50 kHz
10
10.5
1 Msps 10 Msps 100 Msps
Sampling frequency
2 MHz
10 MHz
Electrical characteristics RHF1401
20/42 Doc ID 13317 Rev 8
Figure 31. ENOB vs. temperature Figure 32. Power consumption vs. temp.
10.5
11
11.5
12
12.5
ENOB (bits)
Fs =
200 sps
1 ksps
10 k
9
9.5
10
-55 -35 -15 5 25 45 65 85 105 125
Temperature (C°)
10
k
sps
100 ksps
1 Msps
20
30
40
50
e
r cons umption (mW)
R pol=330 kOhms
Fs =
10 ksps
100 k
0
10
-55 -35 -15 5 25 45 65 85 105 125
Pow
e
Temperature (C°)
100
k
sps
1 Msps
Figure 33. DNL, differential input Figure 34. INL, differential input
DNL (LSB)
INL (LSB)
RHF1401 Electrical characteristics
Doc ID 13317 Rev 8 21/42
2.5 Results for single ended input
Setup
●AVCC = DVCC = VCCBI = VCCBE = 2.5 V
●VREFP = 1 V
●VREFM = 0 V
●INCM = Vin/2
●REFMODE = 1 (internal references are disabled)
●Vin = 1 Vpp
●Tamb = 25 °C
●A square clock is applied
Unless other test conditions are specified.
In the following graphs, the input signal is seldom full scale.
Figure 35. Single-ended input configuration
Cf is a filter capacitor to cut the HF noise. Its value is 10 nF for input frequencies equal to or
below 20 kHz. The value of the capacitor is divided by two when the input frequency is
multiplied by 2.
AM04566
Single ended
input signal
VIN
VINB
INCM
REFM
REFP
Ground
External 1V
External
2.5 V
VCCBE
VCCBI
AVCC
DVCC
VOCM
GENERATOR
C
f
V
OC
M
G
ENERAT
O
R
Electrical characteristics RHF1401
22/42 Doc ID 13317 Rev 8
Figure 36. ENOB vs. Fin, single-ended Figure 37. SINAD vs. Fin, single-ended
Figure 38. THD vs. Fin, single-ended Figure 39. SNR vs. Fin, single-ended
Figure 40. SFDR vs. Fin, single-ended Figure 41. Power consumption vs. Fin
10
10.5
11
11.5
ENOB (bits)
Fs =
10 ksps
100 ksps
9
9.5
1E +1 1E +2 1E +3 1E +4 1E +5 1E +6 1E +7 1E +8
Input frequency
100
ksps
1 Msps
10 Msps
30 Msps
-60
-55
-50
SINAD (dB)
Fs =
10 ksps
100 ksps
1 Msps
10 Msps
30 Msps
-70
-65
1E +1 1E +2 1E +3 1E +4 1E +5 1E +6 1E +7 1E +8
Input frequency
-75
-70
-65
-60
-55
THD (dB)
Fs =
10 ksps
100 ksps
1 Msps
10 Msps
30 Msps
-85
-80
1E +1 1E +2 1E +3 1E +4 1E +5 1E +6 1E +7 1E +8
Input frequency
61
64
67
70
SNR (dB)
Fs =
10 ksps
100 ksps
55
58
1E +1 1E +2 1E +3 1E +4 1E +5 1E +6 1E +7 1E +8
Input frequency
1 Msps
10 Msps
30 Msps
65
70
75
80
85
SFDR (dB)
Fs =
10 ksps
00 k
55
60
1E +1 1E+2 1E+3 1E +4 1E+5 1E+6 1E +7 1E+8
Input frequency
1
00
k
sps
1 Msps
10 Msps
30 Msps
60
80
100
120
w
er consumption (mW)
Fs =
10 ksps
100 ksps
1 Msps
10 Msps
30 Msps
20
40
1E +1 1E +2 1E +3 1E +4 1E +5 1E +6 1E +7 1E +8
Po
Input frequency
RHF1401 Electrical characteristics
Doc ID 13317 Rev 8 23/42
Figure 42. ENOB vs. Vin, Fin 1 kHz, Vrefp = 0.8 V Figure 43. ENOB vs Vin, Fin = 2 MHz, Vrefp = 0.8 V
Figure 44. ENOB vs. Vin, Fin 1 kHz, Vrefp = 1.0 V Figure 45. ENOB vs Vin, Fin = 2 MHz, Vrefp = 1.0 V
Figure 46. ENOB vs. Vin, Fin 1 kHz, Vrefp = 1.2 V Figure 47. ENOB vs Vin, Fin = 2 MHz, Vrefp = 1.2 V
10.0
10.5
11.0
11.5
ENOB (bits)
Fin = 1 kHz - VREFP=0.8V
Fs =
10 ksps
9.0
9.5
1.01.11.21.31.41.51.6
Vin (Vpp)
100 ksps
1 Msps
10 Msps
20 Msps
25 Msps
30 Msps
10.0
10.5
11.0
11.5
ENOB (bits)
Fin = 2MHz - VREFP=0.8V
Fs =
9.0
9.5
1.0 1.1 1.2 1.3 1.4 1.5 1.6
Vin (Vpp)
2 Msps
10 Msps
20 Msps
25 Msps
30 Msps
10.0
10.5
11.0
11.5
ENOB (bits)
Fin = 1kHz - VREFP=1.0V
Fs =
10 ksps
100 k
9.0
9.5
1.0 1.1 1.2 1.3 1.4 1.5 1.6
Vin (Vpp)
100
k
sps
1 Msps
10 Msps
20 Msps
25 Msps
30 Msps
10.0
10.5
11.0
11.5
ENOB (bits)
Fin = 2MHz - VREFP=1.0V
Fs =
9.0
9.5
1.01.11.21.31.41.51.6
Vin (Vpp)
2 Msps
10 Msps
20 Msps
25 Msps
30 Msps
10.0
10.5
11.0
11.5
ENOB (bits)
Fin = 1kHz - VREFP=1.2V
Fs =
10 ksps
9.0
9.5
1.0 1.1 1.2 1.3 1.4 1.5 1.6
Vin (Vpp)
100
k
sps
1 Msps
10 Msps
20 Msps
25 Msps
30 Msps
10.0
10.5
11.0
11.5
ENOB (bits)
F in = 2MHz - VR E F P =1.2V
Fs =
9.0
9.5
1.0 1.1 1.2 1.3 1.4 1.5 1.6
Vin (Vpp)
Fs
=
2 Msps
10 Msps
20 Msps
25 Msps
30 Msps
Electrical characteristics RHF1401
24/42 Doc ID 13317 Rev 8
Figure 48. ENOB vs. Vin, Fin 1 kHz, Vrefp = 1.4 V Figure 49. ENOB vs Vin, Fin = 2 MHz, Vrefp = 1.4 V
10.0
10.5
11.0
11.5
ENOB (bits)
Fin = 1kHz - VREFP=1.4V
Fs =
10 ksps
9.0
9.5
1.0 1.1 1.2 1.3 1.4 1.5 1.6
Vin (Vpp)
100 ksps
1 Msps
10 Msps
20 Msps
25 Msps
30 Msps
10.0
10.5
11.0
11.5
ENOB (bits)
Fin = 2MHz - VREFP=1.4V
Fs =
9.0
9.5
1.01.11.21.31.41.51.6
Vin (V pp)
2 Msps
10 Msps
20 Msps
25 Msps
30 Msps
RHF1401 User manual
Doc ID 13317 Rev 8 25/42
3 User manual
3.1 Optimizing the power consumption
The polarization current in the input stage is set by an external resistor (Rpol). When
selecting the resistor value, it is possible to optimize the power consumption according to
the sampling frequency of the application. For this purpose, an external Rpol resistor is
placed between the IPOL pin and the analog ground.
The values in Figure 50 are achieved with VREFP = 1 V, VREFM = 0 V, INCM = 0.5 V and
the input signal is 2 Vpp with a differential DC connection. If the conditions are changed, the
Rpol resistor varies slightly.
Figure 50 shows the optimum Rpol resistor value to obtain the best ENOB value. It also
shows the minimum and maximum values to get good results. ENOB decreases by
approximately 0.2 dB when you change Rpol from optimum to maximum or minimum.
If Rpol is higher than the maximum value, there is not enough polarization current in the
analog stage to obtain good results. If Rpol is below the minimum, THD increases
significantly.
Therefore, the total dissipation can be adjusted across the entire sampling range to fulfill the
requirements of applications where power saving is critical.
For sampling frequencies below 2 MHz, the optimum resistor value is approximately
400 kOhms.
Figure 50. Rpol values vs. Fs
The power consumption depends on the Rpol value and the sampling frequency. In
Figure 51, it is shown with the internal references disabled (REFMODE = 1) and Rpol
defined in Figure 50 as the optimum.
100
1000
is tor (k Ohms )
maximum
optimum
minimum
1
10
0 5 10 15 20 25 30 35 40
R pol res
S ampling frequency (Msps )
User manual RHF1401
26/42 Doc ID 13317 Rev 8
Figure 51. Power consumption values vs. Fs with internal references disabled
80
100
120
140
160
180
200
o
nsumption (mW)
0
20
40
60
0 5 10 15 20 25 30 35 40
Power c
o
S ampling frequency (MHz)
RHF1401 User manual
Doc ID 13317 Rev 8 27/42
3.2 Driving the analog input
The input frequency can range from DC to tens of MHz.
The input stages (VIN and VINB) have a special design that limits the input amplitude. For
each of them, the maximum input voltage is about 1.6 V for low sampling frequencies and
less for high sampling frequencies. Low voltage is ground.
Consequently, the maximum input voltage read by the ADC for Single-ended mode is 1.6 V
regardless of the VREFP and VREFM voltages.
3.2.1 Differential mode
The INCM value must be equal to the medium input voltage value.
In differential mode, high sampling limitation is seen in Figure 25.
For all input frequencies, it is mandatory to add a capacitor on the PCB (between VIN and
VINB) to cut the HF noise. The lower the frequency, the higher the capacitor.
The full-scale range is twice the difference between Vrep and Vrefm.
Figure 52. Equivalent VIN - VINB (differential input)
The RHF1401 is designed to obtain optimum performance when driven on differential inputs
with a differential amplitude of two volts peak-to-peak (2 Vpp). This is the result of 1 Vpp on
the VIN and VINB inputs in phase opposition.
The RHF1401 is specifically designed to meet sampling requirements for intermediate
frequency (IF) input signals. In particular, the track-and-hold in the first stage of the pipeline
is designed to minimize the linearity limitations as the analog frequency increases.
Table 12. Differential mode output codes
Vin - Vinb = DFSB = 1 DFSB = 0
+ (VREFP-VREFM) 3FFF 1FFF
01FFF3FFF
- (VREFP-VREFM) 0000 2000
AM04567
INCM (level 0, code 8191)
(level - FS, code 0)
(level + FS, code 16383)
FS (full-scale)
= 2(VREFP - VREFM)
VIN
VINB
VIN -VINB
User manual RHF1401
28/42 Doc ID 13317 Rev 8
Figure 53. 2 Vpp differential input
Figure 54 shows a differential input solution. The input signal is fed to the transformer’s
primary, while the secondary drives both ADC inputs. The transformer must be matched
with generator output impedance: 50 Ω in this case for proper matching with a 50 Ω
generator. The tracks between the secondary and VIN and VINB pins must be as short as
possible.
Figure 54. Differential implementation using a balun
The input common-mode voltage of the ADC (INCM) is connected to the center tap of the
transformer’s secondary in order to bias the input signal around the common voltage (see
Table 7: Internal reference voltage).The INCM is decoupled to maintain a low noise level on
this node. Ceramic technology for decoupling provides good capacitor stability across a
wide bandwidth.
AM04570
VIN
VINB
1 Vp -p
INCM
1 Vp -p
Ground
REFP
REFM
VIN -VINB (2 Vp-p)
1 V
INCM
INCM
0.5V
REFMODE 2.5
V
AM04571
100 nF* ceramic
(as close as
possible to
INCM pin)
50 Ω
33 pF
ADT1 -1
1:1
Analog input signal
50 Ω track Short track
470 nF* ceramic
(as close as possible
to the transformer)
External
INCM
(optional)
*the use of a ceramic technology is
preferable for a large bandwidth
stability of the capacitor
VIN
VINB
INCM
(50 Ω output)
RHF1401 User manual
Doc ID 13317 Rev 8 29/42
3.2.2 Single-ended mode
Figure 55. Optimized single-ended configuration (DC coupling), external REFP
The RHF1401 is designed for use in a differential input configuration. Nevertheless, it can
achieve good performance in a single-ended input configuration. In single-ended,
performances depend on the input voltage, input frequency, voltage of references and
sampling frequency (refer to Figure 42. to Figure 49.)
VREFP and INCM internal voltage references are not adapted to Single-ended mode.
Some applications may require a single-ended input, which can easily be achieved with the
configuration shown in Figure 56, Figure 57 for AC coupling or Figure 35. for DC coupling.
However, with this type of configuration, a degradation in the rated performance of the
RHF1401 may occur compared with a differential configuration. A sufficiently decoupled DC
reference should be used to bias the RHF1401 inputs. An AC-coupled analog input can also
be used and the DC analog level set with a high value resistor R (6 kΩ to 100 kΩ) connected
to a proper DC source. Cin and R behave like a high-pass filter and are calculated to set the
lowest possible cut-off frequency.
Each input is limited to about 1.6 V due to the CMOS transistor on the input path. Voltage
can be a bit more or less than 1.6 V depending on temperature, AVCC, and variations from
one die to another (see Figure 3 for the analog input schematic). This “input limitation” is
independent of the VREFP and VREFM values.
Table 13. Single-ended mode output codes with Vinb = INCM
Vin = DFSB = 1 DFSB = 0
INCM + (VREFP-VREFM) 3FFF 1FFF
INCM 1FFF 3FFF
INCM - (VREFP-VREFM) 0000 2000
AM04569
VIN
VINB
External
VIN
INCM
Ground
INCM
VIN
REFM
max = 1.6V
INCM
0 V (ground)
REFP
External
User manual RHF1401
30/42 Doc ID 13317 Rev 8
The OR pin should rise to 1 when the signal is out of range. However, when VREFP = 0.8 V,
VREFM = 0 V, and input voltage max = 1.6 V, the ADC may not read the maximum input
voltage due to the CMOS input transistor. Consequently, the OR pin does not rise to 1. To
avoid this situation occurring, it is recommended to limit the input amplitude to 1.5 V, VREFP
to 0.75 V, and VREFM to 0 V.
Figure 56. AC-coupling single-ended input configuration
Figure 57. AC-coupling single-ended input configuration for low frequencies
The C capacitor is efficient in reducing noise at high frequencies. When coupled with the
resistors, R and C together behave like a high-pass filter. For example, if R = 10 k and
C = 33 pF, the cut-off frequency of this filter equals 482 kHz.
AM04572
100 nF ceramic*
(as close as possible
to INCM pin)
R
Cin
Short track
50 Ω
External INCM
(optional)
R
VIN
VINB
INCM
Short track
470 pF
ceramic* 100 nF
ceramic*
*the use of a ceramic technology is
preferable for a large bandwidth
stability of the capacitor
Analog input signal
(50 Ω output)
50 Ω track
AM04573
100 nF ceramic*
(as close as possible
to INCM pin)
R
Short track
50 Ω
External INCM
(optional)
*ceramic technology for a large
bandwidth stability of the capacitor
R
VIN
VINB
INCM
Short track
C
Analog input signal
(50 Ω output)
50 Ω track
Cin
RHF1401 User manual
Doc ID 13317 Rev 8 31/42
3.3 Reference connections
3.3.1 Internal voltage reference
In standard configuration, the ADC is biased with two internal voltage references: VREFP
and INCM. They should be decoupled to minimize low and high frequency noise. When the
REFMODE pin is set to 0 both internal voltage references are enabled and they can drive
external components or be forced by an external value.
The VREFM pin has no internal reference and must be connected to a voltage reference. It
is usually connected to the analog ground.
Figure 58. Internal voltage reference setting
3.3.2 External voltage reference
External voltage references can be used for specific applications requiring better linearity,
enhanced temperature behavior, or different voltage values (see Table 7: Internal reference
voltage). Internal voltage references are disabled when the REFMODE pin is equal to 1. In
this case, external voltage references must be applied to the device.
External voltage references can be applied when internal voltage references are disabled or
not.
When internal voltage reference are disabled, ADC consumption is about 13 mA less than
when they are enabled.
The external voltage references with the configuration shown in Figure 59 and Figure 60
can be used to obtain optimum performance. Decoupling is achieved by using ceramic
capacitors, which provide optimum linearity versus frequency.
AM04574
470 nF*
100 nF*
VIN
VINB
VREFM
VREFP
As close as possible
to the ADC pins
*the use of a ceramic technology is
preferable for a large bandwidth
stability of the capacitor.
REFMODE
470 nF*
100 nF*
INCMINCM
User manual RHF1401
32/42 Doc ID 13317 Rev 8
Note: *The use of ceramic technology is preferable to ensure large bandwidth stability of the
capacitor.
In multi-channel applications, the high impedance input (when REFMODE = 1) of the
references allows one to drive several ADCs with only two voltage reference devices.
In Differential mode the voltage of the analog input common mode (INCM) should be around
VREFP/2. Higher levels introduce more distortion.
Figure 59. External voltage reference setting Figure 60. Example with zeners
AM04575
470 nF*
100 nF*
VIN
VINB
VREFM
VCCA VREFP
As close as possible
to the ADC pins
DC
source
INCM
REFMODE
470 nF*
100 nF*
DC
source
AM04576
470 nF*
100 nF*
R
As close as possible
to the ADC pins
470 nF*
100 nF*
VIN
VINB
VREFM
VCCA VREFP
R1
As close as possible
to the ADC pins
REFMODE
470 nF*
100 nF* 470 nF*
100 nF*
R2
INCM
RHF1401 User manual
Doc ID 13317 Rev 8 33/42
3.4 Clock input
The quality of the converter very much depends on the accuracy of the clock input in terms
of jitter. The use of a low-jitter, crystal-controlled oscillator is recommended.
The following points should also be considered.
●The clock’s power supplies must be independent of the ADC’s output supplies to avoid
digital noise modulation at the output.
●When powered-on, the circuit needs several clock periods to reach its normal operating
conditions.
Figure 61. Clock input schematic
The signal applied to the CLK pin is critical to obtain full performance from the RHF1401.
Below 10 MHz, the sine clock does not have transition times fast enough to achieve good
performances. It is recommended to use a square signal with fast transition times and to
place proper termination resistors as close as possible to the device.
The sampling instant is determined by the clock signal’s rising edge. The jitter associated
with this instant must be as low as possible to avoid SNR degradation on fast moving input
signals. To make sure any error is less than 0.5 LSB, the total jitter Tj must satisfy the
following condition for a full-scale input signal.
For example, the total jitter with a 14-bit resolution for a 10 MHz full-scale input should be no
more than 1 picosecond (rms).
In most cases, the clock signal jitter is responsible for noise. Therefore, you must pay
attention to the clock signal when fast signals are acquired with a low frequency clock.
AM04577
50 Ω
CLK
DVcc/2
DVcc/2
Square clock
Sine clock Short track
CLK
Short track
50 Ω
50 Ω clock generator
Tj1
πFin 2n1+
⋅⋅
---------------------------------------
<
User manual RHF1401
34/42 Doc ID 13317 Rev 8
3.5 Operating modes
Extra functionalities are provided to simplify the application board as much as possible. The
operating modes offered by the RHF1401 are described in Table 14.
3.5.1 Digital inputs
Data format select bit (DFSB): when set to low level (VIL), the digital input DFSB provides
a two’s complement digital output MSB. This can be of interest when performing some
further signal processing. When set to high level (VIH), DFSB provides standard binary
output coding (see Table 12).
Output enable bit (OEB): when set to low level (VIL), all digital outputs remain active. When
set to high level (VIH), all digital output buffers are in a high impedance state while the
converter goes on sampling. When OEB is set to a low level again, the data arrives on the
output with a very short Ton delay. This feature enables the chip select of the device.
Figure 11: Timing diagram summarizes this functionality.
Reference mode control (REFMODE): this allows the internal or external settings of the
voltage references VREFP and INCM. REFMODE = 0 for internal references,
REFMODE = 1 for external references (and disables both references VREFP and INCM).
3.5.2 Digital outputs
Out of range (OR): this function is implemented on the output stage in order to set an "out-
of-range" flag whenever the digital data is over the full-scale range. Typically, there is a
detection of all data at ‘0’ or all data at ‘1’. It sets an output signal OR, which is in a low level
state (VOL) when the data stays within the range, or in a high-level state (VOH) when the
data read by the ADC is out of range.
Data ready (DR): the Data Ready output is an image of the clock being synchronized on the
output data (D0 to D13). This is a very helpful signal that simplifies the synchronization of
the measurement equipment of the controlling DSP. Like all other digital outputs, DR goes
into high impedance when OEB is set to a high level, as shown in Figure 11: Timing
diagram.
Table 14. RHF1401 operating modes
Inputs Outputs
Analog input differential
amplitude DFSB OEB OR DR Most significant bit (MSB)
(VIN-VINB) above maximum range HLHCLKD13
L L H CLK D13 complemented
(VIN-VINB) below minimum range HLHCLKD13
L L H CLK D13 complemented
(VIN-VINB) within range HLLCLKD13
L L L CLK D13 complemented
XXHHZ
(1)
1. High impedance.
HZ HZ (all digital outputs are in high
impedance)
RHF1401 User manual
Doc ID 13317 Rev 8 35/42
3.5.3 Digital output load considerations
The features of the internal output buffers limit the maximum load on the digital data output.
In particular, the shape and amplitude of the Data Ready signal, toggling at the clock
frequency, can be weakened by a higher equivalent load.
In applications that impose higher load conditions, it is recommended to use the falling edge
of the master clock instead of the Data Ready signal. This is possible because the output
transitions are internally synchronized with the falling edge of the clock.
3.6 PCB layout precautions
●The use of dedicated analog and digital ground planes on the PCB is recommended for
high-speed circuit applications to provide low parasitic inductance and resistance.
AGND is connected to the analog ground plane and DGND, GNDBI, GNDBE are
connected to the digital ground plane.
●To minimize the transition current when the output changes, the capacitive load at the
digital outputs must be reduced as much as possible by using the shortest-possible
routing tracks. One way to reduce the capacitive load is to remove the ground plane
under the output digital pins and layers at high sampling frequencies.
●The separation of the analog signal from the clock signal and digital outputs is
mandatory to prevent noise from coupling onto the input signal.
●Power supply bypass capacitors must be placed as close as possible to the IC pins to
improve high-frequency bypassing and reduce harmonic distortion.
●All leads must be as short as possible, especially for the analog input, so as to
decrease parasitic capacitance and inductance.
●Choose the smallest-possible component sizes (SMD).
Figure 62. Output buffer fall time Figure 63. Output buffer rise time
10
15
20
25
Fall time (nS)
VCCBE=2.5V
VCCBE=3.3V
0
5
0 1020304050
load capacitor (pF)
10
15
20
25
Rise time (nS)
VCCBE=2.5V
VCCBE=3.3V
0
5
0 1020304050
load capacitor (pF)
Definitions of specified parameters RHF1401
36/42 Doc ID 13317 Rev 8
4 Definitions of specified parameters
4.1 Static parameters
Differential non-linearity (DNL)
The average deviation of any output code width from the ideal code width of 1 LSB.
Integral non-linearity (INL)
An ideal converter exhibits a transfer function that is a straight line from the starting code to
the ending code. The INL is the deviation from this ideal line for each transition.
4.2 Dynamic parameters
Spurious free dynamic range (SFDR)
The ratio between the power of the worst spurious signal (not always a harmonic) and the
amplitude of the fundamental tone (signal power) over the full Nyquist band.
Expressed in dBc.
Total harmonic distortion (THD)
The ratio of the rms sum of the first five harmonic distortion components to the rms value of
the fundamental line. Expressed in dB.
Signal to noise ratio (SNR)
The ratio of the rms value of the fundamental component to the rms sum of all other spectral
components in the Nyquist band (Fs/2) excluding DC, fundamental and the first five
harmonics. Reported in dB.
Signal-to-noise and distortion ratio (SINAD)
A similar ratio to the SNR but that includes the harmonic distortion components in the noise
figure (not the DC signal). Expressed in dB. From SINAD, the effective number of bits
(ENOB) can easily be deduced using the formula:
SINAD = 6.02
×
ENOB + 1.76 dB
When the analog input signal is not full-scale (FS) but has an A0 amplitude, the SINAD
expression becomes:
SINAD = 6.02
×
ENOB + 1.76 dB + 20 log (A0 / FS)
Analog input bandwidth
The maximum analog input frequency at which the spectral response of a full power signal
is reduced by 3 dB. Higher values can be achieved with smaller input levels.
Pipeline delay
The delay between the initial sample of the analog input and the availability of the
corresponding digital data output on the output bus. Also called data latency. Expressed as
a number of clock cycles.
RHF1401 Package information
Doc ID 13317 Rev 8 37/42
5 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Package information RHF1401
38/42 Doc ID 13317 Rev 8
Figure 64. Ceramic SO-48 package mechanical drawing
Note: The upper metallic lid is not electrically connected to any pins, nor to the IC die inside the
package. Connecting unused pins or metal lid to ground or to the power supply will not affect
the electrical characteristics.
Table 15. Ceramic SO-48 package mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 2.18 2.47 2.72 0.086 0.097 0.107
b 0.20 0.254 0.30 0.008 0.010 0.012
c 0.12 0.15 0.18 0.005 0.006 0.007
D 15.57 15.75 15.92 0.613 0.620 0.627
E 9.52 9.65 9.78 0.375 0.380 0.385
E1 10.90 0.429
E2 6.22 6.35 6.48 0.245 0.250 0.255
E3 1.52 1.65 1.78 0.060 0.065 0.070
e 0.635 0.025
f 0.20 0.008
L 12.28 12.58 12.88 0.483 0.495 0.507
P 1.30 1.45 1.60 0.051 0.057 0.063
Q 0.66 0.79 0.92 0.026 0.031 0.036
S1 0.25 0.43 0.61 0.010 0.017 0.024
RHF1401 Ordering information
Doc ID 13317 Rev 8 39/42
6 Ordering information
Table 16. Order codes
Note: Contact your local ST sales office for information regarding the specific conditions for
products in die form and QML-Q versions.
Order code Quality level Temp range Package Marking Packing
RHF1401KSO1 Engineering model -55 °C to
+125 °C SO-48 RHF1401KSO1 Strip pack
RHF1401KSO-01V QMLV-Flight 5962F0626001VXC
Revision history RHF1401
40/42 Doc ID 13317 Rev 8
7 Revision history
Table 17. Document revision history
Date Revision Changes
29-Jun-2007 1
First public release.
Failure immune and latchup immune value increased to
120 MeV-cm2/mg.
Updated package mechanical information.
Removed reference to non rad-hard components from External
references, common mode: on page 16.
29-Oct-2007 2
Updated Figure 1: RHF1401 block diagram.
Added explanation on Figure 3: Timing diagram.
Added introduction to Section 6: Typical performance characteristics.
Updated Section 7.2: Clock signal requirements and Section 7.3:
Power consumption optimization.
Added Section 7.4: Low sampling rate recommendations.
Updated information on Data Ready signal in Section 7.5: Digital
inputs/outputs.
Added Figure 24: Impact of clock frequency on RHF1401
performance and Figure 25: CLK signal derivation.
09-Nov-2009 3
Changed input clock features in Table 10.
Modified Table 1 4.
Added Figure 62 to Figure 42.
26-Feb-2010 4
Modified Figure 1: RHF1401 block diagram.
Added details for Tdr and changed values for Tpd in Table 5: Timing
characteristics.
Modified Figure 11: Timing diagram.
Changed values for VREFP in Table 4 .
Changed Vin operating conditions in Table 4 , Figure 42 and
Figure 55.
Changed values for DNL in Table 9.
13-Sep-2010 5
Modified Figure 1 on page 7 and Figure 9 on page 11.
Added note 2. on page 13.
Modified CIN typ value in Table 6: Analog inputs as per Figure 3.
Modified Figure 11: Timing diagram.
Replaced Figure 18.
Added Table 12: Output codes for DFSB = 1.
Modified Figure 53: 2 Vpp differential input.
29-Jul-2011 6 Added Note: on page 31 and in the "Pin connections" diagram on the
cover page.
RHF1401 Revision history
Doc ID 13317 Rev 8 41/42
06-Apr-2012 7
Added Table 1: Device summary on cover page.
Updated curves in Section 2.3: Electrical characteristics (after
300 kRad).
Modified Section 3.1: Optimizing the power consumption.
Modified Section 3.2: Driving the analog input.
Modified Section 3.3.1: Internal voltage reference.
Modified Section 3.3.2: External voltage reference.
Modified Section 3.6: PCB layout precautions.
24-Oct-2012 8
Updated Table 1
Modified Figure 1: RHF1401 block diagram
Modified Figure 4: Output buffers
Modified Table 4 , Table 7, and Table 8
Modified Section 2.4: Results for differential input
Modified Section 2.5: Results for single ended input
Added comments and changed layout of Section 3.2: Driving the
analog input.
Modified Table 12
Modified Figure 55
Added Table 13
Added comments to Section 3.3: Reference connections
Modified Section 3.5.1: Digital inputs
Table 17. Document revision history (continued)
Date Revision Changes
RHF1401
42/42 Doc ID 13317 Rev 8
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2012 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com