4 ANALOG DEVICES LC?MOS Complete Embedded Servo Front Ends for HDD AD7773/AD7775* FEATURES 10-Bit, 3 ps ADC Two DACs with Output Amplifiers One 10-Bit, 4 ps Settling DAC One 8-Bit, 3 ps Settling DAC Fully Integrated Burst Demodulator Power-Down Mode +5 V Only Fast Interface Port 28-Pin SOIC Package APPLICATIONS Embedded Servo For HDD Combined Dedicated/Embedded Servo GENERAL DESCRIPTION The AD7773 and AD7775 provide all the functionality necessary to implement the servo demodulator and head positioning tasks in embedded servo systems. A power-down mode which turns all the linear circuitry OFF enhances the use of the AD7773 and AD7775 in portable systems. The demodulator channel can capture high speed servo data from a variety of embedded servo patterns. Up to four sequen- tial servo burst signals can be synchronously demodulated, full- wave rectified and integrated. At the end of a burst period the integrated output voltage, representing the amplitude of a cap- tured burst, is sampled and held on one of four internal track/ hold amplifiers prior to conversion. After conversion the digi- tized burst signals from the ADC are fed to four 10-bit wide data registers. The AD7773 and AD7775 also contain two independent voltage- output DACs: one with 10-bit resolution and one with 8-bit resolution. The two DACs produce output signals of the form Varas * Vswing Where Vpras and Vew yg are internally gener- ated on-chip. The Vgz,s signal is available externally on the REFOUT pin. The devices are easily interfaced to popular DSP processors and microcontrollers. The AD7773 has a 10-bit data port with separate address pins. The AD7775 has a 10-bit multiplexed address/data bus with an ALE input to latch the address. The AD7773 and AD7775 are fabricated in linear compatible CMOS (LC?CMOS), an advanced, mixed technology process that combines precision bipolar circuits with low power CMOS logic. The devices are available in 28-pin SOIC packages and 32-pin TSOPs. *Protected by U.S. Patent No. 4,990,916. REV.A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may resuit from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. FUNCTIONAL BLOCK DIAGRAMS Cint(-) C inrl+) CLKIN Voc fs. f\ i. fy Vv Tt VW Vin (+) zen & TRACK/ 10-BIT RECTIFIER HOLD ADC Vin (-) (X4) ADCREGS ADCREG3 DEMODULATOR ADCREG2 TR eTRL O77 CONTROL LOGIC ADGREGI STATUS AD7773 REGISTER | 49 DBO 10 DBO Vswinc CONTROL REGISTER 10-BIT ji DACA VoutA Ao ADDRESS 4, At DECODE 8-BIT VcB g-| oace out BUS INTERFACE CONTROL LOGIC REF Veias REFOUT cS wR wD DGND AGND AGND Cwt-) C int(+) CLKIN Vec fy f\. in fy NMS T V/s Vin (+) zep & TRACK 10-BIT RECTIFIER HOLD ADC Vin) (X4) ADCREGS ADCREG3 DEMODULATOR ADCREG2 TRL CTRL O) contROL Locic ADOREG STATUS AD7775 REGISTER | 49 DBO 10 DB9 Vswinc 37 | CONTROL REGISTER 10-BIT DACA VoutA ADDRESS 8, Z ALE DECODE e-BIT Vout8 | pace BUS INTERFACE RESET CONTROL LoGic REF Veuas REFOUT OGND AGND AGND One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Telex: 924491 Fax: 617/326-8703 Twx: 710/394-6577 Cable: ANALOG NORWOODMASS(Veg = +5 V + 5%; AGND = DEND = 0 V; CLKIN = 6.67 MHz; Cy; = 200 pF; Burst Frequency = 5 MHz; Cycles Integrated = 4. All specifications Ty, to Ty,x, unless otherwise stated.) AD7773/AD7775SPECIFICATIONS Parameter J Version! Units Conditions/Comments DEMODULATOR CHANNEL All AC Test Waveforms are Sinusoidal. Minimum Signal Frequency Is 2 MHz. ADC Resolution 10 Bits Demodulator Channel Gain, Gay 352 LSB/V p-p min |Channel Gain is (384 + 32) LSB/V p-p 416 LSB/V p-p max Intercept of Transfer Function on ADC Code Axis, ADC), 7cpr 137/+35 LSB min/max |See Terminology & Figure 19 Differential Input Resistance 4/6.5 kQ min/max Typically 5 kQ; Measured at DC; See Terminology Differential Input Capacitance? 1/4 pF min/max Common-Mode Input Resistance 2/3.5 kQ, min/max Typically 2.5 kQ; Measured at DC; See Terminology Common-Mode Input Capacitance 5/15 pF min/max ZCD Differential Hysteresis, Vj}, 40/120 mV p-p min/max|Typically 55 mV; See Figure 20 under Design Information Frequency Response to Pulse Harmonics 2nd Harmonics +10 % typ See Terminology 3rd Harmonics +20 % typ Common-Mode Rejection Ratio 46 dB min See Terminology Power Supply Rejection Ratio 40 dB min See Terminology Channel Noise Level? 49 dB min See Terminology Composite Noise Rejection 38 dB min Referenced to Half-Scale; See Terminology Vin Differential Input Signal Range for Guaranteed Positive Slope 0.24/2.26 V p-p min/max |See Terminology ADC Code for 0 mV p-p Differential Input Voltage, ADC, +35 LSB max See Figure 19 ADC Code for 240 mV p-p Differential Input Voltage, ADC j4g |ADCi99 + 4 LSB min ADCyo9 Is ADC Code for 200 mV pp Differential Input Voltage ADC Code for 417 mV p-p Differential Input Voltage, ADC,,, |ADC, + 10 LSB min ADC Code for 2260 mV p-p Differential Input Voltage, ADC,,,9 j|ADC 599 4 LSB min ADC, 599 Is ADC Code for 2500 mV p-p Differential Input Voltage ADC Code for 2500 mV p-p Differential Input Voltage, ADC,<59) | |1022 LSB max Voltage Change Across Cy for Full-Scale ADC Range REFOUT/2 V typ Gm, Transconductance from Vj, to Tour at Cynt(+) 0.277/0.306 mS min/max Relative Accuracy +4 LSB max 0.625 V to 1.875 V; See Terminology +8 LSB max 0.417 V to 2.083 V Differential Nonlinearity 1.3/+2 LSB max Guaranteed Monotonic to 9 Bits; See Terminology Channel Mismatch 10 LSB max Measured at Half-Scale; See Terminology Crosstalk Between Bursts 5 LSB max See Terminology ADC Conversion Time 14 Tern ps max Per Captured Burst; See Terminology TeixiIn 0.15/0.5 ps min/max Period of Input Clock CLKIN Te kin High? 60 ns min Minimum High Time for CLKIN Torin Low? 60 ns min Minimum Low Time for CLKIN Output Coding Unipolar Binary ANALOG OUTPUTS? Applies to Both DACs Output Voltage Range Varas Vswing|V min Vaias + Vswine|V max Digital-to-Analog Glitch Impulse 15 nV sec typ See Terminology Digital Feedthrough? 1 nV sec typ See Terminology DC Output Impedance 5 QO max Typically 0.5 0 Short-Circuit Current 20 mA max See Terminology Power Supply Rejection Ratio 20 dB min See Terminology Input Coding Offset Binary/2s Complement Programmable via Location CR6 of the Control Register REV. AAD7773/AD7775 Parameter J Version! Units Conditions/Comments ANALOG OUTPUTS? (Continued) DAC A Resolution 10 Bits Output Voltage Settling Time? 4 ps max Settling Time to Within + 1/2 LSB of Final Value; Typically 2.0 ys Relative Accuracy +1 LSB max Differential Nonlinearity +1 LSB max Guaranteed Monotonic Bias Offset Error +20 LSB max Plus or Minus Full-Scale Error +16 LSB max Referenced to REFOUT/2 DAC B Resolution 8 Bits Output Voltage Settling Time? 3 ps max Settling Time to Within +1/2 LSB of Final Value; Typically 2.0 ws Relative Accuracy +1 LSB max Differential Nonlinearity +1 LSB max Guaranteed Monotonic Bias Offset Error +6 LSB max Plus or Minus Full-Scale Error +6 LSB max Referenced to REFOUT/2. LOGIC INPUTS CS, WR, RD, CTRL, CLKIN, RESET & ALE (AD7775), AO & Al (AD7773) Input Low Voltage, Viny 0.8 V max Input High Voltage, Vix 2.4 V min Input Leakage Current 10 pA max Input Capacitance* 10 pF max LOGIC OUTPUTS DBO-DB9 (AD7773) ADO0-DB9 (AD7775) Vo. Output Low Voltage 0.4 V max Igsnwx = 1.6mA Vou Output High Voltage 4.0 V min Isource ~ 200 pA Floating State Leakage Current 10 pA max Floating State Capacitance 10 pF max POWER REQUIREMENTS Vcc Range 4.75/5.25 V min/V max |For Specified Performance Icc, Normal Mode* 30 mA max Control Register Locations CR8 = CR9 = Logic High Icc, Power Down Mode* 1.5 mA max Control Register Locations CR8 = Logic High, CR9 = Logic Low; All Linear Circuitry OFF Power-Up Time to Operational Specifications 500 ps max From Power Down Mode DAC REFERENCE INPUTS Varas for both DACs REFOUT v Internally Connected. Available Externally on REFOUT Pin Vswing for both DACs REFOUT/2 Vv Internally Connected REFERENCE OUTPUT REFOUT 2.1/2.2 V min/max Reference Load Change +3 mV max For Reference Load Current Change of 0 to +500 A +5 mV max For Reference Load Current Change of 0 to +2 mA Reference Load Should Not Change During Conversion NOTES 'Temperature range as follows: J Version: 0C to +70C. *Guaranteed by design, not production tested. Output load of 10k|100 pF is referenced to REFOUT. ee Input signal levels are as follows: Vixy;, = 0.85 V, Vinn = 2.35 V; CS = WR = RD = RESET (AD7775 only) = AO, Al (AD7773 only) = Vinu3 ALE (AD7775 Only) = CTRL = V,y,3 CLKIN = 6.67 MHz at 50% Mark-Space ratio between Vine & Vins nO conversion in progress and data bus, DBO-DB9 (AD7773 Only), ADO-DB9 (AD7775 only), tied to 0 V. oe Input signal levels are as follows: Ving. = 0 V, Vinn = Voeci CS = WR = RD = RESET (AD7775 only) = AO, Al (AD7773 Only) = Vinu3 ALE (AD7775 only) = CTRL = CLKIN = Vjx;3 data bus, DBO-DB9 (AD7773 only), ADO-AD9 (AD7775 only) tied to 0 V. For capacitive loads greater than 100 pF a series resistor is required. Specifications subject to change without notice. REV.AAD7773/AD7775 INTERFACE TIMING CHARACTERISTICS AD7773" 2 w,, = +5 v + 5%; Agno = penD = 0) Limit at Parameter Label Taan> Tmax Units Test Conditions/Comments INTERFACE TIMING Address Setup to WR or RD Falling Edge t 4 ns min Address Hold after WR or RD Rising Edge by 0 ns min Address Setup to CS Falling Edge ty 9 ns min WR or RD Rising Edge to CS Rising Edge ty 0 ns min WR or RD Pulse Width ts 53 ns min CS or RD Active to Valid Data? te 60 ns max Timed from Whichever Occurs Last Bus Relinquish Time after RD* b 10 ns min 22 ns max Data Valid to WR Rising Edge tg 55 ns min Data Valid after WR Rising Edge ty 10 ns min Delay Time Between Stack Reads tis 100 ns min See Figure 12b NOTES 'See Figures ] and 2. Timing Specifications in bold print are 100% production tested. All other times are sample tested at +25C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 34, is measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.8 V or 2.4 V. 4t, is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured time is then extrapo- lated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time t, quoted above is the true bus relinquish time of the device and, as such, is independent of the external bus loading capacitance. Specifications subject to change without notice. AO-A1 x le ty to cs wits it, AD r ts * << > +> t7 te DBO-DB9 Figure 1. Read Cycle Timing for AD7773 Interface AO-At DBO-DB9 mt to i pits \ ts > i o tg >t Figure 2. Write Cycle Timing for AD7773 Interface 42.1V Figure 3. Load Circuit for Bus Timing Characteristics REV.AAD7773/AD7775 INTERFACE TIMING CHARACTERISTICSAD7775" 2 wv, = +5 v + 59%, acho = pono = ow Limit at Parameter Label Tun to Tyax Units Test Conditions/Comments INTERFACE TIMING ALE Pulse Width t 50 ns min WR or RD Rising Edge to ALE Rising Edge ty 50 ns min ALE Rising Edge to CS Falling Edge ts 22 ns min CS Falling Edge to RD Falling Edge ty 60 ns min CS Falling Edge to WR Falling Edge ts 30 ns min WR or RD Rising Edge to CS Rising Edge te 0 ns min WR Pulse Width ty 53 ns min ALE Falling Edge to WR or RD Falling Edge ty 22 ns min Address Setup to ALE Falling Edge to 47 ns min Address Hold after ALE Falling Edge tio 22 ns min RD Active to Valid Data? th 75 ns max Measured with t, = 60 ns Bus Relinquish Time after RD? ty 10 ns min 62 ns max Data Valid to WR Rising Edge ty3 55 ns min Data Valid after WR Rising Edge lia 10 ns min Delay Time Between Stack Reads Us 100 ns min See Figure 13b NOTES See Figures 4 and 5. Timing specifications in bold print are 100% production tested. All other times are sample tested at +25C to ensure compliance. All input signals are specified with t, = ty = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. *Data access time depends directly on t,, the CS to RD setup time, e.g., t,, = 135 t,. Time t,, is measured with the load circuit of Figure 3 and is defined as the time required for an output to cross 0.8 V or 2.4 V. t,, is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time t,, quoted above is the true bus relinquish time of the device and, as such, is independent of external bus loading capacitance. Specifications subject to change without notice. t4 t > 1 to to ALE | ts ts cs ta cs ts > Hts, >| ts _ \ / _ P< RD tg K wR tg L j i me tay ato bag ADO-DB9 ADDRESS X DATA ADO-DB9 ADDRESS DATA }_____ + t 19 t12 it1i9 t13 Pe t14 Figure 4. Read Cycle Timing for AD7775 Figure 5. Write Cycle Timing for AD7775 REV.A 5-AD7773/AD7775 DEMODULATOR TIMING CHARACTERISTICS! w,, = +5 v = 5%; acno = peno = 0) Limit at Parameter Label Tan Tmax Units Test Conditions/Comments RESET Rising Edge to CTRL Rising Edge - 100 ns min For AD7775 Only WR Rising Edge to CTRL Rising Edge - 200 ns min Applies Only after a Write Instruction to the Control Register RESET Pulse Width? - 100 ns min For AD7775 Only SYNCHRONOUS DETECTOR MODE? CTRL High Time te; (N + 3.5) teye ns min Minimum N for Guaranteed Performance Is 4, Maximum N Is 15. Programmable via Locations CRO-CR3 of the Control Register CTRL Low Time? tc2 L.5 teye ns min Input Signal Period teyc 200 ns min Fundamental Input Frequency Must Lie Between 500 ns max 2 MHz and 5 MHz GATED DETECTOR MODE* CTRL High Time tc) 800 ns min CTRL Low Time? tcp 600 + 0.375 tcl ns min Input Signal Frequency fin 5 MHz max Corresponds to 200 ns Minimum Input Signal Period CALIBRATION MODE? CTRL High Time tc} 800 ns min Assumes Internal Calibration Voltage Has Settled; See Under Circuit Description for Calibration Mode CTRL Low Time te> 300 ns min NOTES 1A] input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. ?Sample tested at +25C to ensure compliance. ch Vv or 3See Figures 8a and 8b. 4See Figure 9. >See Figure 10. ABSOLUTE MAXIMUM RATINGS* Vcc to AGND or DGND AGND to DGND Digital Inputs to DGND Digital Outputs to DGND -0.3V,+7V -0.3 V, Veg +0.3 V -0.3 V, Voc +0.3.V -0.3 V, Veg +0.3 V Cir) Ciwrl+) Vee Analog Inputs to AGND ........... -0.3 V; Vee +0.3 V DIFFERENTIAL {FA vn Analog Outputs to AGND .......... -0.3 V, Vee +0.3 V INPUT SIGNAL o4 bY Vw) VourA Operating Temperature Range Commercial (J Version) ............... 0C to +70C Junction Temperature ..............200 0 eae + 150C AD7773/AD7775 REFOUT Storage Temperature Range ........... 65C to +150C Va B ou Power Dissipation, SOIC ....... 0.0... eee ee 1W our ;, Thermal Impedance ................0.-. 75CIW Lead Temperature (Soldering, 10 secs) ......... +300C Power Dissipation, TSOP ................... 750 mW Pp REFOUT @,, Thermal Impedance ................... 80C/W K REFOUT J : 9 INTERFACE Lead Temperature (Soldering, 10 secs) ......... +235C DGND_AGND_AGND *Stresses above those listed under Absolute Maximum Ratings may cause q A permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the D A operational sections of this specification is not implied. Exposure to absolute . . maximum rating conditions for extended periods may affect device reliability. AC Test Circuit Only one Absolute Maximum Rating may be applied at any one time. CAUTION ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy electro- static fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are inserted. WET Tee Oe ESD SENSITIVE DEVICE REV.AAD7773/AD7775 AD7773 SOIC ata] ao [2 | cikin [3 | oso [a | pai [5 | ps2 [6 | pss [77 | vps [a | pano [9 | pes [ro | oes [11] pe7 [12] OBs {13 DB9 (MSB) | 14 AD7773 TOP VIEW (Not to Scale) 28] RD 271 WR 26] cs 25! Vec 24| CTRL [23] AGND 22] Cint (+) 21) Cnt 20] Vy 19] Vin (+) 3] Vour B 17] REFOUT 16] AGND 5] Vout A AD7775 SOIC Reser [1] ate [2 | cLkin [3 | apo [a | api [5 | avz [6 | aps [7 | psa [8 | panp [9 | pes fio] ope [71 pa? [12| pes [13 DB9 (MSB) [14 AD7775 TOP VIEW (Not to Scale) RD cc LIL] pa 28 271 w 6| CS v 24] CTRL ES SESE) 23] AGND 22] Cinr(+) 21] Cinr(-) [20] VnQ 19] Vin(+) ia] Vout8 7] REFOUT 6] AGND ns] VoutA REV.A PIN CONFIGURATIONS AD7773 TSOP ne G] ano [2 | cTrt [3 | Vec [4] s C5] wr Le] ro [7 | ne [a | ne [9 | ai [10 ao [11 cLKIN [72 pBo [13 pei [14] pez [15] DB3 | 16 32] CINT(+) 31] CINT(-) [30] Vin () [29] Vin (+) [28] VourB 27 | REFOUT 26] AGND [25] VourA 24] NC 23] DBS (MSB) 22] DBS 21] 0B7 20] oB6 19] 0Bs 118] DGND [17] bBa AD7773 TOP VIEW (Not to Scale) NC = NO CONNECT AD7775 TSOP ne [1 | acnp [2 | CTRL [a] Vee L4 cs [5 32} CINT(+) [31] CINT() 30) Vin [23] Vin (+) 28] VourB wr [ | 27 | REFOUT ap [7] AD7775 26] AGND ne [e | TOP VIEW [25] VourA NC [1 (Not to Scale) 2a] NC RESET [10 [23] 0B9 (MSB) Ate [71 22] DBS cLKIN [72 21] 087 Apo [13 20] 086 ant [14 [19] DBs ap2 [75 [48] DaND aps [16 17] DBs NC = NO CONNECT ORDERING GUIDE Model Temperature Range | Package Option AD7773JR | 0C to +70C R-28! AD7773JU | 0C to +70C U-32? AD7775JR | 0C to +70C R-28 AD7775JU | 0C to +70C U-32 NOTES 'R = Small Outline IC (SOIC). ?U = Thin Small Outline Package (TSOP).AD7773/AD7775 SOIC PIN FUNCTION DESCRIPTION Pin Mnemonic Description Power Supplies 25 Vec +5 V Power Supply. 9 DGND Digital Ground. 16 & 23 AGND Analog Ground. Microprocessor Interface a 28 RD Read Input (Active Low). When active it is used in conjunction with CS to read data over the Input/Output bus. See the truth tables for Microprocessor Interfacing. 27 WR Write Input (Active Low). When active it is used in conjunction with CS to write data over the Input/Output bus. 26 CS Chip Select Input (Active Low). The device is selected when this input is low. Microprocessor InterfaceAD7773 Only 4-8 & DBO-DB4 = Input/Output Data Bus. A 10-bit wide bidirectional data port over which data is transferred 10-14 DBS5-DB9 __ into or out of the AD7773. DBO is the Least Significant Bit. 2 AO Address Inputs AO and Al select one of four registers. See Table I for details. 1 Al Microprocessor InterfaceAD7775 Only 4-8 & ADO-DB4 Multiplexed Address/Data Input/Output Bus. An ALE signal is used to demultiplex the bus. 10-14 DBS5-DB9 After the falling edge of ALE the address present on ADO-AD3 must be removed and WR or RD exercised to complete the instruction. The bus now transfers 10 bits of data into or out of the AD7775. ADO is the Least Significant Bit. 2 ALE Address Latch Enable Input used to demultiplex the address/data bus. On the falling edge of ALE address inputs ADI-AD3 are internally latched (ADO is a dont care) and remain latched until ALE returns High. See Table II for details. 1 RESET Reset Input (Active Low). Used as a hardware reset for various functional blocks: Demodulator Channel 19 20 22 21 24 3 Analog Outputs 15 18 17 Vin(+) Vin(-) Crxnr(+) Cinr() CTRL CLKIN VourA VourB REFOUT Loads half-scale code into both DAC registers. Resets the internal ADC register stack Write Pointer to the bottom-most register. Loads Control Register with 364 (Hex). See Control Register Description. Loads Status Register with 3E0 (Hex). See Status Register Description. Differential Inputs to the input amplifier. Analog input signals to these pins should be capac- itively coupled. The value of capacitor connected between these pins sets the integrator time constant. See under Design Information for choosing the Cy, capacitor. Control Input. All signal capture operations are controlled by this input. The number of CTRL pulses applied to the device must equal the number of bursts to be captured. Clock input. A clock is required for the ADC. An external TTL-compatible clock must be applied to this input pin. See the Tg, xin Specifications for CLKIN information. Each of the two DACs has the same output voltage range given by: Vour = Varas + Vswing = REFOUT + Vowine With midcode in either DAC register the respective DAC output is equal to REFOUT. Analog Output Voltage from DAC A. 1 LSB = 2 Vow yyg/1024 = REFOUT/1024 =2.1 mV. Analog Output Voltage from DAC B. 1 LSB = 2 Vewync/256 = REFOUT/256 = 8.6 mV. Voltage Reference Output. Internally this is used as the reference for the ADC and as the bias level (Vgias) for the two DACs. -8- REV.AAD7773/AD7775 TSOP PIN FUNCTION DESCRIPTION Pin Mnemonic Description Power Supplies 4 Voc 18 DGND 2 & 26 AGND Microprocessor Interface 7 RD 6 WR 5 cs +5 V Power Supply. Digital Ground. Analog Ground. Read Input (Active Low). When active it is used in conjunction with CS to read data over the Input/Output bus. See the truth tables for Microprocessor Interfacing. Write Input (Active Low). When active it is used in conjunction with CS to write data over the Input/Output bus. Chip Select Input (Active Low). The device is selected when this input is low. Microprocessor Interface AD7773 Only 13-17 & DBO-DB4 19-23 DB5-DB9 11 AO 10 Al Input/Output Data Bus. A 10-bit wide bidirectional data port over which data is transferred into or out of the AD7773. DBO is the Least Significant Bit. Address Inputs AO and Al select one of four registers. See Table I for details. Microprocessor InterfaceAD7775 Only 13-17 & ADO-DB4 19-23 DB5-DB9 il ALE 10 RESET Demodulator Channel 29 Vin(+) 30 Vin(-) 32 Cwr(+) 31 Cr() 3 CTRL 12 CLKIN Analog Outputs Multiplexed Address/Data Input/Output Bus. An ALE signal is used to demultiplex the bus. After the falling edge of ALE the address present on ADO-AD3 must be removed and WR or RD exercised to complete the instruction. The bus now transfers 10 bits of data into or out of the AD7775. ADO is the Least Significant Bit. Address Latch Enable Input used to demultiplex the address/data bus. On the falling edge of ALE address inputs AD1-AD3 are internally latched (ADO is a dont care) and remain latched until ALE returns High. See Table II for details. Reset Input (Active Low). Used as a hardware reset for various functional blocks: Loads half-scale code into both DAC registers. Resets the internal ADC register stack Write Pointer to the bottom-most register. Loads Control Register with 364 (Hex). See Control Register Description. Loads Status Register with 3E0 (Hex). See Status Register Description. Differential Inputs to the input amplifier. Analog input signals to these pins should be capac- itively coupled. The value of capacitor connected between these pins sets the integrator time constant. See under Design Information for choosing the C,,,7 capacitor. Control Input. All signal capture operations are controlled by this input. The number of CTRL pulses applied to the device must equal the number of bursts to be captured. Clock input. A clock is required for the ADC. An external TTL-compatible clock must be applied to this input pin. See the TQ, xin specifications for CLKIN information. Each of the two DACs has the same output voltage range given by: Vour = Varas + Vswing = REFOUT * Vswine With midcode in either DAC register the respective DAC output is equal to REFOUT. 25 VoutA Analog Output Voltage from DAC A. 1 LSB = 2 Vow nc/1024 = REFOUT/1024 = 2.1 mV. 28 VoutrB Analog Output Voltage from DAC B. 1 LSB = 2 Vewnc/256 = REFOUT/256 = 8.6 mV. 27 REFOUT _ Voltage Reference Output. Internally this is used as the reference for the ADC and as the bias level (Vpras) for the two DACs. 1, 8, 9, 24 NC No Connects. REV.A 9-AD7773/AD7775 CONTROL REGISTER DESCRIPTION The control register is 10-bits wide and can only be written to. Individual bit functions are described below. Normally the de- modulator channel operates as a synchronous detector to capture complete cycles of a servo burst waveform. However, if CRO to CR3 are loaded with all 0s, the demodulator channel performs as a simple gated detector stage, gated ON/OFF by the CTRL input. See under CIRCUIT DESCRIPTION Gated Detector Mode. CRO to CR3 determine the number of complete cycles to be syn- chronously detected within a single burst: CR3 CR2 CRI CRO Cycles 0 0 0 0 Gated Detector 0 0 0 1 NA 0 0 1 0 NA 0 0 1 1 NA 0 l 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 CR4 and CRS5 determine the number of bursts which are to be captured. CRS CR4 Number of Bursts 0 1 are OO 1 2 0 3 1 4 CR6 determines whether DAC coding is offset binary or twos complement. CR6 Coding 0 Offset Binary 1 Twos Complement CR7, CR8 and CR9 are decoded to provide a number of differ- ent functions. CR7 determines whether a signal will be acquired via the synchronous detectors differential inputs or direct from the Cyy--(+) pin. CR7 is ANDed with the internally generated integrate signal INT to make or break the signal path from the rectifier output to the Cy,.7(+) pin. With CR7 low the rectifier output drives the external integrating capacitor on the C,,,7 pins and all input signals are acquired through the V,,,(+) and Vin() differential input pins. With CR7 high the synchronous detector stage is bypassed and all input signals are now acquired through the single-ended C,,7(+) pin. CR9 CR8 CR7_ Function 0 0 X* Soft Reset 0 1 xX Power Down 1 0 0 Not Allowed 1 0 1 Calibration Mode 1 1 0 Normal Mode 1 1 1 Not Allowed *X = dont care. ~10 Soft Reset: Soft Reset performs the same functions that the RESET input performs. On receipt of a reset command (either via software or hardware) the control register is loaded with 364 (Hex) as shown below. CRO CRI CR2 CR3 CR4 CRS CR6 CR7 CR8 CR9 Se Oe KSB OOK CD Also on receipt of a reset command the status register is loaded with 3E0 (Hex); i.e., locations SRO-SR4 are loaded with all 0s indicating four good burst captures and conversions complete. Power Down: In the power down mode all linear circuitry is turned off. Both DAC outputs and the REFOUT output are pulled weakly (5 kQ) to AGND. Calibration Mode: The purpose of this mode is to allow any channel mismatch which may exist between the four internal track/hold amplifiers to be easily measured. See under CIR- CUIT DESCRIPTION Calibration Mode section. Normal Mode: This is the normal operating mode and allows external differential input signals to be acquired and converted. The contents of locations CRO-CR3 determine whether the demodulator channel will be in the synchronous detector mode or gated detector mode. STATUS REGISTER DESCRIPTION The status register (SR) is the bottom-most register of the 5-deep register stack. It is 10 bits wide and can be written to or read from. Its function is to provide status information on device operation. Location SRO acts as a BUSY signal for the demodulator channel. SRO is set high on the rising edge of the first CTRL pulse in a new burst capture sequence and remains high throughout the complete signal acquisition cycle and the subsequent conversion cycle. When the programmed number of conversions are complete, location SRO is set low. The number of conversions carried out equals the number of bursts captured. This number is programmable from 1 to 4 via locations CR4 and CRS5 of the control register. Up to four bursts can be cap- tured and each of these capture operations has an individual sta- tus flag, SRI-SR4, associated with it. A logic low or good flag in location SR1, for instance, indicates that burst #1 was cap- tured correctly. Alternatively, a logic high or bad flag in loca- tion SRI indicates that a problem occurred while capturing burst #1; i.e., for whatever reason, less than the programmed number of cycles in burst #1 were captured. Locations SR5-SR9 of the status register are reserved and must always be read as logic highs for correct operation of the AD7773 and AD7775. Primarily intended as a read only location, the status register has very limited write functionality. A write to the status register automatically loads all 1s into locations SRO-SR4 regardless of data present on the data bus. These flag settings represent four bad burst captures and conversions incomplete. REV.AAD7773/AD7775 As mentioned previously, locations SR5-SR9 are used for pro- duction test purposes and must be written high for correct oper- ation of the AD7773 and AD7775. All write instructions to the status register must load the word 11111XXXXX,. Repeated write instructions to address 11, (AD7773) or 011X, (AD7775) are all decoded to the status register. CIRCUIT DESCRIPTION The AD7773 and AD7775 are intended primarily for embedded servo head positioning applications in Winchester-type disk drives. The demodulator channel can capture high speed servo data from a variety of embedded servo patterns. Up to four sequential input signals can be captured, converted to digital form and stored in the four data registers ADCREG1-ADCREG4. The 10-bit DAC output can be used to control the head position via a voice coil motor (VCM). The 8-bit DAC output can be used for spindle speed control, gain control, filter control etc. There are two major modes of opera- tion of the demodulator channelsynchronous detector mode and gated detector mode. In the synchronous detector mode the differential input signals are applied in bursts to the differential inputs Vjy(+) and V;,(). A zero crossing detector (ZCD) is used to synchronously detect full cycles of the input signal within a given burst which are then rectified and integrated. Both the number of cycles within an individual burst and also the number of bursts to be captured are programmable. In the gated detector mode the synchronous detector is bypassed and the differential input signals are simply rectified and integrated as long as CTRL remains high. Whether in the synchronous detector mode or in the gated detector mode, a third mode, a calibration or CAL mode, is possible where a reference voltage is connected to the C,,,7(+) pin to allow any mismatch which exists between the four track/hold (T/H) amplifiers to be easily measured. A simplified diagram of the demodulator channel is shown in Figure 6. With CR7 a logic Low the normal mode is selected and SW1 is closed when a valid integrate INT signal is provided by the demodulator control logic. Switches SW1 and SW3 are functional only in the normal mode. In the calibrate mode CR7 is set to a logic high and SW is open regardless of the INT signal. Switch SW2 is closed only in the calibrate mode. The sequence of events in each mode is explained in the following text. Synchronous Detector Mode The differential input circuitry is shown in Figure 7. The value of the input capacitors should be chosen so that the pole formed by the capacitor and the 2.5 kQ equivalent input resistance is at least an order of magnitude below the lowest input signal fre- quency. These input resistors have a tolerance of +40% with a typical temperature coefficient of 300 ppm/C. The differential inputs are biased at approximately 1 V above AGND by means of a low output impedance voltage source. Cure) Cint Cint (+) | THAI 1.2V, INTERNAL wa: v Cm RESET VOLTAGE HOLD1 Cit RESET } THA2 Vin (+) swit M M recnren |_[ x Swe }y f-ro Yn x wooed x apc Al INT CR7 } THAR DEMODULATOR Cis CONTROL LOGIC cro vu cre HOLD3 CTRL re | *SWITCH CLOSED WITH HIGH DRIVE 10K | THAS REFOUT/4 ae L__ + 1.2V, INTERNAL orp, HOLD4 RESET VOLTAGE Figure 6. Simplified Block Diagram of Demodulator Channel TO ZCD/RECTIFIER {HIGH IMPEDANCE) TO ZCD/RECTIFIER (HIGH IMPEDANCE) AGND Figure 7. Simplified Input Circuitry of Demodulator Channel REV.A From the input pins the signal passes to both a zero crossing detector (ZCD) and a full wave rectifier. The output of the rec- tifier drives a transconductance amplifier to convert the rectified input voltage into an output current suitable for charging the external integrating capacitor C),--. Except during actual ADC conversions the ZCD is always enabled and produces a continu- ous pulse stream output reflecting the differential input signal transitions through 0 V. In fact, the input signal change must exceed the ZCDs input hysteresis, V,,, before its output changes. See Figure 20 in the DESIGN INFORMATION sec- tion. Since the ZCD output is usually completely asynchronous -11-AD7773/AD7775 with the timing of the CTRL input, the main task of the demodulator control logic is to synchronize these two signals in order to integrate only full cycles of the input waveform. This is achieved by initializing the cycle counter logic on the first ZCD output falling edge recognized after CTRL goes high and releas- ing the counter on the following ZCD output falling edge. This produces the integrate (INT) signal to close switch SW1 to start integrating. Full cycles of the input waveform can now be counted from falling edge to falling edge of the ZCD output. The asynchronous nature of the two signals results in a random lock-in time before the integrator starts, which can vary from 1 cycle to 2 cycles of the input waveform. This is illustrated in Figures 8a and 8b. CTRL must be high for a minimum time of (N + 3.5) teyc3 ie., 7.5 cycles of the maximum burst fre- quency of 5 MHz when N = 4. Firat Falling Edge Recognized by Demodulator Control Logic Second Falling Edge Releases Counter & Closes SW1 Cycle Count Exceeds Preprogrammed Number, SW1 Opened zcD OUTPUT bd bee te2 CTRL at tol >it > INT | (SW1 CONTROL) HOLDN Cit RESET (SW3 CONTROL) Figure 8a. Synchronous Detector Timing Waveforms with Lock-in Time of 2 Cycles & N = 4. First Falling Edge Recognized by Demodulator Control Logic Second Failing Edge Releases Counter & Closes SW1 Cycle Count Exceeds Preprogrammed Number, SW1 Opened zcD OUTPUT CTRL o tel te tc? 5 INT | (SW1 CONTROL) HOLDN | Cyr RESET (SW3 CONTROL) __. Figure 8b. Synchronous Detector Timing Waveforms with Lock-in Time of 1 Cycle & N = 4. 12- After the counter is released, the number of subsequent falling edges is counted and is compared with the number previously loaded into locations CRO-CR3 of the control register. When this count exceeds the preprogrammed number, the demodulator control logic brings INT Low, opening switch SW1 to halt the integrator. To ensure that the selected track/hold amplifier correctly acquires the integrated voltage on Cyy7, a further one full cycle of the ZCD output (i.e., one full cycle of the input waveform) is counted before a hold signal, HOLDI-HOLD4, is generated. When CTRL returns low, switch SW3 is closed to reset the voltage across the integrating capacitor to 0 V. The waveforms in Figure 8 are drawn for a correct burst capture and the status flag associated with this burst, SR1-SR4, is set good a logic lowin the status register. However, there may be occasions when, for whatever reason, less than the programmed number of cycles occur in a burst, and in these circumstances the trail- ing edge of CTRL acts as a fail-safe hold signal for the T/H amplifier. For instance if, while capturing a burst, the signal amplitude drops below the minimum ZCD comparator thresh- old, then the ZCD will obviously cease providing zero-crossing pulses and invalidate the cycle counting logic. In situations like this, the trailing edge of CTRL terminates the integrator directly. If any individual burst capture is terminated by the falling edge of CTRL, then its associated status flag in the status register is set high indicating a bad capture. In the situation where an expected burst is so low in amplitude as not even to trigger the ZCD, switch SW1 remains open and no signal is integrated. Again, this is flagged as incorrect operation and its associated status flag is set high or bad on the falling edge of CTRL. In either of these cases operation of the channel pro- ceeds normally with an A/D conversion being carried out on the incorrectly captured burst and the result stored in its respective data register. As each differential input signal burst is captured, one of the four internal T/H amplifiers tracks the integrated signal on the Ciyr pin. When a burst capture is complete, the tracking T/H amplifier is placed in the hold mode and the voltage on its hold capacitor remains held for subsequent A/D conversion. The selection of which T/H amplifier tracks the integrator output is determined by the contents of a write pointer. The write pointer logic ensures that the integrator output corresponding to the first burst captured is placed on C,,,, the integrator output cor- responding to the second burst captured is placed on Cy,, and so on. The write pointer is incremented after each CTRL pulse. Each individual burst capture operation requires its own sepa- rate CTRL pulse, i.e., if there are four bursts to be captured, four CTRL pulses are required. The number of bursts captured is compared with the number (1, 2, 3 or 4) previously loaded into locations CR4 and CRS5 of the control register. When the number of bursts captured equals the preprogrammed number of bursts expected, the rectifier/integrator section is turned off, the ZCD is disabled and the voltages held on the internal hold capacitors C,,;,;-Cy,, are sequentially applied to the ADC and are converted. As the ADC converts the held voltages, the results are loaded, again sequentially, into the data registers under the control of the write pointer. ADCREGI is filled first, followed REV.AAD7773/AD7775 by ADCREG2, etc. When all held voltages have been converted, the T/H amplifiers are released back into their track mode and the write pointer is left pointing at T/H amplifier #1. At this time also, the ZCD is again enabled. Note, however, that the 4-channel T/H multiplexer is enabled on the rising edge of the first CTRL pulse in a new burst capture sequence and remains enabled only for the duration of the capture sequence. Gated Detector Mode In this mode the synchronous detector is bypassed and the de- modulator channel behaves as a simple gated detector. To select the gated detector mode, locations CROCR3 of the control reg- ister are loaded with all 0s, location CR7 is loaded with a logic low and locations CR8 and CR9 are loaded with logic highs. A simplified timing diagram of the channel operating as a gated detector is shown in Figure 9. When CTRL goes high at the #1 #2 CTRL tco2 <-t,1 > |-at INT (SW1 CONTROL) HOLD1 te3 | << Cint RESET (SW3 CONTROL) Figure 9. Channel Timing Waveforms for Gated Detector Mode start of a signal capture operation, switch SW1 is closed and the integrator starts integrating the rectifiers output. It will con- tinue to do so as long as CTRL remains high, eventually satu- rating if CTRL is held high for too long. A minimum CTRL high pulse width of 800 ns is required in this mode. When CTRL returns low, switch SW1 is opened and the integrator is halted. As the rectifiers output is being integrated across C,.7, it is also being tracked by one of the four T/H amplifiers. To provide additional time for this T/H amplifier to completely ac- quire the integrated voltage, the falling edge of CTRL triggers a one-shot which delays the hold signal, HOLDI-HOLD4, until it times out. This delay, t.3, has a maximum time of 600 ns. When the hold signal is generated the tracking T/H amplifier is put in the hold mode and the voltage on its hold capacitor re- mains held for subsequent A/D conversion. The hold signal, in turn, triggers the C,,;7 reset signal, closing SW3 and resetting the voltage across C;,-7 to 0 V. Note that both plates of the Cyy;7 capacitor are at the internal reset voltage level of 1.2 V, available on C,,-7(), in readiness for the next signal capture operation. The minimum CTRL low time, t.2, depends on the duration of the preceding CTRL high time. The longer the inte- gration time, the longer must be the reset time, since the reset current is fixed. The minimum CTRL low time can be deter- mined from the expression: tc2 = 0.6 ps + 0.375 tel REV.A When the number of gated signals captured equals the pre- programmed number expected, the rectifier/integrator section is disabled and the held voltages are sequentially applied to the ADC and are converted. From here on, channel operation is identical to the synchronous detector mode as previously de- scribed. Note that locations SR1-SR4 of the status register now convey no meaningful information and should be ignored for gated detector operation. Calibration Mode The purpose of this mode is to allow any channel mismatch existing between the internal T/H amplifiers to be easily mea- sured. The number of T/H amplifiers tested will equal the num- ber stored in locations CR4 and CRS of the control register. Additionally the number of CTRL pulses applied must also equal this number. The calibration (CAL) mode is selected by loading locations CR9 and CR8 of the control register with a logic high and a logic low, respectively. This condition is de- coded to close switch SW2 and connect an internal dc reference, nominally REFOUT/4 above the Cj,,7() pin, to the Cyy7(+) pin. Additionally, to avoid shorting the integrator output, switch SW1 must be opened by loading a logic high into location CR7. Unlike either the synchronous or gated detector modes, the volt- age on C,,,7 is not discharged between successive CTRL pulses. In this mode the CTRL pulses simply generate the hold signals for the T/H amplifiers. The falling edge of the first CTRL pulse generates a hold signal, HOLD1, for T/H amplifier #1, the fall- ing edge of the second CTRL pulse generates HOLD2 for T/H amplifier #2, and so on. A timing diagram of the channel in the CAL mode is shown in Figure 10. #1 #2 CTRL te2 HOLD1 HOLD2 Figure 10. Channel Timing Waveforms for Calibration Mode A minimum CTRL pulse width of 800 ns is required to allow sufficient acquisition time for the relevant T/H amplifier. Note that this pulse width assumes that the voltage on the C,.,7(+) pin has settled to the nominal REFOUT/2 level before the first CTRL pulse is applied. In order to use the minimum CTRL pulse widths the demodulator channel must be placed in the calibration mode some time prior to applying the first CTRL pulse. With C),7 = 200 pF, this setup time is no longer than 20 ys. Alternatively, this setup time can be avoided by making the first CTRL pulse sufficiently wide to ensure that the calibra- tion voltage on the C,,7(+) pin has settled. Subsequent CTRL pulses can obviously have minimum pulse widths. ~13-AD7773/AD7775 Analog Outputs The AD7773 and AD7775 contain two independent voltage- output DACs: DAC A with 10-bit resolution and DAC B with 8-bit resolution. The two DACs produce output voltages of the form Vgras + Vswinc- Both Varas and Vswing reference levels are generated internally with Vg;,5 being available externally on the REFOUT pin. Vowing is nominally equal to REFOUT?/2. With half-scale code in a DAC register, the DAC output voltage is equal to Vpras3 with a positive full-scale code the DAC output is Veras + Vswing ! LSB; with a negative full-scale code the DAC output is Vgras Vswinc- Dependent upon the logic level stored in location CR6 of the control regis- ter, the DAC coding (for both DACs) will be either twos com- plement coding (CR6 = 1) or offset binary coding (CR6 = 0). Note that on receipt of a reset command (either via software or hardware), location CR6 is loaded with a logic high and the ana- log outputs of both DACs go to Vpras-. Figures lla and 11b show the DAC transfer functions for twos complement and off- set binary coding, respectively. Veias+Vswinc [ $$ $$ 4 . e ia 7 a - 7% & wi g 7 B 4 8 + e 5 Veias S$ e S$ T e E / 9 / a / Mw MA Ca a CA 7 7 + @ VeusVswing @4 6 $ | + $ + 10-BITDAC A_| 200 201 3FF 000 001 1FE 1FF 8-BIT DAC B 80 81 FF 00 01 7E 7F DIGITAL INPUT Figure 11a. DAC Output Voltages vs. DAC Input Codes in Hex Twos Complement Coding For twos complement coding the DAC output voltage can be expressed as: VourA/B = Varas + Vswine (2 Dap) where subscripts A and B refer to DACs A and B. For DAC A, Dg = N,/1024 where N, is the decimal equivalent of the twos complement input code; i.e., -SIZ=N,a = + S511 For DAC B, Dg = N,/256 where Ny, is the decimal equivalent of the twos complement input code; 1.e., 128 = Ng = + 127 With offset binary coding selected via location CR6 of the con- trol register, the DAC output voltage can be expressed as: VourA/B = Varas + Vswine (2 Dare 1) where subscripts A and B again refer to DACs A and B. For DAC A, D, = N,/1024 as before, where N, is the input code in decimal; i.e., 0=N, = + 1023 For DAC B, Dg = N,/256 as before, where Ng is the input code in decimal; i.e., O05 Ny, = + 255 14- Veias+Vswine [ $$ $$ t T oe 7 7 a BZ {7 & w g 7 6 7 al 8 t 5 Veias s$ S$ = T 2 7 9g 7 2 7 a 2 7 7 + Veias-Vswina @+ 6 + + sf t 10-BIT DAC A | 000 001 1FF 200 201 3FE 3FF 8-BIT DAC B oo (01 7F 80 81 FE FF DIGITAL INPUT Figure 11b. DAC Output Voltages vs. DAC Input Codes in Hex Offset Binary Coding REV. AAD7773/AD7775 MICROPROCESSOR INTERFACING interface to the 80C196, for instance, where word operations to Tables I and II show the truth tables for AD7773 and AD7775 odd addresses are not guaranteed to operate in a consistent man- microprocessor interfacing, respectively. The multiplexed ner. DAC data is always transferred as right-justified data, i.e., address/data bus used by the AD7775 is demultiplexed inter- the LSB should always appear on ADO whether loading the nally by means of the ALE signal. On the falling edge of ALE 10-bit DAC A or 8-bit DAC B. Similarly for the AD7773, address inputs AD1, AD2 and AD3 are latched and remain which has a dedicated 10-bit-wide data bus, DAC data is always latched until ALE returns high again. Note that address input transferred as right-justified data, i.e., the LSB should always ADO is a dont care input. This decoding scheme allows appear on DBO whether loading DAC A or DAC B. 2-byte word operations to even addresses only and simplifies the Table I. AD7773 Truth Table for Microprocessor Interfacing cs | RD | WR | Al AO DBO-DB9 Functions/Comments 1 x* Xx x x High Z Data Port High Impedance. 0 1 0 0 0 DAC Data Load 10-Bit DAC A Data to DAC A Register. 0 0 1 0 0 Low Z Reserved. Do Not Use. 0 1 0 0 1 DAC Data Load 8-Bit DAC B Data to DAC B Register. 0 0 1 0 1 Low Z Reserved. Do Not Use. 0 1 0 1 0 CR Data Load Control Register (CR) Data to CR. See Control Register Description. 0 0 1 1 0 Low Z Reserved. Do Not Use. 0 1 0 1 1 SR Data Load Status Register (SR) Data to SR. See Status Register Description. 0 0 1 1 1 Stack Data Contents of Stack Placed on Data Bus. See Stack Reading Description. *X = dont care. Table II. AD7775 Truth Table for Microprocessor Interfacing CS | RD | WR | AD3* | AD2* | AD1* | ADO | ADO-DB9 | Function/Comments 1 |X**/X |X X X Xx High Z Data Port High Impedance. 0 }1 0 X 0 0 X DAC Data | Load 10-Bit DAC A Data to DAC A Register. 0 1/0 1 0 0 0 xX Low Z Reserved. Do Not Use. 0 71 0 X 0 1 Xx DAC Data | Load 8-Bit DAC B Data to DAC B Register. 0 [0 1 0 0 1 xX Low Z Reserved. Do Not Use. 0 }1 0 Xx 1 0 Xx CR Data | Load Control Register (CR) Data to CR. See Control Register Description. 0 /0 1 0 1 0 x Low Z Reserved. Do Not Use. 0 }1 0 Xx 1 1 Xx SR Data Load Status Register (SR) Data to SR. See Status Register Description. 0 J0 1 0 1 1 Xx Stack Data | Contents of Stack Placed on Data Bus. See Stack Reading Description. 0 0 1 1 0 0 XxX ADC Data | Contents of ADCREGI1 Placed on Data Bus. 0 1/0 1 1 0 1 xX ADC Data | Contents of ADCREG2 Placed on Data Bus. 0 |0 1 1 1 0 xX ADC Data | Contents of ADCREG3 Placed on Data Bus. 0 0 1 1 1 1 x ADC Data | Contents of ADCREG4 Placed on Data Bus. *Latched internally on the falling edge of ALE. **X = dont care. REV.A 15-AD7773/AD7775 Stack Reading The register stack consists of a total of five registers: the status register and the four ADC data registers, ADCREGI-ADCREG4. The status register is the bottom-most register of the 5-deep reg- ister stack. Dependent upon the system architecture, the stack can be read in one of two ways. If the AD7773 and AD7775 are interfaced directly to a microprocessor bus then repeated read instructions to the stack address rotates the active stack locations through the data bus. One stack location is transferred per read instruction. This method of stack reading is shown in Figure 12a for the AD7773 (stack address = 11, ) and in Figure 13a for the AD7775 (stack address = 011X,). However, if the AD7773 or AD7775 is not directly interfaced to the microprocessor bus but comes through some peripheral controller (e.g., a propri- etary gate array), then the stack can be rotated by keeping the CS input low and repeatedly pulsing the RD input. This method of stack reading is shown in Figures 12b and 13b for the AD7773 and AD7775, respectively. For the AD7773, stack rotation is the only way in which data in the upper registers can be accessed. For the AD7775, however, the stack registers are individually addressable and the user can choose to access the data by rotating the stack, or by individu- ally addressing the registers in any order preferred. A read pointer ensures correct operation of the stack by setting equal the number of data registers which can be rotated and the number of bursts to be captured. The first read instruction to the register stack returns the contents of the status register. The read pointer is then incremented so that the next read operation from the stackusing the same addressreturns the conversion data from ADCREGI and so on. If n is the number of bursts to be captured (n = 1, 2, 3 or 4), then n + 1 read instructions are required to rotate the stack through all active stack registers. The stack is rotated only once with all additional read instruc- tions repeatedly placing the contents of the status register on the data bus. Note that the stack will rotate only when the pro- grammed number of conversions are complete; 1.e., only when status register flag SRO has returned low. When new data is loaded to the stack, for example, when a new burst sequence is captured, the read pointer is again enabled to rotate the stack registers through the data bus. Operation of the stack is summa- rized in Table III where all the read instructions are from stack addresses; 11, for the AD7773 and 011X, for the AD7775. Table III. Stack Read Operations Read Instruction Sequence Data Bus Ist Read Status Register 2nd Read ADCREG1 3rd Read Status Register if CR (5, 4) = (0, 0); ADCREG2 otherwise 4th Read Status Register if CR (5, 4) = (0, 0) or (0, 1); ADCREG3 otherwise 5th Read Status Register if CR (5, 4) = (0, 0), (0, 1) or (1, 0); ADCREG4 otherwise 6th Read Status Register. Succeeding Read instructions always call the Status Register -16- #1 Read Cycle A0=1 AO-Al \ Ala DBO-DB9 STATUS ADCREG1 REGISTER Figure 12a. AD7773 Stack Read Option 1 AO-At AO=1 A1l=1 cs #1 Read Cycie #2 Read Cycle RO tis STATUS ADCREG1 DBO-DBS REGISTER Figure 12b. AD7773 Stack Read Option 2 #1 Read Cycle #2 Read Cycle ALE /\ AD1=1 STATUS AD1 =1 ADO-DB9 + AD2 =1 REGISTER AD2=1 ADCREG1 AD3=0 AD3 =0 Figure 13a. AD7775 Stack Read Option 1 ALE /\ cs \ RD \ #1 Read Cycle | | #2 Read Cycle AD1=1 STATUS ADO-DB9 Apes K REGISTER Figure 13b. AD7775 Stack Read Option 2 ADCREG1 REV.AAD7773/AD7775 Microprocessor/Microcomputer Interfacing Circuits With its separate data and address bus architecture the AD7773 is intended to interface to DSP machines such as the ADSP- 2101, ADSP-2105 and the TMS320 family. The AD7775, with its multiplexed address/data bus, is suitable for microcontrollers such as the 80C196 family. Figure 14 shows the AD7773 interfaced to the TMS320C10 @ 20.5 MHz and the TMS320C14 @ 25 MHz. Figure 15 shows the interface with the TMS320C25 @ 40 MHz. Note that one wait state is required with this interface. The ADSP-2101-50 and the ADSP-2105-40 interface is shown in Figure 16. One wait state is required with either of these machines. Figure 17 shows the AD7775 interface to the 80C196KB @ 12 MHz and the 80C196KC @ 16 MHz. One wait state is required with the 16 MHz machine. The 80C196 is configured to operate with a 16-bit multiplexed address/data bus. A13-A0 ADSP-2101-50 ADSP-210540 D23-D8 ADDRESS BUS S ~ b&b Y Y ADDR AO Al DECODE pHwoeN foPlis AD7773* > WR AD DBS_DBO DATA BUS 4 * ADDITIONAL PINS OMITTED FOR CLARITY Figure 16. AD7773 to ADSP-2101 & ADSP-2105 Interface A11-A0 ADDRESS 8US 4 sb yy AD1S-ADB ADDR AQ Al (PORTA) |_ ADDRESS BUS DECODE _ es D . 373 |_| avor AD7773 LATCH DECODE AD7775* WE >) Wh _ (C10)DEN |= cs (C14)REN =| RD ALE - #1 ALE wr fF >| WR TMS320C10-20.5 DBS-DBO Ro K4 -| AD TMS320014-25 80C196KB-12 DBS-ADO D15-Do DATA BUS 5 80C196KC_16 Ld * ADDITIONAL PINS OMITTED FOR CLARITY AD7-ADO (PORT 3) DATA BUS CS Figure 14. AD7773 to TMS320C10 & -C14 Interface * ADDITIONAL PINS OMITTED FOR CLARITY Figure 15. AD7773 to TMS320C25 Interface REV. A A15-A0 ADDRESS BUS is ADDR AO Al READY Ko DECODE = MSC AD7773* STRB _ RW WR RD TMS320C2540 DBS-DB0 D15-D0 DATA BUS -17- * ADDITIONAL PINS OMITTED FOR CLARITY Figure 17. AD7775 to 80C196 InterfaceAD7773/AD7775 Terminology DEMODULATOR CHANNEL Relative Accuracy The relative accuracy specification is similar to a least squares specification for a standard ADC. For the demodulator channel, however, the least squares line is fitted not between the voltage levels corresponding to the traditional first and last code transi- tions, but is fitted now between designated voltage limits on either side of the nominal half-scale input voltage, 1.25 V pp differential. This scheme allows a tighter specification for signals around the half-scale point and a more relaxed specification for signals closer to zero-scale and full-scale. The AD7773/AD7775 specify linearity over the 1/4 FS to 3/4 FS signal range with a related linearity specification from 1/6 FS to 5/6 FS. For either range the ADC output codes which correspond to the designated input signal levels are found by applying a sequence of 5 MHz sinusoidal bursts to the demodulator channel and digitizing the signals. The 1/4 FS to 3/4 FS relative accuracy specification of the demodulator channel is the maximum deviation, in LSBs, of the ADCs actual code transition points from a least squares line fitted between the voltage limits of 0.625 V and 1.875 V inclu- sive. Note that this least squares line is of the form Y=mX +c where m is the gain of the channel, Gc,,, in LSB/V p-p and c is the intercept of the transfer function on the ADC code axis, ADC rcpr> in LSBs. Values for m and c are computed after the least square line is fitted between 1/4 FS and 3/4 FS. The 1/6 FS to 5/6 FS relative accuracy specification is referred to the least squares line already fitted between 1/4 FS and 3/4 FS but which is now extended to range from 0.417 V to 2.083 V inclu- sive. A graphical representation of the two linearity ranges are shown in Figure 18 where ADC code transitions are plotted ver- sus their corresponding input voltage levels; i.e., ADC,,7 repre- sents the ADC output code for a differential input voltage of 417 mV p-p. The LSB size is the inverse of the slope of the least squares line fitted, i.e., typically 1 LSB = 1/384 V = 2.60 mV. Note that due to both the zero-crossing detector threshold and the rectifier threshold, the least squares line shown in Figure 18 will not pass through the origin. acc # OUTPUT CODE ADC 2500 ADC a993 J ADC 1975 ADC g95 FS RANGE 4 ADCay7f RANGE 2 | | | | | 0.417 0.625 1.875 2.083 2.5 =W6FS =1/4FS =3/4FS =5/6FS =FS DIFFERENTIAL INPUT VOLTAGE, Vj, VOLTS Figure 18. Guaranteed Linearity Ranges for the Demodulator Channel Differential Input Resistance This is the dc input resistance measured between V),(+) and Vin(-). Common-Mode Input Resistance This is the dc input resistance measured between the shorted differential inputs, V},y(+) and V,;,\(), and ground. Intercept of Transfer Function on ADC Code Axis When the least squares line fitted between 1/4 FS and 3/4 FS is extended backwards towards the origin, it will intercept the ADC code axis at some value. This value, which is called the intercept of the transfer function on the ADC code axis, is equal to the value c computed from the equation Y=mX +c which the least squares line adheres to. Figure 19 shows the typ- ical demodulator performance for low level input signals. The minimum differential input signal is determined by the rectifier threshold. Apc OUTPUT CODE (LSBs) ADC 447 ADC 240 ADC 200 AM Z| 200 240 417 Vv / DIFFERENTIAL INPUT VOLTAGE, Vin, mV pp ADC intcpt / Figure 19. Demodulator Response for Low Level Input Signals Frequency Response to Pulse Harmonics This specification tests for gain peaking in the channel fre- quency response. Relative measurements, taken at three har- monically related frequencies, are compared and must be within specification. To maintain a constant integral at each frequency, the number of cycles are correspondingly increased as the signal period is decreased. Set up 5 MHz bursts at 0.7 V p-p and digitize. CROCR3 set for 4 cycles. Determine average ADC code, call it Code 1. ~Set up 10 MHz bursts at 0.7 V p-p and digitize. CRO-CR3 set for 8 cycles. Determine average ADC code, call it Code 2. -Set up 16.25 MHz bursts at 0.7 V pp and digitize. CRO-CR3 set for 13 cycles. Determine average ADC code, call it Code 3. Compare (Code 1-Code 2) and (Code 1Code 3) to the limits specified. 18- REV.ATerminology AD7773/AD7775 Due to the demodulation technique used in the AD7773 and AD7775, the frequency spectrum of the input signal can have an impact on the demodulator channel performance. To meet the specifications the following limits are placed on the harmonic content of the input signal (quoted in dB relative to a funda- mental at 5 MHz and 1.25 V p-p): 2nd Harmonic: 50 dB 3rd Harmonic: 12 dB 4th Harmonic: ~50 dB 5th Harmonic: 24 dB Higher Harmonics: 40 dB total Common-Mode Rejection Ratio Common-mode rejection ratio (CMRR) is a measure of the change in digital output code when both inputs are changed by equal amounts. Repeated bursts of half-scale amplitude, differ- ential 1.25 V pp at 5 MHz, are applied to the demodulator channel and digitized. These bursts sit on a common-mode signal of 50 mV pp magnitude and varying in frequency from 60 Hz to 30 kHz. The standard deviation of the resultant distribution of ADC codes is checked to be less than 3.1 LSBs, a result which includes the channel noise level. When corrected for the channel noise level by rms subtraction, e.g., {3.1)? (1.8)}", the standard deviation is found to be less than 2.5 LSBs, which is equivalent to a CMRR of 46 dB. This specifica- tion holds over the allowable Vcc range of 4.75 V to 5.25 V. Power Supply Rejection Ratio For the demodulator channel, power supply rejection ratio (PSRR) is a measure of the change in digital output code due to a change in the power supply voltage. Repeated bursts of half- scale amplitude, differential 1.25 V p~p at 5 MHz, are applied to the input and digitized. An ac signal, 50 mV pp amplitude and varying in frequency from 60 Hz to 30 kHz, is summed with the +5 V power supply Vgc. The standard deviation of the resultant distribution of ADC codes is checked to be less than 5.4 LSBs, a result which includes the channel noise level. When corrected for the channel noise level by rms subtraction, e.g., {(5.4)? (1.8)}", the standard deviation is found to be less than 5.1 LSBs, which is equivalent to a PSRR of 40 dB. This specification holds over the allowable Vcc range of 4.75 V to 5.25 V. Channel Noise Level Channel noise level is a measure of the intrinsic noise level of the modulator channel in the absence of common-mode signals and power supply interference. Repeated bursts of half-scale amplitude, differential 1.25 V p-p at 5 MHz, are applied to the input and digitized. The standard deviation of the resultant dis- tribution of ADC codes is checked to be less than 1.8 LSBs. This is equivalent to a channel noise level of 49 dB. Note that the duration of the burst capture sequence must be less than or equal to | ms. REV. A -19- Composite Noise Rejection Intended as an overall channel performance indicator, the com- posite noise rejection figure is an rms summation of the PSRR, CMRR, the channel noise level as defined above plus an INL error of 2.68 LSBs, representing the standard deviation, under identical test conditions, of the ADC codes from device to device. It is referenced to half-scale. Channel Mismatch Channel mismatch is a measure of the differences which may exist between the four internal track/hold (T/H) amplifiers. To measure mismatch the AD7773/AD7775 must be put in the calibration (CAL) mode by loading control register locations CR9 and CR8 with a logic high and a logic low, respectively. Additionally, CR7 must be loaded with a logic high. These conditions disconnect the output of the integrator from the inte- grating capacitor C,,,; and connect an internal dc reference (Nominally REFOUT/4 above the voltage on the C),-7() pin) to the Cj,,7(+) pin. The remainder of the demodulator channel operates normally: under the control of the CTRL input, the four T/H amplifiers are connected in turn to track-and-hold this reference voltage. Subsequently the held voltages are con- verted. Check the ADC output code for each channel to ensure results are within 10 LSBs of each other. See under CIRCUIT DESCRIPTION for Calibration Mode section. Crosstalk Between Bursts Between successive bursts the integrating capacitor C),,> is dis- charged to 0 V. This occurs during time t<2 of Figures 8a, 8b and 9. Note that both plates of the C,,-; capacitor are at the internal reset voltage level of 1.2 V, available on Cj,,+(). Any residual signal voltage on this capacitor will be added to the integrated signal of the succeeding burst causing an apparent increase in the amplitude of that burst. The crosstalk specifica- tion defines by how much the amplitude of a burst is influenced by a preceding burst. By this definition the first burst suffers no crosstalk, the second burst suffers from the first burst, etc. To measure crosstalk a special burst sequence is applied to the demodulator input which keeps the amplitude of the burst under test constant at half-scale (differential 1.25 V pp at 5 MHz) and alternates the amplitude of the preceding burst between 0 V and full scale. The average error due to crosstalk should be less than 5 LSB. Only two successive bursts are exer- cised in any one sequence. ADC Conversion Time Each conversion takes 14 CLKIN cycles. However, due to the asynchronous relationship between CLKIN and the burst detec- tor operation, it is possible to get a delay of up to 2.5 CLKIN cycles before the first conversion actually starts. This means that the first conversion may not be finished for up to 14 + 2.5 CLKIN cycles after the final burst has been detected. Subse- quent conversions will always take 14 CLKIN cycles. See under DESIGN INFORMATIONADC Corruption for additional applications information.AD7773/AD7775 ANALOG OUTPUTS Relative Accuracy For the DACs, relative accuracy or end-point nonlinearity is a measure of the maximum deviation, in LSBs, from a straight line passing through the end points of the DAC transfer func- tion. A graphical representation of the transfer curves for both twos complement and offset binary coding are shown in Figures lla and 11b, respectively. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of +1 LSB maximum ensures monotonicity. Bias Offset Error If the DACs are ideal, the output voltage of any DAC with mid- scale code loaded will be equal to Vgyas (i.e, REFOUT). The DAC bias offset error is the difference between the actual out- put voltage and Vgy,as, expressed in LSBs. Plus and Minus Full-Scale Error The DACs in the AD7773/AD7775 can be considered to provide bipolar output voltage ranges which are referred to Vgras instead of AGND. Plus full-scale error for any DAC is the dif- ference, expressed in LSBs, between the actual output voltage with plus full-scale code loaded into the DAC register and the ideal output voltage (Vpras + Vswing 1 LSB). Minus full- scale error is similarly defined but the DACs are now loaded with their minus full-scale codes and the ideal output voltage is now Vgras ~ Vswing: Note that plus and minus full-scale errors for the DAC outputs are referenced to REFOUT/2 and are measured after the bias offset errors have been adjusted out. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the digital inputs change state with the DAC selected. It is normally specified as the area of the glitch in nV secs and is measured when the digital input code is changed by 1 LSB at the major carry transition. Regardless of whether offset binary or 2s complement coding is used, the major carry transition occurs at the analog output voltage change of Varas t0 Vpras 1 LSB or vice versa. Digital Feedthrough Digital feedthrough is also a measure of the impulse injected into the analog output from the digital inputs but is measured when the DAC is not selected. It is essentially feedthrough across the die and package. It is important in the AD7773/ AD7775 since it is a measure of the glitch impulse transferred to the analog output when data is transferred over the data bus (either in or out). It is specified in nV secs and is measured with a full-scale code change on the data bus, from all 0s to all 1s and vice versa. Power Supply Rejection Ratio For the analog outputs, power supply rejection ratio (PSRR) is a measure of the change in the analog output of either DAC due to a change in the power supply voltage V-c. For the test both DACs are loaded with their half-scale codes and an ac sig- nal of 200 mV p-p amplitude and varying in frequency from 60 Hz to 30 kHz is summed with the +5 V power supply. The maximum output signal level on either DAC will be 22 mV. Thus, the response will be at least 20 dB below the excitation level. This specification holds over the allowable Vcc range of 4.75 V to 5.25 V. Short Circuit Current This is defined as the maximum current which will be supplied by the DAC output pin, Vo,,;7 A/B, if the pin is shorted to any potential between 0 V and Vcc. This condition can be allowed for up to 10 seconds provided that the power dissipation of the package is not exceeded. DESIGN INFORMATION Zero Crossing Detector The zero crossing detector (ZCD) has a certain amount of hys- teresis to prevent noise from getting through the input stage. The ZCD differential hysteresis, V;;, is typically 55 mV pp and is specified to lie between 40 and 120 mV p-p. Only signals which exceed this level can change the ZCDs output. A 55 mV hysteresis represents approximately 5% of a typical 1.1 V differ- ential input signal level to the demodulator channel. Figure 20 gives a graphical representation of the ZCD sensitivity and hysteresis. Vin, Differential \ 4 Input Voltage \ 4 ZCD OUTPUT WAVEFORM zcD OUTPUT Aa 4 _ 1 V2 OV +Vin2 | Vin = Vin (+)- Vin (-) Vin Differential input Voltage Figure 20. Zero Crossing Detector (ZCD) Sensitivity Layout Hints Ensure that the layout for the printed circuit board has the digi- tal and analog grounds separated as much as possible. Take care not to run any digital track alongside an analog signal track. Guard (screen) the analog inputs with AGND. Establish a single-point analog ground separate from the logic system ground and as close as possible to the AD7773 or AD7775. Both AGND pins on the AD7773/AD7775 and all other signal grounds should be connected to this single-point analog ground. In turn, this star ground should be connected to the digital ground at one point onlypreferably at the low impedance power supply itself. Low impedance analog and digital power supply common returns are important for correct operation of the devices, so make the foil width for these tracks as wide as possible. In order to ensure a low impedance +5 V power supply at the actual Vc pin, it will be necessary to employ bypass capacitors from the pin itself to DGND. A 4.7 F tantalum capacitor in parallel with a 0.1 wF ceramic capacitor is sufficient. -20- REV.AAD7773/AD7775 ADC Corruption Executing a read instruction to the AD7773/AD7775 while con- versions are in progress can result in the conversion-in-progress being corrupted. This is due to transient currents which flow when the output data drivers turn on. The possibility of ADC corruption is avoided if read instructions to the AD7773/AD7775 are avoided for some time after the final CTRL pulse goes Low. The duration of this wait period should be: Torx (NBursts.14 + 2.5 + 1) made up from the following factors; Nis the programmed number of bursts, 1 to 4, to be captured. Although each conversion takes only 14 CLKIN cycles, it can take up to 2.5 CLKIN cycles to synchronize the external clock with CTRL before any conversions start. A further CLKIN cycle should be allowed for location SRO of the status register to be updated. Synchronous Detector Timing Relationships The relative timing between an input burst signal and its respec- tive CTRL pulse determines which of the cycles within an indi- vidual burst are integrated. Two different timing examples which result in different cycles of the input waveform being integrated are shown in Figure 21. This is drawn for a two-burst pattern with N, the programmed number of cycles to be cap- tured, set to 4. In Example 1, the CTRL input goes high just after the rising edge of the ZCD output which itself occurs in the middle of the second cycle of burst 1. Approximately 3/2 cycles after this, the integrate (INT) signal goes high to start the integrator and remains high for four cycles of the input waveform. The CTRL input is maintained high for a further 2 cycles of the input waveform. With this timing relationship, cycles 4, 5, 6 and 7 of burst 1 are integrated. Since CTRL is kept low for the mini- mum time of 3/2 cycles of the captured input waveform, the same timing relationship between CTRL and the input signal is maintained for burst 2 and, again, cycles 4, 5, 6 and 7 are integrated. In Example 2, the CTRL input goes high just after the falling edge of the ZCD output at the start of the first cycle of burst 1. Approximately 2 cycles later the integrate signal, INT, goes 1 2 3 4 5 6 7 8 Vins /\ high and remains high for four cycles. CTRL is maintained high for a further 3/2 cycles before being brought low. With this tim- ing, cycles 3, 4, 5 and 6 are integrated. The same timing rela- tionship between CTRL and the input signal is maintained for burst 2 and, again, cycles 3, 4, 5 and 6 are integrated. Late positioning of the CTRL input can have a similar result. For instance, in Example 1, if CTRL goes high one-half cycle later than shown, then there will be almost two full cycles delay from CTRL to INT going high. This would result in cycles 5, 6, 7 and 8 being integrated. In situations where a degree of syn- chronization is possible between CTRL and V,,,, making the rising edge of CTRL coincident with V,;,, = 0 V and going posi- tive is the optimum situation. Changing Modes of Operation The AD7773 and AD7775 have two normal operating modes synchronous detector and gated detector modes and one cali- bration mode. Changing between any of these modes simply requires changing the appropriate contents of the control regis- ter as already described under the individual descriptions of these modes. However, there are a number of considerations which should be followed when changing between modes. The first is that no mode change be attempted before the burst cap- ture and conversion sequence is complete (i.e., not until location SRO of the Status Register returns low). This will avoid any inadvertent corruption of a conversion in progress. The second consideration involves the delay between writing to the control register and starting a new burst capture sequence. This time is defined under the Demodulator Timing Characteristics as the WR rising edge to CTRL rising edge and is specified as 200 ns minimum. It is required to ensure that the correct conditions have been set up internal to the device. A final consideration involves allowing sufficient time for the integrating capacitor, Cy, to discharge when changing from the calibration mode to one of the other operating modes. This is necessary since, in this mode, C,,,7 is not discharged by the internal discharge switch, SW3, either between successive CTRL pulses or even on completion of the burst capture sequence. A discharge time of 300 nsequivalent to t,2, the CTRL low time in the calibration modeis adequate after transferring out of the calibration mode. This discharge time and the previous set up time of 200 ns must be added together to arrive at a final overall delay. jt t + 4 4 x INPUT BURST WAVEFORM il zcD WAVEFORM EXAMPLE 1 CTRL a | (NT (INTEGRATE SIGNAL) CYCLES 4, 5, 6, 7 INTEGRATED EXAMPLE 2 L__f LL CYCLES 4, 5, 6,7 INTEGRATED CTRL JT INT (INTEGRATE SIGNAL) CYCLES 3, 4, 5, 6 INTEGRATED L__ Lo CYCLES 3, 4, 5, 6 INTEGRATED Figure 21. Two Examples of Movement of the Integration Window as a Result of Relative Timing Between CTRL and the Input Burst Signal REV. A -21-AD7773/AD7775 Choosing the C,,,; Capacitor In both the synchronous detector and gated detector modes the differential input signal is rectified and integrated across the integrating capacitor C,,;. The correct value of integrating capacitor must be used in order to optimize the channel perfor- mance for any particular integration period. If too high a value is chosen then the integrated signal voltage developed across Cnt will be lower than optimum, and hence, ADC resolution will be lost due to this effective compression of the signal. Simi- larly too low a value for C7 can lead to signal voltages being developed across C;,,;; which are beyond the dynamic range of the ADC. This effective signal expansion results in loss of ADC resolution for full-scale input signals. The ideal value of Cy is found from the expression: Cyyp Le Tey nes () where I is the average rectifier output current, T is the integrate time and Vay is the integrated voltage across Cy. Ideally the average rectifier current is a function only of Gm and Vj; but due to the curvature of the transfer function at low input voltages (see Figure 19) an offset term must be subtracted from the peak-peak input voltage to correct for this curvature. Thus the average rectifier output current is expressed as: IT = Gm* Vip (average) 60 ee (2) = Gm [(Vin 0-2 Vorrser/2] (Crest Factor) For sinusoidal burst signals the crest factor is equal to 2/7. In the synchronous detector mode the integrate time can be expressed as: T = tinTEGRATE <n ees (3) = N toyc = Nifin where N is the number programmed into locations CRO-CR3 of the control register. N can range from 4 to 15. Frequency fy, is the frequency of the input signal. The AD7773 and AD7775 are guaranteed to operate with N = 4 and f,, = 5 MHz maximum. In the gated detector mode the integrate time is simply the period of CTRL high or tq; in Figure 9. Very is the voltage change across C,,,; which results in a full-scale change in the ADC output. Vent is typically equal to REFOUT/2 or 1.075 V. Tables IV and V give recommended values of Cy+ versus input signal frequency and number of cycles. These com- puted values of capacitors are a combination of the actual value ~22- of capacitor used, Cy,7 (Cap), plus any stray capacitance on the Cyt (pin) to ground and C)y7(). The tolerance of Cy (Cap) must also be allowed for using the tables. The most significant difference between the tables is that the values in Table IV are computed on the basis that a differential input signal of 2.5 V p-p will always result in an ADC output of 1022 LSBs or less. This in fact is how the AD7773/AD7775 is specified. Table V values are computed on the basis that a 2.5 V p-p differential signal will nominally result in an ADC output of 1022 LSBs. Table IV. Recommended Values for C,,7 in pF vs. Signal Frequency and Cycles for Minimum FS of 2.5 V p-p Input Signal Frequency, MHz Cycles 1 2 3 4 5 4 1000 500 333 250 200 5 1250 625 417 313 250 6 1500 750 500 375 300 7 1750 875 583 438 350 8 2000 1000 667 500 400 9 2250 1125 750 563 450 10 2500 1250 833 625 500 11 2750 1375 917 688 550 12 3000 1500 1000 750 600 13 3250 1625 1083 813 650 14 3500 1750 1167 875 700 15 3750 1875 1250 938 750 Table V. Recommended Values for C,y7 in pF vs. Signal Frequency and Cycles for Nominal FS of 2.5 V p-p Input Signal Frequency, MHz Cycles 1 2 3 4 5 4 830 416 277 208 166 5 1040 520 347 260 208 6 1250 625 417 313 250 7 1455 728 485 364 291 8 1655 833 555 416 333 9 1870 935 623 468 374 10 2080 1040 693 520 416 11 2290 1145 763 573 458 12 2495 1248 832 624 499 13 2705 1353 902 676 541 14 2910 1455 970 728 582 15 3120 1560 1040 780 624 REV. AAD7773/AD7775 REV. A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). SOIC (R-28) AHAAAARAARAAAAAA 0.298 (7.60) > 0.291 (7.39) LEAD NO.1 IDENTIFIER 0.414 (10.52) Lf 0.398 (10.10) HHXBHHHPPRAPEEE Fr 0.03 (0.76) 0.708 (18.02) * 02 a 51) 0.696 (17.67) = 0.096 (2.44) i + 0.089 (2.26) 0.05 (1.27) BSC 0.019 (0.49) 0.01 (0.254) 0. wd (0.32) a 042 (1. Ss 0.014 (0.35) 0.006 (0.15) 0.009 (0.23) 0.018 (0.457) 1. LEAD NO. 1 IDENTIFIED BY A DOT. 2. SOIC LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS. TSOP (U-32) 20.20 (0.795) >| 1.20 (0.047) MAX 19.80 (0.780) 48.50 (0728) |4e- SEATING PLANE 18.30 (0.720) 0,15 (0.006) 0.00 (0.000) = jm, aN = = LEAD NO.1 IDENTIFIER ca = = S E> 0.50 (0.0197) _: b= 8.20 (0.323) 50 (0. +t E= soma Bsc Ta = 7.00 (0.307) eq i = = 0.25 (0.010) = 0.15 (0.005) F __ 1 1.05 (0.0410) 4 FS 1.05 (0.0410) ( 0.20 (0.008) PARTING LINE 0.95 (0.037) 7 a =e pe oun FT et os: ee 0.60 (0.024) l.. SEE DETAIL A\ 2.40 (0.016) | DETAIL "A" -23-