can be achieved by using the DIM pin.

panel temperature.

leadframe plating.

Applications include:

Features and Benefits

OVP–load-dump protection

operate above the AM band

with true output disconnect

be adjusted as high as 38 V

external component failure

OVLO) against VIN variation

Not to scale

SW, OVP, CAP, OUT Pins –0.3 to 40 V

Maximum Junction Temperature TJ(max) 150 ºC

*Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table

is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Characteristic Symbol Test Conditions* Value Units

A8511KLPTR-T –40°C to 125°C 4000 pieces per 13-in. reel

1 BIAS Output of internal 6 V bias supply. Decouple with a 0.1 μF ceramic capacitor to DGND.

2 DGND Digital signal ground. Connect AGND, DGND, LGND, PGND, and PAD using star ground connection.

3 DIM Sets ILED by adjusting the ISET to ILEDx current gain, AISET . When DIM = VIL , AISET = 960 and when DIM=VIH , AISET = 240.

4, 5, 6 SW DMOS switch drain node. Tie these three pins together on the PCB.

is 19.5 V. External resistor can set OVP up to 38 V.

for additional information.

logic high signal for the SEL and DIM pins.

13,14,16,17 LEDX LED current sinks.

15 LGND Power ground for LED current sinks. Connect AGND, DGND, LGND, PGND, and PAD using star ground connection.

18 OUT Output connection for output disconnect switch. Connect LED common connection to this pin.

19 FSET Connect RFSET between FSET and AGND to set boost switching frequency.

21 VIN Input supply for the device. Decouple with a 0.1 μF ceramic capacitor.

22 NC Not connected internally. It is recommended to connect this pin to external ground.

copper layer for enhanced heat dissipation.

Input Voltage Range VIN 8 – 21 V

Undervoltage Lockout Threshold VUVLO(th) VIN falling 5.7 6.5 6.8 V

UVLO Hysteresis Window VUVLO(hys) 0.21 0.55 0.81 V

Overvoltage Lockout Threshold VOVLO(th) VIN rising 29 32 34 V

CAP = VIN = SW = OVP = 16 V,

EN = VIL, not in shutdown, IS = IVIN –24mA

Logic Input levels (DIM, EN, SELx Pins)

Input Voltage Level-Low VIL – – 0.4 V

Input Voltage Level-High VIH 1.5 – – V

Input Leakage Current (EN, DIM pins) Ilkg1 VDIM, VEN = 5 V 30 50 70 μA

Overvoltage Protection

Output Overvoltage Threshold VOVP(th) OVP pin connected to OUT pin 18 19.5 21 V

LED Current Sinks

LEDx Regulation Voltage VLED VLED1 = VLED2 = VLED3 = VLED4 – 850 1100 mV

VTO Pin Voltage VTO IVTO = 1 mA 2.00 2.46 2.65 V

VTO Pin Current Maximum ITO(max) IVTO increased until VTO drops by 1% 1.5 2.4 5 mA

VTI Pin Voltage

ISET Pin Allowable Current Range IISET 20 – 166 μA

LED Switch Leakage Current IS(lkg) VLEDx = 17.5 V, EN = VIL = 0 V 4.8 8.75 12.8 μA

LEDx Short Detect Voltage Threshold VLEDSC On any LEDx pin, forces latched shutdown 17.5 19 21 V

Minimum Switch Off-Time toff(min) – 60 110 ns

Minimum Switch On-Time ton(min) – 60 110 ns

Soft Start

Soft Start Boost Current Limit ISWSS(lim) Initial soft start current for boost switch 0.4 0.6 0.75 A

Soft Start LEDx Current ILEDSS

PWM Timing on EN pin

Maximum PWM Dimming Off-Time tPWML

PWM Low to LED Off Delay tdPWM(off)

Functional Description

regulated current through the load LEDs for uniform display

brightness. All LEDx sinks are rated for 21 V to allow PWM

dimming control.

pin, fSW

f

where fSW is in MHz, and RFSET is in k.

by the combined settings of the SEL1 and SEL2 pins, according

LED strings that are connected to the A8511, but are not enabled

through the SELx pins, may cause a shutdown if the voltage on

between this pin and AGND to set the reference current level,

I

where IISET is in mA and RISET is in k.

This current is multiplied internally with a gain of 960, and mir-

rored on all enabled LED pins. This sets the maximum current

through the LEDs, referred as the 100% current.

rent level by three alternative dimming methods:

the LED current causes an error. To compensate for the error,

a small turn-on delay should be added to the PWM signal as

shown on page 10 of the Performance Characteristics section.

When EN is pulled low, the boost converter and LED sinks are

turned off. The compensation (COMP) pin is floated, and criti-

cal internal circuits are kept active. If EN is pulled low for more

than tPWML , the device enters shutdown mode and clears all

internal fault registers. As an example, for a 2 MHz clock, the

maximum PWM low period while avoiding shutdown is 65 ms.

• Analog dimming using the DIM pin. When the DIM pin is

for setting the OVP level:

R

of the external resistor, in .

A8511 has secondary overvoltage protection to protect internal

switches in the event of an open diode condition. Open Schottky

diode detection is implemented by detecting overvoltage on the

SW pin. If voltage on the SW pin exceeds the device safe operat-

ing voltage rating, the A8511 disables and remains latched. The

istics section, page 14.

In some instances, when the LEDs are connected by long wires

and also some output capacitance (such as ESD capacitors) is

present, a clamping diode on the output must be used. This diode

will prevent the output from momentarily going negative during

a short circuit condition. The diode must be chosen such that its

reverse breakdown voltage is higher than normal operating volt-

age and its reverse current leakage is small. Please refer to the

application note Output Diode Clamping for the A8511 for more

Application Information

This section provides a method for selecting component values

when designing an application using the A8511.

Assumptions For the purposes of this example, the following are

given as the application requirements:

• Quantity of LED channels, #CHANNELS

• Quantity of series LEDs per channel, #SERIESLEDS : 8

quencies. A small delay between the PWM signal and the LED

current may have a noticeable effect at high PWM frequencies

combined with low PWM duty cycles. For example, at 100 Hz

and 10% PWM duty cycle, the PWM on-period is 1 ms. In that

period, the delay causes only a 0.6% error. If the PWM frequency

is 1 kHz, this error is 6%. However, the error caused by the turn-

on delay can be decreased by increasing the applied PWM duty

cycle as shown on page 10 in the Performance Characteristics

Procedure The procedure consists of selecting the appropriate

3. Select resistor RISET (connected between pin ISET and

AGND). Given ILED = 80 mA and AISET = 960, then:

R

Substituting:

R

switch voltage drop, then:

+ VLED + (RODS(on) × ILED × #CHANNELS )

converter duty cycle, D(max), at VBAT(min) and 90% ef-

ficiency, η.

Given, during switch on-time:

8 = L × 0.289 × 2 ×106 / 0.75, and

L = 10.4 H .

Select a common value: L(used) = 10 H.

It is recommended to select an inductor that can handle a DC

current level that is greater than 963 mA, at the peak current

level (saturation) of 963 mA + 289 mA / 2 = 1.11 A. This is

to ensure that the inductor does not saturate at any steady

state or transient condition, within specified temperature and

assuming 20% minimum dimming PWM duty cycle,

output disconnect switch at VOUT = 28 V is 165 A and

Select the output capacitor as:

COUT = Ilk × (1 – DPWM(min)) / (fPWM × VCOUTripple ) . (17)

COUT = 165 A× (1 – 0.2) / (100 × 0.25) = 5.3 F . (18)

The RMS current through COUT is given by:

r = ΔIL / IBAT(max) , and (20)

Figure 8. Typical circuit with ESD capacitors across LEDs (CPx ≤10 nF),

with thermal derating

Package LP, 28-Pin TSSOP with Exposed Thermal Pad

Copyright ©2010, Allegro MicroSystems, Inc.

The products described here are manufactured under one or more U.S. patents or U.S. patents pending.

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mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

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failure of that life support device or system, or to affect the safety or effectiveness of that device or system.