DS1642-120 - Maxim Integrated Products, Inc.

patents and other intellectual property rights, please refer to

Dallas Semiconductor data books.

DS1642

Nonvolatile Timekeeping RAM

DS1642

041697 1/10

FEATURES

•Form, fit, and function compatible with the MK48T02

T imekeeping RAM

•Integrated NV SRAM, real time clock, crystal, power

fail control circuit and lithium energy source

•Standard JEDEC bytewide 2K x 8 static RAM pinout

•Clock registers are accessed identical to the static

RAM. These registers are resident in the eight top

RAM locations.

•Totally nonvolatile with over 10 years of operation in

the absence of power

•Access times of 120 ns and 150 ns

•Quartz accuracy ±1 minute a month @ 25°C, factory

calibrated

•BCD coded year, month, date, day, hours, minutes,

and seconds with leap year compensation valid up to

2100

•Power fail write protection allows for ±10% VCC power

supply tolerance

PIN ASSIGNMENT

DQ0

DQ1

DQ2

GND

VCC

A10

DQ7

DQ6

DQ5

DQ4

DQ3

PIN DESCRIPTION

A0–A10 – Address Input

CE – Chip Enable

OE – Output Enable

WE – Write Enable

VCC – +5 Volts

GND – Ground

DQ0–DQ7 – Data Input/Output

DESCRIPTION

The DS1642 is an 2K x 8 nonvolatile static RAM with a

full function real time clock which are both accessible in

a bytewide format. The nonvolatile time keeping RAM is

pin and function equivalent to any JEDEC standard

2K x 8 SRAM. The device can also be easily substituted

in ROM, EPROM and EEPROM sockets providing read/

write nonvolatility and the addition of the real time clock

function. The real time clock information resides in the

eight uppermost RAM locations. The RTC registers

contain year , month, date, day , hours, minutes, and se-

conds data in 24 hour BCD format. Corrections for the

day of the month and leap year are made automatically .

The RTC clock registers are double buffered to avoid

access of incorrect data that can occur during clock up-

date cycles. The double buffered system also prevents

time loss as the timekeeping countdown continues un-

abated by access to time register data. The DS1642

also contains its own power fail circuitry which deselects

the device when the VCC supply is in an out of tolerance

condition. This feature prevents loss of data from un-

predictable system operation brought on by low VCC as

errant access and update cycles are avoided.

DS1642

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CLOCK OPERATIONS–READING THE CLOCK

While the double buffered register structure reduces the

chance of reading incorrect data, internal updates to the

DS1642 clock registers should be halted before clock

data is read to prevent reading of data in transition.

However, halting the internal clock register updating

process does not affect clock accuracy. Updating is

halted when a 1 is written into the read bit, the seventh

most significant bit in the control register. As long as a 1

remains in that position, updating is halted. After a halt

is issued, the registers reflect the count, that is day,

date, and time that was current at the moment the halt

command was issued. However , the internal clock reg-

isters of the double buffered system continue to update

so that the clock accuracy is not affected by the access

of data. All of the DS1642 registers are updated simul-

taneously after the clock status is reset. Updating is

within a second after the read bit is written to zero.

DS1642 BLOCK DIAGRAM Figure 1

OSCILLA TOR AND

CLOCK COUNTDOWN

CHAIN

POWER MONITOR,

SWITCHING, AND

WRITE PROTECTION

VCC

POWER GOOD

CLOCK

REGISTERS

2K X 8 NV SRAM

A0–A10

DQ0–DQ7

32.768

DS1642 TRUTH TABLE Table 1

VCC CE OE WE MODE DQ POWER

5 VOLTS 10%

VIH X X DESELECT HIGH Z STANDBY

5 VOLTS ±10%

VIL X VIL WRITE DATA IN ACTIVE

VOLTS

10%

VIL VIL VIH READ DATA OUT ACTIVE

VIL VIH VIH READ HIGH Z ACTIVE

<4.5 VOLTS

>VBAT X X X DESELECT HIGH Z CMOS STANDBY

<VBAT X X X DESELECT HIGH Z DATA RETENTION

MODE

DS1642

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SETTING THE CLOCK

The eighth bit of the control register is the write bit. Set-

ting the write bit to a 1, like the read bit, halts updates to

the DS1642 registers. The user can then load them with

the correct day , date and time data in 24 hour BCD for-

mat. Resetting the write bit to a 0 then transfers those

values to the actual clock counters and allows normal

operation to resume.

STOPPING AND STARTING THE CLOCK

OSCILLATOR

The clock oscillator may be stopped at any time. To in-

crease the shelf life, the oscillator can be turned off to

minimize current drain from the battery. The OSC bit is

the MSB for the seconds registers. Setting it to a 1 stops

the oscillator.

FREQUENCY TEST BIT

Bit 6 of the day byte is the frequency test bit. When the

frequency test bit is set to logic “1” and the oscillator is

running, the LSB of the seconds register will toggle at

512 Hz. When the seconds register is being read, the

DQ0 line will toggle at the 512 Hz frequency as long as

conditions for access remain valid (i.e., CE low , and OE

low) and address for seconds register remain valid and

stable.

CLOCK ACCURACY

The DS1642 is guaranteed to keep time accuracy to

within ±1 minute per month at 25°C. The clock is cali-

brated at the factory by Dallas Semiconductor using

special calibration nonvolatile tuning elements. The

DS1642 does not require additional calibration and tem-

perature deviations will have a negligible ef fect in most

applications. For this reason, methods of field clock cal-

ibration are not available and not necessary. Attempts

to calibrate the clock that may be used with similar de-

vice types (MK48T02 family) will not have any effect

even though the DS1642 appears to accept calibration

data.

DS1642 REGISTER MAP – BANK1 Table 2

ADDRESS

DATA

FUNCTION

ADDRESS

B7B6B5B4B3B2B1B0

FUNCTION

7FF – – – – – – – – YEAR 00–99

7FE X X X – – – – – MONTH 01–12

7FD X X – – – – – – DATE 01–31

7FC X FT X X X – – – DAY 01–07

7FB X X – – – – – – HOUR 00–23

7FA X – – – – – – – MINUTES 00–59

7F9 OSC – – – – – – – SECONDS 00–59

7F8 W R X X X X X X CONTROL A

OSC = STOP BIT R = READ BIT FT = FREQUENCY TEST

W = WRITE BIT X = UNUSED

NOTE:

All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.

DS1642

041697 4/10

RETRIEVING DATA FROM RAM OR CLOCK

The DS1642 is in the read mode whenever WE (write

enable) is high, and CE (chip enable) is low . The device

architecture allows ripple–through access to any of the

address locations in the NV SRAM. Valid data will be

available at the DQ pins within tAA after the last address

input is stable, providing that the CE and OE access

times and states are satisfied. If CE or OE access times

are not met, valid data will be available at the latter of

chip enable access (tCEA) or at output enable access

time (tOEA). The state of the data input/output pins (DQ)

is controlled by CE and OE. If the outputs are activated

before tAA, the data lines are driven to an intermediate

state until tAA. If the address inputs are changed while

CE and OE remain valid, output data will remain valid for

output data hold time (tOH) but will then go indeterminate

until the next address access.

WRITING DATA TO RAM OR CLOCK

The DS1642 is in the write mode whenever WE and CE

are in their active state. The start of a write is referenced

to the latter occurring transition of WE or CE. The ad-

dresses must be held valid throughout the cycle. CE or

WE must return inactive for a minimum of tWR prior to

the initiation of another read or write cycle. Data in must

be valid tDS prior to the end of write and remain valid for

tDH afterward. In a typical application, the OE signal will

be high during a write cycle. However, OE can be active

provided that care is taken with the data bus to avoid bus

contention. If OE is low prior to WE transitioning low the

data bus can become active with read data defined by

the address inputs. A low transition on WE will then dis-

able the outputs tWEZ after WE goes active.

DATA RETENTION MODE

When VCCI is within nominal limits (VCC > 4.5 volts) the

DS1642 can be accessed as described above by read

or write cycles. However , when VCC is below the power

fail point VPF (point at which write protection occurs) the

internal clock registers and RAM is blocked from ac-

cess. This is accomplished internally by inhibiting ac-

cess via the CE signal. When VCC falls below the level

of the internal battery supply, power input is switched

from the VCC pin to the internal battery and clock activity,

RAM, and clock data are maintained from the battery

until VCC is returned to nominal level.

INTERNAL BATTERY LONGEVITY

The DS1642 has a self contained lithium power source

that is designed to provide energy for clock activity , and

clock and RAM data retention when the VCCI supply is

not present. The capability of this internal power supply

is sufficient to power the DS1642 continuously for the

life of the equipment in which it is installed. For specifi-

cation purposes, the life expectancy is 10 years at 25°C

with the internal clock oscillator running in the absence

of VCC power. The DS1642 is shipped from Dallas

Semiconductor with the clock oscillator turned off, so

the expected life should be considered to start from the

time the clock oscillator is first turned on. Actual life ex-

pectancy of the DS1642 will be much longer than 10

years since no internal lithium battery energy is con-

sumed when VCC is present. In fact, in most applica-

tions, the life expectancy of the DS1642 will be approxi-

mately equal to the shelf life (expected useful life of the

lithium battery with no load attached) of the lithium bat-

tery which may prove to be as long as 20 years.

DS1642

041697 5/10

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground –0.3V to +7.0V

Operating Temperature 0°C to 70°C

Storage Temperature –20°C to +70°C

Soldering Temperature 260°C for 10 seconds (See Note 7)

* This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Supply Voltage VCC 4.5 5.0 5.5 V 1

Logic 1 Voltage All Inputs VIH 2.2 VCC+0.3 V

Logic 0 Voltage All Inputs VIL –0.3 0.8 V

DC ELECTRICAL CHARACTERISTICS (0°C ≤ tA ≤ 70°C; VCC (MAX) ≤ VCC ≤ VCC (MIN))

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Average VCC Power Supply

Current ICC1 30 50 mA 2, 3

TTL Standby Current (CE = VIH) ICC2 3 6 mA 2, 3

CMOS Standby Current

(CE=VCC–0.2V) ICC3 24.0 mA 2, 3

Input Leakage Current (any input) IIL –1 +1 µA

Output Leakage Current IOL –1 +1 µA

Output Logic 1 Voltage

(IOUT = –1.0 mA) VOH 2.4 V

Output Logic 0 Voltage

(IOUT = +2.1 mA) VOL 0.4 V

Write Protection Voltage VTP 4.0 4.25 4.5 V

DS1642

041697 6/10

AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 5.0V + 10%)

PARAMETER

SYMBOL

DS1642–120 DS1642–150

UNITS

NOTES

PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

Read Cycle Time tRC 120 150 ns

Address Access Time tAA 120 150 ns

CE Access Time tCEA 120 150 ns

CE Data Off Time tCEZ 40 50 ns

Output Enable Access T ime tOEA 100 120 ns

Output Enable Data Off Time tOEZ 40 50 ns

Output Enable to DQ Low–Z tOEL 5 5 ns

CE to DQ Low–Z tCEL 5 5 ns

Output Hold from Address tOH 5 5 ns

Write Cycle Time tWC 120 150 ns

Address Setup T ime tAS 0 0 ns

CE Pulse Width tCEW 100 120 ns

Address Hold from End of Write tAH1

tAH2 5

30 5

30 ns

ns 5

Write Pulse Width tWEW 120 150 ns

WE Data Off Time tWEZ 40 50 ns

WE or CE Inactive T ime tWR 10 10 ns

Data Setup T ime tDS 85 110 ns

Data Hold T ime High tDH1

tDH2 0

25 0

25 ns

ns 5

AC TEST CONDITIONS

Input Levels: 0V to 3V

T ransition Times: 5 ns

CAPACITANCE (tA = 25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Capacitance on all pins

(except DQ) CI7 pF

Capacitance on DQ pins CDQ 10 pF

DS1642

041697 7/10

AC ELECTRICAL CHARACTERISTICS (POWER–UP/DOWN TIMING) (0°C to 70°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

CE or WE at VIH before Power

Down tPD 0µs

VPF (Max) to VPF (Min) VCC Fall

Time tF300 µs

VPF (Min) to VSO VCC Fall Time tFB 10 µs

VSO to VPF (Min) VCC Rise Time tRB 1µs

VPF (Min) to VPF (Max) VCC Rise

Time tR0µs

Power Up tREC 15 25 35 ms

Expected Data Retention T ime

(Oscillator On) tDR 10 years 4

DS1642 READ CYCLE TIMING

tRC tRC tRC

READ READ WRITE

tAH

tAS

tWEW

VALID INVALID OUTVALID OUT

tOEZ

tAA

tOH

tCEA

tCEL

tOEA

tOEL

A0–A10

DQ0–DQ7

tWR

DS1642

041697 8/10

DS1642 WRITE CYCLE TIMING

tWC tWC tWC

WRITE WRITE READ

A0–A10

DQ0– VALID OUTVALID INVALID IN

VALID

OUT

tAA

tAH1

tOEA

tWEZ

tAS

tCEW

tCEZ tDS tDH2

tDH1

tDS

DQ7

tWR

tWEW

tWR

tAH2

POWER DOWN/POWER UP TIMING

VCC

tPD

tFB

DATA RETENTION

tDR

IBATT

VPF (MAX)

VPF (MIN)

tREC

tRB

VPF

VSO

DS1642

041697 9/10

NOTES:

1. All voltages are referenced to ground.

2. Typical values are at 25°C and nominal supplies.

3. Outputs are open.

4. Data retention time is at 25°C and is calculated from the date code on the device packag. The date code XXYY

is the year followed by the week of the year in which the device was manufactured. For example, 9225, would

mean the 25th week of 1992.

5. tAH1, tDH1 are measured from WE going high.

6. tAH2, tDH2 are measured from CE going high.

7. Real–T ime Clock Modules can be successfully processed through conventional wave–soldering techniques as

long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post solder

cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used.

OUTPUT LOAD

+5 VOLTS

100 pF

D.U.T.

1.8KΩ

1KΩ

DS1642

041697 10/10

DS1642 24–PIN PACKAGE

GKD

DIM MIN MAX

A IN.

B IN.

C IN.

D IN.

E IN.

F IN.

G IN.

H IN.

J IN.

K IN.

1.270

37.34 1.290

37.85

0.675

17.15 0.700

17.78

0.315

8.00 0.335

8.51

0.075

1.91 0.105

2.67

0.015

0.38 0.030

0.76

0.140

3.56 0.180

4.57

0.090

2.29 0.110

2.79

0.590

14.99 0.630

16.00

0.010

0.25 0.018

0.45

0.015

0.43 0.025

0.58

24–PINPKG