1
File Number 4521.4
HI5660
8-Bit, 165/125/60MSPS, High Speed D/A
Converter
The HI5660 is an 8-bit, 125MSPS, high speed, low power,
D/A converter which is implemented in an advanced CMOS
process. Operating from a single +3V to +5V supply, the
converter provides 20mA of full scale output current and
includes edge-triggered CMOS input data latches. Low glitch
energy and excellent frequency domain performance are
achieved using a segmented current source architecture. For
an equivalent performance dual version, see the HI5628.
This device complements the CommLink™ HI5X60 family of
high speed converters offered by Intersil, which includes 8,
10, 12, and 14-bit devices.
†Contact factory for availability.
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .125MSPS
• Low Power . . . . . . . . . . . . . . . 165mW at 5V, 27mW at 3V
• Power Down Mode . . . . . . . . . . 23mW at 5V, 10mW at 3V
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . ±0.25 LSB
• Adjustable Full Scale Output Current. . . . . 2mA to 20mA
• SFDR to Nyquist at 10MHz Output . . . . . . . . . . . . .60dBc
• Internal 1.2V Bandgap Voltage Reference
• Single Power Supply from +5V to +3V
• CMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
Applications
• Medical Instrumentation
• Wireless Communications
• Direct Digital Frequency Synthesis
• Signal Reconstruction
• Test Instrumentation
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
Pinout HI5660 (SOIC, TSSOP)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP.
RANGE
(oC) PACKAGE PKG.
NO. CLOCK
SPEED
HI5660/16IB†-40 to 85 28 Ld SOIC M28.3 165MHz
HI5660/16IA†-40 to 85 28 Ld TSSOP M28.173 165MHz
HI5660IB -40 to 85 28 Ld SOIC M28.3 125MHz
HI5660IA†-40 to 85 28 Ld TSSOP M28.173 125MHz
HI5660/6IB†-40 to 85 28 Ld SOIC M28.3 60MHz
HI5660/6IA -40 to 85 28 Ld TSSOP M28.173 60MHz
HI5660EVAL1†25 Evaluation Platform 125MHz
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
DCOM
DCOM
DCOM
DCOM
DCOM
DCOM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
DCOM
NC
AVDD
NC
IOUTB
COMP1
FSADJ
REFIO
REFLO
SLEEP
DVDD
IOUTA
ACOM
Data Sheet November 1999
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Copyright © Intersil Corporation 1999
CommLink™ is a trademark of Intersil Corporation.
2
Typical Applications Circuit
Functional Block Diagram
D7 (MSB) (1)
D6 (2)
D5 (3)
D4 (4)
D3 (5)
D2 (6)
D1 (7)
D0 (LSB) (8)
D7
D6
D5
D4
D3
D2
D1
D0
DCOM (26)
CLK (28)
(19) COMP1
(24) AVDD
D/A OUT
(22) IOUTA
(21) IOUTB
50Ω
(18) FSADJ
(16) REFLO
HI5660
DVDD (27) +5V OR +3V (VDD)
0.1µF
50Ω
10µF
(20) ACOM
50Ω
(15) SLEEP
(17) REFIO
0.1µF
1.91kΩ
FERRITE
10µH
0.1µF
(23) NC
0.1µF
D/A OUT
+
BEAD
RSET
(9-14, 25)
DCOM DCOM
ACOM
10µF+
FERRITE
10µH
BEAD
UPPER
VOLTAGE
REFERENCE
(LSB) D0
D1
D2
D3
D4
(MSB) D7
CLK
D5
D6
5-BIT
DECODER
REFIO
LATCH
AVDD ACOM DVDD DCOM
LATCH
CASCODE
CURRENT
SOURCE
SWITCH
MATRIX
BIAS
GENERATION
INT/EXT
FSADJ
REFERENCE
INT/EXT
SELECT
REFLO
31
34 34
31 MSB
SEGMENTS
3 LSBs
+
COMP1
SLEEP
IOUTA IOUTB
HI5660
3
Absolute Maximum Ratings Thermal Information
Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AVDD to ACOM. . . . . . . . . . . . . . . . . . +5.5V
Grounds, ACOM TO DCOM. . -0.3VTo +0.3V Digital Input Voltages
(D9-D0, CLK, SLEEP) . . . . . . . . . . . . . . . . . . . . . . . . . DVDD + 0.3V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . . ±50µA
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1) θJA(oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values
PARAMETER TEST CONDITIONS
TA = -40oC TO 85oC
UNITSMIN TYP MAX
SYSTEM PERFORMANCE
Resolution 8 - - Bits
Integral Linearity Error, INL “Best Fit” Straight Line (Note 7) -0.5 ±0.25 +0.5 LSB
Differential Linearity Error, DNL (Note 7) -0.5 ±0.25 +0.5 LSB
Offset Error, IOS (Note 7) -0.025 +0.025 % FSR
Offset Drift Coefficient (Note 7) - 0.1 - ppm
FSR/oC
Full Scale Gain Error, FSE With External Reference (Notes 2, 7) -10 ±2 +10 % FSR
With Internal Reference (Notes 2, 7) -10 ±1 +10 % FSR
Full Scale Gain Drift With External Reference (Note 7) - ±50 - ppm
FSR/oC
With Internal Reference (Note 7) - ±100 - ppm
FSR/oC
Full Scale Output Current, IFS 2 - 20 mA
Output Voltage Compliance Range (Note 3) -0.3 - 1.25 V
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, fCLK (Notes 3, 9) 125 - - MHz
Output Settling Time, (tSETT) 0.8% (±1 LSB, equivalent to 7 Bits) (Note 7) - 5 - ns
0.4% (±1/2 LSB, equivalent to 8 Bits) (Note 7) - 15 - ns
Singlet Glitch Area (Peak Glitch) RL = 25Ω(Note 7) - 5 - pV•s
Output Rise Time Full Scale Step - 1.5 - ns
Output Fall Time Full Scale Step - 1.5 - ns
Output Capacitance 10 pF
Output Noise IOUTFS = 20mA - 50 - pA/√Hz
IOUTFS = 2mA - 30 - pA/√Hz
AC CHARACTERISTICS HI5660/16IB, HI5660/16IA - 165MHz
Spurious Free Dynamic Range,
SFDR Within a Window fCLK = 165MSPS , fOUT = 66.7MHz, 50MHz Span (Notes 4, 7, 9) - 60 - dBc
fCLK = 165MSPS , fOUT = 20.2MHz, 30MHz Span (Notes 4, 7, 9) - 69 - dBc
fCLK = 125MSPS , fOUT = 32.9MHz, 10MHz Span (Notes 4, 7) - 70 - dBc
fCLK = 100MSPS , fOUT = 5.04MHz, 4MHz Span (Notes 4, 7) - 73 - dBc
HI5660
4
Total Harmonic Distortion (THD) to
Nyquist fCLK = 165MSPS, fOUT = 8.2MHz (Notes 4, 7) - 64 - dBc
fCLK = 100MSPS, fOUT = 2.00MHz (Notes 4, 7) - 67 - dBc
Spurious Free Dynamic Range,
SFDR to Nyquist fCLK = 165MSPS , fOUT = 66.7MHz, 82.5MHz Span (Notes 4, 7, 9) - 46 - dBc
fCLK = 165MSPS , fOUT = 20.2MHz, 82.5MHz Span (Notes 4, 7, 9) - 54 - dBc
fCLK = 125MSPS , fOUT = 32.9MHz, 62.5MHz Span (Notes 4, 7) - 51 - dBc
fCLK = 125MSPS , fOUT = 10.1MHz, 62.5MHz Span (Notes 4, 7) - 61 - dBc
fCLK = 100MSPS , fOUT = 40.4MHz, 50MHz Span (Notes 4, 7) - 48 - dBc
fCLK = 100MSPS , fOUT = 20.2MHz, 50MHz Span (Notes 4, 7) - 56 - dBc
fCLK = 100MSPS , fOUT = 5.04MHz, 50MHz Span (Notes 4, 7) - 68 - dBc
AC CHARACTERISTICS HI5660IB, HI5660IA - 125MHz
Spurious Free Dynamic Range,
SFDR Within a Window fCLK = 125MSPS , fOUT = 32.9MHz, 10MHz Span (Notes 4, 7) - 70 - dBc
fCLK = 100MSPS , fOUT = 5.04MHz, 4MHz Span (Notes 4, 7) - 73 - dBc
Total Harmonic Distortion (THD) to
Nyquist fCLK = 100MSPS, fOUT = 2.00MHz (Notes 4, 7) - 67 - dBc
Spurious Free Dynamic Range,
SFDR to Nyquist fCLK = 125MSPS , fOUT = 32.9MHz, 62.5MHz Span (Notes 4, 7) - 51 - dBc
fCLK = 125MSPS , fOUT = 10.1MHz, 62.5MHz Span (Notes 4, 7) - 61 - dBc
fCLK = 100MSPS , fOUT = 40.4MHz, 50MHz Span (Notes 4, 7) - 48 - dBc
fCLK = 100MSPS , fOUT = 20.2MHz, 50MHz Span (Notes 4, 7) - 56 - dBc
fCLK = 100MSPS , fOUT = 5.04MHz, 50MHz Span (Notes 4, 7) - 68 - dBc
fCLK = 100MSPS , fOUT = 2.51MHz, 50MHz Span (Notes 4, 7) - 68 - dBc
AC CHARACTERISTICS HI5660/6IB, HI5660/6IA - 60MHz
Spurious Free Dynamic Range,
SFDR Within a Window fCLK = 60MSPS , fOUT = 10.1MHz, 10MHz Span (Notes 4, 7) - 62 - dBc
fCLK = 50MSPS , fOUT = 5.02MHz, 2MHz Span (Notes 4, 7) - 73 - dBc
fCLK = 50MSPS , fOUT = 1.00MHz, 2MHz Span (Notes 4, 7) - 74 - dBc
Total Harmonic Distortion (THD) to
Nyquist fCLK = 50MSPS, fOUT = 2.00MHz (Notes 4, 7) - 67 - dBc
fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 7) - 68 - dBc
Spurious Free Dynamic Range,
SFDR to Nyquist fCLK = 60MSPS , fOUT = 20.2MHz, 30MHz Span (Notes 4, 7) - 54 - dBc
fCLK = 60MSPS , fOUT = 10.1MHz, 30MHz Span (Notes 4, 7) - 60 - dBc
fCLK = 50MSPS , fOUT = 20.2MHz, 25MHz Span (Notes 4, 7) - 53 - dBc
fCLK = 50MSPS , fOUT = 5.02MHz, 25MHz Span (Notes 4, 7) - 67 - dBc
fCLK = 50MSPS , fOUT = 2.51MHz, 25MHz Span (Notes 4, 7) - 68 - dBc
fCLK = 50MSPS , fOUT = 1.00MHz, 25MHz Span (Notes 4, 7) - 68 - dBc
fCLK = 25MSPS , fOUT = 5.02MHz, 25MHz Span (Notes 4, 7) - 71 - dBc
VOLTAGE REFERENCE
Internal Reference Voltage, VFSADJ Voltage at Pin 18 with Internal Reference 1.04 1.16 1.28 V
Internal Reference Voltage Drift - ±60 - ppm/oC
Internal Reference Output Current
Sink/Source Capability - 0.1 - µA
Reference Input Impedance -1-MΩ
Reference Input Multiplying Bandwidth (Note 7) - 1.4 - MHz
DIGITAL INPUTS D7-D0, CLK
Input Logic High Voltage with
5V Supply, VIH (Note 3) 3.5 5 - V
Input Logic High Voltage with
3V Supply, VIH (Note 3) 2.1 3 - V
Electrical Specifications AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued)
PARAMETER TEST CONDITIONS
TA = -40oC TO 85oC
UNITSMIN TYP MAX
HI5660
5
Input Logic Low Voltage with
5V Supply, VIL (Note 3) - 0 1.3 V
Input Logic Low Voltage with
3V Supply, VIL (Note 3) - 0 0.9 V
Input Logic Current, IIH -10 - +10 µA
Input Logic Current, IIL -10 - +10 µA
Digital Input Capacitance, CIN -5- pF
TIMING CHARACTERISTICS
Data Setup Time, tSU See Figure 3 (Note 3) 3 - - ns
Data Hold Time, tHLD See Figure 3 (Note 3) 3 - - ns
Propagation Delay Time, tPD See Figure 3 - 1 - ns
CLK Pulse Width, tPW1, tPW2 See Figure 3 (Note 3) 4 - - ns
POWER SUPPLY CHARACTERISTICS
AVDD Power Supply (Note 8, 9) 2.7 5.0 5.5 V
DVDD Power Supply (Note 8, 9) 2.7 5.0 5.5 V
Analog Supply Current (IAVDD) 5V or 3V, IOUTFS = 20mA - 23 30 mA
5V or 3V, IOUTFS = 2mA - 4 - mA
Digital Supply Current (IDVDD) 5V, IOUTFS = Don’t Care (Note 5) - 3 5 mA
3V, IOUTFS = Don’t Care (Note 5) - 1.5 - mA
Supply Current (IAVDD) Sleep Mode 5V or 3V, IOUTFS = Don’t Care - 1.6 3 mA
Power Dissipation 5V, IOUTFS = 20mA (Note 6) - 165 - mW
5V, IOUTFS = 20mA (Note 10) - 150 - mW
5V, IOUTFS = 2mA (Note 6) - 70 - mW
3.3V, IOUTFS = 20mA (Note 10) - 75 - mW
3V, IOUTFS = 20mA (Note 6) - 85 - mW
3V, IOUTFS = 20mA (Note 10) - 67 - mW
3V, IOUTFS = 2mA (Note 6) - 27 - mW
Power Supply Rejection Single Supply (Note 7) -0.2 - +0.2 % FSR/V
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625µA). Ideally the
ratio should be 32.
3. Parameter guaranteed by design or characterization and not production tested.
4. Spectral measurements made with differential transformer coupled output and no external filtering.
5. Measured with the clock at 50MSPS and the output frequency at 1MHz.
6. Measured with the clock at 100MSPS and the output frequency at 40MHz.
7. See ‘Definition of Specifications’.
8. It is recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V. DVDD and
AVDD do not have to be equal.
9. For operation above 125MHz, it is recommended that the power supply be 3.3V or greater. The part is functional with the clock above 125MSPS
and the power supply below 3.3V, but performance is degraded (valid for 165MHz version only).
10. Measured with the clock at 60MSPS and the output frequency at 10MHz.
Electrical Specifications AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued)
PARAMETER TEST CONDITIONS
TA = -40oC TO 85oC
UNITSMIN TYP MAX
HI5660
6
Timing Diagrams
FIGURE 1. OUTPUT SETTLING TIME DIAGRAM FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
CLK
D7-D0
IOUT
50%
tSETT
1/2 LSB ERROR BAND
tPD
V
t(ps)
HEIGHT (H)
WIDTH (W)
GLITCH AREA = 1/2 (H x W)
CLK
IOUT
50%
tPW1 tPW2
tSU
tHLD
tSU tSU
tPD
tPD tPD
tHLD tHLD
tSETT
tSETT tSETT
D7-D0
HI5660
7
Definition of Specifications
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Differential Linearity Error, DNL, is the measure of the
step size output deviation from code to code. Ideally the step
size should be 1 LSB. A DNL specification of 1 LSB or less
guarantees monotonicity.
Output Settling Time, is the time required for the output
voltage to settle to within a specified error band measured
from the beginning of the output transition. In the case of the
HI5660, the measurement was done by switching from code
0 to 64, or quarter scale. Termination impedance was 25Ω
due to the parallel resistance of the output 50Ω and the
oscilloscope’s 50Ωinput. This also aids the ability to resolve
the specified error band without overdriving the oscilloscope.
Singlet Glitch Area, is the switching transient appearing on
the output during a code transition. It is measured as the
area under the overshoot portion of the curve and is
expressed as a Volt-Time specification.
Full Scale Gain Error, is the error from an ideal ratio of 32
between the output current and the full scale adjust current
(through RSET).
Full Scale Gain Drift, is measured by setting the data inputs
to all ones and measuring the output voltage through a
known resistance as the temperature is varied from TMIN to
TMAX. It is defined as the maximum deviation from the value
measured at room temperature to the value measured at
either TMIN or MAX. The units are ppm of FSR (full scale
range) per degree C.
Total Harmonic Distortion, THD, is the ratio of the DAC output
fundamental to the RMS sum of the first five harmonics.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from the fundamental to the largest harmonically or
non-harmonically related spur within the specified window.
Output Voltage Compliance Range, is the voltage limit
imposed on the output. The output impedance load should
be chosen such that the voltage developed does not violate
the compliance range.
Offset Error, is measured by setting the data inputs to all
zeros and measuring the output voltage through a known
resistance. Offset error is defined as the maximum deviation
of the output current from a value of 0mA.
Offset Drift, is measured by setting the data inputs to all
zeros and measuring the output voltage through a known
resistance as the temperature is varied from TMIN to MAX.It
is defined as the maximum deviation from the value
measured at room temperature to the value measured at
either TMIN or TMAX. The units are ppm of FSR (full scale
range) per degree C.
Power Supply Rejection, is measured using a single power
supply. Its nominal +5V is varied ±10% and the change in the
DAC full scale output is noted.
Reference Input Multiplying Bandwidth, is defined as the
3dB bandwidth of the voltage reference input. It is measured
by using a sinusoidal waveform as the external reference
with the digital inputs set to all 1s. The frequency is
increased until the amplitude of the output waveform is 0.707
of its original value.
Internal Reference Voltage Drift, is defined as the
maximum deviation from the value measured at room
temperature to the value measured at either TMIN or TMAX.
The units are ppm per degree C.
Detailed Description
The HI5660 is an 8-bit, current out, CMOS, digital to analog
converter. Its maximum update rate is 165MSPS and can be
powered by either single or dual power supplies in the
recommended range of +3V to +5V. It consumes less than
165mW of power when using a +5V supply with the data
switching at 100MSPS. The architecture is based on a
segmented current source arrangement that reduces glitch
by reducing the amount of current switching at any one time.
The five MSBs are represented by 31 major current sources
of equivalent current. The three LSBs are comprised of
binary weighted current sources. Consider an input pattern
to the converter which ramps through all the codes from 0 to
255. The three LSB current sources would begin to count up.
When they reached the all high state (decimal value of 7)
and needed to count to the next code, they would all turn off
and the first major current source would turn on. To continue
counting upward, the 3 LSBs would count up another 7
codes, and then the next major current source would turn on
and the three LSBs would all turn off. The process of the
single, equivalent, major current source turning on and the
three LSBs turning off each time the converter reaches
another 7 codes greatly reduces the glitch at any one
switching point. In previous architectures that contained all
binary weighted current sources or a binary weighted
resistor ladder, the converter might have a substantially
larger amount of current turning on and off at certain, worst-
case transition points such as midscale and quarter scale
transitions. By greatly reducing the amount of current
switching at certain ‘major’ transitions, the overall glitch of
the converter is dramatically reduced, improving settling
times and transient problems.
Digital Inputs and Termination
The HI5660 digital inputs are guaranteed to CMOS levels.
However, TTL compatibility can be achieved by lowering the
supply voltage to 3V due to the digital threshold of the input
buffer being approximately half of the supply voltage. The
internal register is updated on the rising edge of the clock. To
minimize reflections, proper termination should be
implemented. If the lines driving the clock and the digital
HI5660
8
inputs are 50Ω lines, then 50Ω termination resistors should
be placed as close to the converter inputs as possible
connected to the digital ground plane (if separate grounds
are used).
Ground Plane(s)
If separate digital and analog ground planes are used, then
all of the digital functions of the device and their
corresponding components should be over the digital ground
plane and terminated to the digital ground plane. The same
is true for the analog components and the analog ground
plane.
Noise Reduction
To minimize power supply noise, 0.1µF capacitors should
be placed as close as possible to the converter’s power
supply pins, AVDD and DVDD. Also, should the layout be
designed using separate digital and analog ground planes,
these capacitors should be terminated to the digital ground
for DVDD and to the analog ground for AVDD. Additional
filtering of the power supplies on the board is
recommended.
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.2V with a ±60 ppm/oC dr ift coefficient over the
full temperature range of the converter. It is recommended
that a 0.1µF capacitor be placed as close as possible to the
REFIO pin, connected to the analog ground. The REFLO
pin (16) selects the reference. The inter nal reference can
be selected if pin 16 is tied low (ground). If an external
reference is desired, then pin 16 should be tied high (to the
analog supply voltage) and the external reference driven
into REFIO, pin 17. The full scale output current of the
converter is a function of the voltage reference used and
the value of RSET.I
OUT should be within the 2mA to 20mA
range, through operation below 2mA is possible, with
performance degradation.
If the internal reference is used, VFSADJ will equal
approximately 1.16V (pin 18). If an external reference is
used, VFSADJ will equal the external reference. The
calculation for IOUT (full scale) is:
IOUT (Full Scale) = (VFSADJ/RSET)x 32.
If the full scale output current is set to 20mA by using the
internal voltage reference (1.16V) and a 1.86kΩ RSET
resistor, then the input coding to output current will resemble
the following:
Outputs
IOUTA and IOUTB are complementary current outputs. The
sum of the two currents is always equal to the full scale
output current minus one LSB. If single ended use is
desired, a load resistor can be used to convert the output
current to a voltage. It is recommended that the unused
output be either grounded or equally terminated. The voltage
developed at the output must not violate the output voltage
compliance range of -0.3V to 1.25V. RLOAD should be
chosen so that the desired output voltage is produced in
conjunction with the output full scale current, which is
described above in the ‘Reference’ section. If a known line
impedance is to be driven, then the output load resistor
should be chosen to match this impedance. The output
voltage equation is:
VOUT = IOUT X RLOAD.
These outputs can be used in a differential-to-single-ended
arrangement to achieve better harmonic rejection. The
SFDR measurements in this data sheet were performed with
a 1:1 transformer on the output of the DAC (see Figure 1).
With the center tap grounded, the output swing of pins 21
and 22 will be biased at zero volts. It is important to note
here that the negative voltage output compliance range limit
is -300mV, imposing a maximum of 600mVP-P amplitude
with this configuration. The loading as shown in Figure 1 will
result in a 500mV signal at the output of the transformer if
the full scale output current of the DAC is set to 20mA.
VOUT = 2 x IOUT x REQ, where REQ is ~12.5Ω.
TABLE 1. INPUT CODING vs OUTPUT CURRENT
INPUT CODE (D7-D0) IOUTA (mA) IOUTB (mA)
111 11111 20 0
100 00000 10 10
000 00000 0 20
PIN 21
PIN 22
VOUT= (2 x IOUT x REQ)V
100Ω
HI5660
50Ω
50Ω
50Ω
IOUTB
IOUTA
FIGURE 4.
HI5660
9
Pin Descriptions
PIN NO. PIN NAME PIN DESCRIPTION
1-8 D7 (MSB) Through
D0 (LSB) Digital Data Bit 7, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).
9-14 DCOM Connect to digital ground.
15 SLEEP ControlPinfor Power-Down mode.SleepModeis active high;Connecttoground for NormalMode.Sleep
pin has internal 20µA active pulldown current.
16 REFLO Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal refer-
ence.
17 REFIO Reference voltage input if internal reference is disabled. Ref erence voltage output if internal reference is en-
abled. Use 0.1µF cap to ground when internal reference is enabled.
18 FSADJ Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current = 32 x VFSADJ/RSET.
19 COMP1 For use in reducing bandwidth/noise. Recommended: connect 0.1µF to AVDD.
20 ACOM Analog Ground.
21 IOUTB The complimentary current output of the device. Full scale output current is achieved when all input bits
are set to binary 0.
22 IOUTA Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.
23 NC Internally connected to ACOM via a resistor. Recommend leave disconnected. Adding a capacitor to
ACOM for upward compatibility is valid. Grounding to ACOM is valid. (For upward compatibility to 12-bit
and 14-bit devices, pin 23 needs the ability to have a 0.1µF capacitor to ACOM.)
24 AVDD Analog Supply (+3V to +5V).
25 NC No Connect (for upward compatibility to 12 and 14b, pin 25 needs to be grounded to ACOM).
26 DCOM Digital Ground.
27 DVDD Digital Supply (+3V to +5V).
28 CLK Input for clock. Positive edge of clock latches data.
HI5660
10
HI5660
Thin Shrink Small Outline Plastic Packages (TSSOP)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AM BS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004) c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AE, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension“b”doesnot includedambarprotrusion.Allowabledambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M28.173
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.047 - 1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.051 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.378 0.386 9.60 9.80 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N28 287
α0o8o0o8o-
Rev. 0 6/98
11
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
HI5660
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbolsaredefined in the“MOSeriesSymbolList” inSection2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AM BS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H0.25(0.010) BM M
α
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.6969 0.7125 17.70 18.10 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.01 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N28 287
α0o8o0o8o-
Rev. 0 12/93
