September 2006
Advance Information
Copyright © Alliance Memory. All rights reserved.
AS7C31026C
3.3 V 64K X 16 CMOS SRAM
9/20/06, v 2.0Alliance MemoryP. 1 of 10
®
Features
Industrial (-40o to 85oC) temperature
Organization: 65,536 words × 16 bits
Center power and ground pins for low noise
High speed
- 12 ns address access time
- 6 ns output enable access time
Low power consumption via chip deselect
Upper and Lower byte pin
Easy memory expansion with CE,OE inputs
TTL-compatible, three-state I/O
JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin TSOP 2-400
- 48-ball 7 × 7 mm BGA
ESD protection ? 2000 volts
Logic block diagram
65,536 × 16
Array
OE
CE
WE Address decoder
redoced sserddA
A0
A1
A2
A3
A4
A5
A7
VCC
GND
8A
9A
01A
11A
21A
31A
41A
51A
Control circuit
I/O0–I/O7
I/O8–I/O15
UB
LB
I/O
buffer
A6
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O13
I/O12
GND
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
44-Pin SOJ (400 mil), TSOP 2
21
22
A12
NC
UB
LB
I/O15
I/O14
2
A3
3
A2
4
A1
1
A4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A6
A7
OE
A5
C62013C7SA
Pin arrangement
0000048 - BGA Ball-Grid-Array Package
1 2 3 4 5 6
A LB OE A0A1A2NC
B I/O8 UB A3 A4 CE I/O0
C I/O9
I/O10
A5 A6 I/O1 I/O2
D VSS
I/O11
NC A7 I/O3 VDD
E VDD
I/O12
NC NC I/O4 VSS
F I/O14
I/O13
A14 A15 I/O5 I/O6
G I/O15 NC A12 A13 WE I/O7
H NC A8 A9 A10 A11 NC
AS7C31026C
9/20/06, v 2.0Alliance MemoryP. 2 of 10
®
Functional description
The AS7C31026C is a 3V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized
as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing
are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for high-
performance applications.
When CE is high, the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip
enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle
2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable
(OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chips
drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write
enable is active, output drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The AS7C31026C is packaged in
common industry standard packages.
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Key: H = high, L = low, X = don’t care.
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on VCC relative to GND Vt1 –0.50 +4.60 V
Voltage on any pin relative to GND Vt2 –0.50 VCC +0.50 V
Power dissipation PD 1.25 W
Storage temperature (plastic) Tstg –55 +125 °C
Ambient temperature with VCC applied Tbias –55 +125 °C
DC current into outputs (low) IOUT 50 mA
Truth table
CE WE OE LB UB I/O0–I/O7 I/O8–I/O15 Mode
H X X X X High Z High Z Standby (ISB), ISBI)
L H L L H DOUT High Z Read I/O0–I/O7 (ICC)
L H L H L High Z DOUT Read I/O8–I/O15 (ICC)
L H L L L DOUT DOUT Read I/O0–I/O15 (ICC)
L L X L L DIN DIN Write I/O0–I/O15 (ICC)
L L X L H DIN High Z Write I/O0–I/O7 (ICC)
L L X H L High Z DIN Write I/O8–I/O15 (ICC)
L
L
H
X
H
X
X
H
X
HHigh Z High Z Output disable (ICC)
9/20/06, v 2.0Alliance MemoryP. 3 of 10
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VIL = -2.0V for pulse width less than 5ns, once per cycle.
VIH = VCC +2.0V for pulse width less than 5ns, once per cycle.
Recommended operating conditions
Parameter Symbol Min Nominal Max Unit
Supply voltage VCC 3.0 3.3 3.6 V
Input voltage VIH 2.0 VCC + 0.5 V
VIL –0.5 0.8 V
Ambient operating temperature (industrial) TA–40 85 o C
DC operating characteristics (over the operating range)1
Parameter Sym Test conditions
AS7C31026C-12
UnitMin Max
Input leakage current | ILI | VCC = Max
VIN = GND to VCC
5 µA
Output leakage current | ILO |
VCC = Max
CE = VIH,
VOUT = GND to VCC
5 µA
Operating power supply current ICC
VCC = Max,
CE ? VIL, IOUT = 0mA
f = fMax
160 mA
Standby power supply current
ISB
VCC = Max,
CE ? VIH, f = fMax
45 mA
ISB1
VCC = Max, CE ? VCC–0.2 V,
VIN ? 0.2 V or
VIN ? VCC–0.2 V, f = 0
10 mA
Output voltage VOL IOL = 8 mA, VCC = Min 0.4 V
VOH IOH = –4 mA, VCC = Min 2.4 V
Capacitance (f = 1MHz, Ta = 25 °C, VCC = NOMINAL)2
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A, CE, WE, OE, LB, UB VIN = 0 V 6 pF
I/O capacitance CI/O I/O VIN = VOUT = 0 V 7 pF
Note:
1. This parameter is guaranteed by device characterization, but is not production tested.
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Key to switching waveforms
Read waveform 1 (address controlled)3,6,7,9
Read waveform 2 (OE, CE, UB, LB controlled)3,6,8,9
Read cycle (over the operating range)3,9
Parameter Symbol
AS7C31026C-12
Unit NotesMin Max
Read cycle time tRC 12 ns
Address access time tAA 12 ns 3
Chip enable (CE) access time tACE 12 ns 3
Output enable (OE) access time tOE 6 ns
Output hold from address change tOH 4 ns 5
CE low to output in low Z tCLZ 4 ns 4, 5
CE high to output in high Z tCHZ 6 ns 4, 5
OE low to output in low Z tOLZ 0 ns 4, 5
Byte select access time tBA 5 ns
Byte select Low to low Z tBLZ 0 ns 4, 5
Byte select High to high Z tBHZ 6 ns 4, 5
OE high to output in high Z tOHZ 6 ns 4, 5
Power up time tPU 0 ns 4, 5
Power down time tPD 12 ns 4, 5
Undefined output/don’t careFalling inputRising input
t
OH
t
AA
t
RC
t
OH
Data
OUT
Address
Data validPrevious data valid
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
HZ
t
BHZ
t
ACE
t
LZ
Address
OE
CE
LB, UB
Data
IN
AS7C31026C
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Write waveform 1 (WE controlled)10,11
Write cycle (over the operating range) 11
Parameter Symbol
AS7C31026C-12
Unit NotesMin Max
Write cycle time tWC 12 ns
Chip enable (CE) to write end tCW 8 ns
Address setup to write end tAW 8 ns
Address setup time tAS 0 ns
Write pulse width tWP 8 ns
Write recovery time tWR 0 ns
Address hold from end of write tAH 0 ns
Data valid to write end tDW 6 ns
Data hold time tDH 0 ns 5
Write enable to output in high Z tWZ 6 ns 4, 5
Output active from write end tOW 3 ns 4, 5
Byte select low to end of write tBW 8 ns
Address
CE
LB, UB
WE
Data
IN
Data
OUT
t
WC
t
CW
t
BW
t
AW
t
AS
t
WP
t
DW
t
DH
t
OW
t
WZ
t
WR
Data undefined high Z
Data valid
t
AH
AS7C31026C
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Write waveform 2 (CE controlled)10,11
AC test conditions
Notes
1 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A and B.
4 These parameters are specified with CL = 5 pF, as in Figures B. Transition is measured ± 200 mV from steady-state voltage.
5 This parameter is guaranteed, but not tested.
6 WE is high for read cycle.
7 CE and OE are low for read cycle.
8 Address is valid prior to or coincident with CE transition low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
Address
CE
LB, UB
WE
Data
IN
t
WC
t
CW
t
BW
t
WP
t
DW
t
DH
t
OW
t
WZ
t
WR
Data
OUT
Data undefined
high Z high Z
t
AS
t
AW
Data valid
t
CLZ
t
AH
255
?
C
13
320
?
GND
+3.3 V
Figure B: 3.3 V Output load
168
?
Thevenin Equivalent:
D
OUT
+1.728 V
10%
90%
10%
90%
GND
+3.0 V
Figure A: Input pulse
3 ns
D
OUT
Output load: see Figure B.
Input pulse level: GND to 3.0 V. See Figure A.
Input rise and fall times: 3 ns. See Figure A.
Input and output timing reference levels: 1.5
AS7C31026C
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Package dimensions
44-pin TSOP 2
Min
(mm)
Max
(mm)
A1.2
A1 0.05 0.15
A2 0.95 1.05
b0.30 0.45
c0.120 0.21
D18.31 18.52
E10.06 10.26
He 11.68 11.94
e0.80 (typical)
l0.40 0.60
D
He
1 2 3 4 5 6 7 8 9 10 11 12 13 14
4443 42 41 40 39 38 37 36 35 3433 32 31
15 16
30 29
1718 19 20
28 27 26 25
c
l
A1
A2
e
44-pin TSOP 2
0–5
°
21
24
22
23
E
A
b
Seating
plane
44-pin SOJ
44-pin SOJ
400 mil
Min (in) Max (in)
A0.128 0.148
A10.025
A20.105 0.115
B0.026 0.032
b0.015 0.020
c0.007 0.013
D1.120 1.130
E0.370 NOM
E10.395 0.405
E20.435 0.445
e0.050 NOM
e
Pin 1
A1
b
B
A
A2
E2
E1
D
c
E
AS7C31026C
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®
Notes
1 Bump counts: 48 (8 row x 6 column).
2 Pitch: (x,y) = 0.75 mm x 0.75 mm (typ).
3 Units: millimeters.
4 All tolerance are +/- 0.050 unless otherwise specified.
5 Typ: typical.
6 Y is coplanarity: 0.010 (max).
7 “A1” ID corner must be identified by chamfer, ink mark,
metallized marking, indentation or other feature on the pack-
age body.
8 If “A1” ID corner is on the package body, it must be located
within the zone indicated.
Minimum Typical Maximum
A 0.75
B 7.00 BSC
B1 3.75
C7.00 BSC
C1 5.25
D0.25 0.30 0.40
E 1.14 1.24 1.34
E1 0.68
E2 0.15 0.20 0.25
Y 0.010
48-ball BGA
Bottom View
6 5 4 3 2 1 Ball A1
C1
A
B
C
D
F
G
H
J
A
B1
Side View
Top View
Ball #A1 index (see note 7)
C
SRAM DIE
B
Detail View
A
Y
Die
0.3/T
µ
p
E2
E
Die
D
E1
E2
E
*pin 1 indicator will show as
engraved circle and/or Inc. trade mark
B/4
C/4
(see note 8)
AS7C31026C
9/20/06, v 2.0Alliance MemoryP. 9 of 10
®
Ordering codes
Package Volt/Temp 12 ns
Plastic SOJ, 400 mil 3.3V industrial AS7C31026C-12JIN
TSOP 2, 10.2 x 18.4 mm 3.3V industrial AS7C31026C-12TIN
BGA, 7 x 7 mm 3.3V industrial AS7C31026C-12BIN
Part numbering system
AS7C X 1026B –XX X X X
SRAM
prefix
Voltage:
3 = 3.3 V
CMOS
Device
number
Access
time
Package:
J = SOJ 400 mil
T = TSOP 2, 10.2 x 18.4 mm
B=BGA, 7 x 7 mm
Temperature
I = industrial: -40° C
to 85° C
N = Lead Free Part
AS7C31026C
Alliance Memory, Inc.
511 Taylor Way
San Carlos, CA 94070, USA
Tel: 650-610-6800
Fax: 650-620-9211
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
Part Number: AS7C31026C-12JIN
Document Version: v 2.0
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AS7C31026C
®
®