October 1987
Revised January 1999
CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate • Quad 2-Input NAND Buffered B Series Gate
© 1999 Fairchild Semicond uctor Corpor ation DS005939.prf www.fairchildsemi.com
CD4001BC/CD4011BC
Quad 2-Input NOR Buffered B Series Gate •
Quad 2-Input NAND Buffered B Series Gate
General Descript ion
The CD4001BC and CD4011BC quad gates are monolithic
complementary MOS (CMOS) integrated circuits con-
structed with N- and P-channel enhancement mode tran-
sistors. They have equal source and sink current
capabilities and conform to standard B series output drive.
The devices also have buffered outputs which improve
transfer characteristics by providing very high gain.
All inputs are protected against static discharge with diodes
to VDD and VSS.
Features
■Low power TTL:
Fan out of 2 driving 74L compatibility: or 1 driving 74LS
■5V–10V–15V parametric ratings
■Symmetrical output characteristics
■Maximum input leakage 1 µA at 15V over full
temperature range
Ordering Code:
Devices also available in Tape and Reel. Spe c if y by appendin g t he suffix lett er “X” to the order ing code.
Connection Diagrams
Pin Assignments for DIP, SOIC and SOP
CD4001BC
Top View
Pin Assignments for DIP and SOIC
CD4011BC
Top View
Order Number Package Number Package Description
CD4001BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
CD4001BCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE I I, 5.3mm Wide
CD4001BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
CD4011BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
CD4011BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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CD4001BC/CD4011BC
Schematic Diagrams
CD4001BC
1/4 of device sh ow n
J = A + B
Logica l “1” = HIGH
Logica l “0” = LOW
All input s prot ected by st andard
CMOS protect ion circuit.
CD4011BC
1/4 of device sh ow n
J = A • B
Logica l “1” = HIGH
Logica l “0” = LOW
All input s prot ected by st andard
CMOS protect ion circuit.
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CD4001BC/CD4011BC
Absolute Maximum Ratings(Note 1)
(Note 2) Recommended Operating
Conditions
Note 1: “Absolute Ma ximum Rating s” are those values beyond whic h the
safety of the device c annot be guaranteed. Ex c ept for “Operating Tempera-
ture Rang e” they are not meant to imp ly that the devices shoul d be oper-
ated at t hese limits. The E lec t rical Ch arac t eris tics t ables provide c onditions
for actual device operation.
Note 2: All voltag es m eas ured w ith re spe ct to VSS unless ot herw ise speci-
fied.
DC Electrical Characteristics (Note 2)
Note 3: IOL and IOH are tes t ed one ou tp ut at a ti m e.
AC Electri cal Characteristics (Note 4)
CD4001BC: TA = 25°C, Input tr; tf = 20 ns. CL = 50 pF, RL = 200k. Typical temperature coefficient is 0.3%/°C.
Note 4: AC Paramete rs are guarant eed by DC cor related te sting.
Voltage at any Pin −0.5V to VDD +0.5V
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
VDD Range −0.5 VDC to +18 VDC
Storage Temperature (TS)−65°C to +150°C
Lead Temperature (TL)
(Soldering, 10 seco nds ) 260°C
Operating Range (VDD)3 V
DC to 15 VDC
Operating Temperature Range
CD400 1B C, CD4011B C −40°C to +85°C
Symbol Parameter Conditions −40°C+25°C+85°CUnits
Min Max Min Typ Max Min Max
IDD Quiescent Device VDD = 5V, VIN = VDD or VSS 1 0.004 1 7.5 µA
Current VDD = 10V, VIN = VDD or VSS 20.0052 15µA
VDD = 15V, VIN = VDD or VSS 40.0064 30µA
VOL LOW Level VDD = 5V 0.05 0 0.05 0.05 V
Output Voltage VDD = 10V |IO| < 1 µA 0.05 0 0.05 0.05 V
VDD = 15V 0.05 0 0.05 0.05 V
VOH HIGH Level VDD = 5V 4.95 4.95 5 4.95 V
Output Voltage VDD = 10V |IO| < 1 µA 9.95 9.95 10 9.95 V
VDD = 15V 14.95 14.95 15 14.95 V
VIL LOW Level VDD = 5V, VO = 4.5V 1.5 2 1.5 1.5 V
Input Voltage VDD = 10V, VO = 9.0V 3.0 4 3.0 3.0 V
VDD = 15V, VO = 13.5V 4.0 6 4.0 4.0 V
VIH HIGH Level VDD = 5V, VO = 0.5V 3.5 3.5 3 3.5 V
Input Voltage VDD = 10V, VO = 1.0V 7.0 7.0 6 7.0 V
VDD = 15V, VO = 1.5V 11.0 11.0 9 11.0 V
IOL LOW Level Output VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA
Current VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA
(Note 3) VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA
IOH HIGH Level Output VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA
Current VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.9 mA
(Note 3) VDD = 15V, VO = 13.5V −3.6 −3.0 −8.8 −2.4 mA
IIN Input Current VDD = 15V, VIN = 0V −0.30 −10−5−0.30 −1.0 µA
VDD = 15V, VIN = 15V 0.30 10−50.30 1.0 µA
Symbol Parameter Conditions Typ Max Units
tPHL Propagation Delay Time, VDD = 5V 120 250 ns
HIGH-to-LOW Level VDD = 10V 50 100 ns
VDD = 15V 35 70 ns
tPLH Propagation Delay Time, VDD = 5V 110 250 ns
LOW-to-HIGH Level VDD = 10V 50 100 ns
VDD = 15V 35 70 ns
tTHL, tTLH Transition Time VDD = 5V 90 200 ns
VDD = 10V 50 100 ns
VDD = 15V 40 80 ns
CIN Average Input Capacitance Any Input 5 7.5 pF
CPD Power Dissipation Capacity Any Gate 14 pF
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CD4001BC/CD4011BC
AC Electri cal Characteristics (Note 5)
CD4011BC: TA= 25°C, Input tr; tf = 20 ns. CL = 50 pF, RL = 200k. Typical Temperature Coefficient is 0.3%/°C.
Note 5: AC Parameters are guaranteed by DC cor related test ing.
Typical Performance Characteristics
Typical
Transfer Characteristics
Typical
Transfer Characteristics
Typical
Transfer Characteristics
Symbol Parameter Conditions Typ Max Units
tPHL Propagation Delay, VDD = 5V 120 250 ns
HIGH-to-LOW Level VDD = 10V 50 100 ns
VDD = 15V 35 70 ns
tPLH Propagation Delay, VDD = 5V 85 250 ns
LOW-to-HIGH Level VDD = 10V 40 100 ns
VDD = 15V 30 70 ns
tTHL, tTLH Transition Time VDD = 5V 90 200 ns
VDD = 10V 50 100 ns
VDD = 15V 40 80 ns
CIN Average Input Capacitance Any Input 5 7 .5 pF
CPD Power Dissipation Capacity A ny Gate 14 pF
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CD4001BC/CD4011BC
Typical Transfer Characteristics
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CD4001BC/CD4011BC
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CD4001BC/CD4011BC
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
F airchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate • Quad 2-Input NAND Buffered B Series Gate
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or sys tem s ar e devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A criti cal comp onent in any comp onent of a l ife suppor t
device or system whose failure to perform can be rea-
sonably expected to cau se the failure of the li fe support
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
