SLAS062E - JANUARY 1987 - REVISED NOVEMBER 2008 D Easily Interfaced to Microprocessors D On-Chip Data Latches D Monotonic Over the Entire A/D Conversion D D D D Range Interchangeable With Analog Devices AD7528 and PMI PM-7528 Fast Control Signaling for Digital Signal Processor (DSP) Applications Including Interface With TMS320 Voltage-Mode Operation CMOS Technology DW, N OR PW PACKAGE (TOP VIEW) AGND OUTA RFBA REFA DGND DACA/DACB (MSB) DB7 DB6 DB5 DB4 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 OUTB RFBB REFB VDD WR CS DB0 (LSB) DB1 DB2 DB3 KEY PERFORMANCE SPECIFICATIONS FN PACKAGE (TOP VIEW) description The TLC7528C, TLC7528E, and TLC7528I are dual, 8-bit, digital-to-analog converters (DACs) designed with separate on-chip data latches and feature exceptionally close DAC-to-DAC matching. Data are transferred to either of the two DAC data latches through a common, 8-bit, input port. Control input DACA/DACB determines which DAC is to be loaded. The load cycle of these devices is similar to the write cycle of a random-access memory, allowing easy interface to most popular microprocessor buses and output ports. Segmenting the high-order bits minimizes glitches during changes in the most significant bits, where glitch impulse is typically the strongest. RFBA OUTA AGND OUTB RFBB 8 bits 1/2LSB 20mW 100ns 80ns REFA DGND DACA/DACB (MSB) DB7 DB6 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 REFB VDD WR CS DB0 (LSB) DB5 DB4 DB3 DB2 DB1 Resolution Linearity Error Power Dissipation at VDD = 5V Settling Time at VDD = 5V Propagation Delay Time at VDD = 5V These devices operate from a 5V to 15V power supply and dissipates less than 15mW (typical). The 2- or 4-quadrant multiplying makes these devices a sound choice for many microprocessor-controlled gain-setting and signal-control applications. It can be operated in voltage mode, which produces a voltage output rather than a current output. Refer to the typical application information in this data sheet. The TLC7528C is characterized for operation from 0C to +70C. The TLC7528I is characterized for operation from -25C to +85C. The TLC7528E is characterized for operation from - 40C to +85C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2000-2008, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SLAS062E - JANUARY 1987 - REVISED NOVEMBER 2008 functional block diagram DB0 14 REFA 13 12 8 11 Data Inputs Input Buffer 10 Latch A 9 8 DB7 DACA/DACB WR CS III III III III IIIII IIIII IIIII IIIII RFBA 4 8 2 OUTA DACA 1 AGND 7 8 6 16 Logic Control 15 III III III III Latch B 8 IIIII IIIII IIIII IIIII DACB 18 REFB operating sequence tsu(CS) th(CS) tsu(DAC) th(DAC) CS DACA/DACB tw(WR) WR tsu(D) Data In Stable DB0 -DB7 2 3 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 th(D) 19 20 RFBB OUTB SLAS062E - JANUARY 1987 - REVISED NOVEMBER 2008 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VDD (to AGND or DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16.5V Voltage between AGND and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Input voltage range, VI (to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3 Reference voltage, VrefA or VrefB (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V Feedback voltage VRFBA or VRFBB (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V Input voltage (voltage mode out A, out B to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3 Output voltage, VOA or VOB (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V Peak input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10A Operating free-air temperature range, TA: TLC7528C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C TLC7528I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C TLC7528E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Case temperature for 10 seconds, TC: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260C Lead temperature 1,6mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . +260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. package/ordering information For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. recommended operating conditions VDD = 4.75V to 5.25V MIN NOM MAX VDD = 14.5V to 15.5V MIN NOM MAX 10 Reference voltage, VrefA or VrefB High-level input voltage, VIH 10 2.4 Low-level input voltage, VIL CS setup time, tsu(CS) 50 CS hold time, th(CS) V 13.5 0.8 UNIT V 1.5 V 50 ns 0 0 ns DAC select setup time, tsu(DAC) 50 50 ns DAC select hold time, th(DAC) 10 10 ns Data bus input setup time tsu(D) 25 25 ns Data bus input hold time th(D) 10 10 ns Pulse duration, WR low, tw(WR) 50 TLC7628C Operating free-air temperature, TA 50 ns 0 +70 0 +70 TLC7628I -25 +85 -25 +85 TLC7628E -40 +85 -40 +85 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 C C 3 SLAS062E - JANUARY 1987 - REVISED NOVEMBER 2008 electrical characteristics over recommended operating free-air temperature range, VrefA = VrefB = 10V, VOA and VOB at 0V (unless otherwise noted) PARAMETER IIH IIL TEST CONDITIONS High-level input current VI = VDD VI = 0 Low-level input current VDD = 5V MIN TYP MAX VDD = 15V MIN TYP MAX 10 10 A -10 A 20 20 k 5 Reference input impedance REFA or REFB to AGND IIkg 5 12 DAC data latch loaded with 00000000, VrefA = 10V 400 200 OUTB DAC data latch loaded with 00000000, VrefB = 10V 400 200 1% 1% VDD = 10% All digital inputs at VIHmin or VILmax 0.04 0.02 %/% 2 2 mA All digital inputs at 0V or VDD 0.5 0.5 mA DB0-DB7 10 10 pF WR, CS, DACA/DACB 15 15 pF DAC data latches loaded with 00000000 50 50 DAC data latches loaded with 11111111 120 120 Output leakage current DC supply sensitivity, gain/VDD IDD Supply current (quiescent) IDD Supply current (standby) Ci Input capacitance Output capacitance (OUTA, OUTB) All typical values are at TA = +25C. 4 -10 OUTA Input resistance match (REFA to REFB) Co 12 UNIT POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 nA pF SLAS062E - JANUARY 1987 - REVISED NOVEMBER 2008 operating characteristics over recommended operating free-air temperature range, VrefA = VrefB = 10V, VOA and VOB at 0V (unless otherwise noted) PARAMETER TEST CONDITIONS VDD = 5V MIN TYP MAX VDD = 15V MIN TYP MAX UNIT 1/2 1/2 LSB Linearity error Settling time (to 1/2LSB) See Note 1 100 100 ns Gain error See Note 2 2.5 2.5 LSB -65 -65 -65 -65 REFA to OUTA AC feedthrough REFB to OUTB See Note 3 Temperature coefficient of gain See Note 4 0.007 Propagation delay (from digital input to 90% of final analog output current) See Note 5 80 REFA to OUTB See Note 6 77 77 REFB to OUTA See Note 7 77 77 Channel-to-channel isolation dB 0.0035 %FSR/C 80 ns dB Digital-to-analog glitch impulse area Measured for code transition from 00000000 to 11111111, TA = +25C 160 440 nV-s Digital crosstalk Measured for code transition from 00000000 to 11111111, TA = +25C 30 60 nV-s Harmonic distortion NOTES: 1. 2. 3. 4. 5. 6. 7. Vi = 6V, f = 1kHz, TA = +25C -85 -85 dB OUTA, OUTB load = 100, Cext = 13pF; WR and CS at 0V; DB0-DB7 at 0V to VDD or VDD to 0V. Gain error is measured using an internal feedback resistor. Nominal full scale range (FSR) = Vref - 1LSB. Vref = 20V peak-to-peak, 100kHz sine wave; DAC data latches loaded with 00000000. Temperature coefficient of gain measured from 0C to +25C or from +25C to +70C. VrefA = VrefB = 10V; OUTA/OUTB load = 100, Cext = 13pF; WR and CS at 0V; DB0-DB7 at 0V to VDD or VDD to 0V. Both DAC latches loaded with 11111111; VrefA = 20V peak-to-peak, 100kHz sine wave; VrefB = 0; TA = +25C. Both DAC latches loaded with 11111111; VrefB = 20V peak-to-peak, 100kHz sine wave; VrefA = 0; TA = +25C. PRINCIPLES OF OPERATION These devices contain two identical, 8-bit-multiplying DACs, DACA and DACB. Each DAC consists of an inverted R-2R ladder, analog switches, and input data latches. Binary-weighted currents are switched between DAC output and AGND, thus maintaining a constant current in each ladder leg independent of the switch state. Most applications require only the addition of an external operational amplifier and voltage reference. A simplified DAC circuit for DACA with all digital inputs low is shown in Figure 1. Figure 2 shows the DACA equivalent circuit. A similar equivalent circuit can be drawn for DACB. Both DACs share the analog ground terminal 1 (AGND). With all digital inputs high, the entire reference current flows to OUTA. A small leakage current (IIkg) flows across internal junctions, and as with most semiconductor devices, doubles every 10C. Co is due to the parallel combination of the NMOS switches and has a value that depends on the number of switches connected to the output. The range of Co is 50pF to 120pF maximum. The equivalent output resistance (ro) varies with the input code from 0.8R to 3R where R is the nominal value of the ladder resistor in the R-2R network. These devices interface to a microprocessor through the data bus, CS, WR, and DACA/DACB control signals. When CS and WR are both low, the TLC7528 analog output, specified by the DACA/DACB control line, responds to the activity on the DB0-DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects the analog output. When either the CS signal or WR signal goes high, the data on the DB0-DB7 inputs are latched until the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless of the state of the WR signal. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SLAS062E - JANUARY 1987 - REVISED NOVEMBER 2008 PRINCIPLES OF OPERATION The digital inputs of these devices provide TTL compatibility when operated from a supply voltage of 5V. These devices can operate with any supply voltage in the range from 5V to 15V; however, input logic levels are not TTL-compatible above 5V. R R R REFA 2R 2R 2R 2R 2R RFB S1 S2 S3 RFBA S8 OUTA AGND DACA Data Latches and Drivers Figure 1. Simplified Functional Circuit for DACA RFBA RFB R OUTA REFA I 256 COUT IIkg AGND Figure 2. TLC7528 Equivalent Circuit, DACA Latch Loaded With 11111111 MODE SELECTION TABLE DACA/DACB CS WR DACA DACB L H X X L L H X L L X H Write Hold Hold Hold Hold Write Hold Hold L = low level, 6 H = high level, POST OFFICE BOX 655303 X = don't care * DALLAS, TEXAS 75265 SLAS062E - JANUARY 1987 - REVISED NOVEMBER 2008 APPLICATION INFORMATION These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for 2-quadrant and 4-quadrant multiplication are shown in Figure 3 and Figure 4. Table 1 and Table 2 summarize input coding for unipolar and bipolar operation, respectively. VI(A) 10 V R1 (see Note A) RFBA OUTA 8 Latch VOA AGND Latch RECOMMENDED TRIM RESISTOR VALUES R1, R3 R2, R4 500 150 IIII IIII IIII IIII R4 (see Note A) OUTB 8 DACB C2 (see Note B) + Control Logic III III III III RFBB - 8 6 CS 16 WR 5 DGND DACA + 8 Input Buffer 7 15 IIII IIII IIII REFA DB7 DACA / DACB C1 (see Note B) - 17 VDD 14 DB0 R2 (see Note A) VOB AGND REFB AGND R3 (see Note A) VI(B) 10 V NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Make gain adjustment with digital input of 255. B. C1 and C2 phase compensation capacitors (10pF to 15pF) are required when using high-speed amplifiers to prevent ringing or oscillation. Figure 3. Unipolar Operation (2-Quadrant Multiplication) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SLAS062E - JANUARY 1987 - REVISED NOVEMBER 2008 APPLICATION INFORMATION VI(A) 10 V R6 20 k (see Note B) R1 (see Note A) DACA/ DACB 15 CS 16 WR 5 OUTA 8 DACA 8 III III Latch A1 AGND RFBB Control Logic DGND Latch OUTB DACB REFB AGND R8 20 k A3 AGND VOA R11 5 k R4 (see Note A) C2 (see Note C) 8 - A2 + (see Note B) + 6 III III R9 10 k (see Note B) R3 (see Note A) A4 + 7 8 - Input Buffer R5 20 k R7 10 k - DB7 IIII IIII IIII IIII IIII IIII IIII C1 (see Note C) + DB0 17 14 R2 (see Note A) - VDD RFBA VOB R11 5 k AGND R10 20 k (see Note B) VI(B) 10 V NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table in Figure 3 for recommended values. Adjust R1 for VOA = 0V with code 10000000 in DACA latch. Adjust R3 for VOB = 0V with 10000000 in DACB latch. B. Matching and tracking are essential for resistor pairs R6, R7, R9, and R10. C. C1 and C2 phase compensation capacitors (10pF to 15pF) may be required if A1 and A3 are high-speed amplifiers. Figure 4. Bipolar Operation (4-Quadrant Operation) Table 1. Unipolar Binary Code DAC LATCH CONTENTS MSB LSB ANALOG OUTPUT DAC LATCH CONTENTS MSB LSB ANALOG OUTPUT 11111111 10000001 10000000 01111111 00000001 00000000 -VI (255/256) -VI (129/256) -VI (128/256) = - Vi/2 -VI (127/256) -VI (1/256) -VI (0/256) = 0 11111111 10000001 10000000 01111111 00000001 00000000 VI (127/128) VI (1/128) 0V -VI (1/128) -VI (127/128) -VI (128/128) 1LSB = (2-8)VI 8 Table 2. Bipolar (Offset Binary) Code 1LSB = (2-7)VI POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLAS062E - JANUARY 1987 - REVISED NOVEMBER 2008 APPLICATION INFORMATION microprocessor interface information 8 Address Bus A8 -A15 DACA/DACB Address Decode Logic CPU 8051 A CS A+1 WR TLC7528 DB0 WR DB7 ALE Latch 8 Data Bus AD0 -AD7 NOTE A: A = decoded address for TLC7528 DACA A + 1 = decoded address for TLC7528 DACB Figure 5. TLC7528: Intel 8051 Interface 8 Address Bus A8 -A15 DACA/DACB VMA CPU 6800 Address Decode Logic A CS A+1 WR TLC7528 DB0 2 DB7 8 AD0 -AD7 Data Bus NOTE A: A = decoded address for TLC7528 DACA A + 1 = decoded address for TLC7528 DACB Figure 6. TLC7528: 6800 Interface POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SLAS062E - JANUARY 1987 - REVISED NOVEMBER 2008 APPLICATION INFORMATION 8 Address Bus A8 -A15 DACA/DACB Address Decode Logic IORQ A CS TLC7528 WR A+1 CPU Z80-A DB0 DB7 WR 8 Data Bus D0 -D7 NOTE A: A = decoded address for TLC7528 DACA A + 1 = decoded address for TLC7528 DACB Figure 7. TLC7528 To Z-80A Interface programmable window detector The programmable window comparator shown in Figure 8 determines if the voltage applied to the DAC feedback resistors is within the limits programmed into the data latches of these devices. Input signal range depends on the reference and polarity; that is, the test input range is 0 to -Vref. The DACA and DACB data latches are programmed with the upper and lower test limits. A signal within the programmed limits drives the output high. 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLAS062E - JANUARY 1987 - REVISED NOVEMBER 2008 APPLICATION INFORMATION VCC VDD Test Input 0 to -Vref 3 17 RFBA 1 k OUTA - 4 2 DACA REFA + 8 14 -7 Data Inputs DB0 -DB7 TLC7528 15 16 6 CS 1 WR DACA / DACB OUTB DACB + 5 20 - 18 REFB Vref PASS / FAIL Output AGND DGND RFBB 19 Figure 8. Digitally-Programmable Window Comparator (Upper- and Lower-Limit Tester) digitally-controlled signal attenuator Figure 9 shows a TLC7528 configured as a two-channel programmable attenuator. Applications include stereo audio and telephone signal level control. Table 3 shows input codes vs attenuation for a 0dB to 15.5dB range. Attenuation dB = - 20 log10 D/256, D = digital input code VDD 17 4 VIA REFA RFBA 3 OUTA 2 DACA A1 DB0 -DB7 TLC7528 CS WR 20 VOB DACA / DACB OUTB DACB A2 REFB AGND RFBB DGND 14 -7 Output 8 Data Bus 15 16 6 18 1 5 19 Figure 9. Digitally Controlled Dual Telephone Attenuator POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 SLAS062E - JANUARY 1987 - REVISED NOVEMBER 2008 APPLICATION INFORMATION Table 3. Attenuation vs DACA, DACB Code ATTEN (dB) DAC INPUT CODE CODE IN DECIMAL ATTN (dB) DAC INPUT CODE CODE IN DECIMAL 0 11111111 255 8.0 01100110 102 0.5 11110010 242 8.5 01100000 96 1.0 11100100 228 9.0 01011011 91 1.5 11010111 215 9.5 01010110 86 2.0 11001011 203 10.0 01010001 81 2.5 11000000 192 10.5 01001100 76 3.0 10110101 181 11.0 01001000 72 3.5 10101011 171 11.5 01000100 68 4.0 10100010 162 12.0 01000000 64 4.5 10011000 152 12.5 00111101 61 5.0 10011111 144 13.0 00111001 57 5.5 10001000 136 13.5 00110110 54 6.0 10000000 128 14.0 00110011 51 6.5 01111001 121 14.5 00110000 48 7.0 01110010 114 15.0 00101110 46 7.5 01101100 108 15.5 00101011 43 programmable state-variable filter This programmable state-variable or universal filter configuration provides low-pass, high-pass, and bandpass outputs, and is suitable for applications requiring microprocessor control of filter parameters. As shown in Figure 10, DACA1 and DACB1 control the gain and Q of the filter while DACA2 and DACB2 control the cutoff frequency. Both halves of the DACA2 and DACB2 must track accurately in order for the cutoff-frequency equation to be true. With the TLC7528, this validity is easy to achieve. fc + 1 2p R1C1 The programmable range for the cutoff or center frequency is 0kHz to 15kHz with a Q ranging from 0.3 to 4.5. This parameter defines the limits of the component values. 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLAS062E - JANUARY 1987 - REVISED NOVEMBER 2008 APPLICATION INFORMATION C3 47 pF 17 Data In REFA DACA (RS) VDD RFBA 8 AGND TLC7528 15 16 5 6 3 30 k R4 A1 1 30 k R3 CS OUTB DACB (RF) WR R5 RFBB DGND 20 A2 10 k + VI OUTA 2 + 4 19 High Pass Out REFB 18 DACA / DACB Bandpass Out DACA1 AND DACB1 C1 1000 pF Data In OUTA 2 DACA (R1) VDD RFBA 8 TLC7528 15 16 5 6 AGND 1 C2 OUTB 20 1000 pF CS DACB (R2) WR A3 3 RFBB DGND 19 A4 Low Pass Out + 17 REFA + 4 REFB 18 DACA / DACB DACA2 and DACB2 Circuit Equations: C1 = C2, R1 = R2, R4 = R5 Q= R R3 R4 R F fb(DACB1) Where: R is the internal resistor connected between OUTB and RFBB fb R - F G RS NOTES: A. Op-amps A1, A2, A3, and A4 are TL287. B. CS compensates for the op-amp gain-bandwidth limitations. 256 (DAC ladder resistance) C. DAC equivalent resistance equals DAC digital code Figure 10. Digitally-Controlled State-Variable Filter POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 SLAS062E - JANUARY 1987 - REVISED NOVEMBER 2008 APPLICATION INFORMATION voltage-mode operation It is possible to operate the current multiplying D/A converter of these devices in a voltage mode. In the voltage mode, a fixed voltage is placed on the current output terminal. The analog output voltage is then available at the reference voltage terminal. Figure 11 is an example of a current multiplying D/A that operates in the voltage mode. R R R REF (Analog Output Voltage) 2R 2R 2R "0" 2R "1" R Out (Fixed Input Voltage) AGND Figure 11. Voltage-Mode Operation The following equation shows the relationship between the fixed input voltage and the analog output voltage: VO = VI (D/256) Where: VO = analog output voltage VI = fixed input voltage (must not be forced below 0V.) D = digital input code converted to decimal In voltage-mode operation, these devices meet the following specification: PARAMETER Linearity error at REFA or REFB 14 TEST CONDITIONS VDD = 5V, POST OFFICE BOX 655303 OUTA or OUTB at 2.5V, * DALLAS, TEXAS 75265 MIN TA = +25C MAX UNIT 1 LSB Revision History DATE REV PAGE SECTION DESCRIPTION 11/08 E 13 Application Information Front Page -- Deleted Available Options table. 6/07 D 3 -- Inserted Package/Ordering information. Corrected Figure 10. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. PACKAGE OPTION ADDENDUM www.ti.com 28-May-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC7528CDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7528CDWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7528CDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7528CDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7528CFN ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC7528CFNG3 ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC7528CFNR ACTIVE PLCC FN 20 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC7528CFNRG3 ACTIVE PLCC FN 20 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC7528CN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC7528CNE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC7528CNS ACTIVE SO NS 20 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7528CNSG4 ACTIVE SO NS 20 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7528CNSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7528CNSRG4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7528CPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7528CPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7528CPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7528CPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7528EDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7528EDWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7528EDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7528EDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7528EN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC7528ENE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC7528IDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 28-May-2009 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC7528IDWG4 ACTIVE SOIC DW 20 TLC7528IDWR ACTIVE SOIC DW TLC7528IDWRG4 ACTIVE SOIC TLC7528IFN ACTIVE TLC7528IFNG3 25 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC7528IN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC7528INE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC7528IPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7528IPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7528IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7528IPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC7528CDWR Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) DW 20 2000 330.0 24.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.8 13.0 2.7 12.0 24.0 Q1 TLC7528CNSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1 TLC7528CPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 TLC7528EDWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 TLC7528IDWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 TLC7528IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC7528CDWR SOIC DW 20 2000 367.0 367.0 45.0 TLC7528CNSR SO NS 20 2000 367.0 367.0 45.0 TLC7528CPWR TSSOP PW 20 2000 367.0 367.0 38.0 TLC7528EDWR SOIC DW 20 2000 367.0 367.0 45.0 TLC7528IDWR SOIC DW 20 2000 367.0 367.0 45.0 TLC7528IPWR TSSOP PW 20 2000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MPLC004A - OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56) 44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10) 52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37) 68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45) 4040005 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI's terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers' products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers' products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI's goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or "enhanced plastic" are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such components to meet such requirements. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP(R) Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2012, Texas Instruments Incorporated