a se a at ets PRE LISUNARY CY7C1011 S57 Cypress Features * High speed taa =15 Ns + Low active power 1150 mW (max.} * Low CMOS standby power (L version) 40 mW (max.) + 2.0V Data Retention (4 mW at 2.0V retention) * Automatic power-down when deselected + TTL-compatible inputs and outputs + Easy memory expansion with CE and OE features Functional Description The CY7C1011 is a high-performance GMOS static RAM or- ganized as 131,072 words by 16 bits. Writing to the device is accomplished by taking chip enable (GE} and write enable (WE) inputs LOW. If byte low enable 128K x 16 Static RAM (BLE) is LOW, then data from I/O pins (I/Og through I/O2), is written into the location specified on the address pins (Ap through Ajg}. IF byte high enable (BHE) is LOW, then data from lO pins (/Og through |/O,5) is written into the location speci- fied on the address pins (Ag through Ay). Reading from the device is accomplished by taking chip en- able (CE} and output enable (OE) LOW while forcing the write enable (WE) HIGH. If byte low enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/Og to /O;. If byte high enable (BHE) is LOW, then data from memory will appear on I/Og to I/O45. See the truth table at the back of this datasheet for a complete description of read and write modes. The input/output pins (Og through VO,5) are placed in_a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1011 is available in a standard 44-pin TSOP II pack- age with center power and ground (revolutionary) pinout. Logic Block Diagram INPUT BUFFER Pin Configuration TSOP II Top View Ml Ad! 4D As AL Ww AaQ2 4301 Ag wm As 3 256K x 16 & Og - Oz ne 3 | ar Ay a ARRAY z ' o ; 400 BHE As 3 1024 x 4098 z Og 1/045 cer . 29H BLE ne O97 36 A 1/045 As 0,08 37D O44 "OsQ 36D 1/043 vgn Bios co 8s Vgs 12 3H Voc O40 13 32 r) O44 fO5 O14 3100 1/049 105 Qs 30 1 1/Og 1107 O16 2a Og BHE WEQ17 23] NC WE Aid 18 2710 Ag CE Aid 19 2600 Ag OE Ay 20 25 r] Ato BLE Ayd21 24 Ay tortet Ay] 22 230 NC 1011-2 Selection Guide 701011-15 71011-20 701011-25 Maximum Access Time (ns) 15 20 25 Maximum Operating Current (mA) 230 220 200 Maximum GMOS Standby Current (mA) Com' 8 8 8 Cypress Semiconductor Corporation * 3901 North FirstStreet +* SanJose * GA 95134 + 408-943-2600 November 19, 1998ae ma PRSSLIAINASY CY7C1011 Maximum Ratings DC Input Voltagel"] (Above which the useful life may be impaired. For user guide- Current into Outputs (LOW)... ee eee tree lines, not tested.) Operating Range Storage Temperature 0.0... 65C to +150C : . Ambient Ambient Temperature with [2] Power Applied oo... eee 56C to +125C Range Temperature Vee Supply Voltage on Vgc to Relative GND!" ...-0.5V to +7.0V Commercial O to +70C SV +05 DC Voltage Applied to Outputs in High Z Stately cece -0.5V to Veg + 0.5V Electrical Characteristics Over the Operating Range 701011-15 71011-20 701011-25 Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. |Unit Vou Qutput HIGH Voltage [Vec=Min., loy=4+.0mA | 24 24 24 Vv Voi Output LOW Voltage [Voo=Min., lo, = 8.0 mA 0.4 0.4 04 V Vin Input HIGH Voltage 22 Voc +05) 22 Voc +05] 2.2 Veco +0.5| V Vi Input LOW Voltagel] 0.5 0.8 05 0.8 0.5 08 Vv lix Input Load Current GND < Vis Vee -1 +4 -1 +1 -1 +1 HA loz Output Leakage GND < Vout Voc: 1 +1 1 +1 1 +1 LA Current Ouiput Disabled loc Voc Operating Voc = Max. 230 220 200 mA Supply Current f= fax = Vito Ispi Automatic GE Max. Voc, CE = Vin 40 40 40 mA Power-Down Current [Vijy = Viy or TTL Inputs Vin < ViLs f= fax Isp Automatic CE Max. Voc, Com] 8 8 8 mA Power-Down Current |CE = Vgo 0.3V, CMOS Inputs VIN > Vec- 0. 3V, or Vin s 0.3V, f=0 Capacitance"! Parameter Description Test Conditions Max. Unit Cn Input Capacitance Ta = 25C, f= 1 MHz, 8 pF Cour Capacitance Vac =5.0V 8 pF Notes: 1. V\_ (min.) =-2.0V for pulse durations of less than 20 ns. 2. Tyis the instant on case temperature. 3. AC Test Loads and Waveforms Ri 4812 R1 4812 Tested initially and atter any design or process changes that may atfect these parameters. ALL INPUT PULSES Vv O-o 5V 3.0V 90% OUTPUT , OUTPUT } 5 30 pF = Re 5 pF = R2 = GND oe TL [= PL Le NSmBNe = BING _ SCOPE (a) SCOPE (b) 1011.3 . 1011-4 Equivalent to: THEVENIN EQUIVALENT 1670 OUTPUT QU Oi:Z CypR ESS PRSSLIAINASY CY7C1011 Switching Characteristics!) Over the Operating Range 701011-15 71011-20 7C1011-25 Parameter Description Min. Max. Min. Max. Min. Max. Unit READ CYCLE tre Read Cycle Time 15 20 25 ns toa Address to Data Valid 15 20 25 ns toua Data Hold from Address Change 3 3 3 ns tace CE LOW to Data Valid 15 20 25 ns tpor OE LOW to Data Valid 7 8 10 ns tLz0E OE LOW to Low Z/5 0 0 0 ns tHZ0E OE HIGH to High 2/5 & 7 8 10 ns tLz0E CE LOW to Low ZI 3 3 5 ns tuzce CE HIGH to High Z/5- 61 7 8 10 ns tpy CE LOW to Power-Up 0 0 0 ns tpp CE HIGH to Power-Down 15 20 25 ns tope Byte Enable to Data Valid 7 8 10 ns tLzBe Byte Enable to Low 2 0 0 0 ns tHZBE Byte Disable to High Z 7 8 10 ns WRITE CYCLE! ! twe Write Cycle Time 15 20 25 ns tsce CE LOW to Write End 12 13 15 ns taw Address Set-Up to Write End 12 13 15 ns THA Address Hold from Write End 0 0 0 ns tsa Address Set-Up to Write Start 0 0 0 ns tpwe WE Pulse Width 12 13 15 ns tsp Data Set-Up to Write End 8 9 10 ns tub Data Hold from Write End 0 0 0 ns tizwe WE HIGH to Low ZFl 3 3 5 ns tuzwe WE LOW to High z/> 4 7 8 10 ns tow Byte Enable to End of Write 12 13 15 ns Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified lo Joy and 30-pF load capacitance. At any given temperature and voltage condition, tuze isless than t_ ger, tyzoe is less than t zoe, and ty ~ye_ is less than t, awe for any given device. tuzoe: tyzce. and ty zye_e are specified with a load capacitance of 5 pF asin part (b) of AC Test Loads. Transition is measured +500 mV trom steacly-state voltage. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input cata set-up and hold timing should be referenced to the leacling edge of the signal that terminates the write. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tyzwe and tgp. a NGsnag ay PRESS PRSSLIAINASY CY7C1011 PEP aae Data Retention Characteristics Over the Operating Range Parameter Description Conditions! Min. Max. Unit Vbr Voc for Data Retention 2.0 V locpr Data Retention Current | Com'l Voc = Vor = 2.0V, 2 mA CE = Veco 0.3V, Vin > Veco -0.3V or Vin < 0.3V toprl! Chip Deselect to Data Retention Time 0 ns tpl? Operation Recovery Time tre ns Data Retention Waveform DATA RETENTION MODE Voc 3.0V Von = 2V 3.0V tepR iho 1011-5 Switching Waveforms [11, 12] Read Cycle No. 1 nal tre | ADDRESS x a tan >| r tonn > DATA QUT PREVICUS DATA VALID KXXX DATA VALID 1011-6 Notes: 9. t,<3ns for the -12 and-15 speeds. t, < 5 ns for the -20 and slower speecis. 10. No input may exceed Ver + 0.5V. 11. Device is continuously selected. OE, CE, BHE, and/or BHE = V,. 12. WE is HIGH for read cycle.PRSSLIAINASY CY7C1011 sean att oy gry! YRREGS Lids the Switching Waveforms (continued) Read Cycle No. 2(OE Controlled) !"* '4! ADDRESS x NY ae tro > co n a tace > OE a HH << 4705 = = = bo a {706 | HH q# tpbe +@ tee Ht ee tuzce tier HZBE HIGH HIGH IMPEDANCE IMPEDANCE DATA OUT _ RESSKG DATA VALID >__ y*@ lizce 7 to / Vec 7 tru X loo SUPPLY 50% 50% Ne CURRENT 1011-7 __ 14,1 Write Cycle No. 1 (CE Controlled)!" twe ADDRESS x* * CE isa 7 a iscE 7 INXS An t AW le, > < tpwe > a ; Ny taw i<_ tsp r\ tup DATAIO 1011-8 Notes: 13. Address valid prior to or coincident with CE transition LOW. 14. Data /Ois high impedance if OE or BHE and/or BLE= V,. 15. lfCE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.Soe aie : Y et EE PE mame ae (8 EE Ce: Teer ee EET ED te Switching Waveforms (continued) PRSSLIAINASY CY7C1011 Write Cycle No.2 (BLE or BHE Controlled) twe ADDRESS 4 * EYE BLE a tsa > Os taw > Qs A taw > tag > tpwe > F IWYGGCAYGVVAYVAAAKRL QOL aa tsceE > F IXXAYSAASSADAAYQVAIAQYRL MLL tu tsp ombet trp DATAI/O Write Cycle No.3 (WE Controlled, OE LOW) ai two > ADDRESS 4 * tr sl tsce > NSS LLLLLLE a taw > < Isa << t J _ WE XXX / taw > meee NS LLL DATA I/O tHzwe 1 tsp yt = fe | LZWE 1011-10PRELIMINARY CY7C1011 Truth Table CE | OE | WE/ BLE | BHE VOg-VO; VOpu-VO46 Mode Power H X xX x Xx High 2 High 7 Power Down Standby (Isp) L L H L L Data Out Data Out Read All bits Active (lec) L L H L H Data Out High 2 Read Lower bits only Active (lec} L L H H L High # Data Out Read Upper bits only Active (lec} L x L L L | Data In Data In Write All bits Active (loc) L x L L H Data In High 7 Write Lower bits only Active (lec) L X L H L High 2 Data In Write Upper bits only Active (lec} L H H x X High 2 High Z Selected, Outputs Disabled Active (loc} Ordering Information ns) Ordering Code Package Type 5 011- ype 20 011-20 25 011- ype Document #: 38-00744 Package Diagram 44-Pin TSOP Il 244 DIMENSION IN MM CINCH? MAX PIN 1 1D. 11.938 _<0.470) | 10.262 0.404) | z 4 EJECTOR PIN oP VIEW TTOM 10.262 (0.404> am tse 0.300 atte BASE PLANE TSS 65 [ o-5* Q210 60.0083) COUN 1 L Dist eons t 183517 0.729) ____| J = = 0597 0.02359 & TEST OED EATING ~ ade CODTEeS 3 g BEA 51-85087-A g - a Cypress Semiconductor Corporation, 1998. The information contained herein is subject io change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize Its products for use as critical componenis in life-support systems where a maltunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support sysiems application implies ihat the manulacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.