CAT93C57ZD4A-1.8-GT2 - ON Semiconductor L.L.C.

CAT93C56, CAT93C57

Characteristics subject to change without notice

2-Kb Microwire Serial CMOS EEPROM

FEATURES

 High speed operation: 2MHz

 1.8V to 5.5V supply voltage range

 Selectable x8 or x16 memory organization

 Sequential read

 Software write protection

 Power-up inadvertant write protection

 Low power CMOS technology

 1,000,000 Program/erase cycles

 100 year data retention

 Industrial and Extended temperature r anges

 RoHS-compliant 8-pin PDIP, SOIC, TSSOP and

8-pad TDFN packages

PIN CONFIGURATION

PDIP (L)

SOIC (V, X)

TSSOP (Y)

TDFN (VP2, ZD4*)

CS 1 8 VCC

SK 2 7 NC

DI 3 6 ORG

DO 4

5 GND

SOIC (W*)

NC 1 8 ORG

VCC 2 7 GND

CS 3 6 DO

SK 4

5DI

* TDFN 3x3mm (ZD4) and SOIC (W) rotated pin-out packages are

available for CAT93C57 and CAT93C56, Rev. E only (not

recommended for new designs of CAT93C56)

PIN FUNCTION

Pin Name Function

CS Chip Select

SK Clock Input

DI Serial Data Input

DO Serial Data Output

VCC Power Supply

GND Ground

ORG Memory Organization

NC No Connection

DESCRIPTION

The CAT93C56/57 is a 2-Kb CMOS Serial EEPROM

device which is organized as either 128 registers of 16

bits (ORG pin at VCC) or 256 registers of 8 bits (ORG pin

at GND). Each register can be written (or read) serially

by using the DI (or DO) pin. The CAT93C56/57 features

sequential read and self-timed internal write with auto-

clear. On-chip Power-On Reset circuitry protects the

internal logic against powering up in the wrong state.

For Ordering Information details, see page 16.

FUNCTIONAL SYMBOL

ORG

CAT93C56

CAT93C57

GND

Note: When the ORG pin is connected to VCC, the x16 organization

is selected. When it is connected to ground, the x8 pin is selected. If

the ORG pin is left unconnected, then am internal pullup device will

select the x16 organization

CAT93C56, CAT93C57

Doc. No. MD-1088 Rev. Q 2 © Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

Absolute Maximum Ratings(1)

Parameters Ratings Units

Storage Temperature -65 to +150 °C

Voltage on Any Pin with Respect to Ground(2) -0.5 to +6.5 V

Reliability Characteristics(3)

Symbol Parameter Min Units

NEND(4) Endurance 1,000,000 Program/ Erase Cycles

TDR Data Retention 100 Years

D.C. OPERATING CHARACTERISTICS, CAT93C56, Die Rev. G – New Product

VCC = +1.8V to +5.5V, TA=-40°C to +125°C unless otherwise specified.

Symbol Parameter Test Conditions Min Max Units

ICC1 Power Supply Current

(Write) fSK = 1MHz, VCC = 5.0V 1 mA

ICC2 Power Supply Current

(Read) fSK = 1MHz, VCC = 5.0V 500 µA

TA = -40°C to +85°C 2

ISB1 Power Supply Current

(Standby) (x8 Mode)

VIN = GND or VCC,

CS = GND ORG = GND TA = -40°C to +125°C 4

µA

TA = -40°C to +85°C 1

ISB2 Power Supply Current

(Standby) (x16 Mode)

VIN = GND or VCC, CS =

GND ORG = Float or VCC TA = -40°C to +125°C 2

µA

TA = -40°C to +85°C 1

ILI Input Leakage Current VIN = GND to VCC TA = -40°C to +125°C 2

µA

TA = -40°C to +85°C 1

ILO Output Leakage

Current

VOUT = GND to VCC,

CS = GND TA = -40°C to +125°C 2

µA

VIL1 Input Low Voltage 4.5V ≤ VCC < 5.5V -0.1 0.8 V

VIH1 Input High Voltage 4.5V ≤ VCC < 5.5V 2 VCC + 1 V

VIL2 Input Low Voltage 1.8V ≤ VCC < 4.5V 0 VCC x 0.2 V

VIH2 Input High Voltage 1.8V ≤ VCC < 4.5V VCC x 0.7 VCC + 1 V

VOL1 Output Low Voltage 4.5V ≤ VCC < 5.5V,

IOL = 2.1mA 0.4 V

VOH1 Output High Voltage 4.5V ≤ VCC < 5.5V,

IOH = -400µA 2.4 V

VOL2 Output Low Voltage 1.8V ≤ VCC < 4.5V,

IOL = 1mA 0.2 V

VOH2 Output High Voltage 1.8V ≤ VCC < 4.5V,

IOH = -100µA VCC - 0.2 V

Notes:

(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this

specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

(2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may

undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20 ns.

(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100

and JEDEC test methods.

(4) Block Mode, VCC = 5V, 25°C

CAT93C56, CAT93C57

Characteristics subject to change without notice

D.C. OPERATING CHARACTERISTICS, CAT93C56/57, Die Rev. E – Mature Product

(CAT93C56, Rev . E – NOT RECOMMENDED FOR NEW DESIGNS)

VCC = +1.8V to +5.5V, TA=-40°C to +125°C unless otherwise specified.

Symbol Parameter Test Conditions Min Max Units

ICC1 Power Supply Current (Write) fSK = 1MHz, VCC = 5.0V 3 mA

ICC2 Power Supply Current (Read) fSK = 1MHz, VCC = 5.0V 500 µA

ISB1 Power Supply Current

(Standby) (x8 Mode)

VIN = GND or VCC, CS = GND

ORG = GND 10 µA

ISB2 Power Supply Current

(Standby) (x16 Mode)

VIN = GND or VCC, CS = GND

ORG = Float or VCC 10 µA

ILI Input Leakage Current VIN = GND to VCC 1 µA

ILO Output Leakage Current VOUT = GND to VCC, CS = GND 1 µA

VIL1 Input Low Voltage 4.5V ≤ VCC < 5.5V -0.1 0.8 V

VIH1 Input High Voltage 4.5V ≤ VCC < 5.5V 2 VCC + 1 V

VIL2 Input Low Voltage 1.8V ≤ VCC < 4.5V 0 VCC x 0.2 V

VIH2 Input High Voltage 1.8V ≤ VCC < 4.5V VCC x 0.7 VCC + 1 V

VOL1 Output Low Voltage 4.5V ≤ VCC < 5.5V, IOL = 2.1mA 0.4 V

VOH1 Output High Voltage 4.5V ≤ VCC < 5.5V, IOH = -400µA 2.4 V

VOL2 Output Low Voltage 1.8V ≤ VCC < 4.5V, IOL = 1mA 0.2 V

VOH2 Output High Voltage 1.8V ≤ VCC < 4.5V, IOH = -100µA VCC - 0.2 V

PIN CAPACITANCE

TA = 25°C, f = 1MHz, VCC = 5V

Symbol Test Conditions Min Typ Max Units

COUT

(1) Output Capacitance (DO) VOUT = 0V 5 pF

CIN

(1) Input Capacitance (CS, SK, DI, ORG) VIN = 0V 5 pF

Notes:

(1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100

and JEDEC test methods.

CAT93C56, CAT93C57

Doc. No. MD-1088 Rev. Q 4 © Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

A.C. CHARACTERISTICS(1), CAT93C56, Die Rev. G – New Product

VCC = +1.8V to +5.5V, TA = -40°C to +125°C, unless otherwise specified.

Limits

Symbol Parameter Min Max

Units

tCSS CS Setup Time 50 ns

tCSH CS Hold Time 0 ns

tDIS DI Setup Time 100 ns

tDIH DI Hold Time 100 ns

tPD1 Output Delay to 1 0.25 µs

tPD0 Output Delay to 0 0.25 µs

tHZ

(2) Output Delay to High-Z 100 ns

tEW Program/Erase Pulse Width 5 ms

tCSMIN Minimum CS Low Time 0.25 µs

tSKHI Minimum SK High Time 0.25 µs

tSKLOW Minimum SK Low Time 0.25 µs

tSV Output Delay to Status Valid 0.25 µs

SKMAX Maximum Clock Frequency DC 2000 kHz

A.C. CHARACTERISTICS (1), CAT93C56/57, Die Rev. E – Matur e Product

(CAT93C56 Rev. E - NOT RECOMMENDE D FOR NEW DESIGNS)

Limits

VCC = 1.8V - 5.5V VCC = 2.5V - 5.5V VCC = 4.5V - 5.5V

Symbol Parameter

Min Max Min Max Min Max

Units

tCSS CS Setup Time 200 100 50 ns

tCSH CS Hold Time 0 0 0 ns

tDIS DI Setup Time 400 200 100 ns

tDIH DI Hold Time 400 200 100 ns

tPD1 Output Delay to 1 1 0.5 0.25 µs

tPD0 Output Delay to 0 1 0.5 0.25 µs

tHZ

(2) Output Delay to High-Z 400 200 100 ns

tEW Program/Erase Pulse Width 10 10 10 ms

tCSMIN Minimum CS Low Time 1 0.5 0.25 µs

tSKHI Minimum SK High Time 1 0.5 0.25 µs

tSKLOW Minimum SK Low Time 1 0.5 0.25 µs

tSV Output Delay to Status Valid 1 0.5 0.25 µs

SKMAX Maximum Clock Frequency DC 250 DC 500 DC 1000 kHz

Notes:

(1) Test conditions according to “A.C. Test Conditions” table.

(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate

AEC-Q100 and JEDEC test methods.

CAT93C56, CAT93C57

Characteristics subject to change without notice

POWER-UP TIMING(1) (2)

Symbol Parameter Max Units

tPUR Power-up to Read Operation 1 ms

tPUW Power-up to Write Operation 1 ms

Notes:

(1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate

AEC-Q100 and JEDEC test methods.

(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

A.C. Test Conditions

Input Rise and Fall Times ≤ 50 ns

Input Pulse Voltages 0.4V to 2.4V 4.5V ≤ VCC ≤ 5.5V

Timing Reference Voltages 0.8V, 2.0V 4.5V ≤ VCC ≤ 5.5V

Input Pulse Voltages 0.2VCC to 0.7VCC 1.8V ≤ VCC ≤ 4.5V

Timing Reference Voltages 0.5VCC 1.8V ≤ VCC ≤ 4.5V

Output Load Current Source IOLmax/IOHmax; CL=100pF

DEVICE OPERATION

The CAT93C56/57 is a 2048-bit nonvolatile memory

intended for use with industry standard micropro-

cessors. The CAT93C56/57 can be organized as

either registers of 16 bits or 8 bits. When organized as

X16, seven 10-bit instructions for 93C57 or seven 11-

bit instructions for 93C56 control the reading, writing

and erase operations of the device. When organized

as X8, seven 11-bit instructions for 93C57 or seven

12-bit instructions for 93C56 control the reading,

writing and erase operations of the device. The

CAT93C56/57 operates on a single power supply and

will generate on chip, the high voltage required during

any write operation.

Instructions, addresses, and write data are clocked

into the DI pin on the rising edge of the clock (SK).

The DO pin is normally in a high impedance state

except when reading data from the device, or when

checking the ready/busy status after a write operation.

The serial communication protocol follows the timing

shown in Figure 1.

The ready/busy status can be determined after the start

of internal write cycle by selecting the device (CS high)

and polling the DO pin; DO low indicates that the write

operation is not completed, while DO high indicates that

the device is ready for the next instruction. If necessary,

the DO pin may be placed back into a high impedance

state during chip select by shifting a dummy “1” into the

DI pin. The DO pin will enter the high impedance state

on the rising edge of the clock (SK). Placing the DO pin

into the high impedance state is recommended in

applications where the DI pin and the DO pin are to be

tied together to form a common DI/O pin.

Figure 1. Sychronous Data Timing

tDIS tPD0,tPD1 tCSMIN

tCSS

tDIS tDIH

tSKHI tCSH

VALID VALID

DATA VALID

tSKLOW

CAT93C56, CAT93C57

Doc. No. MD-1088 Rev. Q 6 © Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

The format for all instructions sent to the device is a

logical “1” start bit, a 2-bit (or 4-bit) opcode, 7-bit

address (CAT93C57) / 8-bit address (CAT93C56) (an

additional bit when organized X8) and for write

operations a 16-bit data field (8-bit for X8 organi–

zations). The instruction format is shown in Instruction

Set table.

INSTRUCTION SET

Address Data

Instruction Device

Type Start

Bit Opcode x8 x16 x8 x16

Comments

READ 93C56(1) 1 10 A8-A0 A7-A0

93C57 1 10 A7-A0 A6-A0

Read Address

AN–A0

ERASE 93C56(1) 1 11 A8-A0 A7-A0

93C57 1 11 A7-A0 A6-A0

Clear Address

AN–A0

WRITE 93C56(1) 1 01 A8-A0 A7-A0 D7-D0 D15-D0

93C57 1 01 A7-A0 A6-A0 D7-D0 D15-D0

Write Address

AN–A0

EWEN 93C56(1) 1 00 11XXXXXXX 11XXXXXX

93C57 1 00 11XXXXXX 11XXXXX Write Enable

EWDS 93C56(1) 1 00 00XXXXXXX 00XXXXXX

93C57 1 00 00XXXXXX 00XXXXX

Write Disable

ERAL 93C56(1) 1 00 10XXXXXXX 10XXXXXX

93C57 1 00 10XXXXXX 10XXXXX

Clear All

Addresses

WRAL 93C56(1) 1 00 01XXXXXXX 01XXXXXX D7-D0 D15-D0

93C57 1 00 01XXXXXX 01XXXXX D7-D0 D15-D0

Write All

Addresses

Note:

(1) Address bit A8 for 256x8 organization and A7 for 128x16 organization are "Don't Care" bits, but must be kept at either a "1" or "0" for

READ, WRITE and ERASE commands.

CAT93C56, CAT93C57

Characteristics subject to change without notice

Read

Upon receiving a READ command and an address

(clocked into the DI pin), the DO pin of the

CAT93C56/57 will come out of the high impedance

state and, after sending an initial dummy zero bit, will

begin shifting out the data addressed (MSB first). The

output data bits will toggle on the rising edge of the

SK clock and are stable after the specified time delay

(tPD0 or tPD1).

For the CAT93C56/57, after the initial data word has

been shifted out and CS remains asserted with the SK

clock continuing to toggle, the device will auto-

matically increment to the next address and shift out

the next data word in a sequential READ mode. As

long as CS is continuously asserted and SK continues

to toggle, the device will keep incrementing to the next

address automatically until it reaches to the end of the

address space, then loops back to address 0. In the

sequential READ mode, only the initial data word is

preceeded by a dummy zero bit. All subsequent data

words will follow without a dummy zero bit. The READ

instruction timing is illustrated in Figure 2.

Erase/Write Enable and Disable

The CAT93C56/57 powers up in the write disable state.

Any writing after power-up or after an EWDS (erase/write

disable) instruction must first be preceded by the EWEN

(erase/write enable) instruction. Once the write

instruction is enabled, it will remain enabled until power

to the device is removed, or the EWDS instruction is

sent. The EWDS instruction can be used to disable all

CAT93C56/57 write and erase instructions, and will

prevent any accidental writing or clearing of the device.

Data can be read normally from the device regardless of

the write enable/disable status. The EWEN and EWDS

instructions timing is shown in Figure 3.

Figure 2. READ Instruction Timing

Figure 3. EWEN/EWDS Instruction Timing

DO HIGH-Z

11 0

ANAN–1 A0

Dummy 0 D15 . . . D0

D7 . . . D0

Address + 1

D15 . . . D0

D7 . . . D0

Address + 2

D15 . . . D0

D7 . . . D0

Address + n

D15 . . .

D7 . . .

Don't Care

PD0

STANDBY

* ENABLE = 11

DISABLE = 00

CAT93C56, CAT93C57

Doc. No. MD-1088 Rev. Q 8 © Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

Write

After receiving a WRITE command (Figure 4), address

and the data, the CS (Chip Select) pin must be

deselected for a minimum of tCSMIN. The falling edge of

CS will start the self clocking clear and data store cycle

of the memory location specified in the instruction. The

clocking of the SK pin is not necessary after the device

has entered the self clocking mode. The ready/busy

status of the CAT93C56/57 can be determined by

selecting the device and polling the DO pin. Since this

device features Auto-Clear before write, it is NOT

necessary to erase a memory location before it is

written into.

Erase

Upon receiving an ERASE command and address, the

CS (Chip Select) pin must be deasserted for a

minimum of tCSMIN (Figure 5). The falling edge of CS will

start the self clocking clear cycle of the selected

memory location. The clocking of the SaK pin is not

necessary after the device has entered the self clocking

mode. The ready/busy status of the CAT93C56/57 can

be determined by selecting the device and polling the

DO pin. Once cleared, the content of a cleared location

returns to a logical “1” state.

Figure 4. Write Instruction Timing

Figure 5. Erase Instruction Timing

tCSMIN

STANDBY

HIGH-Z

101

ANAN-1 A0DND0

BUSY

READY

STATUS

VERIFY

tSV tHZ

tEW

STANDBY

HIGH-Z

ANAN-1

BUSY READY

STATUS VERIFY

tSV tHZ

tEW

tCS

CAT93C56, CAT93C57

Characteristics subject to change without notice

Erase All

Upon receiving an ERAL command (Figure 6), the CS

(Chip Select) pin must be deselected for a minimum of

tCSMIN. The falling edge of CS will start the self clocking

clear cycle of all memory locations in the device. The

clocking of the SK pin is not necessary after the

device has entered the self clocking mode. The

ready/busy status of the CAT93C56/57 can be deter-

mined by selecting the device and polling the DO pin.

Once cleared, the contents of all memory bits return to

a logical “1” state.

Write All

Upon receiving a WRAL command and data, the CS

(Chip Select) pin must be deselected for a minimum of

tCSMIN (Figure 7). The falling edge of CS will start the

self clocking data write to all memory locations in the

device. The clocking of the SK pin is not necessary

after the device has entered the self clocking mode.

The ready/busy status of the CAT93C56/57 can be

determined by selecting the device and polling the DO

pin. It is not necessary for all memory locations to be

cleared before the WRAL command is executed.

Figure 6. ERAL Instruction Timing

Figure 7. WRAL Instruction Timing

STANDBY

tCS

HIGH-Z

10 1

BUSY READY

STATUS VERIFY

tSV tHZ

tEW

STATUS VERIFY

STANDBY

HIGH-Z

10 1

BUSY READY

tSV tHZ

tEW

tCSMIN

DND0

CAT93C56, CAT93C57

Doc. No. MD-1088 Rev. Q 10 © Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

PACKAGE OUTLINE DRAWINGS

PDIP 8-Lead 300mils (L) (1)

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC standard MS-001.

For current Tape and Reel information, download the PDF file from:

http://www.catsemi.com/documents/tapeandreel.pdf.

TOP VI EW

SIDE VI EW END VIEW

PIN # 1

IDENTIFICATION

SYMBOL MIN NOM MAX

A5.33

A1 0.38

A2 2.92 3.30 4.95

b 0.36 0.46 0.56

b2 1.14 1.52 1.78

c 0.20 0.25 0.36

D 9.02 9.27 10.16

E 7.62 7.87 8.25

e 2.54 BSC

E1 6.10 6.35 7.11

eB 7.87 10.92

L 2.92 3.30 3.80

CAT93C56, CAT93C57

Characteristics subject to change without notice

SOIC 8-Lead 150mils (V, W) (1)

Notes:

1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC standard MS-012.

For current Tape and Reel information, download the PDF file from:

http://www.catsemi.com/documents/tapeandreel.pdf.

E1 E

PIN # 1

IDENTIFICATION

TOP VIEW

SIDE VIEW END VIEW

A 1.35 1.75

A1 0.10 0.25

b 0.33 0.51

c 0.19 0.25

D 4.80 5.00

E 5.80 6.20

E1 3.80 4.00

e 1.27 BSC

h 0.25 0.50

L 0.40 1.27

θ0º 8º

SYMBOL MIN NOM MAX

CAT93C56, CAT93C57

Doc. No. MD-1088 Rev. Q 12 © Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

SOIC 8-Lead EIAJ (208mils) (X) (1)

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with EIAJ EDR-7320

For current Tape and Reel information, download the PDF file from:

http://www.catsemi.com/documents/tapeandreel.pdf.

SIDE VIEW

TOP VIEW

PIN#1 IDENTIFICATION

END VIEW

SYMBOL MIN NOM MAX

A2.03

A1 0.05 0.25

b0.36 0.48

c0.19 0.25

D5.13 5.33

E7.75 8.26

E1 5.13 5.38

e 1.27 BSC

L0.51 0.76

θ0º 8º

CAT93C56, CAT93C57

Characteristics subject to change without notice

TSSOP 8-Lead 4.4mm (Y) (1)

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-153.

For current Tape and Reel information, download the PDF file from:

http:

/www.catsemi.com/documents/tapeandreel.pdf.

E1 E

TOP VIEW

SIDE VIEW END VIEW

θ1

L1 L

SYMBOL MIN NOM MAX

A1.20

A1 0.05 0.15

A2 0.80 0.90 1.05

b0.19 0.30

c0.09 0.20

D 2.90 3.00 3.10

E 6.30 6.40 6.50

E1 4.30 4.40 4.50

e 0.65 BSC

L1.00 REF

L1 0.50 0.60 0.75

θ10° 8°

CAT93C56, CAT93C57

Characteristics subject to change without notice

TDFN 8-Pad 2 x 3mm (VP2) (1)

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC standard MO-229.

For current Tape and Reel information, download the PDF file from:

http://www.catsemi.com/documents/tapeandreel.pdf.

PIN#1

IDENTIFICATION

TOP VIEW SIDE VIEW BOTTOM VIEW

PIN#1 INDEX AREA

FRONT VIEW

SYMBOL MIN NOM MAX

A 0.70 0.75 0.80

A1 0.00 0.02 0.05

A2 0.45 0.55 0.65

A3 0.20 REF

b 0.20 0.25 0.30

D 1.90 2.00 2.10

D2 1.30 1.40 1.50

E 2.90 3.00 3.10

E2 1.20 1.30 1.40

e 050 TYP

L 0.20 0.30 0.40

CAT93C56, CAT93C57

Characteristics subject to change without notice

TDFN 8-Pad 3 x 3mm (ZD4) (1)

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC MO-229.

For current Tape and Reel information, download the PDF file from:

http://www.catsemi.com/documents/tapeandreel.pdf.

SID E VIEW BOTTOM VIEW

TOP VIEW

PIN#1 INDEX AREA

PIN#1 ID

FRONT VIEW

SYMBOL MIN NOM MAX

A 0.70 0.75 0.80

A1 0.00 0.02 0.05

A3 0.20 REF

b 0.23 0.30 0.37

D 2.90 3.00 3.10

D2 2.20 — 2.50

E 2.90 3.00 3.10

E2 1.40 — 1.80

e0.65TYP

L 0.20 0.30 0.40

CAT93C56, CAT93C57

Characteristics subject to change without notice

EXAMPLE OF ORDERING INFORMATION

CAT93C56, Die Rev. G, New Product

Notes:

(1) All packages are RoHS-compliant (Lead-free, Halogen-free).

(2) The standard lead finish is NiPdAu.

(3) The device used in the above example is a CAT93C56VI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel).

(4) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2,000 pcs/reel, i.e. CAT93C56XI-T2.

(5) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.

CAT93C56/57, Die Rev. E, Mature Product

(CAT93C56, Rev. E – Not Recommended for new Designs)

Notes:

(1) All packages are RoHS-compliant (Lead-free, Halogen-free).

(2) The standard finish is NiPdAu.

(3) The device used in the above example is a CAT93C56VI-1.8-GT3 (SOIC green package, Industrial Temperature, 1.8 Volt to 5.5 Volt

Operating Voltage, NiPdAu finish, Tape & Reel.)

(4) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWE). For additional informa-

tion, please contact your Catalyst sales office.

(5) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2,000 pcs/reel, i.e. CAT93C56XI-T2.

(6) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.

Prefix Device # Suffix

CAT 93C56 V I -1.8 -G T3 Rev E

(

Operating Voltage

Blank: VCC = 2.5V to 5.5V

1.8: VCC = 1.8V to 5.5V

Company ID

Product Numbe

93C56

93C57

Temperature Range

I = Industrial (-40ºC to 85ºC)

A = Automotive (-40ºC to 105ºC)

E = Extended

(

-40ºC to 125ºC

)

Lead Finish

Blank: Matte-Tin

G: NiPdAu

Die Revision

93C56: E

93C57: E

Package

L: PDIP

V: SOIC, JEDEC

W: SOIC, JEDEC

X: SOIC, EIAJ(5)

Y: TSSOP

ZD4: TDFN (3x3mm)

Tape & Reel

T: Tape & Reel

2: 2,000 units/Reel(5)

3: 3

000 units/Reel

Prefix Device # Suffix

CAT 93C56 V I -G T3

Company ID

Product Numbe

93C56

Temperature Range

I = Industrial (-40ºC to +85ºC)

E = Extended (-40ºC to +125ºC)

Lead Finish

Blank: Matte-Tin

G: NiPdAu

Package

L: PDIP

V: SOIC, JEDEC

X: SOIC, EIAJ(4)

Y: TSSOP

VP2: TDFN (2x3mm) Tape & Reel

T: Tape & Reel

2: 2,000 units/Reel(4)

3: 3

000 units/Reel

CAT93C56, CAT93C57

Characteristics subject to change without notice

REVISION HISTORY

Date Rev. Comments

05/14/04 L New Data Sheet Created From CAT93C46/56/57/66/86. Parts CAT93C56, CAT93C56,

CAT93C57, CAT93C56/57, CAT93C76 and CAT93C86 have been separated into

single data sheets

10/13/06 M

Updated Instruction Set

03/18/05 N

Updated Description

10/13/06 O Update Features

Update Pin Configuration

Update Functional Symbol

Update Pin Functions

Update D.C. Operating Characteristics (VCC Range)

Update A.C. Characteristics (VCC Range)

Update Ordering Information

08/21/07 P

Updated Features/Description

Remove "Die Rev E" from the title

Update Pin Configuration / Packages

Update Absolute Maximum Rating

Update Reliability Characteristics

Update D.C. Operating Characteristics

Added D.C. / A.C. Characteristics for CAT93C56 Die Rev G

Rearrange / Format Text and Figures

Update Package Outline Drawings

Added Example of Ordering Information for CAT93C56 Die Rev. G

Add MD- to document number

04/10/08 Q

Add Extended Temperature Range

Update Package Outline Drawings

Copyrights, Trademarks and Pat ents

Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:

Adaptive Analog™, Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™, Quad-Mode™ and Quantum Charge Programmable™

I2C™ is a trademark of Philips Corporation. Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.

Catalyst Semiconductor has been issued U. S. and foreign patents and has patent applications pending that protect its products.

CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS

PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE

RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING

OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.

Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other

applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where

personal injury or death may occur.

Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled

"Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.

Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical

semiconductor applications and may not be complete.

Catalyst Semiconductor, Inc.

Corporate Headquarters

2975 Stender Way

Santa Clara, CA 95054

Phone: 408.542.1000 Document No: MD-1088

Fax: 408.542.1200 Revision: Q