TECHNICAL DATA
43
Triple 3-Input NAND Gate
High-Perform ance Silicon-Gate C MOS
The IN74HC10 is id entical in pinout to the LS/ALS10. T he device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
IN74HC10
ORDERING INFORMATION
IN74HC10N Plastic
IN74HC10D SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 14 =VCC
PIN 7 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Output
ABC Y
LXX H
XLX H
XXL H
HHH L
X = don’t care
IN74HC10
44
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±20 mA
IOUT DC Output Current, per Pin ±25 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PDPower Dissipation in Still Air, Plastic DIP+
SOIC Package+ 750
500 mW
Tstg Storage Temperature -65 to +150 °C
TLLead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TAOperating Temperature, All Package Types -55 +125 °C
tr, tfInput Rise and Fall Time (Figure 1) VCC =4.5 V
VCC =2.0 V
VCC =6.0 V
0
0
0
1000
500
400
ns
Thi s device conta ins protection circuitry to guard a gainst damage due to high static voltage s or electri c
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For prop e r o peration, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an approp riate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
IN74HC10
45
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C
to
-55°C
≤85
°C≤125
°CUnit
VIH Minimum High-Level
Input Voltage VOUT=0.1 V or VCC-0.1 V
IOUT≤ 20 µA2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL Max imum Low -
Level Input Voltage VOUT=0.1 V or VCC-0.1 V
IOUT ≤ 20 µA2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH Minimum High-Level
Output Voltage VIN=VIH or VIL
IOUT ≤ 20 µA2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN=VIH or VIL
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA 4.5
6.0 3.98
5.48 3.84
5.34 3.7
5.2
VOL Max imum Low-Level
Output Voltage VIN=VIH
IOUT ≤ 20 µA2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN=VIH
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA 4.5
6.0 0.26
0.26 0.33
0.33 0.4
0.4
IIN Maximum Inpu t
Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
ICC Maximum Quiesc ent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA6.0 2.0 20 40 µA
IN74HC10
46
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC Guaranteed Limit
Symbol Parameter V 25 °C
to
-55°C
≤85°C≤125°CUnit
tPLH, tPHL Maximum Propagation Delay, Input A,B or C to
Output Y (Figures 1 and 2) 2.0
4.5
6.0
95
19
16
120
24
20
145
29
25
ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 2) 2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
CIN Maximum Input Capacitance - 10 10 10 pF
Power Dissipation Capacitance (Per Gate) Typical @25°C,VCC=5.0 V
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
25 pF
Figure 1. Switching Waveforms Figure 2. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/3 of the Device)
