Integrated
Circuit
Systems, Inc.
General Description Features
ICS9148-37
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
Block Diagram
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
9148-37 Rev F 4/25/99
Pin Configuration
Generates the following system clocks:
- 4 CPU(2.5V/3.3V) upto 100MHz.
- 6 PCI(3.3V) @ 33.3MHz
- 2AGP(3.3V) @ 2 x PCI
- 12 SDRAMs(3.3V) @ either CPU or AGP
- 2 REF (3.3V) @ 14.318MHz
Skew characteristics:
- CPU CPU<250ps
- SDRAM SDRAM < 250ps
- CPU SDRAM < 250ps
- CPUAGP: < 1ns
- CPU(early) PCI : 1-4ns
Supports Spread Spectrum modulation +0.25, ±0.6%
Serial I2C interface for Power Management, Frequency
Select, Spread Spectrum.
Efficient Power management scheme through PCI and CPU
STOP CLOCKS.
Uses external 14.318MHz crystal
48 pin 300mil SSOP.
48-Pin SSOP
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24 MHz, 48MHz
VDD4 = AGP (0:1)
VDDL = CPUCLK (0:3)
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
The ICS9148-37 is the single chip clock solution for Desktop/
Notebook designs using the VIA MVP3 style chipset. It
provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9148-37
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection. The SD_SEL
latched input allows the SDRAM frequency to follow the
CPUCLK frequency(SD_SEL=1) or the AGP clock
frequency(SD_SEL=0)
2
ICS9148-37
Pin Descriptions
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
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3
ICS9148-37
Functionality
VDD1, 2, 3, 4 = 3.3V±5%, VDDL = 2.5V ±5% or 3.3 ±5%, TA= 0 to 70°C
Crystal (X1, X2) = 14.31818MHz
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1DDVV5.2
0DDVV3.3
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
Power Management Functionality
Mode Pin - Power Management Input Control
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11 gninnuRgninnuRgninnuRgninnuRgninnuR
10 gninnuRwoLdeppotSgninnuRgninnuRgninnuR
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1=LES_DS0=LES_DS
111 0010016.663.336.66
110 52.5952.595.3657.135.36
101 3.383.386.663.336.66
100 5757060306
011 5757575.7357
010 5.865.865.8652.435.86
001 8.668.668.664.338.66
000 0606060306
4
ICS9148-37
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controler (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3(H) AC
K
Byte Count
ACK Byte
0
ACK Byte 1
ACK Byte
2
ACK Byte
3
ACK Byte 4
ACK Byte
5
ACK
Stop Bit
How to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2(H) AC
K
Dummy Command Code AC
K
Dummy Byte Count AC
K
Byte 0 AC
K
Byte 1 AC
K
Byte 2 ACK
Byte 3 AC
K
Byte 4 AC
K
Byte 5 AC
K
Stop Bit
How to Write:
5
ICS9148-37
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB041 )tcanI/tcA(3KLCUPC
2tiB141 )tcanI/tcA(2KLCUPC
1tiB341 )tcanI/tcA(1KLCUPC
0tiB441 )tcanI/tcA(0KLCUPC
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB71 )tcanI/tcA(F_KLCICP
5tiB511 )tcanI/tcA(0PGA
4tiB311 )tcanI/tcA(4KLCICP
3tiB211 )tcanI/tcA(3KLCICP
2tiB111 )tcanI/tcA(2KLCICP
1tiB011 )tcanI/tcA(1KLCICP
0tiB81 )tcanI/tcA(0KLCICP
Byte0: Functionality and Frequency Select Register
(default = 0)
Serial Configuration Command Bitmap
tiBnoitpircseDDWP
7tiB noitaludoMmurtcepSdaerpS%52.0±-0 noitaludoMmurtcepSdaerpS%6.0±-1 0
tiB4:6
5tiB6tiB 4tiB 111 011 101 001 110 010 100 000
kcolCUPC
001 52.59 3.38 5757 5.86 8.66 06
ICP
3.33 57.13 3.33 03 5.73 52.43 4.33 03
PGA
6.66 5.36 6.66 0657 5.86 8.66 06
etoN1
3tiB ,tceleserawdrahybdetcelessiycneuqerF-0 stupnIdehctaL )evoba(4:6tiBybdetcelessiycneuqerF-1 0
.epytdaerpsretnecmurtcepSdaerpS-0 .epytdaerpsnwodmurtcepSdaerpS-1 0
1tiB lamroN-0 delbanEmurtcepSdaerpS-1 0
0tiB gninnuR-0 stuptuollaetatsirT-1 0
6
ICS9148-37
Byte 3: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
tiB#niPDWPnoitpircseD
7tiB821 )tcanI/tcA(7MARDS
6tiB921 )tcanI/tcA(6MARDS
5tiB131 )tcanI/tcA(5MARDS
4tiB231 )tcanI/tcA(4MARDS
3tiB431 )tcanI/tcA(3MARDS
2tiB531 )tcanI/tcA(2MARDS
1tiB731 )tcanI/tcA(1MARDS
0tiB831 )tcanI/tcA(0MARDS
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB711 )tcanI/tcA(11MARDS )ylnOedoMpotkseD(
2tiB811 )tcanI/tcA(01MARDS )ylnOedoMpotkseD(
1tiB021 )tcanI/tcA(9MARDS
0tiB121 )tcanI/tcA(8MARDS
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB741 )tcanI/tcA(1PGA
3tiB-1 )devreseR(
2tiB-1 )devreseR(
1tiB641 )tcanI/tcA(1FER
0tiB21 )tcanI/tcA(0FER
7
ICS9148-37
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9148-37. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9148-37.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
8
ICS9148-37
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-37. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9148-37 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
9
ICS9148-37
Pins 2, 7, 8, 25, 26 and 46 on the ICS9148-37 serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 4-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the devices
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be used.
Shared Pin Operation -
Input/Output Pins
Fig. 1
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
10
ICS9148-37
Fig. 2a
Fig. 2b
11
ICS9148-37
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Elect ric al Charact erist ics - Input/ Supply/Comm on O utput Par am eters
TA = 0 - 70C; Suppl y Volta ge VDD = 3.3 V +/-5%, VDDL = 2. 5 V + /-5% (unless othe rwis e s ta t ed )
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating IDD2.5OP CL = 0 pF; 66.8 MHz 10 20 mA
Supply Cu rrent TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads -500 200 500 ps
TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads 12.74 ns
1Guarant eed by d e sign, not 100% teste d i n product ion .
Skew1
Elect ric al Charact erist ics - Input/ Supply/Comm on O utput Par am eters
TA = 0 - 70C ; Suppl y Volta ge VDD = VDDL = 3.3 V +/-5% (unless otherwise stat e d)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Volta ge VIH 2V
DD+0.3 V
Input Low Volt a ge VIL VSS-0.3 0.8 V
Input High C urre nt IIH VIN = VDD 0.15mA
Input Low Current IIL1 VIN = 0 V; Inputs with no pul l-up resistors -5 2.0 mA
Input Low Current IIL2 VIN = 0 V; Inputs with pul l -up resis t ors -200 -100 mA
Operating IDD3.3OP CL = 0 pF; 66.8 MHz 100 160 m A
Supply Cu rrent
Input frequenc y F iVDD = 3.3 V; 14.318 MHz
Input Ca pa c it a nce 1CIN Logic Inputs 5 pF
CINX X1 & X2 pins 27 36 45 pF
Tr ansition Time1Ttrans To 1st cros sing of ta rget Fre q. 2 ms
Settling Time1TsFrom 1 st c ros sing to 1% target Freq. ms
Clk S ta biliz ation1TSTAB From VDD = 3.3 V to 1% ta rget Fr e q. 2 ms
TCPU-SDRAM1 VT = 1.5 V; SDRAM Leads -500 200 500 ps
TCPU-PCI1 VT = 1.5 V; CPU Leads 1 2.8 4 ns
TCPU-AGP VT = 1.5 V; CPU Leads -1 0 1 ns
1Guarant eed by d e sign, not 100% teste d in product ion .
Skew1
12
ICS9148-37
Electrical C haracter isti cs - CP U
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unle ss otherwise stat e d )
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage VOH2A IOH = -28 mA 2.5 2.6 V
Output Low Voltage VOL2A IOL = 27 mA 0. 35 0. 4 V
Outpu t High C urrent IOH2A VOH = 2. 0 V -29 -23 mA
Output Low Current IOL2A VOL = 0.8 V 33 37 mA
Rise T im e tr2A1VOL = 0.4 V, VOH = 2.4 V 1.75 2 ns
Fall Time tf2A1VOH = 2.4 V, VOL = 0.4 V 1.1 2 ns
Duty Cycle dt2A1VT = 1.5 V 45 50 55 %
Skew tsk2A1VT = 1.5 V 50 250 ps
Jitter, One S igma tj1s2A1VT = 1. 5 V 65 150 ps
J itte r, Abs olute tjabs2A1VT = 1.5 V -250 165 250 ps
1Guarant eed by de sign, not 100% teste d i n product io n.
Electr ical Charact eri stic s - C PU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF ( unl e ss ot he rw i se stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Volta ge VOH2B IOH = -8 mA 2 2.2 V
Output Low Voltage VOL2B IOL = 12 mA 0. 3 0.4 V
Output High Current IOH2B VOH = 1.7 V -20 -16 mA
Output L ow Curr ent IOL 2B VOL = 0.7 V 19 26 mA
Rise Tim e tr2B1VOL = 0.4 V, VOH = 2.0 V 1.5 1.8 ns
Fall T ime tf2B1VOH = 2.0 V, VOL = 0.4 V 1.6 1.8 ns
Duty Cycle dt2B1VT = 1.25 V 404755%
Skew tsk2B1VT = 1.25 V 60 250 ps
J itter, Single Edge
Displacement2tjsed2B1VT = 1. 2 5 V 200 250 ps
J itter, One S igma tj1s2B1VT = 1. 25 V 65 150 ps
J itte r, Absolute tjabs2B1VT = 1. 2 5 V -300 160 300 ps
1 Guaran te ed by design, not 100% tested in p roduc tion.
2 E dge displace ment of a pe riod relative to a 10- c loc k-cycle rolling average pe riod.
13
ICS9148-37
Electri c al Character isti cs - PC I
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stat e d)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Volta ge VOH1 IOH = -28 mA 2.4 3 V
Output Low Voltage VOL1 IOL = 23 mA 0.2 0.4 V
Outp ut High C urrent IOH1 VOH = 2.0 V -60 -40 mA
Output Low Current IOL1 VOL = 0. 8 V 41 50 m A
Rise T im e tr11VOL = 0.4 V, V OH = 2.4 V 1.8 2 ns
Fall Time tf11VOH = 2.4 V, VOL = 0.4 V 1.6 2 ns
Duty Cycle dt11VT = 1.5 V 45 51 55 %
Skew tsk11VT = 1.5 V 130 250 ps
J itter, One Sigma1tj1s1a VT = 1.5 V, synchronous 40 150 ps
tj1s1b VT = 1. 5 V, asynch ronous 200 250 ps
J itter, Absolute1tabs1a VT = 1.5 V, synchronous -250 135 250 ps
tjabs1b VT = 1.5 V, async h ronous -650 500 650 ps
1Guarant eed by de sign, not 100% teste d in product io n.
Electrical Ch aracteri sti cs - SDR A M
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Volt a ge VOH1 IOH = -28 mA 2.4 3 V
Output Low Voltage VOL1 IOL = 23 mA 0.2 0.4 V
Output High C urr ent IOH1 VOH = 2.0 V -60 -40 mA
Output Low Current IOL1 VOL = 0. 8 V 41 50 mA
Rise T ime1Tr1 VOL = 0.4 V , VOH = 2.4 V 1. 75 2 ns
F all T im e 1Tf1 VOH = 2.4 V, VOL = 0.4 V 1.5 2 ns
Duty Cycle1Dt1 VT = 1.5 V 45 50 55 %
Skew1Tsk1 VT = 1.5 V 200 500 ps
Jitter, One Sigma 1Tj1s1 VT = 1.5 V 50 150 ps
J itte r, Abs olute1Tjabs1 VT = 1.5 V (with sync hronous PCI) -250 +250 ps
J itte r, Abs olute1Tjabs1 VT = 1.5 V (with as ync hronous P C I) -400 400 ps
1Guarant eed by d e sign, not 100% teste d in product ion .
14
ICS9148-37
Electrical C haracter ist ics - A G P
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unle ss o t herwise stat ed)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage VOH1 IOH = -28 mA 2.4 3 V
Out put Low Volt a ge VOL1 IOL = 23 mA 0.2 0.4 V
Output High Curr ent IOH1 VOH = 2.0 V -60 -40 mA
Output Low Current IOL1 VOL = 0.8 V 41 50 mA
Ris e T ime tr11VOL = 0.4 V, VOH = 2.4 V 1.1 2 ns
Fall Time tf11VOH = 2.4 V, VOL = 0.4 V 1 2 ns
Duty Cycle dt11VT = 1.4 V 45 49 55 %
Skew tsk11VT = 1.5 V 130 250 ps
Jitte r, One S igm a 1tj1s1 VT = 1.5 V 2 3 %
Jitter, Abs olute1tabs1a VT = 1.5 V , s ync hronous - 5 2.5 5 %
tjabs1b VT = 1. 5 V, a s yn chronous -6 4.5 6 %
1Gua ranteed by de sign, not 100% teste d i n produc ti on.
Electri c al Characterist ics - 24MHz , 48M H z, REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unles s ot he rwis e stat e d )
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltag e VOH5 IOH = - 16 mA 2.4 2.6 V
Output Low Voltage VOL5 IOL = 9 mA 0.3 0.4 V
Outp ut High C urrent IOH5 VOH = 2.0 V -32 -22 mA
Output Low Current IOL5 VOL = 0.8 V 16 25 mA
Rise T im e tr51VOL = 0.4 V, VOH = 2.4 V 2 4 ns
Fall Time tf51VOH = 2.4 V, VOL = 0.4 V 1.9 4 ns
Duty Cycle dt51VT = 1.5 V 455457%
J itter, One S igm a tj1s51VT = 1.5 V 1 3 %
Jitter, Abs olute tjabs51VT = 1.5 V -5 - 5 %
1Guarant eed by d e sign, not 100% teste d i n product i on.
15
ICS9148-37
General Layout Precautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
2) Make all power traces and vias as
wide as possible to lower
inductance.
Notes:
1) All clock outputs should have series
terminating resistor. Not shown in
all places to improve readibility of
diagram.
2) 47 ohm / 56pf RC termination should
be used on all over 50MHz outputs.
3) Optional crystal load capacitors are
recommended.
Connections to VDD:
16
ICS9148-37
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
Ordering Information
ICS9148yF-37-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - PPP - T