1K/4K/16K x36 x2 Bidirectional
Synchronous FIFO
CY7C43642
CY7C43662
CY7C43682
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06019 Rev. *B Revised December 26, 2002
Features
• High-speed, low-power, bidirectional, First-In, First-Out
(FIFO) memories
• 1Kx36x2 (CY 7C43642)
• 4Kx36x2 (CY 7C43662)
• 16Kx36x2 (CY7C43682)
• 0.35-micron CMOS for optimum speed/power
• High speed 133-MHz operation (7.5-ns read/write cycle
times)
• Low power
—ICC= 100 mA
—ISB= 10 mA
• Fully asynchronous and simultaneous read and write
operation pe rmi tted
• Mailbox bypass register for each FIFO
• P arallel Prog rammable Almost F ull and Almost Emp ty
flags
• Retransmit function
• Standard or FWFT mode user selectable
• 120-pin TQFP packaging
• Easily expandable in width and depth
Logic Block Diagram
Port A
Control
Logic Port B
Control
Logic
Mail1
Register
Input
Register
Write
Pointer Read
Pointer
Status
Flag Logic
Programmable
Flag Offset Timing
Mode
Status
Flag Logic
Write
Pointer Read
Pointer
1K/4K/16K
Dual Ported
Memory
256/512/1K
4K/16K x36
Dual Ported
Memory
Mail2
Register
Output
Register
Input
Register
FIFO1,
Mail1
Reset
Logic
FIFO2,
Mail2
Reset
Logic
CLKA
CSA
W/RA
ENA
MBA
RT2
RST1
FFA/IRA
AFA
FS0
FS1
A0–35
EFA/ORA
AEA
MBF2
RST2
FFB/IRB
AFB
FWFT/STAN
B0–35
CLKB
CSB
W/RB
ENB
MBB
RT1
EFB/ORB
AEB
MBF1
Output
Register
Registers
x36
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 2 of 30
CY7C43642
CY7C43662
CY7C43682
TQFP
Top View
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
MBF2
GND
FS0
RST1
MBA
AEA
AFA
VCC
EFA/ORA
FFA/IRA
CSA
W/RA
ENA
CLKA
GND
W/RB
VCC
CLKB
ENB
CSB
GND
FFB/IRB
EFB/ORB
AFB
AEB
VCC
MBF1
MBB
RST2
FS1
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B26
GND
B24
B25
RT1
B27
B28
B29
B30
B31
GND
B32
B33
B34
B35
B14
GND
B12
B13
B15
VCC
B16
B17
GND
B18
B19
B20
B21
B22
B23
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
A3
A0
A1
A2
VCC
A4
A5
GND
A6
A7
A8
A9
A10
A11
GND
B8
B11
B10
B9
B7
VCC
B6
GND
B5
B4
B3
B2
B1
B0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A27
A23
A24
A25
A26
A28
GND
A30
A31
VCC
A32
A33
A34
A35
A14
A12
RT2
A13
A15
A16
A17
GND
A18
A19
A20
A21
VCC
A22
FWFT/STAN
A29
Pin Configuration
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 3 of 30
Functional Description
The CY7C436X2 is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous (clocked) FIFO memory
whic h supports clock frequ encies up to 133 MHz an d has read
access times as fast as 6 ns. Two independent 1K/4K/16K x
36 dual-port SRAM FIFOs on board each chip buffer data in
opposite directions.
The CY7C436X2 is a synchronous (clocked) FIFO, meaning
each po rt em plo ys a sy nc hro nou s i nterface. All data tran sfe rs
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or
coinc ide nt. T he e nab les for e ac h po rt are a rran ged to pro vi de
a simple bidirectional interface between microprocessors
and/or buses with synchronous control.
Comm unicati on between ea ch port may bypas s the FIFO s via
two mailbox registers. The mailbox registers’ width matches
the sele cted Port B bus width. Each mailbox register has a flag
(MBF1 and MBF2) to signal when new mail has been stored.
Maste r Reset initializes the read and write point ers to the first
location of the memory array, and selects parallel flag
programming, or one of the three possible default flag offset
settings, 8, 16, or 64. Each FIFO has its own independent
Master Reset pi n, RST1 and RST 2.
The CY7C436X2 have two modes of operation: In the CY
Standard Mode, the first word written to an empty FIFO is
deposited into the memory array. A read operation is required
to access that word (along with all other words residing in
memory). In the First-Word Fall-Through Mode (FWFT), the
first word (36-bit wide) written to an empty FIFO appears
automatically on the outputs, no read operation required
(neverth ele ss, a ccessin g sub seque nt words d oe s necess it ate
a formal read request). The state of the FWFT/STAN pin
during FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag
(EFA/ORA and EFB/ORB) and a combined Full/Input Ready
Flag (FFA/IRA and FFB/IRB). The EF and FF functions are
selected in the CY Standard Mode. EF indicates whether the
memory is full o r no t. The IR a nd OR fu nctio ns are s elec ted in
the First-W ord Fall-Through Mode. IR indicates whether or not
the FIFO has ava ila ble m em ory l oc atio ns . O R sho w s whether
the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.[1]
Each FIF O has a pro gra mm ab le Alm ost Em pty fl ag (AEA and
AEB) and a programmable Almost Full flag (AFA and AFB).
AEA and AEB indicate when a selected number of words
written to FIFO memory achieve a predetermined “almost
empty state.” AFA and AFB indicate when a selected number
of words written to the memory achieve a predetermined
“almost full state. ”[2]
IRA, IRB, AF A, and AFB are synchronized to the port clock that
writes data into its array. ORA, ORB, AEA, and AEB are
synchronized to the port clock that reads data from its array.
Programmab le of fset for AEA , AEB, AF A, and AFB are loaded
in parallel using Port A. Three default offset settings are also
provided. The AEA an d A EB threshold can be set at 8, 16, or
64 locations from the empty boundary and AFA and AFB
threshold can be set at 8, 16, or 64 locations from the full
bounda ry. All the se ch oic es are ma de us ing the FS0 a nd FS1
inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths.
The CY7C436X2 are characterized for operation from 0°C to
70°C commercial, and from –40°C to 85°C industrial. Input
ESD protection is greater than 2001V, and latch-up is
prevented by the use of guard rings.
Selection Guide
CY7C43642/62/82
-7 CY7C43642/62/82
-10 CY7C43642/62/82
-15
Maximum Frequency (MHz) 133 100 66.7
Maximum Acce ss Time (ns) 6 8 10
Minimum Cycle Time (ns) 7.5 10 15
Minimum Data or Enable Set-up (ns) 3 4 5
Minimum Data or Enable Hold (ns) 0 0 0
Maximum Flag Delay (ns) 6 8 8
Active Power Supply
Current (ICC1) (mA) Commercial 100 100 100
Industrial 100
CY7C43642 CY7C43662 CY7C43682
Density 1K x 36 4K x 36 16K x 36
Package 120 TQFP 120 TQFP 120 TQFP
Notes:
1. When reading from the FIFO under FWFT, ORA/ORB signal should be included in the read logic to ensure proper operation. To read without gating the
boundary fl ag (e. g., in bursts), use CY standard mode.
2. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to 3 clock cycles for flag assertion and deassertion. Refer to
“Designing with CY7C436xx Synchronous FIFO” application notes for more details on flag uncertainties.
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 4 of 30
Pin Definitions
Signal Name Description I/O Function
A0–35 Port A Data I/O 36-bit bidirectional data port for side A.
AEA Port A Almost
Empty Flag OProgrammable Almost Empty flag synchronized to CLKA. It is LOW when the number
of words i n F IFO2 is less than or equ al to the va lue i n the Almos t Empty A of fse t regi ster,
X2.[2]
AEB Port B Almost
Empty Flag OProgrammable Almost Empty flag synchronized to CLKB. It is LOW when the number
of words i n F IFO1 is less than or equ al to the va lue i n the Almos t Empty B of fse t regi ster,
X1.[2]
AFA Port A Almost
Full Flag OProgrammable Almost Full flag synchronized to CLKA. It is LOW when the number
of empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset
register, Y1.[2]
AFB Port B Almost
Full Flag OProgrammable Almost Full flag synchronized to CLKB. It is LOW when the number
of empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset
register, Y2.[2]
B0–35 Port B Data I/O 36-bit bidirectional data port for side B.
FWFT/STAN Big
Endian/First-Wor
d Fall-Through
Select
IDuring Master Reset. A HIGH on FWFT selects CY Standard mode, a LOW selects
First-Word Fall-Through mode. Once the timing mode has been selected, the level on
FWFT/STAN must be static throughout device operation.
CLKA Port A Clock ICLKA is a continuous clock that synchronizes all dat a transfers through Port A and
can be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are al l
synchronized to the LOW-to-HIGH transition of CLKA.
CLKB Port B Clock ICLKB is a continuous clock that synchronizes all dat a transfers through Port B and
can be asy nc hro nou s or c oi ncide nt to CL KA. FFB /IRB, EFB/ORB, AFB, and AEB are all
synchronized to the LOW-to-HIGH transition of CLKB.
CSA Port A Chip
Select ICSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on
Port A. The A0–35 outputs are in the high-impedance state when CSA is HIGH.
CSB Port B Chip
Select ICSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on
Port B. The B0–35 outputs are in the high-impedance state when CSB is HIGH.
EFA/ORA Port A Empty/
Out put Ready
Flag
OThis is a dua l-function pin. In the CY St andard Mode, the EF A func tion is select ed. EF A
indicates whether or not the FIFO2 memory is empty . In the FWFT mode, the ORA function
is selected. ORA indicates the presence of valid data on A0–35 outputs, available for
reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA.[1]
EFB/ORB Port B Empty/
Out put Ready
Flag
OThis is a dual-function pin. In the CY S tandard Mode, the EFB f unction is s elected. EF B
indicates whether or not the FIFO1 memory is empty . In the FWFT mode, the ORB function
is selected. ORB indicates the presence of valid data on B0–35 outputs, available for
reading. EFB / ORB is sy nc hron iz ed to the LOW-to-HIG H transi tion of CLKB.[1]
ENA Port A Enable IENA must be HIG H to enable a LOW -to-HIGH transitio n of CLKA to read or write dat a
on Port A.
ENB Port B Enable IENB must be HIG H to enable a LOW -to-HIGH transitio n of CLKB to read or write dat a
on Port B.
FFA/IRA Port A Full/Input
Ready Flag OThis is a dual-functi on pin. In the CY St andard Mode , the FFA function is sele cted. FFA
indicates wh ether or n ot the FI FO1 memory i s full. In the FW FT mode, the IRA function is
selected. IRA indicates whether or not there is space available for writing to the FIFO1
memo ry. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.
FFB/IRB Port B Full/Input
Ready Flag OThis is a dua l-function pin. In the CY S t andard Mo de, the FFB func tion is sel ected. FFB
indicates wh ether or n ot the FI FO2 memory i s full. In the FW FT mode, the IRB function is
selected. IRB indicates whether or not there is space available for writing to the FIFO2
memor y. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB.
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 5 of 30
Signal Description
Reset (RST1, RST2)
Each of the two FIFO memories of the CY7C436X2 undergoes
a complete reset by taking its associated Master Reset (RST1,
RST2) input LOW for at least four Port A clock (CLKA) and four
Port B clock (CLKB) LOW-to-HIGH transitions. The Master
Reset inputs can switch asynchronously to the clocks. A
Master Reset initializes the internal read and write pointers
and forces the Full/Input Ready flag (FF A/IRA, FFB/IRB) LOW,
the Empty/Output Ready flag (EF A/ORA, EFB/ORB) LOW , the
Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag
(AFA, AFB) HIGH. A Master Reset also forces the Mailbox flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a
Master Reset, the FIFO’s Full/Input Ready flag is set HIGH
after two clock cycles to begin normal operation. A Master
FS1 Fl ag Offs et
Select 1 IThe LOW-to -HIGH transition of a FIFO’s reset input latches the values of FS0 and
FS1. If e ither FS0 or FS1 is H IGH when a res et inp ut goes H IGH, o ne of the thre e pres et
values (8, 16, or 64) is selected as the offset for the FIFO’s Almost Full and Almo st Empty
flags. If b oth FIFOs are reset simultaneously and bot h FS0 and FS1 are LOW when RST1
and RST2 go HIGH, the first four writes to FIFO1 Almost Empty offsets for both FIFOs.
FS0 Fl ag Offs et
Select 0 I
MBA Port A Mailbox
Select IA HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
When a read operation is performed on Port A, a HIGH level on MBA selects data from
the Mail2 register for output and a LOW level selects FIFO2 output register data for output.
When a write operation is performed on Port A, a HIGH level on MBA will write the data
into Mail1 register while a LOW level will write the data into FIFO1.
MBB Port B Mailbox
Select IA HIGH level on MBB chooses a mailbox register for a Port B read or write operation.
When a read operation is performed on Port B, a HIGH level on MBB selects data from
the Mail1 register for output and a LOW level selects FIFO1 output register data for output.
When a write operation is performed on Port B, a HIGH level on MBB will write the data
into Mail2 register while a LOW level will write the data into FIFO2.
MBF1 Mail1 Register
Flag OMBF1 is set LOW by a LOW-to-HIGH transition of CLKA t hat writes dat a to the Ma il1
register. Write s to the Ma il1 reg ister ar e inhib ited whi le M BF1 is LOW. MBF1 is set HI GH
by a LOW -to-H IGH tran sitio n of CLKB when a Port B read i s selecte d and M BB is HIGH .
MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2 Mail2 Register
Flag OMBF2 is set LOW by a LOW-to-HIGH transition of CLKB t hat writes dat a to the Ma il2
register. Write s to the Ma il2 reg ister ar e inhib ited whi le M BF2 is LOW. MBF2 is set HI GH
by a LOW -to-H IGH tran sitio n of CLKA when a Port A read i s selecte d and M BA is HIGH .
MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
RT1 Retransmit
FIFO1 IA LOW strobe on this pin will retransmit the data on FIFO1. This is achieved by
bringing the read pointer back to location zero. The user will still need to perform read
operations to retransmi t the dat a . R etran sm it func tio n app li es to CY s t an dard mode on ly.
RT2 Retransmit
FIFO2 IA LOW st robe o n thi s pin w ill re transm it da ta on FI FO 2. This is ac hi ev ed by brin gin g
the read p oin ter back to location ze ro. The user will s til l n eed to pe rform re ad operations
to retransmit the data. Retransmit function applies to CY standard mode only.
W/RA Port A Write/
Read Select IA HIGH s ele cts a wr it e ope r ation and a LO W se lec ts a re ad o per at ion on Por t A for
a LOW -to-HIG H tra nsi tio n of CLKA. Th e A0–35 out puts are in the HIGH im pedance state
when W/RA is HIGH.
W/RB Port B Write/
Read Select IA LOW sel ects a write operation a nd a H IG H se lec ts a read o per at ion on Port B for
a LOW -to-HIG H tra nsi tio n of CLKB. Th e B0–35 out puts are in the HIGH im pedance state
when W/RB is LOW.
RST1 FIFO1 Maste r
Reset IA LOW on this pin initializ es the FIFO1 read and write po inters to the first l ocation of
memory and sets the Port B outp ut reg is ter to al l ze roes . A LOW pul se on RST1 selects
the programming method (serial or parallel) and one of three programmable flag default
offsets. It also configures Port A for bus size and endian arrangement. Four LOW -to-HIGH
transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST1
is LOW.
RST2 FIFO2 Maste r
Reset IA LOW on this pin initializ es the FIFO2 read and write po inters to the first l ocation of
memory and sets the Port B outp ut reg is ter to al l ze roes . A LOW pul se on RST2 selects
the programming method (serial or parallel) and one of three programmable flag default
offsets. It also configures Port B for bus size and endian arrangement. Four LOW -to-HIGH
transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST2
is LOW.
Pin Definitions (continued)
Signal Name Description I/O Function
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 6 of 30
Reset must be performed on the FIFO after power-up, before
data is written to its memory.
A LOW-to-HIGH transition on a FIFO reset (RST1, RST2)
input latches the values of the Flag select (FS0, FS1) for
choosing the Almost Full and Almost Empty offset
program ming m ethod (see Almos t Empty and Almos t Full fl ag
offset programming below).
First-Word Fall-Through (FWFT/STAN)
After Master Reset, the FWFT select function is active,
permitting a choice between two possible timing modes: CY
Standard Mode or First-Word Fall-Through (FWFT) Mode.
Once the Master Reset (RST1, RST2) input is HIGH, a HIGH
on the FWFT/STAN input during the next LOW-to-HIGH
transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select
CY Standard Mode. This mode uses the Empty Flag function
(EFA, EFB) to indicate whether or not there are any words
present in the FIFO memory. It uses the Full Flag function
(FFA, FFB) to indicate whether or not the FIFO memory has
any free space for writing. In CY Standard mode, every word
read from the FIFO, including the first, must be requested
using a formal read operation.
Once the Master Reset (RST1, RST2) input is HIGH, a LOW
on the FWFT/STAN input during the next LOW-to-HIGH
transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select
FWFT Mode. This mode uses the Output Ready function
(ORA, ORB) to indicate whether or not there is valid data at
the data outputs (A0–35 or B0–35). (See footnote #1) It also
uses the Input Ready function (IRA, IRB) to indicate whether
or not the FIFO memory has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes
directly to data outputs, no read request necessary. Subse-
quent words must be accessed by performing a formal read
operation.
Following Master Reset, the level applied to the FWFT/STD
input to choose the desired timing mode must remain static
through out the FIFO opera tio n.
Programming the Almost Empty and Almost Full Flags
Four registers in the CY7C436X2 are used to hold the offset
values for th e Almo st Emp ty and Almost F ull fl ags. Th e Port B
Almost Empty flag (AEB) offset register is labeled X1 and the
Port A Almost Empty flag (AEA) offset register is labeled X2.
The Port A Almost Full flag (AFA) offset register is labeled Y1
and the Port B Almost Full flag (AFB) offset reg is ter is la bel ed
Y2. The index of each register name corresponds with preset
values during the reset of a FIFO, programmed in parallel
using the FIFO’s Port A data inputs (see Table 1).
To program the X1, X2, Y1, and Y2 registers from Port A,
perform a Master Reset on both FIFOs simultaneously with
FS0 and FS1 LOW during the LOW-to-HIGH transition of
RST1 and RST2. After this reset is complete, the first four
writes to FIFO1 do not store data in RAM but load the offset
registers in the order Y1, X1, Y2, X2. The Port A data inputs
used by the offset registers are (A0–9), (A0–11), or (A0–13), for
the CY7C436X2, respectively. The highest numbered input is
used as the most significant bit of the binary number in each
case. Valid programmi ng v alues fo r the reg isters ra nge fr om 0
to 1023 for the CY7C43642; 0 to 4095 for the CY7C43662; 0
to 16383 for the CY7C43682. (See footnote #2) After all the
offset registers are programmed from Port A, the Port B
Full/In put Ready (FFB/IRB) is set HIG H and both F IFOs beg in
normal operation.
FS0 an d FS1 func tion the same way in both C Y St and ard and
FWFT mo des .
FIFO Write/Read Operation
The state of the Port A data (A0–35) lines is controlled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A0–35 lines are in the high-impedance state when either
CSA or W/RA is HIGH. The A0–35 lines are active outputs
when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0–35 inputs on a
LOW-to -HIGH transition of CLKA when CSA is LOW, W/RA is
HIGH, ENA is HIGH, MBA is LOW , and FF A/IRA is HIGH. Data
is read from FIFO2 to the A0–35 outputs by a LOW-to-HIGH
tran si t io n of CL K A w h en C SA is LOW, W/RA is LOW, ENA is
HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2).
FIFO reads and writes on Port A are independent of any
concurrent Port B operation.
The Port B c ont rol s ig nal s a r e i den tic al to those of Port A w i th
the exception that the Port B Write/Read select (W/RB) is the
inverse of the Port A Write/Read Select (W/RA). The state of
the Port B data (B0–35) lines is controlled by the Port B Chip
Select (CSB) and Port B W rite/Read Select (W/RB).Th e B0–35
lines are in the high-impedance state when either CSB is HIGH
or W/RB is LOW. The B0–35 lines are active outputs whe n CSB
is LOW and W/RB is HIGH.
Data is loaded into FIFO2 from the B0–35 inputs on a
LOW-to -HIGH transition of CLKB when CSB is LOW, W/RB is
LOW , ENB is HIGH, MBB is LOW , and FFB/IRB is HIGH. Data
is read from FIFO1 to the B0–35 outputs by a LOW-to-HIGH
transiti on of CL KB when CSB is LOW, W/RB is HIGH, ENB is
HIGH, MBB is LOW, and EFB/ORB is HIGH (see Table 3).
FIFO reads and writes on Port B are independent of any
concurrent Port A operation.
The set-u p and hold tim e con st r ain t s to the po rt clocks for the
port Chip Selects and Write/Read Selects are only for enabling
write and read operations and are not related to
high-im pe dance co ntrol of t he d ata out puts. If a port enab le i s
LOW during a clock cycle, the port’s Chip Select and
Write/Read select may change states during the set-up and
hold time window of the cycle.
When operating the FIFO in FWFT Mode and the Output
Ready flag is LOW, the ne xt word writ ten is auto matic ally se nt
to the FIFO’s output regist er by the LOW -to-HIGH trans ition of
the port clock that sets the Output Ready flag HIGH, data
residing in the FIFO’s memory array is clocked to the output
register only when a read is selected using the port’s Chip
Select, Write/Read Select, Enable, and Mailbox select.
When op erating the FIFO in CY S ta ndard Mod e, regardle ss of
whether the Empty Flag is LOW or HIGH, data residing in the
FIFO’s memory array is clocked to the output register only
when a read is selected using the port’s Chip Select,
Write/Read Select, Enable, and Mailbox Select.
Synchronized FIFO Flags
Each FIFO is synchronized to its port clock through at least two
flip-flop stages. This is don e to improve flag-signal reliability by
reducing the probability of the metastable events when CLKA
and CL KB operate async hronousl y to one ano ther . EFA/ORA,
AEA, FFA/IRA, and AFA are synchronized to CLKA.
EFB/ORB, AEB, FFB/IRB, and AFB are synchronized to
CLKB. Table 4 and Table 5 show the rel ati ons hi p of ea ch port
flag to FIFO1 and FIFO2.
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Empty/Output Ready Flags (EFA/ORA, EFB/ORB)
These a r e du al-p urp ose fla gs . In the FWFT Mo de, the O ut put
Ready (ORA, ORB) function is selected. When the
Output-Ready flag is HIGH, new data is present in the FIFO
output register. When the Output Ready flag is LOW, the
previous data word is present in the FIFO output register and
attempted FIFO reads are ignored. (See footnote #1)
In the CY S tandard Mode, the Empty Flag (EF A, EFB) fun ction
is selected. When the Empty Flag is HIGH, data is available in
the FIFO’s RAM memory for reading to the output register.
When the Empty Flag is LOW, the previous data word is
presen t in th e FIFO output regis ter and attem pted FIF O read s
are ignored.
The Empty/Output Ready flag of a FIFO is synchronized to the
port clock that reads data from its array. For both the FWFT
and CY S tandard modes, the FIFO read pointer is incremented
each time a new word is clocked to its output register. The
state machine that controls an Output Ready flag monitors a
write poi nte r a nd read po in ter c om p a rator that ind ic ates w h en
the FIFO SRAM status is empty, or empty+1.
In FWFT Mode, from the time a word is written to a FIFO, it
can be shifted to the FIFO output register in a minimum of
three cycles of the Output Ready flag synchronizing clock.
Therefore, an Output Ready flag is LOW if a word in memory
is the next data to be sent to the FIFO output register and three
cycle s hav e not elapse d si nce t he tim e th e wor d was wr it ten .
The Output Ready flag of the FIFO remains LOW until the third
LOW-to-HIGH transition of the synchronizing clock occurs,
simultaneously forcing the Output Ready flag HIGH and
shifting the word to the FIFO output register.
In the CY Standard Mode, from the time a word is written to a
FIFO, the Empty flag will indicate the presence of data
availa bl e for rea di ng in a minimum of two c yc les of th e Emp ty
flag synchronizing clock. Therefore, an Empty Flag is LOW if
a word in memory is the next data to be sent to the FIFO output
register and two cycles have not elapsed since the time the
word was written. The Empty flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing
clock occurs, forcing the Empty flag HIGH; only then can data
be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synch ron iz ing c loc k be gins the fi rst synchro ni zat ion cycle of a
write if the clock transition occurs at time tSKEW1 or greater
after the write. Otherwise, the subsequent clock cycle can be
the first synchronization cycle.
Full/Input Ready Flags (FFA/IRA, FFB/IRB)
This is a dual-purpose flag. In FWFT Mode, the Input Ready
(IRA and IRB) function is selected. In CY Standard Mode, the
Ful l Fl ag (F FA and FFB) function is selected. For both timing
modes, when the Full/Input Ready flag is HIGH, a memory
location is free in the SRAM to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and
attempted writes to the FIFO are ignored.
The Full/Input Read y flag of a FI FO is sync hronized to t he port
clock that writes data to its array. For both FWFT and CY
Standard modes, each time a word is written to a FIFO, its
write pointer is incremented. The state machine that controls
a Full/Input Ready flag monitors a write pointer and read
pointer comparator that indicates when the FIFO SRAM status
is full, or full–1. From the time a word is read from a FIFO, its
previous memory location is ready to be written to in a
minimum of two cycles of the Full/Input Ready flag synchro-
nizing clock. The refore, an Full/ Input Ready flag is LOW if l ess
than two cycles of the Full/Input Ready flag synchronizing
clock ha ve el apsed sinc e the ne xt me mory w rite locati on h as
been read. The second LOW-to-HIGH transition on the
Full/Input Ready flag synchronizing clock after the read sets
the Full/Input Ready flag HIGH.
A LOW -to-HIGH trans ition on a Fu ll/Input Rea dy flag synch ro-
nizing clock begins the first synchronization cycle of a read if
the clock transition occurs at time tSKEW1 or greater after the
read. Otherwise, the subsequent clock cycle can be the first
synchroni zation cycle.
Almost Empty Flags (AEA, AEB)
The Almost Empty flag of a FIFO is synchronized to the port
clock that reads data from its array. The state machine that
controls an Almost Empty flag monitors a write pointer and
read pointer comparator that indicates when the FIFO SRAM
sta tus is almo st empty, or alm ost empty+1. Th e Almost Emp ty
state is defined by the contents of register X1 for AEB and
register X2 for AEA. These registers are loaded with preset
values during a FIFO reset, programmed from Port A, or
programmed serially (see Almost Empty flag and Almost Full
flag of fset program ming above). An Alm ost Empty flag is LOW
when its FIFO contains X or less words and is HIGH when its
FIFO contains (X+1) or more words.[2]
Two LOW-to-HIGH transitions of the Almost Empty flag
synchronizing clock are required after a FIFO write for its
Almost Empty fl ag to reflect th e new le vel of fill . Therefore, t he
Almost Full flag of a FIFO containing (X+1) or more words
rema ins LOW if two cycl es of it s sy nchron izing clock hav e not
elapsed since the write that filled the memory to the (X+1)
level. An Almost Empty flag is set HIGH by the second
LOW-to-HIGH transition of its synchronizing clock after the
FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH
transition of an Almost Empty flag synchronizing clock begins
the first synchronization cycle if it occurs at time tSKEW2 or
greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle may be
the first synchronization cycle.
Almost Full Flags (AFA, AFB)
The Almost Full flag of a FIFO is sy nchronized to the port cl ock
that write s data to it s array . The st ate machine that controls an
Almost Full flag monitors a write pointer and read pointer
comparator that indicates when the FIFO SRAM status is
almos t full, or al most full–1 . The Alm ost Full st ate is def ined by
the contents of register Y1 for AFA and register Y2 for AFB.
These registers are loaded with preset values during a FIFO
reset, programmed from Port A, or programmed serially (see
Almost Empty flag and Almost Full flag offset programming
above). An Almost Full flag is LOW when the nu mber of words
in its FIFO is greater than or equal to (1024–Y), (4096–Y), or
(16384–Y) for the CY7C436X2 respectively. An Almost Full
flag is HIGH when th e numbe r of word s in it s FIFO is le ss than
or equal to [ 1024–(Y+1)], [4096–(Y+1)], or [16384–(Y+1)], for
the CY7C436X2 respectively. (See footnote #2)
Two LOW-to-HIG H transi tions o f the Almo st Full flag sy nchro-
nizin g clo ck a re re qui red af ter a FIF O re ad for its Al most Full
flag to reflect the new level of fill. Therefore, the Almost Full
flag of a FIFO containing [1024/4096/16384–(Y+1)] or less
words remains LOW if two cycles of its synchronizing clock
have not elapsed since the read that reduced the number of
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Document #: 38-06019 Rev. *B Page 8 of 30
words i n mem ory to [102 4/4096/16 384–(Y+1)]. An Al most Full
flag is set HIGH by the second LOW-to-HIGH transition of its
synchronizing clock after the FIFO read that reduces the
number of words in memory to [1024/4096/16384–(Y+1)]. A
LOW-to-HIGH transition of an Almost Full flag synchronizing
clock begins the first synchronization cycle if it occurs at time
tSKEW2 or greater after the read that reduces the number of
words in memory to [1 024/4096/1638 4–(Y+1)]. Otherwise, the
subsequent synchronizing clock cycle may be the first
synchronization cycle.
Mailbox Registers
Each FIFO h as a 36 -bit byp ass re gister to p ass comm and and
control information between Port A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation. The usable width of both the Mail1 and Mail2
registers matches the selected bus size for Port B.
A LOW-to-HIGH transition on CLKA writes A0-35 data to the
Mail1 Register when a Port A write is sel ected by CSA, W/RA,
and ENA with MBA HIGH. If the selected Port A bus size is
also 36 bits, then the usable width of the Mail1 Register
empl oys data li nes A0-35. If the selected Port A bus size is 18
bits , then th e u sa ble width of t he Ma il1 R eg is ter em plo ys da t a
lines A0-17. (In this case, A18-35 are don’t care inputs.) If the
selec ted Port A bus si ze is 9 bits, then th e us abl e w idth of the
Mail1 Register employs data lines A0-8. (In this case , A9-35 are
don’t care inputs.)
A LOW-to-HIGH transition on CLKB writes B0–35 data to the
Mail2 Register when a Port B write is sel ected by CSB, W/RB,
and ENB with MBB HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail2 Register
emplo ys data lines B 0–35. If th e s ele cte d Po rt B bus s ize is 18
bits , then th e u sa ble width of t he Ma il2 R eg is ter em plo ys da t a
lines B0–17. (In this case, B18–35 are don’t care inputs.) If the
selec ted Port B bus si ze is 9 bits, then th e us abl e w idth of the
Mail2 Register employs data lines B0-8. (In this case , B9-35 are
don’t care inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW . Attemp ted writes to a ma il register are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the port
Mailbox Select inp ut is HI GH .
The Mail1 Register flag (MBF1) is set HIGH by a
LOW-to-HIGH transition on CLKB when a Port B read is
selected by CSB, W/RB, and ENB with MBB HIGH. For a
36-bit bus s ize, 36 bits of mailbox data are placed on B0–35.
For an 18-bit bus size, 18 bits of mailbox data are placed on
B0–17. (In th is c ase, B 18–35 are indetermi nate.) For a 9-b it bus
size, 9 bits of mailbox data are placed on B0–8. (In this ca se,
B9–35 are indeterminate.)
The Mail2 Register flag (MBF2) is set HIGH by a
LOW-to-HIGH transition on CLKA when a Port A read is
selec ted by CSA, W/RA, and ENA with MBA HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on
A0–35. For an 18-bit bus size, 18 bits of mailbox data are
placed on A0–17. (In this case, A18–35 are indeterminate.) For
a 9-bit bus size, 9 bits of mai lbox data are plac ed on A0–8. (In
this case, A9–35 are indeterminate.)
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Retransmit (RT1, RT2)
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. Retransmit
function applies to CY standard mode only.
The number of 36-/18-/9-bit words written into the FIFO should
be less than full depth min us 2/4/8 word s betwe en the rese t of
the FIFO (master or partial) and Retransmit setup.A LOW
pulse on RT1, (RT2) resets the int ernal read pointer to the first
physical location of the FIFO. CLKA and CLKB may be free
running but ENB (ENA) must be deasserted during and tRTR
after the retransmit pulse. With every valid read cycle after
retransmit, previously accessed data is read and the read
pointer is incremented until it is equal to the write pointer . Flags
are governed by the relative locations of the read and write
pointers and are updated during a retransmit cycle. Data
written to the FIFO after activation of RT1, (RT2) are trans-
mitted also.
Table 1. Flag Program ming [2]
FS1 FS0 RST1 RST2 X1 and Y1 Registers[3] X2 and Y2 Registers[4]
H H ↑X64 X
H H X ↑X64
H L ↑X16 X
H L X ↑X16
L H ↑X 8 X
L H X ↑X 8
L L ↑ ↑ Programming via Port A Programming via Port A
Table 2. Port A Enable Function
CSA W/RA ENA MBA CLKA A0–35 Outputs Port Function
H X X X X In high-impedance state None
L H L X X In high-impedance state None
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L H H L ↑In high-impe dan ce state FIFO1 write
L H H H ↑In high-impe dance st ate Mail1 write
L L L L X Active, FIFO2 output register None
L L H L ↑Active, FIFO2 output register FIFO2 read
L L L H X Active, Mail2 register None
L L H H ↑Active, Mail2 register Mail2 read (set MBF2 HIGH)
Table 3. Port B Enable Function
CSB W/RB ENB MBB CLKB B0–35 Outputs Port Function
H X X X X In high-impedance state None
L L L X X In high-impedance state None
L L H L ↑In high-impedance state FIFO2 write
L L H H ↑In high-impedance state Mail2 write
L H L L X Active, FIFO1 output register None
L H H L ↑Active, FIFO1 output register FIFO1 read
L H L H X Active, Mail1 register None
L H H H ↑Active, Mail1 register Mail1 read (set MBF1 HIGH)
Table 4. FIFO1 Flag Operation (CY Standard and FWFT modes)[2]
Number of Words in FIFO Memory[5, 6, 7 , 8] Synchronized to CLKB Synchronized to CLKA
CY7C43642 CY7C43662 CY7C43682 EFB/ORB AEB AFA FFA/IRA
0 0 0 L L H H
1 TO X1 1 TO X1 1 TO X1 H L H H
(X1+1) to
[1024–(Y1+1)] (X1+1) to
[4096–(Y1+1)] (X1+1) to
[16384–(Y1+1)] H H H H
(1024–Y1) to 1023 (4096–Y1) to 4095 (16384–Y1) to 16383 H H L H
1024 4096 16384 H H L L
Table 2. Port A Enable Function (continued)
Table 5. FIFO2 Flag Operation (CY Standard and FWFT modes)[2]
Number of Words in FIFO Memory[6, 7, 8, 9] Synchronized to CLKA Synchronized to CLKB
CY7C43642 CY7C43662 CY7C43682 EFA/ORA AEA AFB FFB/IRB
000 LLHH
1 TO X2 1 TO X2 1 TO X2 H L H H
(X2+1) to
[1024–(Y2+1)] (X2+1) to
[4096–(Y2+1)] (X2+1) to
[16384–(Y2+)1] HHHH
(1024–Y2) to 1023 (4096–Y2) to 4095 (16384–Y2) to 16383 H H L H
1024 4096 16384 H H L L
Notes:
3. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
4. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
5. X1 is the Almost Empty offset for FIFO1 used by AEB. Y1 is the Almost Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset
or port A programming.
6. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
7. Data in the output register does not count as a “word i n FI F O m e mory.” Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the
output register (no read operation necessary), it is not included in the FIFO memory count.
8. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in CY Standard Mode.
9. X2 is the Almost Empty offset for FIFO2 used by AEA. Y2 is th e A lm os t Fu l l offs et f or FI FO 2 us ed by A FB. Both X2 and Y2 are selected during a FIFO2 reset
or port A programming.
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Maximum Ratings[10,11]
(Abov e wh ic h th e us eful life ma y be imp aire d. For user gui de-
lines, not tested.)
Storage Temperature ...................................–65°C to +150°C
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Supply Voltage to Ground Potential...............–0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State[12] ....................................–0.5V to VCC+0.5V
DC Input Volta ge[12] .................................–0.5V to VCC+0.5V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current......................................................> 200mA
Operating Range
Range Ambient
Temperature VCC[13]
Commercial 0°C to + 70°C 5.0V ± 0.5V
Industrial −40°C to +85°C 5.0V ± 0.5V
Electri cal Characteristics Over the Operating Range
Parameter Description Te st Conditions
CY7C43642/62/82
UnitMin. Max.
VOH Output HIGH Voltage VCC = 4.5 V,
IOH = −4.0 mA 2.4 V
VOL Output LOW Voltage VCC = 4.5 V,
IOL = 8.0 mA 0.5 V
VIH Input HIGH Voltage 2.0 VCC V
VIL Input LOW Voltage –0.5 0.8 V
IIX Input Leakage Current VCC = Max. –10 +10 µA
IOZL
IOZH Output OFF, High-Z
Current OE > VIH,
VSS < VO< VCC –10 +10 µA
ICC1[14] Active Power Supply Current Com’l100 mA
Ind 100 mA
ISB[15] Average Standby Current Com’l10 mA
Ind 10 mA
Capacitance[16]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 3.3V 4pF
COUT Output Capacitance 8pF
Notes:
10. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
11. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
12. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
13. Operating VCC Range for -7 spee d is 5.0 V ± 0.25V.
14. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz.
Outputs are unloaded.
15. All inputs = VCC – 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.
16. Tested initially and after any design or process changes that may affect these parameters.
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AC Test Loads and Wavefor ms (-10 and -15)
AC Test Loads and Wavefor ms (-7)
3.0V
5V
OUTPUT
R2 = 680Ω
CL = 30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤3ns ≤3ns
ALL INPUT PULSES
R1 = 1.1kΩ
3.0V
GND
90%
10%
90%
10%
≤3ns ≤3ns
ALL INPUT PULSES
I/O
50Ω
VCC/2
Z0 = 50Ω
Switching Characteristics Over the Op erat ing Range
Parameter Description
CY7C43642/62/82
-7 CY7C43642/62/82
-10 CY7C43642/62/82
-15 UnitMin. Max. Min. Max. Min. Max.
fSClock Frequency, CLKA or CLKB 133 100 67 MHz
tCLK Clock Cycle Time, CLKA or CLKB 7.5 10 15 ns
tCLKH Pulse Duration, CLKA or CLKB HIGH 3.5 4 6 ns
tCLKL Pulse Duration, CLKA or CLKB LOW 3.5 4 6 ns
tDS Set-up Time, A0–35 before CLKA↑ and B0–35
before CLKB↑3 4 5 ns
tENS Set-up Time, CSA, W/RA, ENA, and MBA before
CLKA↑; CSB, W/RB, ENB, and MBB before
CLKB↑
3 4 5 ns
tRSTS Set-up Time, RST1, RST2, RT1 or RT2 LOW
before CLKA↑ or CLKB↑[17] 2.5 4 5 ns
tFSS Set-up Time, FS0 and FS1 before RST1 and
RST2 HIGH 6 7 7.5 ns
tSDS Set-up Time, FS0 before CLKA↑3 4 5 ns
tSENS Set-up Time, FS1 before CLKA↑3 4 5 ns
tFWS Set-up Time, FWFT before CLKA↑0 0 0 ns
tDH Hold Time, A0–35 after CLKA↑ and B0–35 after
CLKB↑0 0 0 ns
tENH Hold Time, CSA, W/RA, ENA, and MBA after
CLKA↑; CSB, W/RB, ENB, and MBB after
CLKB↑
0 0 0 ns
tRSTH Hold Time, RST1, RST2, RT1 or RT2 LOW after
CLKA↑ or CLKB↑[17] 1 2 4 ns
tFSH Hold Time, FS0 and FS 1 aft er RS T1 and RS T2
HIGH 1 1 2 ns
tSDH Hold Time, FS0 after CLKA↑0 0 0 ns
tSENH Hold Time, FS1 after CLKA↑0 0 0 ns
Note:
17. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
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tSPH Hold Time, FS1 HIGH after RST1 and RST2
HIGH 0 1 2 ns
tSKEW1[17] Skew Time between CLKA↑ and CLKB ↑ for
EFA/ORA, EFB/ORB, FFA/IRA, and FFB/IRB 5 5 7.5 ns
tSKEW2[17] Skew Time between CLKA↑ and CLKB ↑ for
AEA, AEB, AFA, AFB 7 8 12 ns
tAAccess Time, CLKA↑ to A0–35 and CLKB↑ to
B0–35 1 6 1 8 3 10 ns
tWFF Propagation Delay Time, CLKA↑ to FFA/IRA
and CLKB↑ to FFB/IRB 1 6 1 8 2 8 ns
tREF Propagation Delay Time, CLKA↑ to EFA/ORA
and CLKB↑ to EFB/ORB 1 6 1 8 1 8 ns
tPAE Propagat ion Delay Time, C LKA↑ to AEA and
CLKB↑ to AEB 1 6 1 8 1 8 ns
tPAF Propagat ion Delay Time, C LKA↑ to AFA and
CLKB↑ to AFB 1 6 1 8 1 8 ns
tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW
or MBF2 HIGH and CLKB↑ to MBF2 LOW or
MBF1 HIGH
0 6 0 8 0 12 ns
tPMR Propagation Delay Time, CLKA↑ to B0–35[18] and
CLKB↑ to A0–35[19] 1 7 2 11 312 ns
tMDV Propagation Delay Time, MBA to A0–35 valid and
MBB to B0–35 valid[20] 1 6 2 9 3 11 ns
tRSF Propagation Delay Time, RST1 LOW to AEB
LOW, AFA HIGH, FFA/IRA Low, EFB/ORB
LOW, and M B F1 HIGH an d RST2 LOW to AEA
LOW, AFB HIGH, FFB/IRB Low, EFA/ORA
LOW, and MBF2 HIGH
1 6 1 10 115 ns
tEN Enable T ime, CSA or W/RA LOW to A0–35 Active
and CSB LOW and W/RB HIGH to B0–35 Active 1 6 2 8 2 10 ns
tDIS Disable T ime, CSA or W/RA HIGH to A0–35 at
High Im pedan ce and CSB HIGH or W/RB LOW
to B0–35 at High Impedance
1 5 1 6 1 8 ns
tRTR Re transmit Recovery Time 90 90 90 ns
Notes:
18. Writing data to the Mail1 register when the B0–35 outputs are active and MBB is HIGH.
19. Writing data to the Mail2 register when the A0–35 outputs are active and MBA is HIGH.
20. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
Switching Characteristics Over the Op erat ing Range (continue d)
Parameter Description
CY7C43642/62/82
-7 CY7C43642/62/82
-10 CY7C43642/62/82
-15 UnitMin. Max. Min. Max. Min. Max.
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Switching Waveforms
Note:
21. Reset is performed in the same manner for FIFO2 to load X2 and Y2 with a preset value.
FIFO1 Reset Loading X1 and Y1 with a Preset Value of Eight
CLKA
tRSF
tRSF
tRSF
tWFF
tFSS tFSH
tRSTH
tRSTS
tFWS
CLKB
RST1
FWFT/STAN
FS1, FS0
FFA/IRA
EFB/ORB
AEB
AFA
MBF1
[21]
tRSF
tRSF
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Notes:
22. CSA = LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.
23. tSKEW1 is the minimum time betwee n the r ising CLKA edge and a rising CLKB for FFB/IRB to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one cycle later than shown.
24. If W/RA switches from read to write before the assertion of CSA, tENS = tDIS+tENS.
25. Written to FIFO1.
Switching Waveforms (continued)
Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes)
tWFF
tDS
tENS tENH
tDH
tSKEW1[23]
AFA Offset (Y1) AFB Offse t (Y2) First W ord to FIFO1
CLKA
RST1, RST2
FS1, FS0
FFA/IRA
ENA
A0−35
CLKB
FFB/IRB
[22]
AEB Offset (X1) AEA Of fset (X2)
tFSS tFSH
tWFF
tCLKH tCLKL
tENS tENH
tENS tENH
tDS tDH
tENS tENH tENS tENH
HIGH
W1[25] W2[25]
tCLK
CLKA
FFA/IRA
CSA
W/RA[24]
MBA
ENA
A0–35
Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
tENS tENH
tENS tENH
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 15 of 30
Notes:
26. If W/RB switches from read to write before the assertion of CSB, tENS = tDIS+tENS.
27. Written to FIFO2.
28. Read fro m FIF O1.
Switching Waveforms (continued)
Port B Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
CLKB
FFB/IRB
CSB
W/RB[26]
MBB
ENB
B0−35
tCLKH tCLKL
tCLK
tENS tENH
tENS tENH
tDS tDH
tENS tENH
HIGH
W1[27] W2[27]
tENS tENH
tENS tENH tENS tENH
OR
tENS
tDIS
tENH
tENS tENH
tAtA
tA
tEN tMDV
W1[28] W2[28]
W2[28] W2[28]
W3[28]
Previous Data
No Operation
CLKB
EFB/ORB
CSB
W/RB[26]
MBB
ENB
B0–35
(Standard Mode)
B0–35
(FWFT Mode)
Port B Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
tCLKH tCLKL
tCLK
HIGH
tENS tENH
tEN tMDV tDIS
[1]
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 16 of 30
Note:
29. Read Fr om FIF O2.
Switching Waveforms (continued)
OR
CLKA
EFA/ORA
CSA
W/RA[24]
MBA
ENA
A0−35
(Standard Mode)
A0−35
(FWFT Mode)
Port A Read Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
tENS
tDIS
tENH
tENS tENH
tAtA
tA
tEN tMDV
W1[29] W2[29]
W2[29] W2[29]
W3[29]
Previous Data
No Operation
tCLKH tCLKL
tCLK
HIGH
tENS tENH
tEN tMDV tDIS
[1]
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 17 of 30
Note:
30. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load
of the first word to the output register may occur one CLKB cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS
tCLK
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO1 Em pty
LOW
HIGH
LOW
Old Data in FIFO1 Output Register W1
tENS tENH
tREF tREF
tCLKH tCLKL
tCLK
tSKEW1[30]
CLKA
CSA
W/RA
MBA
ENA
FFA/IRA
A0–35
CLKB
EFB/ORB
CSB
W/RB
MBB
ENB
B0–35
ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)[1]
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 18 of 30
Note:
31. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO1 Empty
LOW
HIGH
LOW
W1
tENS tENH
tREF tREF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[31]
CLKA
CSA
W/RA
MBA
ENA
FFA/IRA
A0–35
CLKB
EFB/ORB
CSB
W/RB
MBB
ENB
B0–35
EFB Flag Timing and First Data Read Fall Through when FIFO1 is
Empty (CY Standard Mode)
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 19 of 30
Notes:
32. tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
33. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output
register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load
of the first word to the output register may occur one CLKA cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS
tENH
tENS
tENH
tA
W1
LOW
tDH
LOW
HIGH
FIFO2 Em pty
LOW
LOW
LOW
Old Data in FIFO2 Outpu t Register W1
tENS tENH
tREF tREF
tCLKH tCLKL
tCLK
tSKEW1[33]
tCLK
tDS
CLKB
CSB
W/RB
MBB
ENB
FFB/IRB
B0–35
CLKA
EFA/ORA
CSA
W/RA
MBA
ENA
A0–35
ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty
[32]
(FWFT Mode)
[1]
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 20 of 30
Note:
34. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Switching Waveforms (continued)
EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Standard Mode)
tCLKH tCLKL
tENS
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
LOW
HIGH
FIFO2 Empty
LOW
LOW
LOW
W1
tENS tENH
tREF tREF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[34]
CLKB
CSB
W/RB
MBB
ENB
FFB/IRB
B0–35
CLKA
EFA/ORA
CSA
W/RA
MBA
ENA
A0–35
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 21 of 30
Note:
35. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS tENH
tA
LOW
HIGH
HIGH
FIFO1 Full
LOW
HIGH
tENS tENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[35]
tDH
tDS
tENH
tENS
Previous Word in FIFO1
Output Register Next Word From FIFO1
To FIFO1
CLKB
CSB
W/RB
MBB
ENB
EFB/ORB
B0–35
CLKA
FFA/IRA
CSA
W/RA
MBA
ENA
A0–35
IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
LOW
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 22 of 30
Note:
36. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FFA HIGH may occur one CLKA cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS tENH
tA
LOW
HIGH
HIGH
FIFO1 Full
LOW
HIGH
tENS tENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[36]
tDH
tDS
tENH
tENS
Previous Word in FIFO1
Output Register Next Wo rd From FIFO1
CLKB
CSB
W/RB
MBB
ENB
EFB/ORB
B0–35
CLKA
FFA/IRA
CSA
W/RA
MBA
ENA
A0−35
FFA Flag Timing and First Available Write when FIFO1 is Full (CY Standard Mode)
LOW
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 23 of 30
Note:
37. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of IRB HIGH may occur one CLKB cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS tENH
tA
LOW
LOW
HIGH
FIFO2 Full
LOW
LOW
tENS tENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[37]
tDH
tDS
tENH
tENS
Previous Word in FIFO2 Out-
put Register Next Wor d From FIFO2
To FIFO2
LOW
CLKA
CSA
W/RA
MBA
ENA
EFA/ORA
A0–35
CLKB
FFB/IRB
CSB
W/RB
MBB
ENB
B0–35
IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 24 of 30
Note:
38. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of FFB HIGH may occur one CLKB cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS tENH
tA
LOW
LOW
HIGH
FIFO2 Full
LOW
LOW
tENS tENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[38
tDH
tDS
tENH
tENS
Previous Word in FIFO2
Output Register Next W ord From FIFO2
To FIFO2
LOW
CLKA
CSA
W/RA
MBA
ENA
EFA/ORA
A0–35
CLKB
FFB/IRB
CSB
W/RB
MBB
ENB
B0–35
FFB Flag Timing and First Available Write when FIFO2 is Full (CY Standard Mode)
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 25 of 30
Notes:
39. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been
read from the FIFO.
40. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
41. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
42. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 Read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been
read from the FIFO.
43. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
44. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
Switching Waveforms (continued)
CLKA
ENA
CLKB
AEB
ENB
Tim ing f or AEB when FIFO1 is Almost Empty (CY Standard and FWFT Modes)[39, 40,2]
tPAE
tPAE
tENH
tENS
tSKEW2[41]
tENS tENH
X1 Word in FIFO1 (X1+1)Words in FIFO1
(X1+1) Words in FIFO1
CLKB
ENB
CLKA
AEA
ENA
Timing for AEA when FIFO2 is Almost Empty (CY Standard and FWFT Modes)[42, 43,2]
tPAE
tPAE
tENH
tENS
tSKEW2[44]
tENS tENH
X2 Word in FIFO2 (X2+1) Words in FIFO2
(X2+1) W ords in FI FO2
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 26 of 30
Notes:
45. FIFO1 Write (CSA = LOW , W/RA = HIGH, MBA = LOW), FIFO1 Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been
read from the FIFO.
46. D = Maximum FIFO Depth 1K for the CY7C43642, 4K for the CY7C43662, and 16K for the CY7C43682.
47. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown.
48. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKA cycle later than shown.
Switching Waveforms (continued)
Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Modes)
CLKA
ENA
AFA
CLKB
ENB
[43,2,45, 46]
tPAF
tENH
tENS
tPAF
tENS tENH
[D–(Y1+1)] Words in FIFO1 (D–Y1)Words in FIFO1
tSKEW2[47]
CLKB
ENB
AFB
CLKA
ENA
Timing for AFB when FIFO2 is Almost Full (CY Standard and FWFT Modes)[42,2, 46]
tPAF
tENH
tENS
tPAF
tENS tENH
[D–(Y2+1)] Words in FIFO2 (D–Y2)Wo rds in FIFO2
tSKEW2[48]
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 27 of 30
49. Simultaneous writing to and reading from mailbox register is not allowed.
Switching Waveforms (continued)
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO1 Output Register W1 (Remains valid in Mail1 Register after read)
CLKA
CSA
W/RA[24]
MBA
ENA
A0–35
CLKB
MBF1
CSB
W/RB[26]
MBB
ENB
Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes)
B0-35
[49]
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 28 of 30
Notes:
50. Retransmit is performed in the same manner for FIFO2.
51. Clocks are free-running in this case. CY standard mode only . Write operation should be prohibited one write clock cycle before the falling edge of RT1, and
during the retransmit operation, i.e. when RT1 is LOW and tRTR after the RT1 rising edge.
52. The Empty and Full flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.
53. For the AEA, AEB, AFA, and AFB flags, two clock cycle are necessar y aft er tRTR to update the se flags.
54. The number of 36-/18-/9-bit words written into the FIFO should be less than full depth minus 2/4/8 words between the reset of the FIFO (master or partial) and
the Retransmit setup.
Switching Waveforms (continued)
tENH
tENS
tENHtENS
tENH
tENS
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO2 Output Register W1 (Remains valid in Mail2 Regis ter after read)
CLKB
CSB
W/RB[26]
MBB
ENB
B0–35
CLKA
MBF2
CSA
W/RA[24]
MBA
ENA
A0−35
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes) [49]
FIFO1 Retransmit Timing
ENB
RT1
tRTR
EFB/FFA
[50,51,52,53,54]
tRSTS tRSTH
CLKA
CLKB
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 29 of 30
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Ordering Information
1K x36 x2 Bidirectional Synchronous FIFO
4K x36 x2 Bidirectional Synchronous FIFO
16K x36 x2 Bidirectional Synchronous FI FO
All product and company names mentioned in this document are the trademarks of their respective holders.
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
7 CY7C43642–7AC A120 120-lead Thin Quad Flat Package Commercial
10 CY7C43642–10AC A120 120-lead Thin Quad Flat Package Commercial
15 CY7C43642–15AC A120 120-lead Thin Quad Flat Package Commercial
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
7 CY7C43662–7AC A120 120-lead Thin Quad Flat Package Commercial
10 CY7C43662–10AC A120 120-lead Thin Quad Flat Package Commercial
15 CY7C43662–15AC A120 120-lead Thin Quad Flat Package Commercial
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
7 CY7C43682–7AC A120 120-lead Thin Quad Flat Package Commercial
10 CY7C43682–10AC A120 120-lead Thin Quad Flat Package Commercial
15 CY7C43682–15AC A120 120-lead Thin Quad Flat Package Commercial
15 CY7C43682–15AI A120 120-lead Thin Quad Flat Package Industrial
Package Diagram
120-pin Thin Quad Flatpack (14 x 14 x 1.4 mm) A120
51-85100
CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B Page 30 of 30
Document Title: CY7C43642, CY7C43662, CY7C43682 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO
Document Number: 38-06019
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 106556 06/08/01 SZV Change from Spec #: 38-00698 to 38-06019
*A 117171 08/23/02 OOR Added footnote to retransmit timing
Added note to retransmit section
*B 122271 12/26/02 RBI Power up requirements added to Maximum Ratings Information
