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confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
© 1996
MOS INTEGRATED CIRCUIT
µ
µµ
µ
PD434004AL
4M-BIT CMOS FAST SRAM
1M-WORD BY 4-BIT
DATA SHEET
The mar k •
••
• shows major revised points.
Document No. M12225EJ5V0DS00 (5th edition)
Date Published May 2000 NS CP(K)
Printed in Japan
Description
The
µ
PD434004AL is a high speed, low power, 4,194,304 bits (1,048,576 words by 4 bits) CMOS static RAM.
Operating supply voltage is 3.3 V ± 0.3 V.
The
µ
PD434004AL is packaged in a 32-pin plastic SOJ.
Features
• 1,048,576 words by 4 bits organization
• Fast access time : 15, 17, 20 ns (MAX.)
• Output Enable input for easy application
• Single +3.3 V power supply
Ordering Information
Part number Pack age Acc ess t i me Supply current m A (MA X.)
ns (MAX.) At operati ng At standby
µ
PD434004ALLE-A 15 32-pin plast i c SOJ 15 130 5
µ
PD434004ALLE-A 17 (10.16 m m (400)) 17 120
µ
PD434004ALLE-A20 20 110
2
µ
µµ
µ
PD434004AL
Data Sheet M12225EJ5V0DS00
Pin Configuration (Marking Side)
/xxx ind icates active low signal.
32-pin plastic SOJ (10.16 mm (400))
[
µ
µµ
µ
PD434004ALLE ]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A0
A1
A2
A3
A4
/CS
I/O1
V
CC
GND
I/O2
/WE
A5
A6
A7
A8
A9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A19
A18
A17
A16
A15
/OE
I/O4
GND
V
CC
I/O3
A14
A13
A12
A11
A10
NC
A0 - A19 : Address Inputs
I/O1 - I/O4 : Data Inputs / Outputs
/CS : Chip Select
/WE : Write Enable
/OE : Output Enable
VCC : Power supply
GND : Ground
NC : No connection
Remark Refer to Package Drawing for the 1-pin index mark.
•
3
µ
µµ
µ
PD434004AL
Data Sheet M12225EJ5V0DS00
Block Diagram
A0
|
A19
Address buffer
Row decoder
Memory cell array
4,194,304 bits
GND
V
CC
/WE
/OE
/CS
Input data
controller Sense amplifier /
Switching circuit
Column decoder
Address buffer
I/O1
|
I/O4
Output data
controller
Truth Table
/CS /OE /WE Mode I/O Supply current
H×× Not selected High im pedance ISB
L L H Read DOUT ICC
L×LWrite D
IN
L H H Output disable High im pedanc e
Remark × : Don’t care
4
µ
µµ
µ
PD434004AL
Data Sheet M12225EJ5V0DS00
Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Supply volt age VCC –0.5 Note to +4.6 V
Input / Output volt age VT–0.5 No te to +4.6 V
Operating ambient t emperature TA0 to 70 °C
Storage temperature Tstg –55 t o +125 °C
Note –2.0 V (MIN.) (pulse width : 2 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply volt age VCC 3.0 3.3 3.6 V
High level input voltage VIH 2.2 VCC+0.3 V
Low level input voltage VIL –0.3 Note +0.8 V
Operating ambient t emperature TA070
°C
Note –2.0 V (MIN.) (pulse width : 2 ns)
5
µ
µµ
µ
PD434004AL
Data Sheet M12225EJ5V0DS00
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter Symbol Test c ondi t i on MIN. TYP. MAX. Unit
Input leak age current ILI VIN = 0 V to VCC –2 +2
µ
A
Output leak age current ILO VI/O = 0 V to VCC,–2+2
µ
A
/CS = VIH or /OE = VIH or /W E = VIL
Operating suppl y current ICC /CS = VIL, Cycle ti me : 15 ns 130 mA
II/O = 0 mA, Cycle time : 17 ns 120
Minimum cyc l e tim e Cyc l e t i me : 20 ns 110
Standby s uppl y current ISB /CS = VIH, VIN = VIH or VIL 50 mA
ISB1 /CS ≥ VCC – 0.2 V, 5
VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
High level out put voltage VOH IOH = –4.0 m A 2.4 V
Low level output voltage VOL IOL = +8.0 mA 0.4 V
Remark VIN : Input voltage
VI/O : Input / Output voltage
Capacitance (TA = 25 °
°°
°C, f = 1 MHz)
Parameter S ymbol Test c ondi t i on MIN. TYP. MAX. Uni t
Input capacitanc e CIN VIN = 0 V 6 pF
Input / Output capacitanc e CI/O VI/O = 0 V 10 pF
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These parameters are periodically sampled and not 100% tested.
6
µ
µµ
µ
PD434004AL
Data Sheet M12225EJ5V0DS00
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
Input Waveform (Rise and Fall Time ≤
≤≤
≤ 3 ns)
Test Points
GND
3.0 V
1.5 V 1.5 V
Output Waveform
Test Points1.5 V 1.5 V
Output Load
AC characteristics directed with the note should be measured with the output load shown in Figure 1 or
Figure 2.
Figure 1 Figure 2
(for tAA, tACS, tOE, tOH) (for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, tOW)
V
TT
= +1.5 V
I/O (Output)
50 Ω
Z
O
= 50 Ω
30 pF
C
L
+3.3 V
I/O (Output)
317 Ω
5 pF
C
L
351 Ω
Remark CL includes capacitances of the probe and jig, and stray capacitances.
7
µ
µµ
µ
PD434004AL
Data Sheet M12225EJ5V0DS00
Read Cycle
Parameter Symbol
µ
PD434004AL-A15
µ
PD434004AL-A17
µ
PD434004AL-A20 Unit Notes
MIN. MAX. MIN. MAX. MIN. MAX.
Read cycle t i me tRC 15 17 20 ns
Address access time tAA 15 17 20 ns 1
/CS access time tACS 15 17 20 ns
/OE access time tOE 7 8 10 ns
Output hold f rom address change tOH 333ns
/CS to out put in low im pedanc e tCLZ 3 3 3 ns 2, 3
/OE to output in low impedance tOLZ 000ns
/CS to out put in high impedance tCHZ 788ns
/OE to output hold in hi gh i mpedanc e tOHZ 788ns
Notes 1. See the output load shown in Figure 1.
2. Transition is measured at ± 200 mV from steady-state voltage with the output load show n in Figure 2.
3. These parameters are periodically sampled and not 100% tested.
Read Cycle Timing Chart 1 (Address Access)
t
OH
t
RC
t
AA
Address (Input)
I/O (Output) Previous data out Data out
Remarks 1. In read cycle, /WE should be fixed to high level.
2. /CS = /OE = VIL
8
µ
µµ
µ
PD434004AL
Data Sheet M12225EJ5V0DS00
Read Cycle Timing Chart 2 (/CS Access)
Address (Input)
t
RC
t
AA
t
OLZ
/CS (Input)
I/O (Output) Data out
t
OHZ
High impedance
t
ACS
/OE (Input)
t
OE
t
CLZ
t
CHZ
High impedance
Caution Address valid prior to or coincident with /CS low level input.
Remark In read cycle, /W E should be fixed to high level.
9
µ
µµ
µ
PD434004AL
Data Sheet M12225EJ5V0DS00
Write Cycle
Parameter Symbol
µ
PD434004AL-A15
µ
PD434004AL-A17
µ
PD434004AL-A20 Unit Notes
MIN. MAX. MIN. MAX. MIN. MAX.
W rite cycle time tWC 15 17 20 ns
/CS to end of write tCW 10 11 12 ns
Address val i d to end of write tAW 10 11 12 ns
Write pul se width tWP 10 11 12 ns
Data valid to end of write tDW 789ns
Data hold ti me tDH 000ns
Address setup ti me tAS 000ns
Writ e recovery time tWR 111ns
/WE t o output in high i mpedance tWHZ 7 8 8 ns 1, 2
Output active from end of write t OW 333ns
Notes 1. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2.
2. These parameters are periodically sampled and not 100% tested.
Write Cycle Timing Chart 1 (/WE Controlled)
tWC
tCW
tWP
tAS tWR
Address (Input)
/CS (Input)
/WE (Input)
I/O (Input / Output)
tDHtWHZ
tAW
High
impe-
dance
High
impe-
dance
tOW
Indefinite data out Data in Indefinite data out
tDW
Caution /CS or /WE should be fixed to high level during address transition.
Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE.
2. During tWHZ, I/O pins are in the output state, therefore the input signals must not be applied to the
output.
3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read
operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance.
•
10
µ
µµ
µ
PD434004AL
Data Sheet M12225EJ5V0DS00
Write Cycle Timing Chart 2 (/CS Controlled)
t
WC
t
AS
t
CW
t
AW
t
WP
t
WR
t
DW
t
DH
Address (Input)
/CS (Input)
/WE (Input)
I/O (Input) High impedance Data in High impedance
Caution /CS or /WE should be fixed to high level during address transition.
Remark Write operation is done during the overlap time of a low level /CS and a low level /WE.
11
µ
µµ
µ
PD434004AL
Data Sheet M12225EJ5V0DS00
Package Drawing
ITEM MILLIMETERS
B
C
D
E
F
G
H
I
J
K
21.26±0.2
11.18±0.2
3.5±0.2
2.545±0.2
0.8 MIN.
10.16
M
N9.4±0.20
0.12
1.27(T.P.)
2.6
0.40±0.10
P
1.005±0.1
0.74
P32LE-400A-1
U 0.20
0.1Q
T R0.85
+0.10
−0.05
NOTE
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
32-PIN PLASTIC SOJ (10.16mm (400))
17
16
32
1
S
N
M
Q
M
G
E
F
T
U
J
I
H
K
B
CD
P
S
•
12
µ
µµ
µ
PD434004AL
Data Sheet M12225EJ5V0DS00
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
µ
PD434004AL.
Type of Surface Mount Device
µ
PD434004ALLE : 32-pin plastic SOJ (10.16 mm (400))
13
µ
µµ
µ
PD434004AL
Data Sheet M12225EJ5V0DS00
[ MEMO ]
14
µ
µµ
µ
PD434004AL
Data Sheet M12225EJ5V0DS00
[ MEMO ]
15
µ
µµ
µ
PD434004AL
Data Sheet M12225EJ5V0DS00
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
µ
µµ
µ
PD434004AL
M8E 00. 4
The information in this document is current as of May, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
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responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
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