Precision, Dual-Channel, JFET Input,
Rail-to-Rail Instrumentation Amplifier
Data Sheet AD8224
Rev. C Document Feedback
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FEATURES
Two channels in a small 4 mm × 4 mm LFCSP
Custom LFCSP package with hidden paddle
Permits routing and vias underneath package
Allows full bias current performance
Low input currents
10 pA maximum input bias current (B Grade)
0.6 pA maximum input offset current (B Grade)
High CMRR
100 dB CMRR (minimum), G = 10 (B Grade)
90 dB CMRR (minimum) to 10 kHz, G = 10 (B Grade)
Excellent ac specifications and low power
1.5 MHz bandwidth (G = 1)
14 nV/√Hz input noise (1 kHz)
Slew rate: 2 V/μs
750 μA quiescent current per amplifier
Versatility
Rail-to-rail output
Input voltage range to below negative supply rail
4 kV ESD protection
4.5 V to 36 V single supply
±2.25 V to ±18 V dual supply
Gain set with single resistor (G = 1 to 1000)
APPLICATIONS
Medical instrumentation
Precision data acquisition
Transducer interfaces
Differential drives for high resolution input ADCs
Remote sensors
FUNCTIONAL BLOCK DIAGRAM
AD8224
1
2
3
4
12
11
10
9
5678
13141516
–IN1
R
G1
R
G1
+IN1
–IN2
R
G2
R
G2
+IN2
+V
S
REF1
REF2
–V
S
+V
S
OUT1
OUT2
–V
S
06286-001
Figure 1.
Table 1. In Amps and Difference Amplifiers by Category
High
Perform
Low
Cost
High
Voltage
Mil
Grade
Low
Power
Digital
Gain
AD82201 AD85531 AD628 AD620 AD6271 AD82311
AD8221 AD6231 AD629 AD621 AD8250
AD8222 AD524 AD8251
AD526 AD85551
AD624 AD85561
AD85571
1 Rail-to-rail output.
GENERAL DESCRIPTION
The AD8224 is the first single-supply, JFET input instrumentation
amplifier available in the space-saving 16-lead, 4 mm × 4 mm
LFCSP. It requires the same board area as a typical single
instrumentation amplifier yet doubles the channel density
and offers a lower cost per channel without compromising
performance.
Designed to meet the needs of high performance, portable
instrumentation, the AD8224 has a minimum common-mode
rejection ratio (CMRR) of 86 dB at dc and a minimum CMRR
of 80 dB at 10 kHz for G = 1. Maximum input bias current is
10 pA and typically remains below 300 pA over the entire
industrial temperature range. Despite the JFET inputs, the
AD8224 typically has a noise corner of only 10 Hz.
With the proliferation of mixed-signal processing, the number
of power supplies required in each system has grown. Designed
to alleviate this problem, the AD8224 can operate on a ±18 V
dual supply, as well as on a single +5 V supply. The device’s rail-
to-rail output stage maximizes dynamic range on the low voltage
supplies common in portable applications. Its ability to run on a
single 5 V supply eliminates the need for higher voltage, dual
supplies. The AD8224 draws 750 μA of quiescent current per
amplifier, making it ideal for battery powered devices.
In addition, the AD8224 can be configured as a single-channel,
differential output, instrumentation amplifier. Differential
outputs provide high noise immunity, which can be useful when
the output signal must travel through a noisy environment, such
as with remote sensors. The configuration can also be used to
drive differential input ADCs. For a single-channel version, use
the AD8220.
AD8224 Data Sheet
Rev. C | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 20
Gain Selection ............................................................................. 20
Reference Terminal .................................................................... 21
Layout .......................................................................................... 21
Solder Wa sh ................................................................................. 22
Input Bias Current Return Path ............................................... 22
Input Protection ......................................................................... 22
RF Interference ........................................................................... 23
Common-Mode Input Voltage Range ..................................... 23
Applications Information .............................................................. 24
Driving an ADC ......................................................................... 24
Differential Output .................................................................... 24
Driving a Differential Input ADC ............................................ 25
Driving Cabling .......................................................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 27
REVISION HISTORY
12/13—Rev. B to Rev. C
Changes to Input Current Parameter and Power Supply
Parameter, Table 2 ............................................................................. 3
Changes to Table 3 and Table 4 ....................................................... 5
Changes to Input Current Parameter and Power Supply
Parameter, Table 5 ............................................................................. 6
Changes to Table 9 ............................................................................ 9
Changes to Figure 53 ...................................................................... 19
Change to Theory of Operation Section ..................................... 20
Change to Exposed Paddle Package Section ............................... 21
Change to Input Protection Section ............................................. 22
Updated Outline Dimensions (Dimensions Not Changed,
Minimums and Maximums Added) ............................................ 26
5/10—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Added Table 10 ................................................................................. 9
Changes to Figure 3 and Table 11 ................................................. 10
Added Hidden Paddle Package Section and Exposed Paddle
Package Section and Figure 58 ...................................................... 21
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 27
4/07—Rev. 0 to Rev. A
Changes to Features, General Description, and Figure 1 ............. 1
Changes to Table 2 ............................................................................. 3
Changes to Table 3 and Table 4 ....................................................... 5
Changes to Table 5 ............................................................................. 6
Changes to Table 6 and Table 7 ....................................................... 8
Changes to Figure 2 ........................................................................... 9
Changes to Figure 3 ........................................................................ 10
Inserted Figure 4, Figure 5, and Figure 6; Renumbered
Sequentially ..................................................................................... 11
Changes to Figure 7 ........................................................................ 11
Changes to Figure 20 and Figure 21............................................. 13
Changes to Figure 28 ...................................................................... 15
Changes to Theory of Operation and Figure 55 ........................ 20
Changes to Ordering Guide .......................................................... 26
1/07—Revision 0: Initial Version
Data Sheet AD8224
Rev. C | Page 3 of 28
SPECIFICATIONS
VS+ = +15 V, VS− = −15 V, VREF = 0 V, T A = 25°C, G = 1, RL = 2 kΩ1, unless otherwise noted. Table 2 displays the specifications for an
individual instrumentation amplifier configured for a single-ended output or dual instrumentation amplifiers configured for differential
outputs as shown in Figure 63.
Table 2. Individual Amplifier in Single-Ended Configuration or Dual Amplifiers in Differential Output Configuration2, VS = ±15 V
A Grade B Grade
Parameter Test Conditions Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR)
CMRR DC to 60 Hz with
1 kΩ Source Imbalance
VCM = ±10 V
G = 1 78 86 dB
G = 10 94 100 dB
G = 100 94 100 dB
G = 1000 94 100 dB
CMRR at 10 kHz VCM = ±10 V
G = 1 74 80 dB
G = 10 84 90 dB
G = 100 84 90 dB
G = 1000 84 90 dB
NOISE RTI noise =
√(eni2 + (eno/G)2)
Voltage Noise, 1 kHz
Input Voltage Noise, eni VIN+, VIN− = 0 V 14 14 17 nV/√Hz
Output Voltage Noise, eno VIN+, VIN− = 0 V 90 90 100 nV/√Hz
RTI, 0.1 Hz to 10 Hz
G = 1 5 5 µV p-p
G = 1000
0.8
0.8
Current Noise f = 1 kHz 1 1 fA/√Hz
VOLTAGE OFFSET RTI VOS =
(VOSI) + (VOSO/G)
Input Offset, VOSI 300 175 µV
Average TC T = −40°C to +85°C 10 5 µV/°C
Output Offset, VOSO 1200 800 µV
Average TC T = −40°C to +85°C 10 5 µV/°C
Offset RTI vs. Supply (PSR) VS = ±5 V to ±15 V
G = 1 86 86 dB
G = 10 96 100 dB
G = 100 96 100 dB
G = 1000 96 100 dB
INPUT CURRENT
Input Bias Current 25 10 pA
Over Temperature3 T = −40°C to +85°C 300 300 pA
Input Offset Current 2 0.6 pA
Over Temperature
3
T = −40°C to +85°C
5
5
REFERENCE INPUT
RIN 40 40 kΩ
IIN VIN+, VIN− = 0 V 70 70 µA
Voltage Range
−V
S
+V
S
−V
S
+V
S
Gain to Output 1 ±
0.0001
1 ±
0.0001
V/V
AD8224 Data Sheet
Rev. C | Page 4 of 28
A Grade B Grade
Parameter Test Conditions Min Typ Max Min Typ Max Unit
GAIN G = 1 + (49.4 kΩ/RG)
Gain Range 1 1000 1 1000 V/V
Gain Error VOUT = ±10 V
G = 1 0.06 0.04 %
G = 10 0.3 0.2 %
G = 100 0.3 0.2 %
G = 1000 0.3 0.2 %
Gain Nonlinearity VOUT = −10 V to +10 V
G = 1 RL = 10 kΩ 8 15 8 15 ppm
G = 10 RL = 10 kΩ 5 10 5 10 ppm
G = 100 RL = 10 kΩ 15 25 15 25 ppm
G = 1000 RL = 10 kΩ 100 150 100 150 ppm
G = 1 RL = 2 kΩ 15 20 15 20 ppm
G = 10 RL = 2 kΩ 12 20 12 20 ppm
G = 100 RL = 2 kΩ 35 50 35 50 ppm
G=1000 RL = 2 kΩ 180 250 180 250 ppm
Gain vs. Temperature
G = 1 3 10 2 5 ppm/°C
G > 10 −50 −50 ppm/°C
INPUT
Impedance (Pin to Ground)4 104||5 104||5 GΩ||pF
Input Operating Voltage Range5 VS = ±2.25 V to ±18 V
for dual supplies
−VS − 0.1 +VS − 2 −VS − 0.1 +VS − 2 V
Over Temperature T = −40°C to +85°C −VS − 0.1 +VS − 2.1 −VS − 0.1 +VS − 2.1 V
OUTPUT
Output Swing RL = 2 kΩ −14.25 +14.25 −14.25 +14.25 V
Over Temperature T = −40°C to +85°C −14.3 +14.1 −14.3 +14.1 V
Output Swing RL = 10 kΩ −14.7 +14.7 −14.7 +14.7 V
Over Temperature T = −40°C to +85°C −14.6 +14.6 −14.6 +14.6 V
Short-Circuit Current 15 15 mA
POWER SUPPLY
Operating Range ±2.256 ±18 ±2.256 ±18 V
Quiescent Current (Per Amplifier) 750 800 750 800 μA
Over Temperature T = −40°C to +85°C 850 900 850 900 μA
TEMPERATURE RANGE
For Specified Performance −40 +85 −40 +85 °C
Operational7 −40 +125 −40 +125 °C
1 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ.
2 Refers to the differential configuration shown in Figure 63.
3 Refer to Figure 14 and Figure 15 for the relationship between input current and temperature.
4 Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2.
5 The AD8224 can operate up to a diode drop below the negative supply; however, the bias current increases sharply. The input voltage range reflects the maximum
allowable voltage where the input bias current is within the specification.
6 At this supply voltage, ensure that the input common-mode voltage is within the input voltage range specification.
7 The AD8224 is characterized from −40°C to +125°C. See the Typical Performance Characteristics section for expected operation in this temperature range.
Data Sheet AD8224
Rev. C | Page 5 of 28
VS+ = +15 V, VS− = −15 V, VREF = 0 V, T A = 25°C, G = 1, RL = 2 kΩ1, unless otherwise noted. Table 3 displays the specifications for the
dynamic performance of each individual instrumentation amplifier.
Table 3. Dynamic Performance of Each Individual Amplifier—Single-Ended Output Configuration, VS = ±15 V
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
DYNAMIC RESPONSE
Small Signal Bandwidth −3 dB
G = 1 1500 1500 kHz
G = 10 800 800 kHz
G = 100 120 120 kHz
G =1000 14 14 kHz
Settling Time 0.01%
ΔV
O
= ±10 V step
G = 1 5 5 µs
G = 10 4.3 4.3 µs
G = 100 8.1 8.1 µs
G =1000 58 58 µs
Settling Time 0.001% ΔVO = ±10 V step
G = 1 6 6 µs
G = 10 4.6 4.6 µs
G = 100 9.6 9.6 µs
G =1000 74 74 µs
Slew Rate
G = 1 to 100 2 2 V/µs
1 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ.
VS+ = +15 V, VS− = −15 V, VREF = 0 V, T A = 25°C, G = 1, RL = 2 kΩ1, unless otherwise noted. Table 4 displays the specifications for the
dynamic performance of both amplifiers when used in the differential output configuration shown in Figure 63.
Table 4. Dynamic Performance of Both Amplifiers—Differential Output Configuration2, VS = ±15 V
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
DYNAMIC RESPONSE
Small Signal Bandwidth −3 dB
G = 1 1500 1500 kHz
G = 10 800 800 kHz
G = 100
120
120
kHz
G =1000 14 14 kHz
Settling Time 0.01% ΔVO = ±10 V step
G = 1 5 5 µs
G = 10 4.3 4.3 µs
G = 100 8.1 8.1 µs
G =1000 58 58 µs
Settling Time 0.001% ΔVO = ±10 V step
G = 1 6 6 µs
G = 10 4.6 4.6 µs
G = 100
9.6
9.6
µs
G =1000 74 74 µs
Slew Rate
G = 1 to 100 2 2 V/µs
1 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ.
2 Refers to the differential configuration shown in Figure 63.
AD8224 Data Sheet
Rev. C | Page 6 of 28
VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = 25°C, G = 1, RL = 2 kΩ1, unless otherwise noted. Table 5 displays the specifications for an
individual instrumentation amplifier configured for a single-ended output or dual instrumentation amplifiers configured for differential
outputs as shown in Figure 63.
Table 5. Individual Amplifier in Single-Ended Configuration or Dual Amplifiers in Differential Output Configuration2, VS =+5 V
A Grade B Grade
Parameter Test Conditions Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR)
CMRR DC to 60 Hz with
1 kΩ Source Imbalance
VCM = 0 to 2.5 V
G = 1 78 86 dB
G = 10 94 100 dB
G = 100
94
100
dB
G = 1000 94 100 dB
CMRR at 10 kHz
G = 1 74 80 dB
G = 10 84 90 dB
G = 100 84 90 dB
G = 1000
84
90
dB
NOISE RTI noise = √(eni2 + (eno/G)2)
Voltage Noise, 1 kHz VS = ±2.5 V
Input Voltage Noise, eni VIN+, VIN− = 0 V, VREF = 0 V 14 14 17 nV/√Hz
Output Voltage Noise, eno VIN+, VIN− = 0 V, VREF = 0 V 90 90 100 nV/√Hz
RTI, 0.1 Hz to 10 Hz
G = 1 5 5 µV p-p
G = 1000 0.8 0.8 µV p-p
Current Noise
f = 1 kHz
1
1
fA/√Hz
VOLTAGE OFFSET RTI VOS = (VOSI) + (VOSO/G)
Input Offset, VOSI 300 250 µV
Average TC
T = −40°C to +85°C
10
5
µV/°C
Output Offset, VOSO 1200 800 µV
Average TC T = −40°C to +85°C 10 5 µV/°C
Offset RTI vs. Supply (PSR)
G = 1 86 86 dB
G = 10 96 100 dB
G = 100 96 100 dB
G = 1000 96 100 dB
INPUT CURRENT
Input Bias Current 25 10 pA
Over Temperature3 T = −40°C to +85°C 300 300 pA
Input Offset Current 2 0.6 pA
Over Temperature3 T = −40°C to +85°C 5 5 pA
REFERENCE INPUT
RIN 40 40 kΩ
IIN VIN+, VIN− = 0 V 70 70 µA
Voltage Range −VS +VS −VS +VS V
Gain to Output
1 ±
0.0001
1 ±
0.0001
V/V
Data Sheet AD8224
Rev. C | Page 7 of 28
A Grade B Grade
Parameter Test Conditions Min Typ Max Min Typ Max Unit
GAIN G = 1 + (49.4 kΩ/RG)
Gain Range 1 1000 1 1000 V/V
Gain Error
G = 1 VOUT = 0.3 V to 2.9 V 0.06 0.04 %
G = 10 VOUT = 0.3 V to 3.8 V 0.3 0.2 %
G = 100 VOUT = 0.3 V to 3.8 V 0.3 0.2 %
G = 1000 VOUT = 0.3 V to 3.8 V 0.3 0.2 %
Nonlinearity VOUT = 0.3 V to 2.9 V for G = 1
V
OUT
= 0.3 V to 3.8 V for G > 1
G = 1 RL = 10 kΩ 35 50 35 50 ppm
G = 10 RL = 10 kΩ 35 50 35 50 ppm
G = 100 RL = 10 kΩ 50 75 50 75 ppm
G = 1000 RL = 10 kΩ 90 115 90 115 ppm
G = 1 RL = 2 kΩ 35 50 35 50 ppm
G = 10
R
L
= 2 kΩ
35
50
35
50
ppm
G = 100 RL = 2 kΩ 50 75 50 75 ppm
G = 1000 RL = 2 kΩ 175 200 175 200 ppm
Gain vs. Temperature
G = 1 3 10 2 5 ppm/°C
G > 10 −50 −50 ppm/°C
INPUT
Impedance (Pin to Ground)4 104||6 104||6 GΩ||pF
Input Voltage Range5
−0.1
+V
S
− 2
−0.1
+V
S
− 2
V
Over Temperature T = −40°C to +85°C −0.1 +VS − 2.1 −0.1 +VS − 2.1 V
OUTPUT
Output Swing
R
L
= 2 kΩ
0.25
4.75
0.25
4.75
V
Over Temperature T = −40°C to +85°C 0.3 4.70 0.3 4.70 V
Output Swing RL = 10 kΩ 0.15 4.85 0.15 4.85 V
Over Temperature T = −40°C to +85°C 0.2 4.80 0.2 4.80 V
Short-Circuit Current 15 15 mA
POWER SUPPLY
Operating Range 4.5 36 4.5 36 V
Quiescent Current (Per Amplifier) 750 800 750 800 µA
Over Temperature
T = −40°C to +85°C
850
900
850
900
µA
TEMPERATURE RANGE
For Specified Performance −40 +85 −40 +85 °C
Operational6
−40
+125
−40
+125
°C
1 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ.
2 Refers to the differential configuration shown in Figure 63.
3 Refer to Figure 14 and Figure 15 for the relationship between input current and temperature.
4 Differential and common-mode impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2.
5 The AD8224 can operate up to a diode drop below the negative supply, but the bias current increases sharply. The input voltage range reflects the maximum
allowable voltage where the input bias current is within the specification.
6 The AD8224 is characterized from −40°C to +125°C. See the Typical Performance Characteristics section for expected operation in that temperature range.
AD8224 Data Sheet
Rev. C | Page 8 of 28
VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = 25°C, G = 1, RL = 2 kΩ1, unless otherwise noted. Table 6 displays the specifications for the
dynamic performance of each individual instrumentation amplifier.
Table 6. Dynamic Performance of Each Individual Amplifier—Single-Ended Output Configuration, VS = +5 V
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
DYNAMIC RESPONSE
Small Signal Bandwidth −3 dB
G = 1 1500 1500 kHz
G = 10 800 800 kHz
G = 100 120 120 kHz
G =1000 14 14 kHz
Settling Time 0.01%
G = 1 ΔVO = 3 V step 2.5 2.5 µs
G = 10 ΔVO = 4 V step 2.5 2.5 µs
G = 100 ΔVO = 4 V step 7.5 7.5 µs
G =1000 ΔVO = 4 V step 60 60 µs
Settling Time 0.001%
G = 1 ΔVO = 3 V step 3.5 3.5 µs
G = 10 ΔVO = 4 V step 3.5 3.5 µs
G = 100 ΔVO = 4 V step 8.5 8.5 µs
G =1000 ΔVO = 4 V step 75 75 µs
Slew Rate
G = 1 to 100 2 2 V/µs
1 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ.
VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = 25°C, G = 1, RL = 2 kΩ1 unless otherwise noted. Table 7 displays the specifications for the
dynamic performance of both amplifiers when used in the differential output configuration shown in Figure 63.
Table 7. Dynamic Performance of Both Amplifiers—Differential Output Configuration2, VS = +5 V
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
DYNAMIC RESPONSE
Small Signal Bandwidth −3 dB
G = 1 1500 1500 kHz
G = 10 800 800 kHz
G = 100 120 120 kHz
G =1000 14 14 kHz
Settling Time 0.01%
G = 1 ΔVO = 3 V step 2.5 2.5 µs
G = 10 ΔVO = 4 V step 2.5 2.5 µs
G = 100
ΔV
O
= 4 V step
7.5
7.5
µs
G =1000 ΔVO = 4 V step 60 60 µs
Settling Time 0.001%
G = 1 ΔVO = 3 V step 3.5 3.5 µs
G = 10 ΔVO = 4 V step 3.5 3.5 µs
G = 100 ΔVO = 4 V step 8.5 8.5 µs
G =1000 ΔVO = 4 V step 75 75 µs
Slew Rate
G = 1 to 100 2 2 V/µs
1 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ.
2 Refers to the differential configuration shown in Figure 63.
Data Sheet AD8224
Rev. C | Page 9 of 28
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter Rating
Supply Voltage ±18 V
Power Dissipation See Figure 2
Output Short-Circuit Current Indefinite1
Input Voltage (Common Mode) ±VS
Differential Input Voltage ±VS
Storage Temperature Range −65°C to +130°C
Operating Temperature Range2 −40°C to +125°C
Lead Temperature (Soldering, 10 sec)
300°C
Junction Temperature 130°C
Package Glass Transition Temperature 130°C
ESD (Human Body Model) 4 kV
ESD (Charge Device Model) 1 kV
ESD (Machine Model) 0.4 kV
1 Assumes the load is referenced to midsupply.
2 Temperature for specified performance is −40°C to +85°C. For performance
to 125°C, see the Typical Performance Characteristics section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 9.
Exposed Paddle Package θJA Unit
CP-16-13: LFCSP, EPAD Soldered to Board 48 °C/W
CP-16-13: LFCSP, EPAD Not Soldered to Board 86 °C/W
Table 10.
Hidden Paddle Package θJA Unit
CP-16-19: LFCSP 86 °C/W
The θJA values in Table 9 and Table 10 assume a 4-layer JEDEC
standard board. If the thermal pad is soldered to the board, it is
also assumed it is connected to a plane. θJC at the exposed pad is
4.4°C/W.
Maximum Power Dissipation
The maximum safe power dissipation for the AD8224 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 130°C, which is the glass transition temperature,
the plastic changes its properties. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric performance
of the amplifiers. Exceeding a temperature of 130°C for an
extended period can result in a loss of functionality. Figure 2
shows the maximum safe power dissipation in the package vs.
the ambient temperature for the LFCSP on a 4-layer JEDEC
standard board.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–60 –40 –20 020 40 60 80 100 120 140
06286-002
AMBI E NT TE M P E RATURE ( °C)
MAXIMUM POWER DISSIPATIO N (W)
θJA = 48° C/W WHEN THERMAL PAD
IS S OLDE RE D TO BOARD
θJA = 86° C/W WHEN THERMAL PAD
IS NOT SOLDERED TO BOARD
Figure 2. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
AD8224 Data Sheet
Rev. C | Page 10 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
06286-003
12
11
10
9
–IN1 1
RG1 2
RG1 3
+VS5
REF1 6
REF2 7
–VS8
+IN1 4
16
15
14
13
PIN 1
INDICATOR
TOP VI EW
AD8224
–IN2
RG2
RG2
+IN2
+VS
OUT1
OUT2
–VS
NOTES
1. THE AD8224 COMES IN T WO P ACKAGE TYPE S — E ACH IS A 16 LEAD
4mm × 4mm LFCSP . O NE P ACKAGE HAS AN E X P OSE D THERMAL PAD,
WHICH IS CONNECTED T O +VS. THE O THER P ACKAGE TYPE DOES NOT
EXP OSE THE THERMAL PAD. SEE THE P ACKAGE CONSI DE RATI ONS
SECTION FOR MORE INFORMATION.
Figure 3. Pin Configuration
Table 11. Pin Function Descriptions
Pin Number Mnemonic Description
1 −IN1 Negative Input Instrumentation Amplifier (In-Amp) 1
2 RG1 Gain Resistor In-Amp 1
3 RG1 Gain Resistor In-Amp 1
4 +IN1 Positive Input In-Amp 1
5 +VS Positive Supply
6 REF1 Reference Adjust In-Amp 1
7 REF2 Reference Adjust In-Amp 2
8 −VS Negative Supply
9 +IN2 Positive Input In-Amp 2
10
R
G2
Gain Resistor In-Amp 2
11 RG2 Gain Resistor In-Amp 2
12 −IN2 Negative Input In-Amp 2
13 −VS Negative Supply
14 OUT2 Output In-Amp 2
15 OUT1 Output In-Amp 1
16 +VS Positive Supply
Data Sheet AD8224
Rev. C | Page 11 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
25°C, VS = ±15 V, R L =10 kΩ, unless otherwise noted.
06286-070
0
CMRR (µV/V)
NUMBER OF UNIT S
–40 –20 020 40
400
350
300
250
200
150
100
50
Figure 4. Typical Distribution of CMRR (G = 1)
06286-071
0
V
OSI
(µV)
NUMBER OF UNIT S
–200 –100 0100 200
400
350
300
250
200
150
100
50
Figure 5. Typical Distribution of Input Offset Voltage
06286-072
400
300
200
100
0
–1200 –900 –600 –300 0300 600 900 1200
VOSO (µV)
NUMBER OF UNIT S
Figure 6. Typical Distribution of Output Offset Voltage
1000
11100k
FRE QUENCY ( Hz )
VOLTAGE NOISE RTI (nV/ Hz)
10 100 1k 10k
10
100
GAIN = 100 BANDW IDT H ROLL-OFF
GAIN = 1
GAIN = 10
GAIN = 100/ GAI N = 1000
GAIN = 1000 BANDW IDT H ROLL-OFF
06286-009
Figure 7. Voltage Spectral Density vs. Frequency
XX
XX
XX XX
XXX (X)
XXX (X)
1s/DIV
5µV/DIV
06286-010
Figure 8. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)
XX
XX
XX XX
XXX (X)
XXX (X)
1s/DIV1µV/DIV
06286-011
Figure 9. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)
AD8224 Data Sheet
Rev. C | Page 12 of 28
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0.1 110 100 1000
06286-012
TIME (s)
DEL TA VOSI (µV)
Figure 10. Change in Input Offset Voltage vs. Warmup Time
150
1011M
FRE QUENCY ( Hz )
PSRR ( dB)
10 100 1k 10k 100k
130
110
90
70
50
30
BANDWIDTH
LIMITED
GAIN = 1
GAIN = 10
GAIN = 100
GAIN = 1000
06286-013
Figure 11. Positive PSRR vs. Frequency, RTI
150
1011M
FRE QUENCY ( Hz )
PSRR ( dB)
10 100 1k 10k 100k
130
110
90
70
50
30
GAIN = 1
GAIN = 10
GAIN = 100
GAIN = 1000
06286-014
Figure 12. Negative PSRR vs. Frequency, RTI
06286-068
COMMON-MODE VOLT AGE (V)
INP UT BIAS CURRE NT (pA)
–1
1
3
5
7
9
–16 –12 –8 –4 04812 16–0.5
–0.3
–0.1
0.1
0.3
INP UT OFF S E T CURRENT ( pA)
–15.1V INPUT BIAS
CURRENT ±15
INPUT
OFFSET
CURRENT ±5
INP UT BIAS
CURRENT ±5
–5.1V
INPUT OFFSET
CURRENT ±15
Figure 13. Input Bias Current and Input Offset Current vs. Common-Mode Voltage
10n
1n
100p
10p
1p
0.1p
–50 150
TEMPERATURE (°C)
INP UT BIAS CURRE NT (A)
–25 025 50 75 100 125
I
OS
I
BIAS
06286-016
Figure 14. Input Bias Current and Offset Current vs. Temperature,
VS = ±15 V, VREF = 0 V
10n
1n
100p
10p
1p
0.1p
–50 150
TEMPERATURE (°C)
CURRENT ( A)
–25 025 50 75 100 125
I
OS
I
BIAS
06286-017
Figure 15. Input Bias Current and Offset Current vs. Temperature,
VS = 5 V, VREF = 2.5 V
Data Sheet AD8224
Rev. C | Page 13 of 28
40
60
80
100
120
140
160
10 100 1000 10000 100000
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
06286-018
FREQUENCY (Hz)
CMRR (dB)
BANDWIDTH
LIMITED
Figure 16. CMRR vs. Frequency
40
60
80
100
120
140
160
1 10 100 1000 10000 100000
GAIN = 1000
GAIN = 100
GAIN = 1
GAIN = 10
06286-019
FREQUENCY (Hz)
CMRR (dB)
BANDWIDTH
LIMITED
Figure 17. CMRR vs. Frequency, 1 kΩ Source Imbalance
0
1
3
5
2
4
6
7
–50 –30 –10 10 30 50 70 90 110 130
06286-020
TEMPERATURE (°C)
CMRR (µV/V)
Figure 18. Change in CMRR vs. Temperature, G = 1
70
–40
100 10M
FREQUENCY (Hz)
GAIN (dB)
1k 10k 100k 1M
60
50
40
30
20
10
0
–10
–20
–30
GAIN = 1
GAIN = 10
GAIN = 100
GAIN = 1000
06286-021
Figure 19. Gain vs. Frequency
OUTPUT VOLTAGE (V)
XXX
NONLINEARITY (10ppm/DIV)
–8–10 –6 –4 –2 0 2 4 6 8 10
R
LOAD
= 2kΩ
R
LOAD
= 10kΩ
V
S
= ±15V
06286-022
Figure 20. Gain Nonlinearity, G = 1
OUTPUT VOLTAGE (V)
XXX
NONLINEARITY (10ppm/DIV)
–8–10 –6 –4 –2 0 2 4 6 8 10
R
LOAD
= 2kΩ
R
LOAD
= 10kΩ
V
S
= ±15V
06286-023
Figure 21. Gain Nonlinearity, G = 10
AD8224 Data Sheet
Rev. C | Page 14 of 28
OUTPUT VOLTAGE (V)
XXX
NONLINE ARIT Y ( 20ppm/DI V )
–8–10 –6 –4 –2 0246810
R
LOAD
= 2kΩ
R
LOAD
= 10kΩ
V
S
= ±15V
06286-024
Figure 22. Gain Nonlinearity, G = 100
OUTPUT VOLTAGE (V)
XXX
NONLINE ARIT Y ( 100ppm/DI V )
–8–10 –6 –4 –2 0 2 46 8 10
R
LOAD
= 2kΩ
R
LOAD
= 10kΩ
V
S
= ±15V
06286-025
Figure 23. Gain Nonlinearity, G = 1000
18
–18
–16 16
OUTPUT VOLTAGE (V)
INPUT COMMON-MODE VOLT AGE (V)
12
6
0
–6
–12
–12 –8 –4 0 4 8 12
–15.3V
+13V
±15V SUPPLIES
±5V SUPPLIES
+14.9V , –8. 3V
+14.9V , +5.5V
+4.95V , –3. 3V
+4.95V , +0.6V
–14.8V , +5. 5V
–14.8V , –8.3V
–4.8V , –3.3V
–4.8V , +0. 6V
–5.3V
+3V
06286-026
Figure 24. Input Common-Mode Voltage Range vs. Output Voltage,
G = 1, VREF = 0 V
0 1 2 3 4 5
4
–1–1 6
OUTPUT VOLTAGE (V)
INPUT COMMON-MODE VOLT AGE (V)
3
2
1
0
–0.3V
+3V
+4.9V , +0.5V
+4.9V , +1.7V
+5V SINGLE SUPPLY,
VREF = +2.5V
+0.1V , +0.5V
+0.1V , +1.7V
06286-027
Figure 25. Input Common-Mode Voltage Range vs. Output Voltage,
G = 1, VS = 5 V, VREF = 2.5 V
18
–18
–16 16
OUTPUT VOLTAGE (V)
INPUT COMMON-MODE VOLT AGE (V)
12
6
0
–6
–12
–12 –8 –4 04 8 12
+13V
–15.3V
±15V SUPPLIES
+14.9V , –9V
+14.9V , +5.4V
+4.9V , +0.5V
+4.9V , –4. 1V
–4.9V , +0. 4V
–4.9V , –4.1V
–5.3V
+3V
–14.8V , –9V
–14.9V , +5. 4V
±5V SUPPLIES
06286-028
Figure 26. Input Common-Mode Voltage Range vs. Output Voltage,
G = 100, VREF = 0 V
0 1 2 3 4 5
4
–1–1 6
OUTPUT VOLTAGE (V)
INPUT COMMON-MODE VOLT AGE (V)
3
2
1
0
+3V
–0.3V
+4.9V , +1.7V
+4.9V , –0. 5V
+0.1V , +1.7V
+0.1V , –0. 5V
+5V SINGLE SUPPLY,
VREF = +2.5V
06286-029
Figure 27. Input Common-Mode Voltage Range vs. Output Voltage,
G = 100, VS = 5 V, VREF = 2.5 V
Data Sheet AD8224
Rev. C | Page 15 of 28
V
S
+
–1
218
SUPPLY VOLTAGE (V)
INPUT VOLTAGE LIMIT (V)
–1
–2
+1
V
S
–
4 6 8 10 12 14 16
–40°C +125°C
+25°C +85°C
+25°C–40°C
NOTES
1. THE AD8224 CAN OPERATE UP TO A V
BE
BELOW
THE NEGATIVE SUPPLY, BUT THE BIAS CURRENT
WILL INCREASE SHARPLY.
+85°C +125°C
06286-030
Figure 28. Input Voltage Limit vs. Supply Voltage, G = 1, VREF =0 V
V
S+
VS–
218
DUAL SUPPLY VOLTAGE (±V)
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
–1
–2
–3
–4
+4
+3
+2
+1
4 6 8 10 12 14 16
–40°C +25°C
+125°C
+85°C
–40°C
+25°C
+85°C
+125°C
06286-031
Figure 29. Output Voltage Swing vs. Dual Supply Voltage,
RLOAD = 2 kΩ, G = 10, VREF = 0 V
V
S
+
V
S
–
218
DUAL SUPPLY VOLTAGE (±V)
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
–0.2
–0.4
+0.4
+0.2
4 6 8 10 12 14 16
+85°C
+125°C +25°C –40°C
–40°C
+25°C
+85°C
+125°C
06286-032
Figure 30. Output Voltage Swing vs. Dual Supply Voltage,
RLOAD = 10 kΩ, G = 10, VREF = 0 V
15
–15
100 10k
R
LOAD
(Ω)
OUTPUT VOLTAGE SWING (V)
1k
10
5
0
–5
–10
+125°C
+85°C
+25°C
–40°C
+125°C
+85°C
+25°C
–40°C
06286-033
Figure 31. Output Voltage Swing vs. Load Resistance, VS = ±15 V, VREF = 0 V
5
0
100 10k
R
LOAD
(Ω)
OUTPUT VOLTAGE SWING (V)
1k
4
3
2
1
–40°C
–40°C
+125°C
+125°C
+25°C
+25°C
+85°C
+85°C
06286-034
Figure 32. Output Voltage Swing vs. Load Resistance, VS = 5 V, VREF = 2.5 V
V
S
+
V
S
–
016
I
OUT
(mA)
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
–1
–2
–3
–4
+4
+3
+2
+1
2 4 6 8 101214
–40°C
+125°C +85°C
+25°C
–40°C
+25°C
+85°C
+125°C
06286-035
Figure 33. Output Voltage Swing vs. Output Current, VS = ±15 V, VREF = 0 V
AD8224 Data Sheet
Rev. C | Page 16 of 28
V
S
+
V
S
–
016
I
OUT
(mA)
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
–1
–2
+2
+1
2 4 6 8 101214
–40°C
+125°C
+85°C
+25°C
+125°C
+25°C
+85°C
06286-036
Figure 34. Output Voltage Swing vs. Output Current, VS = 5 V, VREF = 2.5 V
XX
XX
XX XX
XXX (X)
XXX (X)
5µs/DIV20mV/DIV
100pF
47pF
NO LOAD
06286-037
Figure 35. Small Signal Pulse Response for Various Capacitive Loads,
VS = ±15 V, VREF = 0 V
XX
XX
XX XX
XXX (X)
XXX (X)
5µs/DIV20mV/DIV
100pF
47pF
NO LOAD
06286-038
Figure 36. Small Signal Pulse Response for Various Capacitive Loads,
VS = 5 V, VREF = 2.5 V
35
0
100 10M
FREQUENCY (Hz)
OUTPUT VOLTAGE SWING (V p-p)
1k 10k 100k 1M
30
25
20
15
10
5
GAIN = 1
GAIN = 10, 100, 1000
06286-039
Figure 37. Output Voltage Swing vs. Large Signal Frequency Response
X
X
XX
XX XX
XXX (X)
XXX (X)
20µs/DIV
5µs TO 0.01%
6µs TO 0.001%
5V/DIV
0.002%/DIV
06286-040
Figure 38. Large Signal Pulse Response and Settle Time, G = 1,
RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V
X
X
XX
XX XX
XXX (X)
XXX (X)
20µs/DIV
5V/DIV
4.3μs TO 0.01%
4.6μs TO 0.001%
0.002%/DIV
06286-041
Figure 39. Large Signal Pulse Response and Settle Time, G = 10,
RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V
Data Sheet AD8224
Rev. C | Page 17 of 28
XX
XX
XX XX
XXX (X)
XXX (X)
20µs/DIV
8.1μs TO 0.01%
9.6μs TO 0.001%
0.002%/DIV
5V/DIV
06286-042
Figure 40. Large Signal Pulse Response and Settle Time,
G = 100, RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V
XX
XX
XX XX
XXX (X)
XXX (X)
200µs/DIV
58μs TO 0.01%
74μs TO 0.001%
0.002%/DIV
5V/DIV
06286-043
Figure 41. Large Signal Pulse Response and Settle Time, G = 1000,
RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V
XXX
XXX
4µs/DIV
20mV/DIV
06286-044
Figure 42. Small Signal Pulse Response,
G = 1, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = ±15 V, VREF = 0 V
XXX
XXX
4µs/DIV
20mV/DIV
06286-045
Figure 43. Small Signal Pulse Response,
G = 10, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = ±15 V, VREF = 0 V
XXX
XXX
4µs/DIV
20mV/DIV
06286-046
Figure 44. Small Signal Pulse Response,
G = 100, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = ±15 V, VREF = 0 V
XXX
XXX
20mV/DIV
40µs/DIV
06286-047
Figure 45. Small Signal Pulse Response,
G = 1000, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = ±15 V, VREF = 0 V
AD8224 Data Sheet
Rev. C | Page 18 of 28
XXX
XXX
4µs/DIV
20mV/DIV
06286-048
Figure 46. Small Signal Pulse Response,
G = 1, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = 5 V, VREF = 2.5 V
XXX
XXX
4µs/DIV
20mV/DIV
06286-049
Figure 47. Small Signal Pulse Response,
G = 10, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = 5 V, VREF = 2.5 V
XXX
XXX
4µs/DIV
20mV/DIV
06286-050
Figure 48. Small Signal Pulse Response,
G = 100, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = 5 V, VREF = 2.5 V
XXX
XXX
40µs/DIV
20mV/DIV
06286-051
Figure 49. Small Signal Pulse Response, G = 1000, RLOAD = 2 kΩ,
CLOAD = 100 pF, VS = 5 V, VREF = 2.5 V
15
0020
OUTPUT VOLTAGE STEP SIZE (V)
SETTLING TIME (µs)
10
5
51015
SETTLED TO 0.01%
SETT LED TO 0.001%
06286-052
Figure 50. Settling Time vs. Output Voltage Step Size, (G = 1) ±15 V, VREF = 0 V
100
11 1000
GAIN (V/V)
SETTLING TIME (µs)
10 100
10
SETTLED TO 0.01%
SETTLED TO 0.001%
06286-053
Figure 51. Settling Time vs. Gain for a 10 V Step, VS = ±15 V, VREF = 0 V
Data Sheet AD8224
Rev. C | Page 19 of 28
06286-069
FRE QUENCY ( Hz )
CHANNEL S E P ARATION (dB)
40
60
80
100
120
140
160
180
110 100 1k 10k 100k 1M
THE RM AL CROS S TAL K
VARIES WITH LOAD
GAIN = 1000
GAIN = 1
SOURCE
VOUT = 20V p-p SOURCE V
OUT
SMALLER TO
AVOID SLEW
RATE LI MIT
Figure 52. Channel Separation vs. Frequency,
RLOAD = 2 kΩ, Source Channel at G = 1
–40
–20
0
20
40
60
06286-055
FRE QUENCY ( Hz )
GAIN (d B)
10k1k100 100k 1M 10M
GAIN = 1
GAIN = 10
GAIN = 100
GAIN = 1000
Figure 53. Differential Output Configuration: Gain vs. Frequency
110k1k10010 100k 1M
FRE QUENCY ( Hz )
06286-056
100
90
80
70
60
50
40
30
20
10
0
CMR
OUT
(d B)
LIMITED BY
MEASUREMENT
SYSTEM
CMR
OUT
= 20 log V
DIFF_OUT
V
CM_OUT
Figure 54. Differential Output Configuration:
Common-Mode Output (CMROUT) vs. Frequency
AD8224 Data Sheet
Rev. C | Page 20 of 28
THEORY OF OPERATION
Q2
Q1
NODE A NODE B
NODE C NODE D
VB
C1 C2
A1 A2
–VS
+VS
–VS
J1
+IN
VPINCH
+VS
–VS
J2 –IN
VPINCH
+VS
–VS
RG
+VS+VS
+VS
–VS
20kΩ
20kΩ
20kΩ
20kΩ
+VS
–VS
+VS
–VS
REF
OUTPUT
A3
NODE E
NODE F
I I
R2
24.7kΩ
R1
24.7kΩ
06286-057
Figure 55. Simplified Schematic
The AD8224 is a JFET input, monolithic instrumentation amplifier
based on the classic three op amp topology (see Figure 55). Input
Transistor J1 and Input Transistor J2 are biased at a fixed current so
that any input signal forces the output voltages of A1 and A2 to
change accordingly. The input signal creates a current through RG
that flows in R1 and R2 such that the outputs of A1 and A2 provide
the correct, gained signal. Topologically, J1, A1, and R1 and J2, A2,
and R2 can be viewed as precision current feedback amplifiers. The
common-mode voltage and amplified differential signal from
A1 and A2 are applied to a difference amplifier that rejects the
common-mode voltage but amplifies the differential signal. The
difference amplifier employs 20 kΩ laser trimmed resistors that
result in an in-amp with a gain error of less than 0.04%. New trim
techniques were developed to ensure that the CMRR exceeds 86 dB
(G = 1).
Using JFET transistors, the AD8224 offers an extremely high
input impedance, extremely low bias currents of 10 pA maximum,
low offset current of 0.6 pA maximum, and no input bias
current noise. In addition, input offset is less than 175 µV
and drift is less than 5 µV/°C. Ease of use and robustness were
considered. A common problem for instrumentation amplifiers
is that at high gains, when the input is overdriven, an excessive
milliampere input bias current can result, and the output can
undergo phase reversal.
Overdriving the input at high gains refers to when the input
signal is within the supply voltages but the amplifier cannot
output the gained signal. For example, at a gain of 100, driving
the amplifier with 10 V on ±15 V constitutes overdriving the
inputs because the amplifier cannot output 100 V.
The AD8224 has none of these problems; its input bias current
is limited to less than 10 µA, and the output does not phase
reverse under overdrive fault conditions.
The AD8224 has extremely low load induced nonlinearity. All
amplifiers that comprise the AD8224 have rail-to-rail output
capability for enhanced dynamic range. The input of the AD8224
can amplify signals with wide common-mode voltages even slightly
lower than the negative supply rail. The AD8224 operates over a
wide supply voltage range. It can operate from either a single
+4.5 V to +36 V supply or a dual ±2.25 V to ±18 V. The transfer
function of the AD8224 is
G
R
GkΩ49.4
1+=
Users can easily and accurately set the gain using a single,
standard resistor. Because the input amplifiers employ a current
feedback architecture, the AD8224 gain bandwidth product
increases with gain, resulting in a system that does not experience
as much bandwidth loss as voltage feedback architectures at
higher gains.
GAIN SELECTION
Placing a resistor across the RG terminals sets the gain of the
AD8224. This is calculated by referring to Tabl e 12 or by using
the following gain equation
1
kΩ49.4
−
=G
RG
Data Sheet AD8224
Rev. C | Page 21 of 28
Table 12. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG (Ω) Calculated Gain
49.9 k 1.990
12.4 k 4.984
5.49 k 9.998
2.61 k 19.93
1.00 k
50.40
499 100.0
249 199.4
100 495.0
49.9 991.0
The AD8224 defaults to G = 1 when no gain resistor is used.
The tolerance and gain drift of the RG resistor should be added
to the AD8224 specifications to determine the total gain
accuracy of the system. When the gain resistor is not used,
gain error and gain drift are kept to a minimum.
REFERENCE TERMINAL
The output voltage of the AD8224 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF1 pin or the
REF2 pin to level-shift the output so that the AD8224 can drive
a single-supply ADC. Pin REFx is protected with ESD diodes
and should not exceed either +VS or −VS by more than 0.5 V.
For best performance, source impedance to the REF terminal
should be kept below 1 Ω. As shown in Figure 55, the reference
terminal, REF, is at one end of a 20 kΩ resistor. Additional
impedance at the REF terminal adds to this 20 kΩ resistor and
results in amplification of the signal connected to the positive
input. The amplification from the additional RREF can be
computed by
( )
REF
REF
R
R
+
+
kΩ
40
kΩ
202
Only the positive signal path is amplified; the negative path is
unaffected. This uneven amplification degrades the CMRR of
the amplifier.
INCORRECT
AD8224
V
REF
CORRECT
AD8224
OP2177
+
–
V
REF
CORRECT
AD8224
AD8224
+
–
V
REF
06286-058
Figure 56. Driving the Reference Pin
LAYOUT
The AD8224 is a high precision device. To ensure optimum
performance at the PCB level, care must be taken in the design
of the board layout. The AD8224 pinout is arranged in a logical
manner to aid in this task.
Package Considerations
The AD8224 is available in two version s of the 16-lead, 4 mm ×
4 mm LFCSP package: with or without an exposed paddle. Blindly
copying the footprint from another 4 mm × 4 mm LFCSP part
is not recommended because it may not have the same thermal
pad size and leads. Refer to the Outline Dimensions section to
verify that the PCB symbol has the correct dimensions.
Hidden Paddle Package
The AD8224 is available in an LFCSP package with a hidden
paddle. It is the preferred package for the AD8224. Unlike
chip scale packages where the pad limits routing capability,
this package allows routes and vias directly underneath the
chip, so that the full space savings of the small LFCSP can be
realized. Although the package has no metal in the center of
the part, the manufacturing process does leave a very small
section of exposed metal at each of the package corners, shown
in Figure 57 as well as Figure 68 in the Outline Dimensions
section. This metal is connected to +VS through the part.
Because of a possibility of a short, vias should not be placed
underneath these exposed metal tabs.
06286-101
HIDDEN
PADDLE
BOTTOM VIEW
EXPOSED LEAD
FRAM E TABS
NOTES
1. EXP OSED LEAD FRAME TABS AT THE FO UR CORNERS
OF THE P ACKAGE ARE INTE RNALL Y CONNECT E D TO
+VS. REFER TO THE OUTLINE DIMENSIONS PAGE, FOR
FURTHER I NFO RM ATION O N P ACKAGE AVAIL ABIL ITY .
Figure 57. Hidden Paddle Package: Bottom View
Exposed Paddle Package
The AD8224 4 mm × 4 mm LFCSP is also available with an
exposed thermal paddle package version. This pad is connected
internally to +VS. The pad can either be left unconnected or
connected to the positive supply rail. Space between the leads
and thermal pad should be kept as wide as possible for the best
bias current performance. To maintain the AD8224 ultralow
bias current performance, the thermal pad area can be reduced
to extend the gap between the leads and the pad. The exposed
paddle package also has exposed lead frame tabs at the corners
of the package, similar to those of the hidden paddle package,
which are internally connected to +VS. Do not place vias
underneath these metal tabs.
AD8224 Data Sheet
Rev. C | Page 22 of 28
To preserve maximum pin compatibility with other dual
instrumentation amplifiers, such as the AD8222, leave the pad
unconnected. This can be done by not soldering the paddle at
all or by soldering the part to a landing that is a not connected
to any other net. For high vibration applications, a landing is
recommended.
Because the AD8224 dissipates little power, heat dissipation is
rarely an issue. If improved heat dissipation is desired (for example,
when driving heavy loads), connect the exposed pad to the
positive supply rail. For the best heat dissipation performance,
the positive supply rail should be a plane in the board. See
the Thermal Resistance section for more information.
Common-Mode Rejection over Frequency
The AD8224 has a higher CMRR over frequency than typical
in-amps, which gives it greater immunity to disturbances, such
as line noise and its associated harmonics. A well-implemented
layout is required to maintain this high performance. Input
source impedances should be matched closely. Source resistance
should be placed close to the inputs so that it interacts with as
little parasitic capacitance as possible.
Parasitics at the RGx pins can also affect CMRR over frequency.
The PCB should be laid out so that the parasitic capacitances at
each pin match. Traces from the gain setting resistor to the RGx
pins should be kept short to minimize parasitic inductance.
Reference
Errors introduced at the reference terminal feed directly to
the output. Take care to tie the REFx pins to the appropriate
local ground.
Power Supplies
A stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect
performance.
The AD8224 has two positive supply pins (Pin 5 and Pin 16)
and two negative supply pins (Pin 8 and Pin 13). While the part
functions with only one pin from each supply pair connected,
both pins should be connected for specified performance and
optimum reliability.
The AD8224 should be decoupled with 0.1 µF bypass capacitors,
one for each supply. Place the positive supply decoupling
capacitor near Pin 16, and the negative supply decoupling
capacitor near Pin 8. Each supply should also be decoupled with
a 10 µF tantalum capacitor. The tantalum capacitor can be
placed further away from the AD8224 and can generally be
shared by other precision integrated circuits. Figure 58 shows an
example layout.
AD8224
1
2
3
4
12
11
9
5678
13
14
1516
0.1µF
0.1µF
R
G
R
G
10
06286-059
Figure 58. Example Layout
SOLDER WASH
The solder process can leave flux and other contaminants on
the board. When these contaminants are between the AD8224
leads and thermal pad, they can create leakage paths that are
larger than the AD8224 bias currents. A thorough washing
process removes these contaminants and restores the device’s
excellent bias current performance.
INPUT BIAS CURRENT RETURN PATH
The input bias current of the AD8224 must have a return path
to common. When the source, such as a transformer, cannot
provide a return current path, one should be created, as shown
in Figure 59.
INPUT PROTECTION
All terminals of the AD8224 are protected against ESD. ESD
protection is guaranteed to 4 kV (human body model). In addition,
the input structure allows for dc overload conditions a diode
drop above the positive supply and a diode drop below the
negative supply. Voltages beyond a diode drop of the supplies
cause the ESD diodes to conduct and enable current to flow
through the diode. Therefore, an external resistor should be
used in series with each of the inputs to limit current for
voltages beyond the supplies. In either scenario, the AD8224
safely handles a continuous 6 mA current at room temperature.
Data Sheet AD8224
Rev. C | Page 23 of 28
For applications where the AD8224 encounters extreme
overload voltages, as in cardiac defibrillators, external series
resistors and low leakage diode clamps, such as BAV199Ls,
FJH1100s, or SP720s, should be used.
TRANSFORMER
+V
S
REF
–V
S
AD8224
INCORRECT
TRANSFORMER
+V
S
REF
–V
S
AD8224
CORRECT
CAPACITI V E LY CO UP LED
+V
S
REF
C
C
–V
S
AD8224
CAPACITI V E LY CO UP LED
+V
S
REF
C
R
R
C
–V
S
AD8224
1
f
HIGH-PASS
= 2πRC
06286-060
Figure 59. Creating an IBIAS Path
RF INTERFERENCE
RF rectification is often a problem in applications where there are
large RF signals. The problem appears as a small dc offset voltage.
The AD8224 by its nature has a 5 pF gate capacitance (CG) at its
inputs. Matched series resistors form a natural low-pass filter that
reduces rectification at high frequency (see Figure 60).
AD8224
V
OUT
C
G
C
G
–V
S
REF
–V
S
R
R
+IN
–IN
+15V
–15V
0.1µF 10µF
0.1µF 10µF
06286-061
+
+
Figure 60. RFI Filtering Without External Capacitors
The relationship between external, matched series resistors and
the internal gate capacitance is expressed as
G
DIFF RC
FilterFreq π
=2
1
G
CM RC
FilterFreq π
=2
1
To eliminate high frequency common-mode signals while using
smaller source resistors, a low-pass RC network can be placed at
the input of the instrumentation amplifier (see Figure 61). The
filter limits the input signal bandwidth according to the
following relationship:
)2(2
1
G
CD
DIFF CCCR
FilterFreq
++π
=
)(2
1
G
C
CM CCR
FilterFreq
+π
=
Mismatched CC capacitors result in mismatched low-pass filters.
The imbalance causes the AD8224 to treat what would have
been a common-mode signal as a differential signal. To reduce
the effect of mismatched external CC capacitors, select a value of
CD greater than 10 times CC. This sets the differential filter
frequency lower than the common-mode frequency.
R
R
AD8224
+15V
+IN
–IN
0.1µF 10µF
10µF
0.1µF
REF
V
OUT
–15V
C
D
C
C
C
C
10nF
1nF
1nF
4.02kΩ
4.02kΩ
06286-062
+
+
Figure 61. RFI Suppression
COMMON-MODE INPUT VOLTAGE RANGE
The 3-op amp architecture of the AD8224 applies gain and then
removes the common-mode voltage. Therefore, internal nodes
in the AD8224 experience a combination of both the gained
signal and the common-mode signal. This combined signal can
be limited by the voltage supplies even when the individual input
and output signals are not. Figure 24 through Figure 27 show the
allowable common-mode input voltage ranges for various
output voltages, supply voltages, and gains.
AD8224 Data Sheet
Rev. C | Page 24 of 28
APPLICATIONS INFORMATION
DRIVING AN ADC
An instrumentation amplifier is often used in front of an ADC
to provide CMRR and additional conditioning such as a voltage
level shift and gain (see Figure 62). In this example, a 2.7 nF
capacitor and a 500 Ω resistor create an antialiasing filter for the
AD7685. The 2.7 nF capacitor also serves to store and deliver
the necessary charge to the switched capacitor input of the ADC.
The 500 Ω series resistor reduces the burden of the 2.7 nF load
from the amplifier. However, large source impedance in front of
the ADC can degrade the total harmonic distortion (THD).
For applications where THD performance is critical, the series
resistor needs to be small. At worst, a small series resistor can
load the AD8224, potentially causing the output to overshoot
or ring. In such cases, a buffer amplifier, such as the AD8615
should be used after the AD8224 to drive the ADC.
AD8224
AD7685
4.7µF
ADR435
+5V
2.7nF
REF
500Ω
1.07kΩ
+2.5V
+IN
–IN
±50mV
+5V
0.1µF10µF
06286-063
+
Figure 62. Driving an ADC in a Low Frequency Application
DIFFERENTIAL OUTPUT
The differential configuration of the AD8224 has the same
excellent dc precision specifications as the single-ended output
configuration and is recommended for applications in the
frequency range of dc to 1 MHz.
The circuit configuration, outlined in Table 4 and Table 7, refers
to the configuration shown in Figure 63 only. The circuit includes
an RC filter that maintains the stability of the loop.
The transfer function for the differential output is
VDIFF_OUT = V+OUT − V−OUT = (V+IN − V−IN) × G
where:
GR
GkΩ49.4
1+=
+IN
–IN
+
–
+
–
AD8224
AD8224
+OUT
33pF
–OUT
+IN2
REF2
20kΩ
R
G
06286-064
Figure 63. Differential Circuit Schematic
Setting the Common-Mode Voltage
The output common-mode voltage is set by the average of +IN2
and REF2. The transfer function is
VCM_OUT = (V+OUT + V−OUT)/2 = (V+IN2 + VREF2)/2
+IN2 and REF2 have different properties that allow the
reference voltage to be easily set for a wide variety of applications.
+IN2 has high impedance but cannot swing to the positive
supply rail. REF2 must be driven with a low impedance but
can go 300 mV beyond the supply rails.
A common application sets the common-mode output voltage
to the midscale of a differential ADC. In this case, the ADC
reference voltage is sent to the +IN2 terminal, and ground is
connected to the REF2 terminal. This produces a common-
mode output voltage of half the ADC reference voltage.
2-Channel Differential Output Using a Dual Op Amp
Another differential output topology is shown in Figure 64.
Instead of a second in-amp, ½ of a dual OP2177 op amp creates
the inverted output. Because the OP2177 comes in an MSOP,
this configuration allows the creation of a dual-channel, precision
differential output in-amp with little board area.
Errors from the op amp are common to both outputs and are,
thus, common mode. Errors from mismatched resistors also
create a common-mode dc offset. Because these errors are
common mode, they are likely to be rejected by the next
device in the signal chain.
+IN
–IN
REF
AD8224
V
REF
4.99kΩ
+
–OP2177
+OUT
–OUT
4.99kΩ
06286-065
Figure 64. Differential Output Using Op Amp
Data Sheet AD8224
Rev. C | Page 25 of 28
AD8224
(DIFF OUT)
100pF
NPO
5%
100pF
NPO
5%
1000pF
–IN
+IN
0.1µF
10µF
0.1µF
10µF
–12V
+12V
1kΩ
1kΩ
+
+
IN+ VDD
GND REF
10µF
X5R
AD7688
IN–
0.1µF
+5V
ADR435
GND
V
IN
V
OUT
0.1µF
+12V
0.1µF
+5V REF
+IN2 REF2
+5V REF
+OUT
–OUT
806Ω
2.7nF 2.7nF
806Ω
06286-066
Figure 65. Driving a Differential ADC
DRIVING A DIFFERENTIAL INPUT ADC
The AD8224 can be configured in differential output mode
to drive a differential ADC. Figure 65 illustrates several of the
concepts.
First Antialiasing Filter
The 1 kΩ resistor, 1000 pF capacitor, and 100 pF capacitors in
front of the in-amp form a 76 kHz filter. This is the first of two
antialiasing filters in the circuit and helps to reduce the noise of
the system. The 100 pF capacitors protect against common-
mode RFI signals. Note that they are 5% COG/NPO types.
These capacitors match well over time and temperature,
which keeps the CMRR of the system high over frequency.
Second Antialiasing Filter
An 806 Ω resistor and a 2.7 nF capacitor are located between
each AD8224 output and ADC input. These components create
a 73 kHz low-pass filter for another stage of antialiasing
protection.
These four elements also isolate the ADC from loading the
AD8224. The 806 Ω resistor shields the AD8224 from the
switched capacitor input of the ADC, which looks like a time-
varying load. The 2.7 nF capacitor provides a charge to the
switched capacitor front end of the ADC. If the application
requires a lower frequency antialiasing filter, increase the value
of the capacitor rather than the resistor.
The 806 Ω resistors can also protect an ADC from overvoltages.
Because the AD8224 runs on wider supply voltages than a
typical ADC, there is a possibility of overdriving the ADC. This
is not an issue with a PulSAR® converter, such as the AD7688.
Its input can handle a 130 mA overdrive, which is much higher
than the short-circuit limit of the AD8224.
However, other converters have less robust inputs and may need
the added protection.
Reference
The ADR435 supplies a reference voltage to both the ADC and
the AD8224. Because REF2 on the AD8224 is grounded, the
common-mode output voltage is precisely half the reference
voltage, exactly where it needs to be for the ADC.
DRIVING CABLING
All cables have a certain capacitance per unit length, which
varies widely with cable type. The capacitive load from the cable
may cause peaking in the AD8224 output response. To reduce
peaking, use a resistor between the AD8224 and the cable.
Because cable capacitance and desired output response vary
widely, this resistor is best determined empirically. A good
starting point is 50 Ω.
The AD8224 operates at a low enough frequency that
transmission line effects are rarely an issue; therefore, the
resistor need not match the characteristic impedance of
the cable.
AD8224
(DIFF OUT)
AD8224
(SINGLE OUT)
06286-067
Figure 66. Driving a Cable
AD8224
Rev. C | Page 26 of 28
OUTLINE DIMENSIONS
COMPLIANT
TO
JEDEC S TANDARDS MO-220- V GGC
04-06-2012-A
1
0.65
BSC
0.25 M IN
PI N 1
INDICATOR
1.95 RE F
0.50
0.40
0.30
TOP VIEW
12° M AX 0. 80 M AX
0.65 TYP
SEATING
PLANE COPLANARITY
0.08
1.00
0.85
0.80
0.30
0.23
0.18
0.05 M AX
0.02 NOM
0.20 RE F
2.65
2.50 S Q
2.35
16
5
13
8
9
12
4
0.60 M AX
0.60 M AX
PI N 1
INDICATOR
4.10
4.00 S Q
3.90
3.75 BS C
SQ
EXPOSED
PAD
FOR PRO P E R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE P IN CONFI GURATIO N AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
BOTTOM VIEW
Figure 67. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-13)
Dimensions are shown in millimeters
COMPLIANT
TO
JEDEC S TANDARDS MO-263- V BBC
04-06-2012-A
1
0.65
BSC
1.95 RE F
0.75
0.60
0.50
TOP VIEW
12° M AX 0. 80 M AX
0.65 TYP
SEATING
PLANE COPLANARITY
0.08
1.00
0.85
0.80
0.35
0.30
0.25
0.05 M AX
0.02 NOM
0.20 RE F
16
5
13
8
9
12
4
0.60 M AX
0.60 M AX
PI N 1
INDICATOR
4.10
4.00 S Q
3.90
3.75 BS C
SQ
BOTTOM VIEW
Figure 68. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad, with Hidden Paddle
(CP-16-19)
Dimensions shown in millimeters
Data Sheet AD8224
Rev. C | Page 27 of 28
ORDERING GUIDE
Model
1
Temperature Range
Product Description
Package Option
AD8224ACPZ-R7 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-13
AD8224ACPZ-RL
−40°C to +85°C
16-Lead LFCSP_VQ
CP-16-13
AD8224ACPZ-WP −40°C to +85°C 16-Lead LFCSP_VQ CP-16-13
AD8224BCPZ-R7 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-13
AD8224BCPZ-RL −40°C to +85°C 16-Lead LFCSP_VQ CP-16-13
AD8224BCPZ-WP −40°C to +85°C 16-Lead LFCSP_VQ CP-16-13
AD8224HACPZ-R7 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-19
AD8224HACPZ-RL −40°C to +85°C 16-Lead LFCSP_VQ CP-16-19
AD8224HACPZ-WP −40°C to +85°C 16-Lead LFCSP_VQ CP-16-19
AD8224HBCPZ-R7 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-19
AD8224HBCPZ-RL −40°C to +85°C 16-Lead LFCSP_VQ CP-16-19
AD8224HBCPZ-WP −40°C to +85°C 16-Lead LFCSP_VQ CP-16-19
AD8224-EVALZ
Evaluation Board
1 Z = RoHS Compliant Part.
AD8224
Rev. C | Page 28 of 28
NOTES
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registered trademarks are the property of their respective owners.
D06286-0-12/13(C)
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