Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper TM 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 1 Introduction The last issue of this data sheet was July 12, 2004 - Revision 9. A change history is included in Section 13, Change History, on page 72. Red change bars have been installed on all text, figures and tables that were added or changed. All changes to the text are highlighted in red. Changes within figures, and the figure title itself, are highlighted in red, if feasible. Formatting or grammatical changes have not been highlighted. Deleted sections, paragraphs, figures or tables will be specifically mentioned. The documentation package for the TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 system chip consists of the following documents: The Register Description and the System Design Guide. These two documents are available on a password-protected website. The Ultramapper Product Description, and the Ultramapper Hardware Design Guide (this document). These two documents are available on the public website shown below. If the reader displays this document using Acrobat Reader (R), clicking on any blue text will bring the reader to that reference point. To access related documents, including the documents mentioned above, please go to the following public website, or contact your Agere representative (see the last page of this document). http://www.agere.com/enterprise_metro_access/index.html This document describes the hardware interfaces to the Agere Systems Inc. TMXF84622 Ultramapper device. Information relevant to the use of the device in a board design is covered. Pin descriptions, dc electrical characteristics, timing diagrams, ac timing parameters, packaging, and operating conditions are included. 622/155 Mbits/s SONET/SDH ADM Front End DS3/E3/DS2/DS1/E1/DS0 PDH Tributary Termination LOPOH 6 High-Speed IF 8 TMUX Clock/Sync Protection Link 622 Mb/STS-12/STM-4 155 Mb/STS-3/STM-1 Clock and Data 8 STS-12/ STM-4/ STS-3/ STM-1 SPEMPR (x3) (0-2) DS1/J1/E1 VT/TU DS2/E2 DS3/E3 (x3) x28/x21 VTMPR STS-1 LT (x3) Miscellaneous 24 6 MPU JTAG IF 49 (x6) DS3/E3 (x3) STS-1 24 (x3) NSMI (x3) STS-1 (x3) (x3) (x3) MPU IF STS-3/STM-1 Mate DS3/E3 PLL IF (Optional) Interconnect Shared Low-Speed I/O Switching Modes 8PSB (x16): x84/X63 DS1/J1/E1 x2016 DS0/E0 4CHI (x42): x2016 DS0/E0 1 (x3) (x3) E13 M13 MUX MUX MCDR 12 (Total of 3 STS-1 Max) 204 3 3 1 X3 x28/x21 DS1/E1 6 5 42 MRXC S T S X C CDR JTAG FRM PLL IF 5 System Interfaces STSPP 6 Rx/Tx Clocks and Sync TPG/TPM SPEMPR (x3) (3-5) CDR CHI/PSB 5 FRM (X3) x28/x21 DS1/J1/E1 CG LOPOH 622 Mb/STS-12/STM-4 155 Mb/STS-3/STM-1 Clock and Data x6 DS3/E3 DJA DJA 1 6 1 2 DS2, E2, VC12 VC11 AIS Clocks DS1XCLK, E1XCLK Transport Modes 4DS1/J1/E1 (x30): x28/x21 + prot. 4DS2/E2 (X30): x21/x12 + prot. 4VT/TU (X30): x28/x21 + prot. Power and GND pins not shown 6 2 TOAC POAC DS3XCLK, E3XCLK 01/18/02 Ultramapper Figure 1-1. Ultramapper Block Diagram and High-Level Interface Definition TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 Table of Contents Contents Page 1 Introduction ........................................................................................................................................................................1 2 Pin Information ...................................................................................................................................................................6 2.1 Ball Diagram ................................................................................................................................................................6 2.2 Package Pin Assignments ...........................................................................................................................................7 2.3 Pin Matrix ...................................................................................................................................................................15 2.4 Pin Types ...................................................................................................................................................................17 2.5 Pin Definitions ............................................................................................................................................................18 3 Operating Conditions and Reliability ................................................................................................................................35 3.1 Absolute Maximum Ratings .......................................................................................................................................35 3.2 Recommended Operating Conditions .......................................................................................................................35 3.3 Handling Precautions ................................................................................................................................................35 3.4 Thermal Parameters (Definitions and Values) ...........................................................................................................36 3.5 Reliability ...................................................................................................................................................................37 3.6 Recommended Powerup Sequence ..........................................................................................................................37 3.7 Power Consumption ..................................................................................................................................................38 4 Electrical Characteristics .................................................................................................................................................39 4.1 LVCMOS Interface Specifications .............................................................................................................................39 4.2 LVDS Interface Characteristics .................................................................................................................................40 5 Timing ..............................................................................................................................................................................41 5.1 TMUX High-Speed Interface Timing ..........................................................................................................................41 5.2 THSSYNC Characteristics .........................................................................................................................................42 5.3 STS-3/STM-1 Mate Interconnect Timing ...................................................................................................................44 5.4 TOAC, POAC, and LOPOH Timing ...........................................................................................................................45 5.5 DS3/E3/STS-1 Timing ...............................................................................................................................................46 5.6 NSMI Timing ..............................................................................................................................................................47 5.7 Shared Low-Speed Line Timing ................................................................................................................................51 5.8 CHI Timing .................................................................................................................................................................51 5.9 Parallel System Bus (PSB) Timing ............................................................................................................................54 6 Reference Clocks ............................................................................................................................................................55 7 Microprocessor Interface Timing .....................................................................................................................................60 7.1 Synchronous Write Mode ..........................................................................................................................................60 7.2 Synchronous Read Mode ..........................................................................................................................................62 7.3 Asynchronous Write Mode ........................................................................................................................................63 7.4 Asynchronous Read Mode ........................................................................................................................................65 8 Other Timing ....................................................................................................................................................................67 9 Hardware Design File References ...................................................................................................................................67 10 700-Pin PBGAM1T Diagrams ........................................................................................................................................68 11 Ordering Information ......................................................................................................................................................70 12 Glossary .........................................................................................................................................................................71 13 Change History ...............................................................................................................................................................72 13.1 Changes to this Document Since Revision 9 .........................................................................................................72 13.2 Navigating Through an Adobe Acrobat (R) Document .............................................................................................72 2 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table of Contents (continued) Tables Page Table 2-1. Package Pin Assignments in Signal Name Order .................................................................................................7 Table 2-2. Package Pin Matrix .............................................................................................................................................15 Table 2-3. Pin Types ............................................................................................................................................................17 Table 2-4. TMUX Block, High-Speed Interface I/O...............................................................................................................18 Table 2-5. TMUX Block, Protection Link I/O.........................................................................................................................18 Table 2-6. TMUX Block, Clock, and Sync I/O.......................................................................................................................19 Table 2-7. STS Cross Connect (STSXC) Block, STS-3/STM-1 Mate Interconnect..............................................................20 Table 2-8. Synchronous Payload Envelope (SPE) Mapper Block, External PLL Control.....................................................20 Table 2-9. Multirate Cross Connect (MRXC) Block, TOAC Input and Output Channels ......................................................21 Table 2-10. Multirate Cross Connect (MRXC) Block, POAC Input and Output Channels....................................................21 Table 2-11. DS3/E3/STS-1 Out ............................................................................................................................................22 Table 2-12. DS3/E3/STS-1 In...............................................................................................................................................22 Table 2-13. NSMI/STS-1 In ..................................................................................................................................................23 Table 2-14. NSMI/STS-1 Out ...............................................................................................................................................24 Table 2-15. Shared Low-Speed Line In................................................................................................................................24 Table 2-16. Shared Low-Speed Line Out .............................................................................................................................25 Table 2-17. TDM Concentration Highway (CHI) In...............................................................................................................26 Table 2-18. TDM Concentration Highway (CHI) Out ............................................................................................................27 Table 2-19. Framer (FRM) Block, CHI/Parallel System Bus (PSB) Clock and Sync............................................................28 Table 2-20. Reference Clocks ..............................................................................................................................................29 Table 2-21. Low-Order Path Overhead Access, Transmit Direction ....................................................................................29 Table 2-22. Low-Order Path Overhead Access, Receive Direction .....................................................................................30 Table 2-23. Clock Generator ................................................................................................................................................30 Table 2-24. Microprocessor Interface...................................................................................................................................31 Table 2-25. Boundary Scan (IEEE(R) 1149.1) ........................................................................................................................32 Table 2-26. General-Purpose Interface ................................................................................................................................32 Table 2-27. CDR Interface....................................................................................................................................................32 Table 2-28. Analog Power and Ground Signals ...................................................................................................................33 Table 2-29. Digital Power and Ground Signals ....................................................................................................................34 Table 3-1. Absolute Maximum Ratings.................................................................................................................................35 Table 3-2. Recommended Operating Conditions .................................................................................................................35 Table 3-3. ESD Tolerance ....................................................................................................................................................35 Table 3-4. Thermal Parameter Values .................................................................................................................................36 Table 3-5. Reliability Data ....................................................................................................................................................37 Table 3-6. Moisture Sensitivity Level....................................................................................................................................37 Table 3-7. Typical Power Consumption by Application ........................................................................................................38 Table 3-8. Typical Power Consumption Per Block ...............................................................................................................38 Table 4-1. LVCMOS Input Specifications .............................................................................................................................39 Table 4-2. LVCMOS Output Specifications ..........................................................................................................................39 Table 4-3. LVCMOS Bidirectional Specifications .................................................................................................................39 Table 4-4. LVDS Interface dc Characteristics ......................................................................................................................40 Table 5-1. High-Speed Interface Inputs Specifications ........................................................................................................41 Table 5-2. Protection Link Inputs Specifications...................................................................................................................42 Table 5-3. High-Speed Interface Outputs Specifications......................................................................................................42 Table 5-4. Protection Link Output Specifications..................................................................................................................42 Table 5-5. STS-3/STM-1 Mate Interconnect Input Specifications ........................................................................................44 Table 5-6. STS-3/STM-1 Mate Interconnect Output Specifications......................................................................................44 Table 5-7. TOAC, POAC, and LOPOH Inputs Specifications...............................................................................................45 Table 5-8. TOAC, POAC, and LOPOH Outputs Specifications............................................................................................45 Table 5-9. DS3/E3 Inputs Specifications ..............................................................................................................................46 Table 5-10. STS-1 Inputs Specifications ..............................................................................................................................46 Table 5-11. DS3/E3/STS-1 Outputs Specifications ..............................................................................................................46 Table 5-12. NSMI Inputs Specifications ...............................................................................................................................50 Table 5-13. NSMI Outputs Specifications.............................................................................................................................50 Table 5-14. Shared Low-Speed Line Timing Input Specifications........................................................................................51 Agere Systems Inc. 3 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 9 April 5, 2005 Table of Contents (continued) Tables Page Table 5-15. Shared Low-Speed Line Timing Output Specifications .....................................................................................51 Table 5-16. CHIRXGCLK and CHITXGCLK Timing Specifications......................................................................................51 Table 5-17. CHI Interface Timing Specifications ..................................................................................................................52 Table 5-18. PSB Inputs Specifications .................................................................................................................................54 Table 5-19. PSB Output Specifications ................................................................................................................................54 Table 6-1. High-Speed Interface Input Clocks Specifications ..............................................................................................55 Table 6-2. Protection Link Input Clock Specifications ..........................................................................................................55 Table 6-3. DS3/E3/STS-1 Input Clocks Specifications.........................................................................................................55 Table 6-4. DS1/E1 DJA Input Clocks Specifications ............................................................................................................55 Table 6-5. M13/E13 Input Clocks Specifications ..................................................................................................................56 Table 6-6. DS3/E3 DJA Input Clocks Specifications ............................................................................................................56 Table 6-7. LOPOH Input Clock Specifications......................................................................................................................56 Table 6-8. Microprocessor Interface Input Clocks Specifications.........................................................................................56 Table 6-9. Framer PLL Input Clocks Specifications .............................................................................................................56 Table 6-10. CHI Input Clocks Specifications ........................................................................................................................56 Table 6-11. PSB Input Clocks Specifications .......................................................................................................................57 Table 6-12. High-Speed Interface Output Clocks Specifications..........................................................................................57 Table 6-13. Protection Link Output Clocks Specifications....................................................................................................57 Table 6-14. Line Timing Interface Output Clocks Specifications ..........................................................................................57 Table 6-15. TOAC Output Clocks Specifications..................................................................................................................57 Table 6-16. POAC Output Clocks Specifications .................................................................................................................58 Table 6-17. DS3/E3/STS-1 Output Clocks Specifications ....................................................................................................58 Table 6-18. LOPOH Output Clock Specifications.................................................................................................................58 Table 6-19. NSMI Output Clocks Specifications...................................................................................................................58 Table 6-20. Framer PLL Output Clocks Specifications.........................................................................................................58 Table 6-21. Shared Low-Speed Receive Line Input/Output Clocks Specifications ..............................................................58 Table 6-22. Shared Low-Speed Transmit Line Input/Output Clocks Specifications .............................................................59 Table 6-23. NSMI Input/Output Clocks Specifications..........................................................................................................59 Table 7-1. Microprocessor Interface Synchronous Write Cycle Specifications ....................................................................61 Table 7-2. Microprocessor Interface Synchronous Read Cycle Specifications ....................................................................62 Table 7-3. Microprocessor Interface Asynchronous Write Cycle Specifications ..................................................................64 Table 7-4. Microprocessor Interface Asynchronous Read Cycle Specifications ..................................................................66 Table 8-1. General-Purpose Inputs Specifications ...............................................................................................................67 Table 8-2. Miscellaneous Output Specifications...................................................................................................................67 Table 8-3. General-Purpose Output Specifications ..............................................................................................................67 Table 11-1. Ordering Information .........................................................................................................................................70 Table 13-1. Document Changes...........................................................................................................................................72 4 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table of Contents (continued) Figures Page Figure 1-1. Ultramapper Block Diagram and High-Level Interface Definition.........................................................................1 Figure 2-1. Ultramapper Package Diagram (Top View) .........................................................................................................6 Figure 5-1. TMUX LVDS Signal Rise/Fall Timing.................................................................................................................41 Figure 5-2. TMUX LVDS Clock and Data Timing .................................................................................................................41 Figure 5-3. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 1)................................................................................42 Figure 5-4. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 0)................................................................................43 Figure 5-5. THSSYNC Timing Diagram for Synchronized VTs ............................................................................................43 Figure 5-6. Relationship Between THSSYNC and THSD ....................................................................................................43 Figure 5-7. STS-3/STM-1 Mate Rise/Fall Timing .................................................................................................................44 Figure 5-8. STS-3/STM-1 Mate Clock and Data Timing.......................................................................................................44 Figure 5-9. TOAC, POAC Timing .........................................................................................................................................45 Figure 5-10. LOPOH Timing.................................................................................................................................................45 Figure 5-11. DS3/E3 Interface Diagram in M13/E13 Block ..................................................................................................46 Figure 5-12. NSMI Clock and Data Timing for the STS-1 Mode ..........................................................................................47 Figure 5-13. NSMI Clock and Data Diagram for SPEMPR NSMI Mode...............................................................................47 Figure 5-14. NSMI Clock and Data Diagram for M13 NSMI Mode (NSMI <---> M13 <---> DS3 External I/O).....................48 Figure 5-15. NSMI Clock and Data Diagram for E13 NSMI Mode 1 (NSMI <---> E13 <---> E3 External I/O.......................48 Figure 5-16. NSMI Clock and Data Diagram for E13 NSMI Mode 2 (NSMI <--> E13 <--> SPEMPR <--> STM-N) .............49 Figure 5-17. NSMI Clock and Data Diagram for Framer (FRM) NSMI Mode .......................................................................50 Figure 5-18. Shared Low-Speed Line Clock and Data Timing .............................................................................................51 Figure 5-19. CHI Clock Timing .............................................................................................................................................51 Figure 5-20. CHI Bus Timing ................................................................................................................................................52 Figure 5-21. Typical Receive CHI Timing (Non-CMS Mode--FRM_CMS = 0) ....................................................................52 Figure 5-22. Transmit CHI Timing (Non-CMS Mode--FRM_CMS = 0)................................................................................53 Figure 5-23. Typical Receive CHI Timing (CMS Mode--FRM_CMS = 1, CHIRX/TXGCLK S 4 MHz).................................53 Figure 5-24. Transmit CHI Timing (CMS Mode--FRM_CMS = 1, CHIRX/TXGCLK S 4 MHz))...........................................53 Figure 5-25. PSB Clock and Data Timing.............................................................................................................................54 Figure 7-1. Microprocessor Interface Synchronous Write Cycle--MPMODE Pin = 1 ..........................................................60 Figure 7-2. Microprocessor Interface Synchronous Read Cycle--MPMODE Pin = 1 ..........................................................62 Figure 7-3. Microprocessor Interface Asynchronous Write Cycle--MPMODE Pin = 0 ........................................................63 Figure 7-4. Microprocessor Interface Asynchronous Read Cycle--MPMODE Pin = 0 ........................................................65 Figure 10-1. 700-Pin PBGAM1T Physical Dimension ..........................................................................................................68 Figure 10-2. Bottom View of 700-Pin PBGAM1T Balls Location ..........................................................................................69 Agere Systems Inc. 5 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 2 Pin Information 2.1 Ball Diagram The TMXF84622 Ultramapper is housed in a 700-pin plastic ball grid array. Figure 1-1 shows the ball assignment viewed from the top of the package. The pins are spaced on a 1.0 mm pitch. 2 1 4 6 5 3 8 10 9 7 14 12 11 16 15 13 18 17 22 20 24 23 21 19 30 28 26 29 27 25 32 34 33 31 A A C C E E G G J J L L N N R R U U W W AA AA AC AC AE AE AG AG AJ AJ AL AL AN AN B B D D F F H H K K M M P P T T V V Y Y AB AB AD AD AF AF AH AH AK AK AM AM AP AP 2 1 4 3 8 6 5 7 10 9 14 12 11 13 16 15 18 17 22 20 19 21 24 23 30 28 26 25 27 29 32 31 34 33 Figure 2-1. Ultramapper Package Diagram (Top View) 6 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 2.2 Package Pin Assignments Table 2-1. Package Pin Assignments in Signal Name Order Signal Name Pin Signal Name Pin ADDR[0] ADDR[1] ADDR[2] ADDR[3] ADDR[4] ADDR[5] ADDR[6] ADDR[7] ADDR[8] ADDR[9] ADDR[10] ADDR[11] ADDR[12] ADDR[13] ADDR[14] ADDR[15] ADDR[16] ADDR[17] ADDR[18] ADDR[19] ADDR[20] ADSN APS_INTN BYPASS CG_PLLCLKOUT CHIRXDATA[1] CHIRXDATA[2] CHIRXDATA[3] CHIRXDATA[4] CHIRXDATA[5] CHIRXDATA[6] CHIRXDATA[7] CHIRXDATA[8] CHIRXDATA[9] CHIRXDATA[10] CHIRXDATA[11] CHIRXDATA[12] CHIRXDATA[13] CHIRXDATA[14] CHIRXDATA[15] CHIRXDATA[16] CHIRXDATA[17] CHIRXDATA[18] CHIRXDATA[19] CHIRXDATA[20] E2 F3 D1 H5 F2 E1 G2 J6 J5 F1 K6 H3 H2 L6 G1 J3 J2 H1 L5 M6 K2 D2 R2 AJ15 AL33 Y34 V29 W33 W34 V30 V32 V33 U33 U32 U30 T34 T33 U29 R34 R33 T29 R32 P34 R30 P33 CHIRXDATA[21] CHIRXDATA[22] CHIRXDATA[23] CHIRXDATA[24] CHIRXDATA[25] CHIRXDATA[26] CHIRXDATA[27] CHIRXDATA[28] CHIRXDATA[29] CHIRXDATA[30] CHIRXDATA[31] CHIRXDATA[32] CHIRXDATA[33] CHIRXDATA[34] CHIRXDATA[35] CHIRXDATA[36] CHIRXDATA[37] CHIRXDATA[38] CHIRXDATA[39] CHIRXDATA[40] CHIRXDATA[41] CHIRXDATA[42] CHIRXGFS CHIRXGCLK CHIRXGTCLK CHITXDATA[1] CHITXDATA[2] CHITXDATA[3] CHITXDATA[4] CHITXDATA[5] CHITXDATA[6] CHITXDATA[7] CHITXDATA[8] CHITXDATA[9] CHITXDATA[10] CHITXDATA[11] CHITXDATA[12] CHITXDATA[13] CHITXDATA[14] CHITXDATA[15] CHITXDATA[16] CHITXDATA[17] CHITXDATA[18] CHITXDATA[19] CHITXDATA[20] R29 N34 P32 N33 P30 M34 P29 M33 L34 M32 N29 L33 K34 L32 M30 J34 K33 M29 L30 H34 J33 J32 Y33 W29 Y32 AJ27 AN31 AP32 AK29 AJ29 AJ30 AM34 AG30 AJ33 AK34 AH33 AF29 AF30 AJ34 AE29 AG32 AG33 AD29 AH34 AF32 Agere Systems Inc. 7 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 Table 2-1. Package Pin Assignments in Signal Name Order (continued) 8 Signal Name Pin Signal Name Pin CHITXDATA[21] CHITXDATA[22] CHITXDATA[23] CHITXDATA[24] CHITXDATA[25] CHITXDATA[26] CHITXDATA[27] CHITXDATA[28] CHITXDATA[29] CHITXDATA[30] CHITXDATA[31] CHITXDATA[32] CHITXDATA[33] CHITXDATA[34] CHITXDATA[35] CHITXDATA[36] CHITXDATA[37] CHITXDATA[38] CHITXDATA[39] CHITXDATA[40] CHITXDATA[41] CHITXDATA[42] CHITXGCLK CHITXGFS CLKIN_PLL CSN CTAPRH CTAPRP CTAPTH CTAPTL DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] DATA[10] DATA[11] DATA[12] DATA[13] DATA[14] AF33 AG34 AD30 AC29 AE33 AF34 AC30 AD32 AE34 AD33 AB29 AC32 AD34 AC33 AA29 AC34 AA30 AB33 AA32 AB34 Y29 AA33 Y30 AA34 AJ32 C1 AK8 AK9 AJ9 AJ13 J1 M5 L3 K1 L2 N6 M3 L1 M2 P6 M1 P5 N2 P3 N1 DATA[15] DS1XCLK DS2AISCLK DS3DATAINCLK[1] DS3DATAINCLK[2] DS3DATAINCLK[3] DS3DATAINCLK[4] DS3DATAINCLK[5] DS3DATAINCLK[6] DS3DATAOUTCLK[1] DS3DATAOUTCLK[2] DS3DATAOUTCLK[3] DS3DATAOUTCLK[4] DS3DATAOUTCLK[5] DS3DATAOUTCLK[6] DS3NEGDATAIN[1] DS3NEGDATAIN[2] DS3NEGDATAIN[3] DS3NEGDATAIN[4] DS3NEGDATAIN[5] DS3NEGDATAIN[6] DS3NEGDATAOUT[1] DS3NEGDATAOUT[2] DS3NEGDATAOUT[3] DS3NEGDATAOUT[4] DS3NEGDATAOUT[5] DS3NEGDATAOUT[6] DS3POSDATAIN[1] DS3POSDATAIN[2] DS3POSDATAIN[3] DS3POSDATAIN[4] DS3POSDATAIN[5] DS3POSDATAIN[6] DS3POSDATAOUT[1] DS3POSDATAOUT[2] DS3POSDATAOUT[3] DS3POSDATAOUT[4] DS3POSDATAOUT[5] DS3POSDATAOUT[6] DS3RXCLKOUT[1] DS3RXCLKOUT[2] DS3RXCLKOUT[3] DS3RXCLKOUT[4] DS3RXCLKOUT[5] DS3RXCLKOUT[6] R6 AK20 R1 U5 V2 W1 W2 Y3 Y5 Y6 AC2 AC3 AD3 AG1 AD6 T1 U2 V5 V6 Y1 AA2 AB1 AA6 AD2 AF1 AC6 AF3 T2 U3 V3 W6 Y2 AA1 AB2 AA5 AD1 AE1 AD5 AF2 AA3 AC1 AB6 AC5 AE2 AH1 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-1. Package Pin Assignments in Signal Name Order (continued) Signal Name Pin Signal Name Pin DS3XCLK DSN DTN E1XCLK E2AISCLK E3XCLK ECSEL ETOGGLE EXDNUP HP_INTN IC3STATEN IDDQ LINERXCLK[1] LINERXCLK[2] LINERXCLK[3] LINERXCLK[4] LINERXCLK[5] LINERXCLK[6] LINERXCLK[7] LINERXCLK[8] LINERXCLK[9] LINERXCLK[10] LINERXCLK[11] LINERXCLK[12] LINERXCLK[13] LINERXCLK[14] LINERXCLK[15] LINERXCLK[16] LINERXCLK[17] LINERXCLK[18] LINERXCLK[19] LINERXCLK[20] LINERXCLK[21] LINERXCLK[22] LINERXCLK[23] LINERXCLK[24] LINERXCLK[25] LINERXCLK[26] LINERXCLK[27] LINERXCLK[28] LINERXCLK[29] LINERXCLK[30] LINERXDATA[1] LINERXDATA[2] LINERXDATA[3] A21 E3 P1 AP21 U6 F18 AM15 AJ16 AL17 R3 AP24 AM24 A19 C18 B17 E17 B16 A15 F16 A14 B14 A13 B13 A12 B12 C12 B11 C11 A9 F12 A8 C9 F11 C8 A6 F9 A5 E8 C6 C5 B4 E6 B19 E18 B18 LINERXDATA[4] LINERXDATA[5] LINERXDATA[6] LINERXDATA[7] LINERXDATA[8] LINERXDATA[9] LINERXDATA[10] LINERXDATA[11] LINERXDATA[12] LINERXDATA[13] LINERXDATA[14] LINERXDATA[15] LINERXDATA[16] LINERXDATA[17] LINERXDATA[18] LINERXDATA[19] LINERXDATA[20] LINERXDATA[21] LINERXDATA[22] LINERXDATA[23] LINERXDATA[24] LINERXDATA[25] LINERXDATA[26] LINERXDATA[27] LINERXDATA[28] LINERXDATA[29] LINERXDATA[30] LINETXCLK[1] LINETXCLK[2] LINETXCLK[3] LINETXCLK[4] LINETXCLK[5] LINETXCLK[6] LINETXCLK[7] LINETXCLK[8] LINETXCLK[9] LINETXCLK[10] LINETXCLK[11] LINETXCLK[12] LINETXCLK[13] LINETXCLK[14] LINETXCLK[15] LINETXCLK[16] LINETXCLK[17] LINETXCLK[18] C17 A16 F17 B15 C15 E15 F15 C14 E14 F14 A11 F13 A10 E12 B10 E11 B9 A7 B8 F10 E9 B7 B6 A4 B5 F8 A3 L29 H32 F34 J29 E34 H30 F32 E32 D33 F30 F29 A32 F27 B30 A31 B29 B28 E26 Agere Systems Inc. 9 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 Table 2-1. Package Pin Assignments in Signal Name Order (continued) 10 Signal Name Pin Signal Name Pin LINETXCLK[19] LINETXCLK[20] LINETXCLK[21] LINETXCLK[22] LINETXCLK[23] LINETXCLK[24] LINETXCLK[25] LINETXCLK[26] LINETXCLK[27] LINETXCLK[28] LINETXCLK[29] LINETXCLK[30] LINETXDATA[1] LINETXDATA[2] LINETXDATA[3] LINETXDATA[4] LINETXDATA[5] LINETXDATA[6] LINETXDATA[7] LINETXDATA[8] LINETXDATA[9] LINETXDATA[10] LINETXDATA[11] LINETXDATA[12] LINETXDATA[13] LINETXDATA[14] LINETXDATA[15] LINETXDATA[16] LINETXDATA[17] LINETXDATA[18] LINETXDATA[19] LINETXDATA[20] LINETXDATA[21] LINETXDATA[22] LINETXDATA[23] LINETXDATA[24] LINETXDATA[25] LINETXDATA[26] LINETXDATA[27] LINETXDATA[28] LINETXDATA[29] LINETXDATA[30] LOPOHCLKIN LOPOHCLKOUT LOPOHDATAIN LOPOHDATAOUT F25 B27 A28 B26 E24 B25 E23 A25 F22 A24 F21 E21 G34 H33 K29 J30 G33 F33 D34 E33 H29 C34 E30 E29 B31 C30 C29 E27 A30 F26 A29 C27 F24 C26 A27 F23 A26 C24 B24 C23 B23 A23 B22 F20 C21 B21 LOPOHVALIDIN LOPOHVALIDOUT LOSEXT LP_INTN MODE0_PLL MODE1_PLL MODE2_PLL MPCLK MPMODE NSMIRXCLK[1] NSMIRXCLK[2] NSMIRXCLK[3] NSMIRXDATA[1] NSMIRXDATA[2] NSMIRXDATA[3] NSMIRXSYNC[1] NSMIRXSYNC[2] NSMIRXSYNC[3] NSMITXCLK[1] NSMITXCLK[2] NSMITXCLK[3] NSMITXDATA[1] NSMITXDATA[2] NSMITXDATA[3] NSMITXSYNC[1] NSMITXSYNC[2] NSMITXSYNC[3] PAR[0] PAR[1] PHASEDETDOWN[1] PHASEDETDOWN[2] PHASEDETDOWN[3] PHASEDETDOWN[4] PHASEDETDOWN[5] PHASEDETDOWN[6] PHASEDETUP[1] PHASEDETUP[2] PHASEDETUP[3] PHASEDETUP[4] PHASEDETUP[5] PHASEDETUP[6] PMRST REF10 REF14 RESHI RESLO A22 E20 AN21 T6 AG29 AK32 AK30 F5 F6 AP26 AP27 AJ24 AK23 AK24 AP28 AN25 AN26 AN27 AP29 AP30 AM29 AJ25 AN28 AP31 AK26 AN29 AN30 P2 R5 AG3 AG5 AF6 AK1 AJ1 AJ3 AG2 AE6 AF5 AH2 AJ2 AL1 AM21 AJ6 AK6 AP3 AJ8 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-1. Package Pin Assignments in Signal Name Order (continued) Signal Name Pin Signal Name Pin RHSCN RHSCP RHSDN RHSDP RHSFSYNCN RLSCLK RLSDATAN[1] RLSDATAN[2] RLSDATAN[3] RLSDATAP[1] RLSDATAP[2] RLSDATAP[3] RPOACCLK RPOACDATA RPOACSYNC RPSCN RPSCP RPSDN RPSDP RSTN RTOACCLK RTOACDATA RTOACSYNC RWN RXDATAEN[1] RXDATAEN[2] RXDATAEN[3] SCAN_EN SCANMODE SCK1 SCK2 TCK TDI TDO THSCN THSCON THSCOP THSCP THSDN THSDP THSSYNC TLSCLK TLSDATAN[1] TLSDATAN[2] TLSDATAN[3] TLSDATAP[1] AN5 AN4 AM6 AM5 AJ20 AK15 AP14 AP16 AP18 AP13 AP15 AP17 AN19 AJ18 AP20 AN11 AN10 AM9 AM8 AP22 AM17 AJ17 AM18 H6 AJ23 AM26 AM27 AN24 AP25 AM23 AJ22 AN22 AK21 AN23 AP7 AP5 AP4 AP6 AN8 AN7 AL15 AL14 AN14 AN16 AN18 AN13 TLSDATAP[2] TLSDATAP[3] TMS TPOACCLK TPOACDATA TPOACSYNC TPSCN TPSCP TPSDN TPSDP TRST TSTMODE TSTPHASE TSTSFTLD TTOACCLK TTOACDATA TTOACSYNC TXDATAEN[1] TXDATAEN[2] TXDATAEN[3] VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 AN15 AN17 AP23 AN20 AJ19 AM20 AP9 AP8 AP11 AP10 AJ21 AK17 AJ14 AM14 AL18 AP19 AK18 AJ26 AK27 AM30 G9 G10 G11 G12 G13 G14 G15 G16 G19 G20 G21 G22 G23 G24 G25 G26 J7 J28 K7 K28 L7 L28 M7 M28 N7 N16 Agere Systems Inc. 11 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 Table 2-1. Package Pin Assignments in Signal Name Order (continued) 12 Signal Name Pin Signal Name Pin VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 N17 N18 N19 N28 P7 P16 P17 P18 P19 P28 R7 R28 T7 T13 T14 T21 T22 T28 U13 U14 U21 U22 V13 V14 V21 V22 W7 W13 W14 W21 W22 W28 Y7 Y28 AA7 AA16 AA17 AA18 AA19 AA28 AB7 AB16 AB17 AB18 AB19 AB28 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 AC7 AC28 AD7 AD28 AE7 AE28 AF7 AF28 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AK11 AJ10 C20 B20 AK14 A2 A33 B1 B3 B32 B34 C2 C33 D5 D8 D11 D14 D17 D20 D23 D26 D29 VDD15A_CDR1 VDD15A_CDR2 VDD15A_DS3PLL VDD15A_E3PLL VDD15A_X4PLL VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-1. Package Pin Assignments in Signal Name Order (continued) Signal Name Pin Signal Name Pin VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 E31 F4 G8 G17 G18 G27 H7 H28 H31 J4 L31 M4 P31 R4 U7 U28 U31 V4 V7 V28 Y31 AA4 AC31 AD4 AF31 AG4 AG7 AG28 AH8 AH17 AH18 AH27 AJ31 AK4 AL6 AL9 AL12 AL21 AL24 AL27 AL30 AM2 AM33 AN1 AN3 AN32 VDD33 VDD33 VDD33 AN34 AP2 AP33 AK33 A1 A17 A18 A34 B2 B33 C3 C32 D6 D9 D12 D15 D18 D21 D24 D27 D30 E4 E5 F31 H4 J31 L4 M31 N13 N14 N21 N22 P4 P13 P14 P21 P22 R31 T16 T17 T18 T19 U1 U4 U16 U17 Agere Systems Inc. VDD33A_SFPLL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 13 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 Table 2-1. Package Pin Assignments in Signal Name Order (continued) 14 Signal Name Pin Signal Name Pin VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS U18 U19 U34 V1 V16 V17 V18 V19 V31 V34 W16 W17 W18 W19 Y4 AA13 AA14 AA21 AA22 AA31 AB13 AB14 AB21 AB22 AC4 AD31 AF4 AG6 AG31 AJ4 AJ5 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AK2 AK3 AK5 AK31 AL2 AL5 AL8 AL11 AL20 AL23 AL26 AL29 AM1 AM3 AM11 AM12 AM32 AN2 AN6 AN9 AN12 AN33 AP1 AP12 AP34 AK12 AJ12 F19 A20 AL34 AJ11 VSSA_CDR1 VSSA_CDR2 VSSA_DS3PLL VSSA_E3PLL VSSA_SFPLL VSSA_X4PLL Agere Systems Inc. Hardware Design Guide, Revision 10 March 7, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 2.3 Pin Matrix Table 2-2. Package Pin Matrix 1 2 3 A VSS VDD33 LINERXDATA[30] B VDD33 VSS VDD33 C CSN VDD33 VSS D ADDR[2] ADSN E ADDR[5] ADDR[0] F ADDR[9] ADDR[4] G ADDR[14] H 4 LINERXDATA [27] LINERXCLK [29] 5 6 LINERXCLK[25] LINERXCLK[23] 7 8 9 LINERXDATA LINERXCLK[19] LINERXCLK[17] [21] LINERXDATA LINERXDATA LINERXDATA [25] [22] [20] LINERXDATA[28] LINERXDATA[26] -- LINERXCLK[28] LINERXCLK[27] -- -- VDD33 VSS -- VDD33 DSN VSS VSS LINERXCLK[30] -- LINERXCLK[26] ADDR[1] VDD33 MPCLK MPMODE -- ADDR[6] -- -- -- -- ADDR[17] ADDR[12] ADDR[11] VSS ADDR[3] J DATA[0] ADDR[16] ADDR[15] VDD33 K DATA[3] ADDR[20] -- L DATA[7] DATA[4] M DATA[10] N DATA[14] -- LINERXCLK[22] LINERXCLK[20] VSS 10 11 LINERXDATA [16] LINERXDATA [18] LINERXDATA [14] LINERXCLK [15] LINERXCLK [16] -- 13 14 15 16 17 LINERXCLK[6] LINERXDATA[5] VSS LINERXCLK[13] LINERXCLK[11] LINERXCLK[9] LINERXDATA[7] LINERXCLK[14] -- -- LINERXDATA [11] VDD33 VSS LINERXDATA [23] LINERXDATA [19] LINERXCLK [21] LINERXDATA [17] LINERXCLK [18] LINERXDATA [15] LINERXDATA [12] LINERXDATA [13] VDD15 VDD15 VDD15 VDD15 VDD15 -- -- -- -- -- VDD15 -- -- -- -- ADDR[10] VDD15 -- -- -- ADDR[18] ADDR[13] VDD15 -- -- VDD33 DATA[1] ADDR[19] VDD15 -- -- -- DATA[5] VDD15 LINERXCLK[3] -- LINERXDATA[4] VSS -- VDD33 -- LINERXCLK[4] LINERXDATA [10] LINERXCLK[7] LINERXDATA[6] VDD15 VDD15 VDD15 VDD33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VSS VSS -- VDD15 VDD15 VDD15 LINERXDATA [29] -- VDD33 RWN VDD33 ADDR[8] ADDR[7] -- -- DATA[2] VSS DATA[8] DATA[6] DATA[12] -- -- -- VDD33 LINERXCLK[5] LINERXDATA[8] LINERXDATA[9] LINERXDATA [24] LINERXCLK [24] -- 12 LINERXCLK[12] LINERXCLK[10] LINERXCLK[8] P DTN PAR[0] DATA[13] VSS DATA[11] DATA[9] VDD15 -- -- -- -- -- VSS VSS -- VDD15 R DS2AISCLK APS_INTN HP_INTN VDD33 PAR[1] DATA[15] VDD15 -- -- -- -- -- -- -- -- -- -- T DS3NEGDATAIN[1] DS3POSDATAIN[1] -- -- -- LP_INTN VDD15 -- -- -- -- -- VDD15 VDD15 -- VSS VSS U VSS DS3NEGDATAIN[2] DS3POSDATAIN[2] VSS DS3DATAINCLK[1] E2AISCLK VDD33 -- -- -- -- -- VDD15 VDD15 -- VSS VSS V VSS DS3DATAINCLK[2] DS3POSDATAIN[3] VDD33 DS3NEGDATAIN[3] DS3NEGDATAIN[4] VDD33 -- -- -- -- -- VDD15 VDD15 -- VSS VSS W DS3DATAINCLK[3] DS3DATAINCLK[4] -- -- -- DS3POSDATAIN[4] VDD15 -- -- -- -- -- VDD15 VDD15 -- VSS VSS Y DS3POSDATAIN[5] DS3DATAINCLK[5] VSS DS3DATAINCLK[6] DS3DATAOUTCLK[1] VDD15 -- -- -- -- -- -- -- -- -- -- DS3POSDATAOUT[2] DS3NEGDATAOUT[2] VDD15 -- -- -- -- -- VSS VSS -- VDD15 VDD15 VDD15 -- -- -- -- -- VSS VSS -- VDD15 VDD15 DS3NEGDATAIN[5] AA DS3POSDATAIN[6] DS3NEGDATAIN[6] DS3RXCLKOUT[1] AB DS3NEGDATAOUT DS3POSDATAOUT [1] AC DS3RXCLKOUT[2] AD DS3POSDATAOUT [3] AE DS3POSDATAOUT [4] -- [1] DS3DATAOUTCLK [2] DS3NEGDATAOUT [3] DS3DATAOUTCLK [3] DS3DATAOUTCLK [4] DS3RXCLKOUT[5] -- AF DS3NEGDATAOUT DS3POSDATAOUT DS3NEGDATAOUT [4] [6] [6] PHASEDETDOWN [1] VDD33 -- VSS VDD33 -- -- DS3RXCLKOUT[3] DS3RXCLKOUT[4] DS3NEGDATAOUT[5] VDD15 -- -- -- -- -- -- -- -- -- DS3POSDATAOUT[5] DS3DATAOUTCLK[6] VDD15 -- -- -- -- -- -- -- -- -- -- VDD15 -- -- -- -- -- -- -- -- -- -- -- -- PHASEDETUP[2] VSS PHASEDETUP[3] PHASEDETDOWN[3] VDD15 -- -- -- -- -- -- -- -- -- VDD33 PHASEDETDOWN[2] VSS VDD33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD33 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD33 AG DS3DATAOUTCLK PHASEDETUP[1] AH DS3RXCLKOUT[6] PHASEDETUP[4] -- AJ PHASEDETDOWN PHASEDETUP[5] PHASEDETDOWN [6] VSS VSS REF10 -- RESLO CTAPTH VDD15A_CDR2 VSSA_X4PLL VSSA_CDR2 CTAPTL TSTPHASE BYPASS ETOGGLE RTOACDATA VSS VSS VDD33 VSS REF14 -- CTAPRH CTAPRP -- VDD15A_CDR1 VSSA_CDR1 -- VDD15A_X4PLL RLSCLK -- TSTMODE [5] AK [5] PHASEDETDOWN [4] AL PHASEDETUP[6] VSS -- -- VSS VDD33 -- VSS VDD33 -- VSS VDD33 -- TLSCLK THSSYNC -- EXDNUP AM VSS VDD33 VSS -- RHSDP RHSDN -- RPSDP RPSDN -- VSS VSS -- TSTSFTLD ECSEL -- RTOACCLK AN VDD33 VSS VDD33 RHSCP RHSCN VSS THSDP THSDN VSS RPSCP RPSCN VSS TLSDATAP[1] TLSDATAN[1] TLSDATAP[2] TLSDATAN[2] TLSDATAP[3] AP VSS VDD33 RESHI THSCOP THSCON THSCP THSCN TPSCP TPSCN TPSDP TPSDN VSS RLSDATAP[1] RLSDATAN[1] RLSDATAP[2] RLSDATAN[2] RLSDATAP[3] Agere Systems Inc. 15 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 Table 2-2. Package Pin Matrix (continued) 18 19 20 21 22 23 A VSS LINERXCLK[1] VSSA_E3PLL DS3XCLK LOPOHVALIDIN LINETXDATA[30] B LINERXDATA[3] LINERXDATA[1] VDD15A_E3PLL LOPOHCLKIN LINETXDATA[29] C LINERXCLK[2] -- VDD15A_DS3PLL -- LINETXDATA[28] D VSS -- VDD33 E LINERXDATA[2] -- LOPOHVALIDOUT LOPOHDATAOUT LOPOHDATAIN VSS LINETXCLK [30] LINETXCLK [29] -- VDD33 -- LINETXCLK[25] 24 25 26 27 28 29 30 31 32 LINETXDATA LINETXDATA LINETXDATA LINETXDATA LINETXCLK LINETXCLK[26] LINETXCLK[21] LINETXCLK[15] LINETXCLK[12] [28] [25] [23] [19] [17] LINETXDATA LINETXDATA LINETXCLK[24] LINETXCLK[22] LINETXCLK[20] LINETXCLK[17] LINETXLCK[16] LINETXCLK[14] VDD33 [27] [13] LINETXDATA LINETXDATA LINETXDATA LINETXDATA LINETXDATA -- -- -- VSS [26] [22] [20] [15] [14] VSS LINETXCLK [23] LINETXDATA [21] 33 34 VDD33 VSS VSS VDD33 VDD33 LINETXDATA [10] -- VDD33 VSS -- VDD33 VSS -- -- LINETXCLK[9] LINETXDATA[7] -- LINETXCLK[18] LINETXDATA [16] -- LINETXDATA [12] LINETXDATA [11] VDD33 LINETXCLK[8] LINETXDATA[8] LINETXCLK[5] LINETXCLK [19] LINETXDATA [18] VSS LINETXCLK[7] LINETXDATA[6] LINETXCLK[3] -- -- LINETXDATA[5] LINETXDATA[1] LINETXCLK[2] LINETXDATA[2] CHIRXDATA[40] F E3XCLK VSSA_DS3PLL LOPOHCLKOUT LINETXCLK[27] LINETXDATA[24] LINETXCLK[13] -- G VDD33 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD33 -- H -- -- -- -- -- -- -- -- -- -- VDD33 LINETXDATA[9] LINETXCLK[6] VDD33 J -- -- -- -- -- -- -- -- -- -- VDD15 LINETXCLK[4] LINETXDATA[4] VSS K -- -- -- -- -- -- -- -- -- -- VDD15 LINETXDATA[3] L -- -- -- -- -- -- -- -- -- -- VDD15 LINETXCLK[1] CHIRXDATA[39] VDD33 CHIRXDATA[34] CHIRXDATA[32] CHIRXDATA[29] VSS CHIRXDATA[30] CHIRXDATA[28] CHIRXDATA[26] LINETXCLK[11] LINETXCLK[10] -- -- -- -- CHIRXDATA[42] CHIRXDATA[41] CHIRXDATA[36] -- CHIRXDATA[37] CHIRXDATA[33] M -- -- -- -- -- -- -- -- -- -- VDD15 CHIRXDATA[38] CHIRXDATA[35] N VDD15 VDD15 -- VSS VSS -- -- -- -- -- VDD15 CHIRXDATA[31] P VDD15 VDD15 -- VSS VSS -- -- -- -- -- VDD15 CHIRXDATA[27] CHIRXDATA[25] VDD33 CHIRXDATA[23] CHIRXDATA[20] CHIRXDATA[18] VSS CHIRXDATA[17] CHIRXDATA[15] CHIRXDATA[14] -- R -- -- -- -- -- -- -- -- -- -- VDD15 CHIRXDATA[21] CHIRXDATA[19] T VSS VSS -- VDD15 VDD15 -- -- -- -- -- VDD15 CHIRXDATA[16] U VSS VSS -- VDD15 VDD15 -- -- -- -- -- VDD33 CHIRXDATA[13] CHIRXDATA[10] V VSS VSS -- VDD15 VDD15 -- -- -- -- -- VDD33 CHIRXDATA[2] W VSS VSS -- VDD15 VDD15 -- -- -- -- VDD15 -- -- -- CHIRXDATA[24] CHIRXDATA[22] -- -- VDD33 CHIRXDATA[9] CHIRXDATA[12] CHIRXDATA[11] CHIRXDATA[8] CHIRXDATA[5] VSS CHIRXDATA[6] CHIRXDATA[7] VSS CHIRXGCLK -- -- -- CHIRXDATA[3] CHIRXDATA[4] CHITXGCLK VDD33 CHIRXGTCLK CHIRXGFS CHIRXDATA[1] VSS Y -- -- -- -- -- -- -- -- VDD15 CHITXDATA[41] AA VDD15 VDD15 -- VSS VSS -- -- -- -- -- VDD15 CHITXDATA[35] CHITXDATA[37] AB VDD15 VDD15 -- VSS VSS -- -- -- -- -- VDD15 CHITXDATA[31] AC -- -- -- -- -- -- -- -- -- -- VDD15 CHITXDATA[24] CHITXDATA[27] VDD33 CHITXDATA[32] CHITXDATA[34] CHITXDATA[36] AD -- -- -- -- -- -- -- -- -- -- VDD15 CHITXDATA[18] CHITXDATA[23] VSS CHITXDATA[28] CHITXDATA[30] CHITXDATA[33] AE -- -- -- -- -- -- -- -- -- -- VDD15 CHITXDATA[15] AF -- -- -- -- -- -- -- -- -- -- VDD15 CHITXDATA[12] CHITXDATA[13] -- -- VSS -- -- CHITXDATA[39] CHITXDATA[42] -- -- CHITXDATA[25] CHITXDATA[29] VDD33 CHITXDATA[20] CHITXDATA[21] CHITXDATA[26] CHITXDATA[16] CHITXDATA[17] CHITXDATA[22] AG -- -- -- -- -- -- -- -- -- -- VDD33 MODE0_PLL CHITXDATA[8] VSS AH VDD33 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD33 -- -- -- -- -- AJ RPOACDATA TPOACDATA RHSFSYNCN TRST SCK2 RXDATAEN[1] CHITXDATA[1] -- CHITXDATA[5] CHITXDATA[6] VDD33 CLKIN_PLL NSMIRXCLK[3] NSMIRXDATA[2] -- NSMITXSYNC[1] TXDATAEN[2] -- CHITXDATA[4] MODE2_PLL VSS -- VSS VDD33 -- VSS VDD33 -- IDDQ -- RXDATAEN[2] RXDATAEN[3] -- NMITXCLK[3] TXDATAEN[3] -- TDO SCAN_EN NSMIRXSYNC [1] NSMIRXSYNC [2] TMS IC3STATEN SCANMODE AK TTOACSYNC -- DS1XCLK TDI -- NSMIRXDATA[1] AL TTOACCLK -- VSS VDD33 -- VSS VDD33 AM RTOACSYNC -- TPOACSYNC PMRST -- SCK1 AN TLSDATAN[3] RPOACCLK TPOACCLK LOSEXT TCK AP RLSDATAN[3] TTOACDATA RPOACSYNC E1XCLK RSTN 16 NSMITXDATA[1] TXDATAEN[1] CHITXGFS CHITXDATA[38] CHITXDATA[40] CHITXDATA[11] CHITXDATA[19] CHITXDATA[9] CHITXDATA[14] MODE1_PLL VDD33A_SFPLL CHITXDATA[10] -- CG_PLLCLKOUT VSSA_SFPLL VSS VDD33 CHITXDATA[7] VSS VDD33 VDD33 VSS NSMIRXSYNC NSMITXSYNC NSMITXSYNC NSMITXDATA[2] CHITXDATA[2] VDD33 [3] [2] [3] NSMIRXDATA NSMIRXCLK[1] NSMIRXCLK[2] NSMITXCLK[1] NSMITXCLK[2] NSMITXDATA[3] CHITXDATA[3] [3] Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 2.4 Pin Types Table 2-3 describes each type of input, output, and I/O pin used in the Ultramapper. Table 2-3. Pin Types Type Label I Description LVCMOS Input, LVTTL Switching Thresholds. I pd LVCMOS Input, LVTTL Switching Thresholds with Internal 50 k Pull-Down Resistor. I pu LVCMOS Input, LVTTL Switching Thresholds with Internal 50 k Pull-Up Resistor. O O od LIN LOUT I/O I/O pd -- LVCMOS Output. Open Drain Output. LVDS Inputs. LVDS Outputs. Bidirectional Pin. LVCMOS input with LVTTL switching thresholds and LVCMOS output. Bidirectional Pin. LVCMOS input with LVTTL switching thresholds with internal 50 k pull-down resistor and LVCMOS output. Power, Ground, Analog Inputs for External Resistors, Capacitors, Voltage References, etc. Agere Systems Inc. 17 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 2.5 Pin Definitions This section describes the function of each of the device pins. All LVDS input buffers have built-in 100 terminating resistor with a center tap pin available for external capacitor connection. All unused LVDS inputs may be left unconnected. Pin functionality is descriptive information. The actual functionality is dependent upon the device configuration via the registers. Table 2-4. TMUX Block, High-Speed Interface I/O Pin Symbol Type Name/Description AM5 RHSDP LIN AM6 RHSDN Receive High-Speed Data. 622/155 Mbits/s input data. Also, input to internal clock and data recovery (CDR). CDR may be bypassed in 155 Mbits/s mode. In 622 Mbits/s mode, the internal CDR must be used. LIN Receive High-Speed Clock. 155 MHz input clock for 155 Mbits/s data if CDR is bypassed. Not used in 622 Mbits/s mode. -- Center Tap RH. LVDS buffer terminator center tap for RHSDP/N and RHSCP/N. An optional 0.1 F capacitor, connected between CTAP pin and ground, will improve the common-mode rejection of the LVDS input buffers. AN4 RHSCP AN5 RHSCN AK8 CTAPRH AN21 LOSEXT I pu External Loss of Signal Input. Active level is programmable by register TMUX_LOSEXT_LEVEL. Default to active-low. This pin can be part of the high-priority interrupt when active. Usually connected to optical transceiver to indicate loss of signal. AN7 THSDP AN8 THSDN LOUT Transmit High-Speed Data. 622/155 Mbits/s output data. The frame location in slave mode is determined by THSSYNC and transmit high-speed control parameter register (TMUX_TFRAMEOFFSETA). In master mode the frame timing is arbitrary. AP4 THSCOP AP5 THSCON AP3, AJ8 RESHI, RESLO -- AJ6 REF10* I Reference 1.0 V. External 1 V reference voltage pin. (Optional). AK6 REF14* I Reference 1.4 V. External 1.4 V reference voltage pin. (Optional). LOUT Transmit High-Speed Clock Output. 622/155 MHz transmit output clock associated with THSDP/N. Resistor. A 100 , 1% resistor is required between RESHI and RESLO pins as a reference for the LVDS input buffer termination. * Optional: selected by MPU/top-level register UMPR_LVDS_REF_SEL. External reference voltage can be sourced from a low-impedance resistor (less than 1 k) divider circuit decoupled with a 0.1 F capacitor. Please refer to Table 4-4 LVDS Interface dc Characteristics, on page 40 for additional information. Table 2-5. TMUX Block, Protection Link I/O Pin Symbol Type Name/Description AM8 AM9 RPSDP RPSDN LIN AN10 AN11 AK9 RPSCP RPSCN CTAPRP LIN Receive Protection High-Speed Data. 622/155 Mbits/s protection input data. Also input to internal protection CDR. CDR may be bypassed in 155 Mbits/s mode. In 622 Mbits/s mode, the internal CDR must be used. Receive Protection High-Speed Clock. 155 MHz input clock for 155 Mbits/s data if protection CDR is bypassed. Not used in 622 Mbits/s mode. AP10 AP11 AP8 AP9 TPSDP TPSDN TPSCP TPSCN 18 -- Center Tap RP. LVDS buffer terminator center tap for RPSDP/N and RPSCP/N. An optional 0.1 F capacitor, connected between the CTAP pin and ground, will improve the commonmode rejection of the LVDS input buffers. LOUT Transmit Protection High-Speed Data. 622/155 Mbits/s protection output data. LOUT Transmit Protection High-Speed Clock. 622/155 MHz transmit output clock associated with TPSDP/N. Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-6. TMUX Block, Clock, and Sync I/O Pin Symbol Type Name/Description AP6 AP7 THSCP THSCN LIN Transmit High-Speed Clock. 622 MHz/155 MHz input clock for transmit 622/155 Mbits/s data. Also used as a reference clock for all CDRs. There are five CDR circuits. The high-speed data and protection high-speed data have CDRs which operate at 155 MHz or 622 MHz. The mate inputs have three CDRs which operate at 155 MHz. The clock on this pin is also internally routed to the DS1/E1 framers and is used as an internal master clock. Note: A 622 MHz clock must be supplied when the device operates in 622 Mbits/s mode. A 155 MHz clock must be supplied when the device operates in 155 Mbits/s mode. For version 3.0 devices and later, the following applies: A 622 MHz clock must be supplied when the device operates in 622 Mbits/s mode. A 155 MHz or 622 MHz clock can be supplied when the device operates in 155 Mbits/s mode (choice provisionable via UMPR_OC3THSC_MODE). AJ9 CTAPTH -- Center Tap TH. LVDS buffer terminator center tap for THSCP/N. An optional 0.1 F capacitor, connected between CTAP pin and ground, will improve the common-mode rejection of the LVDS input buffers. AJ20 RHSFSYNCN O Receive High-Speed Frame Sync. This output indicates the start of the frame in the highspeed data input. Only present when a valid frame signal is detected on the RHSDP/N inputs. It is an active-low pulse with width almost equal to one E1 clock period or approximately 500 ns. AK15 RLSCLK O Receive Low-Speed Clock. 19.44 MHz receive output clock divided down from either RHSCP/N or the recovered high-speed clock (when the CDR is used). May be used as a system timing reference. AL14 TLSCLK O Transmit Low-Speed Clock. 19.44 MHz transmit output clock divided down from THSCP/N. AL15 THSSYNC I/O pd Transmit High-Speed Frame Sync. 2 kHz/8 kHz composite frame sync signal that identifies the locations of the J0, J1-1, J1-2, J1-3 . . . J1-12 , and V1-1 bytes. This signal is used to align transmit frames before multiplexing. Note: J0, J1-1, J1-2, and J1-3 . . . , J1-12 occur every 125 s. V1-1 occurs every 500 s. If register MPU_MASTER_SLAVE = 1, THSSYNC is an output; otherwise, THSSYNC is an input. The positive 8 kHz and 2 kHz pulses are synchronized to TLSCLK (in master mode only). The rising edge is referenced for frame location. For master/slave configuration, the THSSYNC of all Ultramappers (up to four) must be connected together. The master can be one of the Ultramappers, and it sources the frame sync pulse to other Ultramappers. All Ultramappers can also be configured as slaves and receive frame sync from the external system frame sync. Agere Systems Inc. 19 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 Table 2-7. STS Cross Connect (STSXC) Block, STS-3/STM-1 Mate Interconnect Pin Symbol AP17, AP15, AP13 AP18, AP16, AP14 RLSDATAP[3:1] AN17, AN15, AN13 AN18, AN16, AN14 AJ13 RLSDATAN[3:1] TLSDATAP[3:1] TLSDATAN[3:1] CTAPTL Type Name/Description LOUT Receive Low-Speed Data. These pins are usually used in 622 Mbits/s applications (however, they can be used in a 155 Mbits/s application). These pins are used on the device interfacing to the high-speed STS-N/STM-N line. Connect these pins to the high-speed data inputs (RHSDP/N) of the slave devices. This 155 Mbits/s signal uses a SONET structure. The overheads supported are the A1/A2 and B2 bytes and line RDI. The data is scrambled. Data from the RHSD is routed via the STSXC. LIN Transmit Low-Speed Data. These pins are usually used in 622 Mbits/s applications (however, they can be used in a 155 Mbits/s application). These pins are used on the device interfacing to the high-speed STS-N/STM-N line. Connect these pins to the high-speed data outputs (THSDP/N) of the slave devices. This 155 Mbits/s input receives data from the slave high-speed outputs. -- These inputs have built-in clock and data recovery (CDR). The frame location expects a fixed relationship to the high-speed transmit frame sync (THSSYNC). Center Tap TL. LVDS buffer terminator center tap for TLSDATAP/N. An optional 0.1 F capacitor, connected between CTAP pin and ground, will improve the common-mode rejection of the LVDS input buffers. Table 2-8. Synchronous Payload Envelope (SPE) Mapper Block, External PLL Control Pin Symbol Type Name/Description AL1, AJ2, AH2, AF5, AE6, AG2 PHASEDETUP[6:1] O AJ3, AJ1, AK1, AF6, AG5, AG3 PHASEDETDOWN[6:1] O Phase Detector Up. Signal out to external PLL filter and oscillator circuits. Used if SPEMPR outputs DS3/E3 data without going through internal DS3/E3 DJA. If TSTMODE is high, then these pins are used for TSTMUX[5:0] (test mode output). For version 3.0 devices and later, these pins are no longer used. Therefore, the DS3/E3 DJA must be used. PHASEDETUP [6] becomes a transmit CHI frame sync output (CHITXGFS_O) which is only applicable in CHI compression mode. Phase Detector Down. Signal out to external PLL filter and oscillator circuits. Used if SPEMPR outputs DS3/E3 data without going through internal DS3/E3 DJA. If TSTMODE is high, PHASEDETDOWN[4:1] are used for TSTMUX[9:6] (test mode output). For version 3.0 devices and later, these pins are no longer used. Therefore, the DS3/E3 DJA must be used. 20 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-9. Multirate Cross Connect (MRXC) Block, TOAC Input and Output Channels Pin Symbol Type AM17 RTOACCLK O AJ17 RTOACDATA AM18 RTOACSYNC AL18 TTOACCLK AP19 TTOACDATA AK18 TTOACSYNC Name/Description Receive Transport Overhead Access Channel Clock. The frequency of this clock is determined by the TOAC provisioning registers. O Receive Transport Overhead Access Channel Data. 622/155 Mbits/s transport overhead bytes are output on this pin. The content is determined by the TOAC provisioning registers. O Receive Transport Overhead Access Channel Sync. Active-high 8 kHz frame sync. It is active during the clock period of the first bit of each frame. O Transmit Transport Overhead Access Channel Clock. The frequency of this clock is determined by the TOAC provisioning registers. I pd Transmit Transport Overhead Access Channel Data. Input for the transport overhead bytes. O Transmit Transport Overhead Access Channel Sync. Active-high 8 kHz frame sync. It is active during the clock period of the first bit of each frame. Table 2-10. Multirate Cross Connect (MRXC) Block, POAC Input and Output Channels Pin Symbol Type Name/Description AN19 RPOACCLK O AJ18 RPOACDATA O AP20 RPOACSYNC O AN20 TPOACCLK O AJ19 TPOACDATA I pd AM20 TPOACSYNC O Receive Path Overhead Access Channel Clock. Output for the path overhead bytes. This is a 3-state output pin controlled by register provisioning. Receive Path Overhead Access Channel Data. Output for the path overhead bytes. This pin can be 3-stated. Receive Path Overhead Access Channel Sync. Output for POAC channel. Active-high during the first bit of each frame when the POAC is connected to either the TMUX or STS1LT. Active-high during the LSB of the last byte of the frame when connected to the SPEMPR. This pin can be individually 3-stated. Transmit Path Overhead Access Channel Clock. Serial access channel clock output for the path overhead bytes. This pin can be individually 3-stated. Transmit Path Overhead Access Channel Data. Serial access channel data input for the path overhead bytes. Transmit Path Overhead Access Channel Sync. Output for POAC channel. Active-high during the first bit of each frame when the POAC is connected to either the TMUX, the STS1LT, or the SPEMPR. This pin can be individually 3-stated. Agere Systems Inc. 21 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 Table 2-11. DS3/E3/STS-1 Out Pin Symbol Type Name/Description AF2, AD5, AE1, AD1, AA5, AB2 AF3, AC6, AF1, AD2, AA6, AB1 AD6, AG1, AD3, AC3, AC2, Y6 DS3POSDATAOUT[6:1] O DS3/E3/STS-1 Positive Data Output. Contains either the positive rail of the B3ZS/HDB3 encoded output data, or single rail NRZ data. DS3NEGDATAOUT[6:1] O DS3/E3/STS-1 Negative Data Output. Negative rail B3ZS/HDB3 encoded output data. Not used in single rail mode (held low in this case). DS3DATAOUTCLK[6:1] I pd DS3/E3/STS-1 Data Output Clock. 44.736 MHz, 34.368 MHz, or 51.84 MHz clock input and is typically connected to a crystal oscillator or clocking chip. AH1, AE2, AC5, AB6, AC1, AA3 DS3RXCLKOUT[6:1] O This clock is required for M13, E13, or STS1LT applications. For DS3/E3 to SONET/SDH mapping applications, this clock is required only if an external clock smoothing PLL is used. If the DS3/E3 DJA is used, this clock is not required. DS3XCLK/E3XCLK is needed for DS3/E3 DJA in this case. For STS-1 to SONET mapping applications, the TMUX can be used to supply the STS-1 rate DATAOUT clock and this clock is therefore not needed. For STS-1 PDH applications, a 51.84 MHz clock must be supplied at this pin. DS3/E3/STS-1 Receive Clock Output. 44.736 MHz DS3/34.368 MHz E3/51.84 MHz STS-1 clock out to external circuit. Table 2-12. DS3/E3/STS-1 In Pin Symbol Type Name/Description AA1, Y2, W6, V3, U3, T2 AA2, Y1, V6, V5, U2, T1 DS3POSDATAIN[6:1] I pd DS3NEGDATAIN[6:1] I pd DS3DATAINCLK[6:1] I pd DS3/E3/STS-1 Positive Data Input. Contains either the positive rail of the B3ZS/HDB3 encoded input data, or single rail NRZ data. DS3/E3/STS-1 Negative Data Input. Contains either the negative rail of the B3ZS/HDB3 encoded input data or, in single rail mode, this input may be used to count bipolar violations. DS3/E3/STS-1 Data Input Clock. 44.736 MHz, 34.368 MHz, or 51.84 MHz clock for the DS3/E3/STS-1 positive and negative data inputs. Y5, Y3, W2, W1, V2, U5 22 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-13. NSMI/STS-1 In Pin Symbol Type AP28, AK24, AK23 NSMIRXDATA[3:1] I pd AJ24, AP27, AP26 AN27, AN26, AN25 NSMIRXCLK[3:1] NSMIRXSYNC[3:1] AM27, AM26, AJ23 RXDATAEN[3:1] Name/Description Network Serial Multiplex Interface (NSMI) Receive* Data. Used in the following applications: 51.84 Mbits/s serial data input that is used to bring in multiplexed DS1 or E1 channels to FRM. STS-1 rate clear-channel receive data to SPEMPR. DS3/E3 rate clear-channel receive data to M13/E13. Additionally, it could be used as a SONET compliant STS-1 input signal to STS1LT from external LIU. For V3.0 devices, these pins may also be used for DS3 clear channel (positive-rail or single-rail) input data (to the SPEMPR block). I/O pd NSMI Receive Clock. Used in the following applications: Input (51.84 MHz) for the DS1/E1 application. Output (51.84 MHz) for the STS-1 rate clear-channel application. Output (44.736/34.368 MHz) for the DS3/E3 application. Additionally, it could be used as an input clock for SONET compliant STS-1 to STS1LT from external LIU. For V3.0 devices, these pins may also be used for DS3 clear channel DS3 rate input clock for positive (and negative) data inputs. I/O pd NSMI Receive Frame Sync. Used in the following applications: O Input receive NSMI control for FRM. Output receive control frame sync signal for M13/E13. Output receive control frame sync signal for SPEMPR. Additionally, it could be used to carry STS-1 input transmit clock for STS1LTs. For V3.0 devices, these pins may also be used for DS3 clear channel negative-rail input data (to the SPEMPR block). NSMI Receive Data Enable. In FRM NSMI mode, this pin is not used. In the SPEMPR NSMI mode, the signal on this output will be high during the POH of the SPE. In M13 NSMI mode, the signal output on this pin goes low during the M1 byte of the first M1 frame of the DS3 frame. In E13 NSMI mode, the signal output on this pin goes low during the overhead bytes and control bits of the E3 frame. * The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., NSMIRXDATA, on the transmit path are labeled receive. Low-speed outputs, e.g., NSMITXDATA on the receive path are labeled transmit. Agere Systems Inc. 23 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 Table 2-14. NSMI/STS-1 Out Pin Symbol Type Name/Description AP31, AN28, AJ25 NSMITXDATA[3:1] O AM29, AP30, AP29 NSMITXCLK[3:1] O AN30, AN29, AK26 NSMITXSYNC[3:1] O AM30, AK27, AJ26 TXDATAEN[3:1] O NSMI Transmit* Data. NSMI outputs or STS-1 Tx data outputs from STS1LTs. NSMI output data from either the FRM, SPEMPR, or M13/E13 block. For V3.0 devices, these pins may also be used for DS3 clear channel (positive-rail or single-rail) output data (from the DS3 DJA block). NSMI Transmit Clock Output or STS-1 Tx Clock Outputs from STS1LTs. Output clock at 51.84 MHz for the DS1/E1 application, the (51.84 MHz) STS-1 rate clear-channel application, or a (44.736 MHz/ 34.368 MHz) output clock for the DS3/E3 application. For V3.0 devices, these pins may also be used for DS3 clear channel DS3 rate output clock (from the DS3 DJA block). Transmit System Frame Sync Output. Output transmit control frame sync signal from FRM, M13/E13, or SPEMPR. For V3.0 devices, these pins may also be used for DS3 clear channel negative-rail output data (from the DS3 DJA block). Transmit Data Enable for NSMI Mode. This output is used to request data for a particular link when the FRM NSMI is operating in nonloop timing mode. This output acts as a sync signal when the FRM NSMI operates in loop-timing mode. In the SPEMPR NSMI mode, the signal on this output will be high during the POH of the SPE. In M13 NSMI mode, the signal output on this pin goes low during the M1 byte of the first M1 frame of the DS3 frame. In E13 NSMI mode, the signal output on this pin goes low during the overhead bytes and control bits of the E3 frame. * The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., NSMIRXDATA, on the transmit path are labeled receive. Low-speed outputs, e. g., NSMITXDATA on the receive path are labeled transmit. The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., LINERXDATA, on the transmit path are labeled receive. Low-speed outputs, e. g., LINETXDATA, on the receive path are labeled transmit. Table 2-15. Shared Low-Speed Line In Pin Symbol A3, F8, B5, A4, B6, LINERXDATA[30:1] B7, E9, F10, B8, A7, B9, E11, B10, E12, A10, F13, A11, F14, E14, C14, F15, E15, C15, B15, F17, A16, C17, B18, E18, B19 E6, B4, C5, C6, E8, LINERXCLK[30:1] A5, F9, A6, C8, F11, C9, A8, F12, A9, C11, B11, C12, B12, A12, B13, A13, B14, A14, F16, A15, B16, E17, B17, C18, A19 24 Type Name/Description I pd Line Receive Data [30:1]. Inputs to the internal multirate cross connect. The signals support a variety of transport modes such as DS1, E1, VT, or VC. The signals are used for received positive-rail or single-rail DS1/ E1 line data input sourced from an external LIU. In this mode, these signals will be routed via the cross connect to the VT mapper, the M13 multiplexer, E13 multiplexer, or the receive line inputs of the DS1/E1 framers. These signals may also be used as input data for DS2/E2 applications (see the Ultramapper Family System Design Guide). I/O pd Line Receive Clock [30:1]. Configurable inputs to the internal multirate cross connect. These inputs are typically used for asynchronous clocks associated with the line receive data inputs from external line interface units or payload termination functions. For transport mode only. In certain cases, this input can be used as an output. These pins may be used for DS2/E2 clocks in DS2/E2 applications. More information can be found in an application note: Configuring Ultramapper Family of Devices for Ported DS2 Applications. For input specifications, Table 6-21 applies to these pins. Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., LINERXDATA, on the transmit path are labeled receive. Low-speed outputs, e. g., LINETXDATA, on the receive path are labeled transmit. Table 2-16. Shared Low-Speed Line Out Pin Symbol Type A23, B23, C23, LINETXDATA[30:1] B24, C24, A26, F23, A27, C26, F24, C27, A29, F26, A30, E27, C29, C30, B31, E29, E30, C34, H29, E33, D34, F33,G33, J30, K29, H33, G34 O LINETXCLK[30:1] I/O pd E21, F21, A24, F22, A25, E23, B25, E24, B26, A28, B27, F25, E26, B28, B29, A31, B30, F27, A32, F29, F30, D33, E32, F32, H30, E34, J29, F34, H32, L29 Name/Description Line Transmit Data [30:1]. Outputs from the internal multirate cross connect. The outputs support a variety of transport modes such as asynchronous DS1, E1, and synchronous VT or VC. The signals are used to transmit positive-rail or single-rail DS1/E1 line data output sourced to an external LIU. In this mode, these signals will be routed via the cross connect from the VT mapper, the M13 multiplexer, E13 multiplexer, or the transmit line outputs of the DS1/E1 framers. Each of these outputs comes from the internal MRXC and can be individually set to high-impedance. These pins may be used for output data in DS2/ E2 applications (see the Ultramapper Family System Design Guide). Line Transmit Clock [30:1]. Configurable outputs from the internal multirate cross connect. These outputs are typically used for asynchronous clocks associated with the line transmit data outputs to external line interface units or payload termination functions. For transport mode only. Each of these outputs comes from the internal MRXC and can be individually set to high impedance. In certain cases (DS2/E2 applications), this output is used as an input (input DS2/E2 clocks). More information can be found in an application note: Configuring Ultramapper TM Family of Devices for Ported DS2 Applications. For output specifications, Table 6-22 applies to these pins. The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., CHIRXDATA, on the transmit path are labeled receive. Low-speed outputs, e.g., CHITXDATA, on the receive path are labeled transmit. Agere Systems Inc. 25 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 Table 2-17. TDM Concentration Highway (CHI) In Pin Symbol Type J32, J33, H34, L30, M29, K33, J34, M30, L32, K34, L33, N29, M32, L34, M33, P29, M34, P30, N33, P32, N34, R29, P33, R30, P34, R32, T29, R33, R34, U29, T33, T34, U30, U32, U33, V33, V32, V30, W34, W33, V29, Y34 CHIRXDATA[42:1] I pd Name/Description CHI Receive Data [42:1]. Configurable synchronous TDM inputs to the internal multirate cross connect. Can be used in one of the following modes: CHI mode: Receive TDM input highways. Can be configured to operate at 2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s, or 16.384 Mbits/s. Parallel system bus mode: The parallel system bus is a 16-bit wide 19.44 Mbits/s synchronous TDM highway. Bits [16:9] are used for time-slot data. Bits [8:1] are used for robbed-bit signaling data in a ASM like fashion and are optional. CHIRXGFS is the frame synchronization input for the parallel system bus and CHIRXGCLK is the 19.44 MHz clock input. CHIRXDATA[42:17] are not used. Asynchronous mode: In this mode, these inputs are used for DS1/E1 received negative rail data. May also be used for 8 kHz frame synchronization inputs that indicate the position of the F-bits in the line receive data. VT mapper mode: 8 kHz sync for DS1/E1 or 2 kHz sync signal for VC. These pins may be used as input data for DS2/E2 applications. More information can be found in an application note: Configuring Ultramapper Family of Devices for Ported DS2 Applications. 26 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., CHIRXDATA, on the transmit path are labeled receive. Low-speed outputs, e. g., CHITXDATA, on the receive path are labeled transmit. Table 2-18. TDM Concentration Highway (CHI) Out Pin Symbol Type AA33, Y29, AB34, AA32, AB33, AA30, AC34, AA29, AC33, AD34, AC32, AB29, AD33, AE34, AD32, AC30, AF34, AE33, AC29, AD30, AG34, AF33, AF32, AH34, AD29, AG33, AG32, AE29, AJ34, AF30, AF29, AH33, AK34, AJ33, AG30, AM34, AJ30, AJ29, AK29, AP32, AN31, AJ27 CHITXDATA[42:1] I/O Name/Description CHI Transmit Data [42:1]. Configurable synchronous TDM outputs from the internal multirate cross connect. Can be used in one of the following modes: CHI mode: Transmit TDM output highways. Can be configured to operate at 2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s, or at 16.384 Mbits/s. Parallel system bus mode: The parallel system bus is a 16-bit wide 19.44 Mbits/s synchronous TDM highway. Bits [16:9] are used for time-slot data. Bits [8:1] are used for robbed-bit signaling data in a ASM like fashion and are optional. CHITXGFS is the frame synchronization input for the parallel system bus and CHITXGCLK is the 19.44 MHz clock input. CHITXDATA[42:17] are not used. Asynchronous mode: In this mode, these outputs are used for DS1/ E1 transmit negative rail data. May also be used for 8 kHz frame synchronization outputs that indicate the position of the F-bits in the line transmit data. VT mapper mode: 8 kHz frame sync output for DS1/E1 or 2 kHz frame sync output signal for VC. Each of these outputs comes from the internal MRXC and can be individually set to high impedance. In rare cases, this output can be used as an input. These pins have various functionalities in DS2/E2 applications. More information can be found in an application note: Configuring Ultramapper Family of Devices for Ported DS2 Applications. When running in CHI compression mode, CHITXDATA[17] becomes a frame sync output from the device, which signifies the beginning of the CHI output frame. This feature is only available in V3.0 devices and later. Agere Systems Inc. 27 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 Table 2-19. Framer (FRM) Block, CHI/Parallel System Bus (PSB) Clock and Sync Pin Symbol Type Name/Description Y32 CHIRXGTCLK I pd W29 CHIRXGCLK I pd Y33 CHIRXGFS I pd Global Transmit Line Clock. This is the transmit line clock for the DS1 or E1 framer. Normally this input is not used and the transmit clock is generated by an internal phaselock loop which uses CLKIN_PLL as a reference. Note that if this input is used, all the transmit framers must run at the same rate, either 1.544 MHz or 2.048 MHz. This signal could be used for both CHI and parallel system bus. Receive Global System Clock. This signal is used for both CHI and parallel system bus. In CHI mode, it is a 2.048 MHz, a 4.096 MHz, a 8.192 MHz, or a 16.384 MHz TDM clock. In parallel system bus mode, it is a 19.44 MHz clock. Receive System Frame Sync. This signal is used for both CHI and parallel system bus. In CHI mode, it is an 8 kHz pulse that references the location of time slots in the receive CHI inputs. Its polarity, sampling edge, and offset from time slots in the concentration highways may all be programmed. AA34 CHITXGFS I pd In parallel system bus mode, it is an 8 kHz reference for time slots within the parallel system bus input highways. In this mode, the frame strobe is a positive pulse with active edge provisioned by a register. Transmit System Frame Sync. This signal is used for both CHI and parallel system bus. In CHI mode, it is an 8 kHz pulse which references the location of time slots in the transmit CHI outputs. Its polarity, sampling edge, and offset from time slots in the concentration highways may all be programmed. In parallel system bus mode, it is an 8 kHz reference for time slots within the parallel system bus output highways. In this mode, the frame strobe is a positive pulse with active edge provisioned by a register. Y30 28 CHITXGCLK I pd For version 3.0 devices and later, CHITXGFS also serves as a required 8 kHz frame sync when operating in NSMI slip mode. Transmit Global System Clock. This signal is used for both CHI and parallel system bus. In CHI mode, it is a 2.048 MHz, a 4.096 MHz, a 8.192 MHz, or a 16.384 MHz TDM clock. In parallel system bus mode, it is a 19.44 MHz clock. Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-20. Reference Clocks Pin Symbol Type R1 DS2AISCLK I pd Name/Description DS2 AIS Clock. More information can be found in an application note: Configuring Ultramapper Family of Devices for Ported DS2 Applications. VC11 AIS Clock. A 1.664 MHz clock input. In the VT mapper mode, this clock is used to generate VC11 AIS. The clock is used when VC11 is sent from the LINETXDATA[30:1] outputs. The 1.664 MHz clock is for a VC11 payload. There are 27 bytes per VT1.5 in each STS-1 frame, excluding the VT overhead (1 byte), 26 bytes/125 s = 1.664 Mbits/s. (VC11 rate is 1.728 Mbits/s.) U6 E2AISCLK I pd If used, this input can be provided by a free-running crystal oscillator, or a clocking chip. E2 AIS Clock. More information can be found in an application note: Configuring Ultramapper Family of Devices for Ported DS2 Applications. VC12 AIS Clock. A 2.240 MHz clock input. In the VT mapper mode, this clock is used to generate VC12 AIS. The clock is used when VC12 is sent from the LINETXDATA[30:1] outputs. The 2.240 MHz clock is for a VC12 payload. There are 36 bytes per VT2.0 in each STS-1 frame, excluding the VT overhead (1 byte), 35 bytes/125 s = 2.240 Mbits/s. (VC12 rate is 2.304 Mbits/s.) AP21 AK20 E1XCLK DS1XCLK I pd I pd A21 DS3XCLK I pd F18 E3XCLK I pd If used, this input can be provided by a free-running crystal oscillator, or a clocking chip. E1 X Clock. This clock signal is used for three purposes: to generate E1 AIS (all 1s), as a reference to the E1 DJA, and as a clock source for the test pattern generator and test pattern monitor. This input may be provided by a 2.048 MHz, a 32.768 MHz, or a 65.536 MHz 50 ppm free-running crystal oscillator, or clocking chip. Note: For the E1 DJA, an input of 32.768 MHz or 65.536 MHz must be used. DS1 X Clock. This clock signal is used for three purposes: to generate DS1 AIS (all 1s), as a reference to the DS1 DJA, and as a clock source for the test pattern generator and test pattern monitor. This input may be provided by a 1.544 MHz, a 24.704 MHz, or a 49.408 MHz 32 ppm free-running crystal oscillator, or clocking chip. Note: For the DS1 DJA, an input of 24.704 MHz or 49.408 MHz must be used. DS3 X Clock. A 44.736 MHz 20 ppm clock input for DS3 DJA and TPG. This input may be provided by a 44.736 MHz 20 ppm free-running crystal oscillator, or clocking chip. E3 X Clock. A 34.368 MHz 20 ppm clock input for E3 DJA and TPG. This input may be provided by a 34.368 MHz 20 ppm free-running crystal oscillator, or clocking chip. Table 2-21. Low-Order Path Overhead Access, Transmit Direction Pin Symbol Type Name/Description B22 LOPOHCLKIN I pd C21 LOPOHDATAIN I pd Low-Order Path Overhead Clock. 19.44 MHz clock supplied from external circuits that provide the low-order path overhead data. Low-Order Path Overhead Data. The following parts of the low-order (VT) overhead are presented at this pin: communication channel bits (O bits), V5, J2, Z6/N2, Z7, and K4 byte. Agere Systems Inc. 29 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 Table 2-21. Low-Order Path Overhead Access, Transmit Direction Pin Symbol Type Name/Description A22 LOPOHVALIDIN I pd Low-Order Path Overhead Data Input Valid. This signal is a mask that indicates the location of the overhead bytes in the LOPOHDATAIN. Table 2-22. Low-Order Path Overhead Access, Receive Direction Pin Symbol Type Name/Description F20 LOPOHCLKOUT O B21 LOPOHDATAOUT O E20 LOPOHVALIDOUT O Low-Order Path Overhead Clock. 19.44 MHz clock supplied to external circuits that receive the low-order path overhead data. Low-Order Path Overhead Data. Line and path REI and RDI, O-bits, V5, J2, Z6/ N2, and Z7/K4 byte. Low-Order Path Overhead Data Output Valid. This signal is a mask that indicates the location of the overhead bytes in the LOPOHDATAOUT. Table 2-23. Clock Generator Pin Symbol Type Name/Description AJ32 CLKIN_PLL I pd AL33 CG_PLLCLKOUT O AK30, AK32, AG29 MODE[2:0]_PLL I pd Transmit Line Clock Generator Reference Input. The clock generator is used to derive the transmit line clocks for DS1/E1 synchronized to CLKIN_PLL. The derived clock is used in the DS1/E1 transmit framer sections. Framer PLL Test Mode Output. Framer PLL clock (1.544 MHz, 2.048 MHz) selected by device register. Framer PLL Input Clock Mode Select Bits. The settings of these mode select pins must correspond to the frequency of CLKIN_PLL as shown below. 30 MODE[2:0]_PLL CLKIN_PLL MODE[2:0]_PLL CLKIN_PLL 000 001 010 011 Reserved 51.840 MHz 26.624 MHz 19.440 MHz 100 101 110 111 16.384 MHz 8.192 MHz 4.096 MHz 2.048 MHz Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-24. Microprocessor Interface Pin Symbol Type Name/Description F5 MPCLK I F6 MPMODE I C1 CSN I pu D2 ADSN I H6 E3 RWN DSN I I K2, M6, L5, H1, J2, J3, G1, L6, H2, H3, K6, F1, J5, J6, G2, E1, F2, H5, D1, F3, E2 ADDR[20:0] I Microprocessor Clock. This clock is required to properly sample address, data, and control signals from the microprocessor in both asynchronous and synchronous modes of operation. Microprocessor Mode. If the microprocessor interface is synchronous, MPMODE should be set to 1. If the microprocessor interface is asynchronous, MPMODE should be set to 0. Chip Select. Active-low, high-order address signal. Chip select must be set low at the beginning of any read or write access and returned high at the end of the cycle. Address Strobe. Active-low address strobe that indicates the beginning of a read or write access. It is a one MPCLK cycle-wide pulse for synchronous mode. In asynchronous mode, it is active for the entire read/write cycle. Address bus signals, ADDR[20:0], are available to the Ultramapper when ADSN is low. The address bus should remain valid for the duration of ADSN. Read/Write. RWN is set high during a read cycle, or set low during a write cycle. Data Strobe. For a read cycle, the contents of the internal register will be output on DATA [15:0]; and for a write cycle DATA [15:0] will be clocked into the internal register. To initiate the start of the read/write operation, DSN must be low during the entire read/write cycle. This signal should only be used for asynchronous mode. Address [20:0]. ADDR[20] is the most significant bit and ADDR[0] is the least significant bit for addressing all the internal registers during microprocessor access cycles. All addresses are 21-bit word addresses; hence, in a typical application ADDR[0] of the TMXF84622 device would be connected to address bit 1 of a byte addressable system address bus. R6, N1, P3, N2, P5, M1, P6, M2, L1, M3, N6, L2, K1, L3, M5, J1 R5, P2 DATA[15:0] I/O PAR[1:0] I/O P1 DTN R3, T6 HP_INTN, LP_INTN R2 APS_INTN Agere Systems Inc. Note: The Ultramapper is little-endian, i.e., the least significant byte is stored in the lowest address and the most significant byte is stored in the highest address. Care must be exercised in connection to microprocessors that use big-endian byte ordering. Data [15:0]. 16-bit data bus input for write operations and output for read operations. DATA[15] is the MSB, and DATA[0] is the LSB. Data Parity. Byte-wide parity bits for data. PAR[1] is the parity for DATA[15:8], and PAR[0] is the parity for DATA[7:0] O Data Transfer Acknowledge. The delay associated with DTN going low depends on the Ultramapper block being accessed. In asynchronous mode, when ADSN or DSN is deasserted, the deassertion will drive the DTN signal high. When inactive, CSN will drive DTN to be 3-stated. The microprocessor should wait after DTN is deasserted before starting the next operation. O od High-Priority and Low-Priority Interrupt. Active-low. Each of the functional blocks contain their individual low-priority interrupts. High-priority interrupts are generated by TMUX and E13 blocks. Each interrupt is individually maskable. Requires an external 5 k pull-up resistor. O od Automatic Protection Switch Interrupt. Active-low. See the TMUX section in the Register Description for specific interrupts. Each interrupt is individually maskable. Requires an external 5 k pull-up resistor. 31 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 Table 2-25. Boundary Scan (IEEE(R) 1149.1) Pin Symbol Type Name/Description AN22 AK21 TCK TDI I I pu AP23 TMS I pu AJ21 TRST I pu AN23 TDO O Test Clock. This signal provides timing for boundary scan test operations. Test Data In. Boundary scan test data input signal, sampled on the rising edge of TCK. Test Mode Select. Controls boundary scan test operations. TMS is sampled on the rising edge of TCK. Test Reset (Active-Low). This signal provides an asynchronous reset for the boundary scan TAP controller. Test Data Out. Boundary-scan test data output signal is updated on the falling edge of TCK. The TDO output will be high-impedance except when transmitting test data. Table 2-26. General-Purpose Interface Pin Symbol Type AP22 RSTN I pu AM21 PMRST AP24 IC3STATEN AM23 AJ22 AN24 AP25 AM24 SCK1 SCK2 SCAN_EN SCANMODE IDDQ Name/Description Global Hardware Reset. Active-low. Initializes all internal registers to their default state. This is an asynchronous reset on the falling edge, but RSTN should be held low for at least 1 s. RSTN should be held low until both power supplies (1.5 V and 3.3 V) are stabilized upon powerup. I/O pd Performance Monitor Reset. Resets error counters. When enabled as an input, it is a 1 s square wave that forces an update of PM counters upon the rising edge. When the PMRST is generated internally from the MPU clock, this pin is an output. I pu Output Enable. When high, output buffers will operate normally. When low, all outputs will be forced to a high-impedance state. IC3STATEN should be held low until both power supplies (1.5 V and 3.3 V) are stabilized upon powerup. I pd Scan Clock 1. Reserved. Do not connect. I pd Scan Clock 2. Reserved. Do not connect. I pd Scan Enable. Reserved. Do not connect. I pd Serial Scan Input for Testing. Reserved. Do not connect. I IDDQ Input. This pin must be externally pulled down with a 1 k resistor. Table 2-27. CDR Interface 32 Pin Symbol Type AJ15 AJ14 AM15 AJ16 AL17 AK17 AM14 BYPASS TSTPHASE ECSEL ETOGGLE EXDNUP TSTMODE TSTSFTLD I pd I pd I pd I pd I pd I pd I pd Name/Description High-Speed CDR Bypass. Reserved. Do not connect. Test Phase. Reserved. Do not connect. External Clock Select. Reserved. Do not connect. External Toggle. Reserved. Do not connect. External Down Up. Reserved. Do not connect. Test Mode. Reserved. Do not connect. Test Shift Load. Reserved. Do not connect. Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-28. Analog Power and Ground Signals Pin Symbol Type Name/Description AK12 AJ12 AJ11 AL34 F19 A20 AK11 VSSA_CDR1 VSSA_CDR2 VSSA_X4PLL VSSA_SFPLL VSSA_DS3PLL VSSA_E3PLL VDD15A_CDR1 -- -- -- -- -- -- -- AJ10 VDD15A_CDR2 -- AK14 VDD15A_X4PLL -- C20 VDD15A_DS3PLL -- B20 VDD15A_E3PLL -- AK33 VDD33A_SFPLL -- CDR1 Ground. Isolated ground for the internal CDR1. CDR2 Ground. Isolated ground for the internal CDR2. X4PLL Ground. Isolated ground for the internal X4PLL. SFPLL Ground. Isolated ground for the internal SFPLL. DS3PLL Ground. Isolated ground for the internal DS3PLL. E3PLL Ground. Isolated ground for the internal E3PLL. CDR1 Power. 1.5 V power supply for the internal CDR1, which is used by the high-speed receive CDR, the protection receive CDR and the three CDRs associated with the mate interconnect ports. Good engineering practice needs to be applied; refer to the evaluation board schematic. CDR2 Power. 1.5 V power supply for the internal CDR2, which is used by the high-speed receive CDR, the protection receive CDR and the three CDRs associated with the mate interconnect ports. Good engineering practice needs to be applied; refer to the evaluation board schematic. X4PLL Power. 1.5 V power supply for the internal X4PLL, which is used for the transmit protection 1 + 1 port. Good engineering practice needs to be applied; refer to the System Design Guide. DS3PLL Power. 1.5 V power supply for the internal DS3PLL, which is used by the DS3DJA. Good engineering practice needs to be applied; refer to the evaluation board schematic. E3PLL Power. 1.5 V power supply for the internal E3PLL, which is used by the E3DJA. Good engineering practice needs to be applied; refer to the System Design Guide. SFPLL Power. 3.3 V power supply for the internal SFPLL, which is used by the CG block. Good engineering practice needs to be applied; refer to the evaluation board schematic. Agere Systems Inc. 33 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 Table 2-29. Digital Power and Ground Signals Pin Symbol Type Name/Description AA7, AA16, AA17, AA18, AA19, AA28, AB7, AB16, AB17, AB18, AB19, AB28, AC7, AC28, AD7, AD28, AE7, AE28, AF7, AF28, AH9, AH10, AH11, AH12, AH13, AH14, AH15, AH16, AH19, AH20, AH21, AH22, AH23, AH24, AH25, AH26, G9, G10, G11, G12, G13, G14, G15, G16, G19, G20, G21, G22, G23, G24, G25, G26, J7, J28, K7, K28, L7, L28, M7, M28, N7, N16, N17, N18, N19, N28, P7, P16, P17, P18, P19, P28, R7, R28, T7, T13, T14, T21, T22, T28, U13, U14, U21, U22, V13, V14, V21, V22,W7, W13, W14, W21, W28, Y7, Y28, W22 A2, A33, AA4, AC31, AD4, AF31, AG4, AG7, AG28, AH8, AH17, AH18, AH27, AJ31, AK4, AL6, AL9, AL12, AL21, AL24, AL27, AL30, AM2, AM33, AN1, AN3, AN32, AN34, AP2, AP33, B1, B3, B32, B34, C2, C33, D5, D8, D11, D14, D17, D20, D23, D26, D29, E31, F4, G8, G17, G18, G27, H7, H28, H31, J4, L31, M4, P31, R4, U7, U28, U31, V28, V4, V7, Y31 A1, A17, A18, A34, AA13, AA14, AA21, AA22, AA31, AB13, AB14, AB21, AB22, AC4, AD31, AF4, AG6, AG31, AJ4, AJ5, AK2, AK3, AK5, AK31, AL2, AL5, AL11, AL20, AL23, AL26, AL29, AL8, AM1, AM3, AM11, AM12, AM32, AN2, AN6, AN9, AN12, AN33, AP1, AP12, AP34, B2, B33, C3, C32, D6, D9, D12, D15, D18, D21, D24, D27, D30, E4, E5, F31, H4, J31, L4, M31, N13, N14, N21, N22, P4, P13, P14, P21, P22, R31, T16, T17, T18, T19, U1, U4, U16, U17, U18, U19, U34, V1, V16, V17, V18, V19, V31, V34, W16, W17, W18, W19, Y4 VDD15 -- Common power signals for 1.5 V VDD. VDD33 -- Common power signals for 3.3 V VDD. VSS -- Common ground signals. 34 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 3 Operating Conditions and Reliability 3.1 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 3-1. Absolute Maximum Ratings Parameter Supply Voltage (VDD33) Supply Voltage (VDD15) Input Voltage: LVCMOS LVDS Power Dissipation Storage Temperature Range Min -0.5 -0.3 Max 4.2 2.0 Unit V V -0.3 -0.3 -- -65 5.25 VDD33 + 0.3 -- 125 V V mW C 3.2 Recommended Operating Conditions Table 3-2 lists the voltages, along with the tolerances, that are required for proper operation of the TMXF84622 device. Table 3-2. Recommended Operating Conditions Parameter 3.3 V Power Supply 1.5 V Power Supply Ground 1.0 V: LVDS Reference* 1.4 V: LVDS Reference* Ambient Temperature Symbol VDD33 VDD15 VSS REF10 REF14 TA Min 3.14 1.4 -- -- -- -40 Typ 3.3 1.5 0.0 1.0 1.4 -- Max 3.47 1.6 -- -- -- 85 Unit V V V V V C * Internal reference voltage is used if UMPR_LVDS_REF_SEL = 1, or else external voltage is used. 3.3 Handling Precautions Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. Agere employs both a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in each of the models, as defined by JEDEC's JESD22-A114 (HBM) and JESD22-C101 (CDM) standards. Table 3-3. ESD Tolerance Device TMXF84622 Agere Systems Inc. Minimum Threshold HBM 2000 V CDM 500 V 35 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 3.4 Thermal Parameters (Definitions and Values) System and circuit board level performance depends not only on device electrical characteristics, but also on device thermal characteristics. The thermal characteristics frequently determine the limits of circuit board or system performance, and they can be a major cost adder or cost avoidance factor. When the die temperature is kept below 125 C, temperature-activated failure mechanisms are minimized. The thermal parameters that Agere provides for its packages help the chip and system designer choose the best package for their applications, including allowing the system designer to thermally design and integrate their systems. It should be noted that all the parameters listed below are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. JA - Junction to Air Thermal Resistance JA is a number used to express the thermal performance of a part under JEDEC standard natural convection conditions. JA is calculated using the following formula: JA = (TJ - Tamb) / P; where P = power JMA - Junction to Moving Air Thermal Resistance JMA is effectively identical to JA but represents performance of a part mounted on a JEDEC four layer board inside a wind tunnel with forced air convection. JMA is reported at airflows of 200 LFPM and 500 LFPM (linear feet per minute), which roughly correspond to 1 m/s and 2.5 m/s (respectively). JMA is calculated using the following formula: JMA = (TJ - Tamb) / P JC - Junction to Case Thermal Resistance JC is the thermal resistance from junction to the top of the case. This number is determined by forcing nearly 100% of the heat generated in the die out the top of the package by lowering the top case temperature. This is done by placing the top of the package in contact with a copper slug kept at room temperature using a liquid refrigeration unit. JC is calculated using the following formula: JC = (TJ - TC) / P JB - Junction to Board Thermal Resistance JB is the thermal resistance from junction to board. This number is determined by forcing the heat generated in the die out of the package through the leads or balls by lowering the board temperature and insulating the package top. This is done using a special fixture, which keeps the board in contact with a water chilled copper slug around the perimeter of the package while insulating the package top. JB is calculated using the following formula: JB = (TJ - TB) / P JT - Junction Temperature to Case Temperature JT correlates the junction temperature to the case temperature. It is generally used by the customer to infer the junction temperature while the part is operating in their system. It is not considered a true thermal resistance. JT is calculated using the following formula: JT = (TJ - TC) / P Table 3-4. Thermal Parameter Values Parameter Temperature C/Watt JA 13 JMA (1 m/s) 9.7 JMA (2.5 m/s) 8.2 JC 2.5 JB 7.8 JT 1 36 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 3.5 Reliability Product reliability can be calculated as the probability that the product will perform under normal operating conditions for a set period of time. Factors influencing the reliability of a product cover a range of variables, including design and manufacturing. The failure rate of a product is given as the number of units failing per unit time. This failure rate is known as FIT, which is as follows: 1 FIT = 1 failure/1 x 109 hours. Another unit used for failure rate is known as MTBF, which is 1/FIT. Many assumptions are made when calculating the failure rate for a product, such as the average junction temperature and activation energy. The assumptions made for calculating FIT and MTBF are shown in Table 3-5: Table 3-5. Reliability Data Junction Temperature FIT (Per 1 x 109 Device Hours) 55 C 22 MTBF Activation Energy 7 4.55 x 10 hours 0.7eV Moisture Sensitivity Level--This is based on IPC/JEDEC test method J-STD-020 (which lists a means of testing and classifying devices for a certain level of moisture sensitivity). Table 3-6. Moisture Sensitivity Level Device Level TMXF84622 2A L-TMXF84622 (Pb-free) 3 3.6 Recommended Powerup Sequence The Ultramapper device requires dual power supplies, a 3.3 V supply for the I/O and a 1.5 V supply for the core. During powerup, RSTN should be held low (holding the device in reset) and IC3STATEN should be held low (3-stating all output buffers). After the 3.3 V and 1.5 V supplies are stable, MPCLK (which affects the device reset) should be applied and must be present for at least two clock cycles before RSTN and IC3STATEN are released. It is then recommended that IC3STATEN be released concurrent with, or after, the release of RSTN. There are no constraints as to which supply (3.3 V or 1.5 V) must come up first, nor does it matter how long it takes the second supply to come up after the first supply. Additionally, it is recommended that the TRST pin be held low (or pulsed low) upon startup. Agere Systems Inc. 37 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 3.7 Power Consumption The power consumption of the device is application dependent since it is not possible to use all the device features simultaneously. The nominal measured values for power per block are shown in Table 3-8. Table 3-7. Typical Power Consumption by Application Application Conditions Typ 1.5 V Typ 3.3 V Typ Total Power Power Power OC12 to 84 DS1 Cross Connect TMUX, three SPEMPRs, three VTMPRSs, three CHI Loopback DS1DJAs, three FRMs, and CHI at 8 Mbits/s OC12 to 84 DS1 Transport Mode TMUX, three SPEMPRs, three VTMPRSs, three DS1DJAs, and three FRMs OC12 to 6 DS3 Clear Channel TMUX, six SPEMPRs, one DS3DJA, and six DS3 I/Os OC12 to STSPP High-speed loopback through STSPP and TMUX OC12 to 84 DS1 Portless Trans- TMUX, three STS1LTs, five SPEMPRs, three VTMPRs, two M13s, three DS1DJAs, and three FRMs MUX Application, Transport Mode OC12 to 84 DS1 TransMUX TMUX, three STS1LTs, three SPEMPRs, three Application, Transport Mode VTMPRs, three M13s, three DS1DJAs, and three FRMs 1.65 W 0.55 W 2.20 W 1.60 W 0.50.W 2.10 W 1.00 W 0.90 W 1.70 W 0.75 W 0.50 W 0.85 W 1.75 W 1.40 W 2.55 W 1.70 W 0.60 W 2.30 W Table 3-8. Typical Power Consumption Per Block Typical power by block refers to all instances being used. Block TMUX STSPP STSXC MRXC SPEMPR STS1LT VTMPR E13 M13 TPG/TPM FRM DS1DJA DS3DJA MPU CDR/PLL LVDS I/O NSMI I/O DS3 I/O Maximum Instance 1 1 1 1 6 3 3 3 3 1 3 3 1 1 1 15 3 6 Typical, Per Single Instance 0.120 0.020 0.200 0.050 0.009 0.028 0.015 0.013 0.013 TBD 0.195 0.026 0.050 0.420* 0.150 0.020 0.032 0.050 Unit W W W W W W W W W W W W W W W W W W * Measured with a 50 MHz MPCLK. With a 25 MHz MPCLK, the typical per single instance value of MPU power is approximately 0.2 W. Testing has shown that, on the average, approximately 0.35 W can be saved by utilizing the divide by 16 MPU clock power down feature. Please refer to MPU register 0x0019 in the Ultramapper Register Description document for further information. Additional MPU clock divisor options are available. Additional power can be saved by powering down unused LVDS buffers. For details, please see MPU register 0x0026 in the Ultramapper Register Description document. 38 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 4 Electrical Characteristics 4.1 LVCMOS Interface Specifications Table 4-1. LVCMOS Input Specifications Parameter Input Leakage Current High-input Voltage Low-input Voltage Input Capacitance Symbol II VIH VIL CI Conditions VSS < VIN < VDD33 -- -- -- Min -- 2.0 VSS -- Typ -- -- -- -- Max 1.0* -- 0.8 1.5 Unit A V V pF Symbol VOL VOH Conditions IOL = max IOL = max Min VSS VDD - 0.5 Typ -- -- Max 0.5 VDD Unit V V IOL IOH CO IOZ -- -- -- -- -- -- -- -- -- -- 3 -- 6* -6* -- 10 mA mA pF A * Excludes current due to pull-up or pull-down resistors. Table 4-2. LVCMOS Output Specifications Parameter Output Voltage Low Output Voltage High Output Current Low Output Current High Output Capacitance HIZ Output Leakage Current * Output current = 10 mA (maximum) for DTN, NSMITXCLK[3:1], and CHITXDATA[1, 3, 4, 5, 6, 10, 11]. Table 4-3. LVCMOS Bidirectional Specifications Parameter Symbol Conditions Max Unit IL VSS < VIN < VDD33 -- -- 11 A VIH -- 2.0 -- VDD33 + 0.3 V Low-input Voltage VIL -- Biput Capacitance CIB -- VSS -- 0.8 V -- 5.0 -- pF Output Voltage Low VOL IOL = -6 mA* -- -- 0.5 V Output Voltage High VOH IOH = 6 mA* 2.4 -- -- V Output Current Low IOL -- -- -- 6 mA Output Current High IOH -- -- -- -6 mA Leakage Current High-input Voltage Min Typ * The following bidirectional pins can sink/source 10 mA: NSMIRXCLK[3:1]. Agere Systems Inc. 39 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 4.2 LVDS Interface Characteristics 3.3 V 5% VDD, -40 C to +125 C junction temperature. . Table 4-4. LVDS Interface dc Characteristics Parameter Input Voltage Range: High (VIA or VIB) Low (VIA or VIB) Input Differential Threshold Input Differential Hysteresis Receiver Differential Input Impedance Symbol VI VIH VIL VIDTH VHYST RIN Test Conditions Min Typ Max Unit -- 0 -100 -- 80 -- -- -- -- 100 2.4 -- 100 --* 120 V V mV mV Input Buffer Parameters |VGPD| < 925 mV, dc--1 MHz dc-- 450 MHz (+VIDTH) - (-VIDTH) With build-in termination, center-tapped Output Buffer Parameters Output Voltage: High (VOA or VOB) Low (VOA or VOB) Output Differential Voltage Output Offset Voltage Output Impedance, Single Ended RO Mismatch Between A and B Change in Differential Voltage Between Complementary States Change in Output Offset Voltage Between Complementary States Output Current Output Current VOH VOL |VOD| VOS RO RO |VOD| RLOAD = 100 1% RLOAD = 100 1% RLOAD = 100 1% RLOAD = 100 1% VCM = 1.0 V and 1.4 V VCM = 1.0 V and 1.4 V RLOAD = 100 1% -- 0.925 0.25 1.125 80 -- -- -- -- -- -- 100 -- -- 1.475 -- 0.45 1.275 120 10 25 V V V V % mV VOS RLOAD = 100 1% -- -- 25 mV ISA, ISB ISAB Driver shorted to VSS Drivers shorted together -- -- -- -- 24 12 mA mA * The buffer will not produce output transitions when input is open-circuited. When the true and complement inputs are floating, the input buffer will not oscillate. 250 mV |VA - VB| 450 mV Notes: The characteristics in the table above apply under the following conditions: External LVDS reference chosen (UMPR_LVDS_REF_SEL = 0). REF10 = 1.0 V 3% and REF14 = 1.4 V 3%. Internal LVDS reference chosen (UMPR_LVDS_REF_SEL = 1). VDD33 supply controlled to within 3%. When UMPR_LVDS_REF_SEL = 1, the internal reference levels are derived using a resistor ladder from VDD33. These levels will vary as much as the VDD33 supply does and are therefore only as accurate as the VDD33. If VDD33 cannot be controlled to within 3%, one or more IEEE specifications may be violated. While this may not necessarily lead to data errors during transmission, interoperability issues may arise due to specification noncompliance. 40 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 5 Timing 5.1 TMUX High-Speed Interface Timing 80% 20% tR tF Figure 5-1. TMUX LVDS Signal Rise/Fall Timing 50% RHSCP/N tSU RHSDP/N tH 50% 50% THSCOP/N tPD THSDP/N 50% Figure 5-2. TMUX LVDS Clock and Data Timing Table 5-1. High-Speed Interface Inputs Specifications Name Reference Edge Rising/Falling Max Rise Time (ns) Max Fall Time (ns) Min Setup (ns) Min Hold (ns) RHSDP/N (622 MHz)* Asynchronous -- 0.5 0.5 -- -- MHz)* Asynchronous -- 0.5 0.5 -- -- R/F 1.0 1.0 2 0 RHSDP/N (155 RHSDP/N (155 MHz) RHSCP/N * Input serial data stream should have minimum eye opening of 0.4 UIp-p, and no more than 60 consecutive bits that have no transitional edge within one minute. It must meet 100 ps maximum phase variation limit over a 200 ns interval; this translates to a frequency change of 500 ppm. Agere Systems Inc. 41 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 Table 5-2. Protection Link Inputs Specifications Name Reference Edge Rising/Falling Max Rise Time (ns) RPSDP/N (622 MHz)* Asynchronous -- 0.5 0.5 -- -- MHz)* Asynchronous -- 0.5 0.5 -- -- RPSCP/N R 1.0 1.0 2 0 RPSDP/N (155 RPSDP/N (155 MHz) Max Fall Min Setup Time (ns) (ns) Min Hold (ns) * Input serial data stream should have minimum eye opening of 0.4 UIp-p, and no more than 60 consecutive bits that have no transitional edge within one minute. It must meet 100 ps maximum phase variation limit over a 200 ns interval; this translates to a frequency change of 500 ppm. Table 5-3. High-Speed Interface Outputs Specifications Name Edge Rising/Falling Reference THSDP/N (622.08 MHz or 155.52 MHz) THSSYNC (MPU_MASTER_SLAVE = 1) THSCOP/N TLSCLK Propagation Delay Min (ns) Max (ns) 0.3 -0.5 0.8 0.2 R -- Table 5-4. Protection Link Output Specifications Name Reference TPSDP/N (622.08 MHz or 155.52 MHz) Edge Rising/Falling TPSCP/N Propagation Delay Min (ns) Max (ns) 0.3 0.8 R 5.2 THSSYNC Characteristics THSSYNC is an 8 kHz composite frame sync pulse for STS-3 or STS-12. THSSYNC contains J0, J1, and V1-1 information as shown in Figure 5-5. The time delay from any rising edge of a J0 (8 kHz) to the rising edge of the next J0 is 125 s. The time delay between any two V1-1 (2 kHz) pulses is 500 s. This is true whether in STS-3 or STS-12 mode. When MPU_MASTER_SLAVE = 1, then THSSYNC is according to Figure 5-5. J1-1 STS-3 J0 J1-3 J1-2 50 ns J1-1 V1-2 V1-1 V1-3 FIRST FRAME J0 J1-3 J1-2 J1-1 J0 SECOND FRAME J1-3 J1-2 J1-1 J0 THIRD FRAME J1-3 J1-2 FOURTH FRAME 12.5 ns STS-12 SECOND FRAME J0 J0 THIRD FRAME J1-11 J1-9 J1-7 J1-5 J1-3 J1-1 J0 J1-12 J1-10 J1-8 J1-6 J1-4 J1-2 V1-3 J1-11 J1-9 J1-7 J1-5 J1-3 J1-1 FIRST FRAME J1-12 J1-10 J1-8 J1-6 J1-4 J1-2 V1-1 J1-11 J1-9 J1-7 J1-5 J1-3 J1-1 J1-11 J1-9 J1-7 J1-5 J1-3 J1-1 50 ns J1-12 J1-10 J1-8 J1-6 J1-4 J1-2 J1-12 J1-10 J1-8 J1-6 J1-4 J1-2 J0 V1-2 FOURTH FRAME Figure 5-3. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 1) 42 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 When MPU_MASTER_SLAVE = 0, then THSSYNC (supplied from an external source) can be according to Figure 5-4. 125 s STS-3 J0 50 ns J0 J0 FIRST FRAME J0 THIRD FRAME SECOND FRAME FOURTH FRAME 50 ns STS-12 J0 J0 125 s J0 THIRD FRAME SECOND FRAME FIRST FRAME J0 FOURTH FRAME Figure 5-4. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 0) When supplied externally, the 8 kHz THSSYNC may have a 50/50 duty cycle since the signal will only be sampled on the rising edge. In this case, THSSYNC should be synchronous to THSC. Although there are no setup/hold specifications for the THSSYNC input with respect to THSC, THSSYNC still needs to be synchronous to the input transmit high-speed clock (THSC). The device looks for the rising edge of THSSYNC to occur regularly in each frame within a window, defined by the setting in TMUX_SYNC_OFFSET[3:0]. A clock derived from THSC samples the incoming frame sync. If THSSYNC is not synchronous to THSC, over time, the rising edge of THSSYNC will fall outside the window causing an STS-N/STM-N level LOF. However, if the system needs to synchronize VTs, generated from different Ultramappers or other external devices, then THSSYNC needs to look like the waveform representation in Figure 5-5, i.e., THSSYNC must be composed of both the 8 kHz and the 2 kHz sync components (J0 + V1-1--V1-3); the J1 portion is not needed. V1-2 STS-3 J0 V1-1 50 ns FIRST FRAME J0 J0 J0 V1-3 SECOND FRAME THIRD FRAME FOURTH FRAME STS-12 V1-2 J0 50 ns V1-1 FIRST FRAME J0 J0 J0 V1-3 SECOND FRAME THIRD FRAME FOURTH FRAME Figure 5-5. THSSYNC Timing Diagram for Synchronized VTs Figure 5-6 depicts the relationship between the rising edge of the input THSSYNC (when the device is in slave mode) and the beginning of the SONET frame output on THSD. The delay between THSSYNC and the start of the outgoing SONET frame is contributed to internal device delays (pertaining to multiplexing functionality, FIFO, and parallel to serial conversion). THSSYNC Y N THSD X A1 622 Mbits/s mode: N = 80 8 bits. 155 Mbits/s mode: N = 44 8 bits. For the case where TMUX_TLBITCNT, TMUX_TLSTSCNT, TMUX_TLCOLCNT, and TMUX_TLROWCNT, all = 0 (default). Changing these register values will change the location of point X with relation to point Y. Figure 5-6. Relationship Between THSSYNC and THSD Agere Systems Inc. 43 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 5.3 STS-3/STM-1 Mate Interconnect Timing 80% 20% tR tF Figure 5-7. STS-3/STM-1 Mate Rise/Fall Timing CLOCK 50% tSU TLSDATAP/N CLOCK tH 50% 50% tPD RLSDATAP/N 50% Figure 5-8. STS-3/STM-1 Mate Clock and Data Timing Table 5-5. STS-3/STM-1 Mate Interconnect Input Specifications Name Reference TLSDATAP/N[3:1] Asynchronous Edge Rising/Falling -- Max Rise Time (ns) -- Max Fall Time (ns) -- Min Setup (ns) -- Min Hold (ns) -- Table 5-6. STS-3/STM-1 Mate Interconnect Output Specifications Name Reference RLSDATAP/N[3:1] Asynchronous 44 Edge Rising/Falling -- Propagation Delay Min (ns) Max (ns) -- -- Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 5.4 TOAC, POAC, and LOPOH Timing The relationships between data, clock, and sync signals are specific to the TOAC and POAC operation mode selected. This is explained in detail in the TOAC/POAC chapter of the System Design Guide. TTOACCLK TPOACCLK tSU tH TTOACDATA TPOACDATA RTOACCLK RPOACCLK tPD RTOACDATA RPOACDATA Note: For information pertaining to the output clock duty cycle (in various TOAC/POAC modes of operation), please refer toTable 6-15 and Table 6-16. Figure 5-9. TOAC, POAC Timing LOPOHCLKIN tSU tH LOPOHDATAIN LOPOHCLKOUT tPD LOPOHDATAOUT Note: For all modes, SYNC signals are high during the clock period of the first bit of each frame. Figure 5-10. LOPOH Timing Table 5-7. TOAC, POAC, and LOPOH Inputs Specifications Name TTOACDATA TPOACDATA LOPOHDATAIN and LOPOHVALIDIN Reference TTOACCLK (output) TPOACCLK (output) LOPOHCLKIN Edge Max Rise Max Fall Min Setup Min Hold Rising/Falling Time (ns) Time (ns) (ns) (ns) R 10 10 3.5 0 R 10 10 3.5 0 F 8 8 5 5 Table 5-8. TOAC, POAC, and LOPOH Outputs Specifications Name RTOACDATA, RTOACSYNC TTOACSYNC RPOACDATA, RPOACSYNC TPOACSYNC LOPOHDATAOUT and LOPOHVALIDOUT Agere Systems Inc. Reference RTOACCLK TTOACCLK RPOACCLK TPOACCLK LOPOHCLKOUT Edge Rising (R) Falling (F) R R F R R Propagation Delay Min (ns) Max (ns) 0 0 0 0 0 3.5 3.5 3.5 3.5 5 45 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 5.5 DS3/E3/STS-1 Timing Figure 5-11 shows a simplified representation of the DS3/E3/STS-1 I/O. M13/E13 BLOCK DEMUX MUX DS3RXCLKOUT Q CLK CLK D D Q DS3DATAINCLK DS3POSDATAOUT DS3POSDATAIN DS3NEGDATAOUT DS3DATAOUTCLK DS3NEGDATAIN Figure 5-11. DS3/E3 Interface Diagram in M13/E13 Block Table 5-9. DS3/E3 Inputs Specifications Name DS3POSDATAIN[6:1] DS3NEGDATAIN[6:1] Reference DS3DATAINCLK Edge Rising/Falling R/F Max Rise Time (ns) 5 Edge Rising/Falling F Max Rise Time (ns) 5 Max Fall Time (ns) 5 Min Setup (ns) 3 Min Hold (ns) 3 Table 5-10. STS-1 Inputs Specifications Name DS3POSDATAIN[6:1] DS3NEGDATAIN[6:1] Reference DS3DATAINCLK Max Fall Time (ns) 5 Min Setup (ns) 3 Min Hold (ns) 3 Table 5-11. DS3/E3/STS-1 Outputs Specifications Name DS3POSDATAOUT[6:1] DS3NEGDATAOUT[6:1] 46 Reference DS3RXCLKOUT Edge Rising/Falling R/F Propagation Delay Min (ns) Max (ns) 0 3 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 5.6 NSMI Timing NSMIRXCLK NSMITXCLK tSU tH NSMIRXDATA tPD NSMITXDATA Figure 5-12. NSMI Clock and Data Timing for the STS-1 Mode 125 s Separation depends on pointer Z3 SONET Frame (for info only) Z3 TOH TOH Z4 J1 TOH C2 NSMI_TXCLK (51.84 MHz output) NSMI_TXDATAEN (output) 89 Columns NSMI_TXDATA (output) NSMI_TXSYNC (output) Position of above pulse is provisionable 0-89 bytes + 0-7 bits before J1 125 s Z4 SONET Frame (for info only) Z4 TOH J1 TOH C2 TOH G1 NSMI_RXCLK (51.84 MHz output) NSMI_RXDATAEN (output) 89 Columns NSMI_RXDATA (input) NSMI_RXSYNC (Output) Position of above pulse is provisionable 0-89 bytes + 0-7 bits before J1 Note: Tx and Rx J1 are not aligned. Transmit path pointer is fixed at 522. Notes: Clock from SPEMPR is at 51.84 MHz rate and is not gapped. TXDATAEN is provided to mark the POH time of the SPE. J1 can occur anywhere in the frame and its position is optionally marked by TXSYNC, which is provisioned to be N columns (bytes) plus M bits earlier in time than J1. During periods where the POH is present the TXDATAEN signal goes high. Figure 5-13. NSMI Clock and Data Diagram for SPEMPR NSMI Mode Agere Systems Inc. 47 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 4760 bits DS3 frame (for info only) X2 X1 M1 M3 X1 NSMI_TXCLK 44.736 MHz NSMI_TXDATAEN NSMI_TXDATA NSMI_TXSYNC Position of this pulse is provisionable 0-256 bits before M1 4760 bits DS3 Frame X2 X1 M1 M3 X1 NSMI_RXCLK 44.736 MHz Output NSMI_RXDATAEN NSMI_RXDATA NSMI_RXSYNC Position of this pulse is provisionable 0-256 bits before M1 Notes: Clock from M13 is at 44.736 MHz rate and is not gapped. TXDATAEN is provided to mark the DS3 frame overhead times. M1 can occur asynchronously and its position is optionally marked by TXSYNC, which is provisioned to be 0 to 255 bits before the M1 bit. TXDATAEN goes low during DS3 frame overhead bits. Figure 5-14. NSMI Clock and Data Diagram for M13 NSMI Mode (NSMI <---> M13 <---> DS3 External I/O) 1536 bits E3 frame (for info only) C11 = 0 FRAME, RAI, RSVD Cj3 = 0 Stuff = data Frame NSMI_TXCLK (34.368 MHz output) NSMI_TXDATAEN (output) NSMI_TXDATA (output) NSMI_TXSYNC (output) Position of this pulse is provisionable 0-256 bits before C11 1536 bits E3 Frame (For Info only) FRAME, RAI, RSVD C11 = 0 Cj3 = 0 Stuff = data Frame NSMI_RXCLK (34.368 MHz output) NSMI_RXDATAEN (output) NSMI_RXDATA (input) NSMI_RXSYNC (output) Position of this pulse is provisionable 0-256 bits before C11 Notes: Clock from E13 is at 34.368 MHz rate and is not gapped. TXDATAEN is provided to mark the overhead time and control bits time of the E3 frame. C11's (the first C bit of the first tributary) position is optionally marked by TXSYNC, which is provisioned to be 0 to 255 bits before C11 (bit 385 of the E3 frame). During periods where the OH is present the TXDATAEN signal goes low. All C bits are zero and the stuff bits are used for data. Figure 5-15. NSMI Clock and Data Diagram for E13 NSMI Mode 1 (NSMI <---> E13 <---> E3 External I/O 48 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 1536 bits E3 frame (for info only) C11 = 0 FRAME, RAI, RSVD Cj3 = 0 Stuff = data Frame NSMI_TXCLK (51.84 MHz output) NSMI_TXDATAEN (output) NSMI_TXDATA (output) NSMI_TXSYNC (output) Position of this pulse is provisionable 0-256 bits before C11 1536 bits E3 frame (For info only) FRAME, RAI, RSVD C11 = 0 Cj3 = 0 Stuff = data Frame NSMI_RXCLK (51.84 MHz output) NSMI_RXDATAEN (output) NSMI_RXDATA (Input) NSMI_RXSYNC (output) Position of this pulse is provisionable 0-256 bits before C11 Notes: Clock from E13 is at 51.84 MHz rate and is not gapped. TXDATAEN is the combination of an internal clock enable and data enable from SPEMPR. TXDATAEN is used to mark the overhead time and control bits time of the E3 frame. Clock enable is used to gap the clock rate to 34.368 MHz. C11's (the first C bit of the first tributary) position is optionally marked by TXSYNC, which is provisioned to be 0 to 255 bits before C11 (bit 385 of the E3 frame). During periods where the OH is present the TXDATAEN signal goes low. All C bits are zero and the stuff bits are used for data. Figure 5-16. NSMI Clock and Data Diagram for E13 NSMI Mode 2 (NSMI <--> E13 <--> SPEMPR <--> STM-N) Agere Systems Inc. 49 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 NSMITXCLK Data Byte(Time Slot) for a DS0/E0 Link NSMITXDATA NSMITXSYNC MSB LSB START FSYNC LSB MSB RSVD Link number[0:4] NSMITXCLK 51.84MHz NSMITXDATA DATA Link#,Byte# DATA 1,1 DATA 2,1 DATA 1,2 DATA 2,2 DATA 5,1 01100000 01010000 00100000 00010000 01101000 DATA 5,2 DATA 5,3 NSMITXSYNC } Binary Value Link Number Provisionable 1:28 or 0:27 for DS1 FSYNC High signifies 1st byte of link N Start goes low to signify data, high otherwise Links may appear in any order, bytes per link are sequential Note: The 193rd bit of a DS1 frame is not transmitted on the NSMI but is used to locate the FSYNC position. As a consequence of this, signaling bits are not transported in Ultramapper versions 1--2.1. Version 3 devices contain a mode Figure 5-17. NSMI Clock and Data Diagram for Framer (FRM) NSMI Mode Table 5-12. NSMI Inputs Specifications Name Reference NSMIRXDATA[3:1] NSMIRXSYNC[3:1] NSMIRXDATA[3:1]* NSMIRXSYNC[3:1]* NSMIRXCLK NSMIRXCLK NSMIRXCLK NSMIRXCLK Edge Rising/Falling R R R R Max Rise Time (ns) 3.5 3.5 3.5 3.5 Max Fall Time (ns) 3.5 3.5 3.5 3.5 Min Setup (ns) 5 5 3.5 3.5 Min Hold (ns) 0 0 3 3 * Pertinent to DS3 clear channel application, which uses NSMI I/O--this feature is available only in V3.0 devices. Table 5-13. NSMI Outputs Specifications Name NSMITXDATA[3:1] NSMITXSYNC[3:1] RXDATAEN[3:1] TXDATAEN[3:1] NSMIRXSYNC[3:1] 50 Reference NSMITXCLK NSMITXCLK NSMIRXCLK NSMITXCLK NSMIRXCLK Edge Rising/Falling Propagation Delay Min (ns) Max (ns) R R R R R 0.5 0.5 0.5 0.5 0.5 8.75 8.75 8.75 8.75 8.75 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 5.7 Shared Low-Speed Line Timing LINERXCLK LINETXCLK tSU tH LINERXDATA tPD LINETXDATA Note: Single rail shown. Figure 5-18. Shared Low-Speed Line Clock and Data Timing Table 5-14. Shared Low-Speed Line Timing Input Specifications Name Reference LINERXDATA[30:1] LINERXCLK[30:1] Edge Rising/Falling R/F Max Rise Time Max Fall Time Min Setup (ns) (ns) (ns) 10* 10* 15 Min Hold (ns) 10* * Alternative specification: the maximum rise and fall times may be increased to 20 ns each if the minimum hold time is increased to 12 ns. The minimum setup time will remain at 15 ns. Table 5-15. Shared Low-Speed Line Timing Output Specifications Name Reference Edge Rising/Falling LINETXDATA[30:1] LINETXCLK[30:1] R/F Propagation Delay Min (ns) -10 Max (ns) 10 5.8 CHI Timing t2 t1 t3 VDD33 VIH VIH 50% VIL VIL t4 Figure 5-19. CHI Clock Timing Table 5-16. CHIRXGCLK and CHITXGCLK Timing Specifications Parameter Description Min Typ Max Unit -- 2 7 ns t1 Rise Time t2 Width (8.192 MHz)* 48.84 -- 73.24 ns t2 Width (16.384 MHz)* 24.42 -- 36.62 ns t3 Fall Time -- 2 7 ns t4 Period (8.192 MHz) -- 122.07 -- ns t4 Period (16.384 MHz) -- 61.03 -- ns * VIH to VIH or VIL to VIL. Agere Systems Inc. 51 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 CHIRXGFS CHITXGFS t5 t6 t7 t8 Hardware Design Guide, Revision 10 April 5, 2005 CHIRXGCLK CHITXGCLK CHIRXDATA t9 CHITXDATA Note: This figure assumes TMXF846221BL-2 is programmed to sample the frame sync signal on the rising edge of the bit clock. Figure 5-20. CHI Bus Timing Table 5-17. CHI Interface Timing Specifications Parameter Description t5 Frame Sync Setup Time to Active CHI Clock Edge Min Max Unit 15 -- ns t6 Frame Sync Hold Time from Active CHI Clock Edge 4 -- ns t7 CHIRXDATA Setup to Active CHI Clock Edge 15 -- ns t8 CHIRXDATA Hold Time from Active CHI Clock Edge 4 -- ns t9 CHITXDATA Propagation Delay from Active CHI Clock Edge 4 30 ns CHIRXGFS CHIRXGCLK w/ 0 offset w/ 1/2 bit offset w/ bit offset = 1 TS0 B0 TS0 B1 data sampled TS0 B2 TS0 B0 TS0 B1 data sampled TS0 B0 data sampled TS0 B3 TS0 B2 TS0 B1 TS0 B4 TS0 B3 TS0 B2 TS0 B5 TS0 B4 TS0 B3 TS0 B5 TS0 B4 TS0 B 0 w/ bit offset = 7 TS0 B1 data sampled w/ TS offset = 1, bit offset = 0 TS0 B0 data sampled Note: For this timing diagram, it is assumed that the frame sync signal has been programmed to be active-high, and to be sampled by the rising edge of the bit clock. Figure 5-21. Typical Receive CHI Timing (Non-CMS Mode--FRM_CMS = 0) 52 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 CHIRXGFS CHIRXGCLK TS0 B0 w/ 0 offset TS0 B1 TS0 B0 w/ 1/2 bit offset w/ bit offset = 1 w/ TS offset = 1, bit offset = 0 TS255 B0 w/ TS offset = 255, bit offset = 71/2 TS0 B1 TS0 B3 TS0 B2 TS0 B4 TS0 B3 TS0 B5 TS0 B4 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 TS255 B1 TS255 B2 TS255 B3 TS255 B4 TS255 B5 TS0 B1 TS0 B0 TS0 B2 TS0 B2 TS0 B3 TS0 B4 TS0 B5 Note: For this timing diagram, it is assumed that the frame sync signal has been programmed to be active-high, and to be sampled by the rising edge of the bit clock. Figure 5-22. Transmit CHI Timing (Non-CMS Mode--FRM_CMS = 0) CHIRXGFS CHIRXGCLK w/ 0 offset TSn B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 data sampled TSn B7 w/ 1/4 bit offset TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 data sampled TSn B7 w/ 1/2 bit offset TS0 B0 TS0 B1 TS0 B2 TS0 B3 data sampled w/ 3/4 bit offset TSn B6 TSn B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 data sampled w/ bit offset = 1 TSn B6 TSn B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 data sampled w/ 23/4 bit offset TSn B4 TSn B5 TSn B6 TSn B7 TS0 B0 TS0 B1 data sampled w/ bit offset = 7 TSn B0 TSn B1 TSn B2 TSn B3 TSn B4 TSn B5 TSn B1 TSn B2 TSn B3 TSn B4 data sampled w/ TS offset = 1, bit offset = 0 TSn - 1 B7 data sampled w/ TS offset = 13, bit offset = 31/4 w/ TS offset = 127, bit offset = 73/4 TSn B0 TSn - 13 B4 TSn - 13 B5 TSn - 13 B6 TSn - 13 B7 TSn - 12 B0 TSn - 12 B1 data sampled TSn B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 data sampled Notes: n = 127 at 16 MHz, n = 63 at 8 MHz, and n = 31 at 4 MHz. For this timing diagram, it is assumed that the frame sync signal has been programmed to be active-high, and to be sampled by the rising edge of the bit clock. Figure 5-23. Typical Receive CHI Timing (CMS Mode--FRM_CMS = 1, CHIRX/TXGCLK 4 MHz) CHIRXGFS CHIRXGCLK w/ 0 offset w/ 1/4 bit offset TSn B6 TSn B7 TSn B6 w/ 1/2 bit offset TS0 B0 TSn B7 TSn B6 TS0 B1 TS0 B0 TSn B7 TS0 B2 TS0 B1 TS0 B0 TS0 B3 TS0 B3 TS0 B2 TS0 B1 TS0 B2 TS0 B3 w/ bit offset = 1 TSn B5 TSn B6 TSn B7 TS0 B0 TS0 B1 TS0 B2 w/ TS offset = 1, bit offset = 0 TSn - 1 B6 TSn - 1 B7 TSn B0 TSn B1 TSn B2 TSn B3 w/ TS offset = 127, bit offset = 73/4 TSn B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 Note: For this timing diagram, it is assumed that the frame sync signal has been programmed to be active-high, and to be sampled by the rising edge of the bit clock. Figure 5-24. Transmit CHI Timing (CMS Mode--FRM_CMS = 1, CHIRX/TXGCLK 4 MHz)) Agere Systems Inc. 53 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 5.9 Parallel System Bus (PSB) Timing CHIRXGCLK CHITXGCLK CHIRXGFS CHITXGFS 10 ns 0 ns tSU tH CHIRXDATA tPD CHITXDATA Figure 5-25. PSB Clock and Data Timing Table 5-18. PSB Inputs Specifications Name Reference CHIRXDATA[16:1] (PSB mode) CHIRXGFS (PSB mode) CHITXGFS (PSB mode) CHIRXGCLK CHIRXGCLK CHITXGCLK Edge Rising/Falling R/F R/F R/F Max Rise Time (ns) 10 10 10 Max Fall Time (ns) 10 10 10 Min Setup (ns) 10 10 10 Min Hold (ns) 0 0 0 Table 5-19. PSB Output Specifications Name CHITXDATA[16:1] (PSB mode) 54 Reference CHITXGCLK Edge Rising/Falling R/F Propagation Delay Min (ns) Max (ns) 4 22 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 6 Reference Clocks Table 6-1. High-Speed Interface Input Clocks Specifications Clock Name RHSCP/N THSCP/N Period (ns) 6.43 6.43 THSCP/N 1.6 Frequency Accuracy (ppm) 155.52 MHz 20 155.52 MHz 20 622.08 MHz 20 Jitter -- 0.01 UIp-p or 64 psp-p or 0.001 UIrms (12 kHz--1.3 MHz) 0.04 UIp-p or 64 psp-p (12 kHz--5 MHz) Rise (ns) 0.4 0.4 Fall (ns) 0.4 0.4 Min/ Max Nom Nom Duty Cycle 0.4 (nom) 0.6 (max) -- 45%--55% Rise (ns) 0.4 Fall (ns) 0.4 Min/ Max Nom Duty Cycle 45%--55% 45%--55% Table 6-2. Protection Link Input Clock Specifications Clock Name RPSCP/N Period (ns) 6.43 Frequency Accuracy (ppm) 155.52 MHz 20 Jitter -- 45%--55% Table 6-3. DS3/E3/STS-1 Input Clocks Specifications Clock Name DS3DATAOUTCLK[6:1] (DS3) Period Frequency Accuracy (ns) (ppm) 22.353 44.736 MHz 20 DS3DATAINCLK[6:1](DS3) DS3DATAOUTCLK[6:1](E3) 22.353 44.736 MHz 29.090 34.368 MHz 20 20 DS3DATAINCLK[6:1]](E3) 29.090 34.368 MHz DS3DATAOUTCLK[6:1](STS-1) 19.290 51.84 MHz 20 20 DS3DATAINCLK[6:1](STS-1) 20 19.290 51.84 MHz Jitter 0.05 UIp-p or 1.12 nsp-p (10 kHz--400 kHz) -- 0.03 UIp-p or 0.87 nsp-p (100 kHz--800 kHz) -- 0.01 UIp-p or 0.19 nsp-p or 0.001 UIrms (12 kHz--400 kHz) -- Rise Fall Min/ (ns) (ns) Max 5 5 Max Duty Cycle 40%--60% 3.5 5 2.5 5 Max Max 45%--55% 40%--60% 3.5 5 2.5 5 Max Max 45%--55% 40%--60% 3.5 2.5 Max 45%--55% Table 6-4. DS1/E1 DJA Input Clocks Specifications Clock Name E1XCLK DS1XCLK E1XCLK DS1XCLK Agere Systems Inc. Period Frequency Accuracy Jitter (ns) (ppm) 15.25 65.536 MHz 50 0.1 UIp-p or 1.5 nsp-p (20 kHz--100 kHz) 20.20 49.408 MHz 32 0.1 UIp-p or 2.0 nsp-p (10 kHz--40 kHz) 30.52 32.768 MHz 50 0.1 UIp-p or 3.0 nsp-p (20 kHz--100 kHz) 40.40 24.704 MHz 32 0.1 UIp-p or 4.0 nsp-p (10 kHz--40 kHz) Rise Fall Min/ Duty Cycle (ns) (ns) Max 3.5 3.5 Max 40%--60% 3.5 3.5 Max 40%--60% 3.5 3.5 Max 40%--60% 3.5 3.5 Max 40%--60% 55 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 Table 6-5. M13/E13 Input Clocks Specifications Clock Name DS2AISCLK E2AISCLK Period (ns) 158.42 118.37 Frequency 6.312 MHz 8.448 MHz Accuracy (ppm) 30 30 Jitter Rise Fall (ns) (ns) 5 5 5 5 Min/ Max Max Max Duty Cycle Rise Fall (ns) (ns) 3.5 0.01 UIp-p or 0.22 nsp-p 3.5 (10 Hz--400 kHz) 0.01 UIp-p or 0.29 nsp-p 3.5 3.5 (100 Hz--800 kHz) Min/ Max Max Duty Cycle Max 45%--55% Min/ Max Max Duty Cycle -- -- 45%--55% 45%--55% Table 6-6. DS3/E3 DJA Input Clocks Specifications Clock Name DS3XCLK E3XCLK Period (ns) 22.35 Frequency 44.736 MHz Accuracy (ppm) 20 29.09 34.368 MHz 20 Jitter 45%--55% Table 6-7. LOPOH Input Clock Specifications Clock Name LOPOHCLKIN Period (ns) 51.44 Frequency 19.44 MHz Accuracy (ppm) -- Jitter -- Rise Fall (ns) (ns) 8 8 45%--55% Table 6-8. Microprocessor Interface Input Clocks Specifications Clock Name Period (ns) Frequency Accuracy (ppm) Jitter Rise Fall Min/Max (ns) (ns) Duty Cycle MPCLK (min) 62.5 16 MHz -- -- 4 4 Min 45%--55% MPCLK (max)* 15.0 66.67 MHz -- -- 4 4 Max 45%--55% * The following applies to the synchronous microprocessor mode (MPMODE pin = 1): If DTN is used, then the maximum frequency for MPCLK is determined by the processor's setup specification for DTN. MPU maximum bus operating frequency = 1/(MPU DTN setup time + tDTNVPD). For example, an 8 ns setup time would limit MPCLK to 50 MHz for reliable DTN detection. Table 6-9. Framer PLL Input Clocks Specifications Clock Name Period Frequency Accuracy Jitter Rise Fall Min/Max (ns) (ppm) (ns) (ns) CLKIN_PLL 19.2 51.84 MHz 20 GR-499 and G.823 -- -- -- CHIRXGTCLK (DS1 mode) 647.66 1.544 MHz 32 GR-499 10 10 Max CHIRXGTCLK (E1 mode) 488.28 2.048 MHz 50 G.823 10 10 Max Duty Cycle 40%--60% 40%--60% 40%--60% Table 6-10. CHI Input Clocks Specifications Clock Name CHIRXGCLK (CHI mode) CHIRXGCLK (CHI mode) CHIRXGCLK (CHI mode) CHIRXGCLK (CHI mode) CHITXGCLK (CHI mode) CHITXGCLK (CHI mode) CHITXGCLK (CHI mode) CHITXGCLK (CHI mode) 56 Period (ns) 488.28 244.14 122.07 61.035 488.28 244.14 122.07 61.035 Frequency Accuracy (ppm) 2.048 MHz 50 4.096 MHz 50 8.192 MHz 50 16.384 MHz 50 2.048 MHz 50 4.096 MHz 50 8.192 MHz 50 16.384 MHz 50 Jitter -- -- -- -- -- -- -- -- Rise Fall Min/Max (ns) (ns) 10 10 Max 10 10 Max 10 10 Max 10 10 Max 10 10 Max 10 10 Max 10 10 Max 10 10 Max Duty Cycle 40%--60% 40%--60% 40%--60% 40%--60% 40%--60% 40%--60% 40%--60% 40%--60% Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 6-11. PSB Input Clocks Specifications Clock Name Period (ns) 51.44 51.44 Rise Fall Min/ (ns) (ns) Max 10 10 Max 10 10 Max Duty Cycle Period Frequency Accuracy Jitter Rise Fall Min/ (ns) (ppm) (ns) (ns) Max 6.43 155.52 MHz 20 0.1 UIp-p -- -- -- 1.6 622 MHz 20 0.1 UIp-p -- -- -- Duty Cycle CHIRXGCLK (PSB mode) CHITXGCLK (PSB mode) Frequency 19.44 MHz 19.44 MHz Accuracy (ppm) 20 20 Jitter -- -- 40%--60% 40%--60% Table 6-12. High-Speed Interface Output Clocks Specifications Clock Name THSCOP/N THSCOP/N 45%--55% 45%--55% Table 6-13. Protection Link Output Clocks Specifications Clock Name TPSCP/N TPSCP/N Period (ns) 6.43 1.6 Frequency Accuracy Jitter Rise Fall (ppm) (ns) (ns) 155.52 MHz 20 -- -- -- 622.08 MHz 20 -- -- -- Min/ Max -- -- Duty Cycle Frequency Accuracy Jitter Rise Fall Min/ (ppm) (ns) (ns) Max 19.44 MHz 20 -- 1.5 1.5 Nom 19.44 MHz 20 -- 1.5 1.5 Nom Duty Cycle 45%--55% 45%--55% Table 6-14. Line Timing Interface Output Clocks Specifications Clock Name RLSCLK TLSCLK Period (ns) 51.44 51.44 45%--55% 45%--55% Table 6-15. TOAC Output Clocks Specifications Clock Name Frequency Accuracy Jitter Rise Fall (ppm) (ns) (ns) Min/ Max Duty Cycle 578 1.728 MHz -- -- 1.5 1.5 Nom 40%--60% 5.2 (s) 192 kHz -- -- 1.5 1.5 Nom 27%--47%* RTOACCLK (TMUX; STS-12 D4-12 mode) 1.73 (s) 576 kHz -- -- 1.5 1.5 Nom 43%--63%* RTOACCLK (STS1LT; full access) RTOACCLK (TMUX; STS-12 D1-3 mode) Period (ns) RTOACCLK (TMUX; STS-12 full access) 48.22 20.736 MHz -- -- 1.5 1.5 Nom 23%--43%* RTOACCLK (TMUX; STS-3 D1-3 mode) 5.2 (s) 192 kHz -- -- 1.5 1.5 Nom 48%--68%* RTOACCLK (TMUX; STS-3 D4-12 mode) 1.73 (s) 576 kHz -- -- 1.5 1.5 Nom 42%--62%* 192.9 5.184 MHz -- -- 1.5 1.5 Nom 23%--43%* RTOACCLK (TMUX; STS-3 full access) TTOACCLK (STS1LT; full access) 578 1.728 MHz -- -- 1.5 1.5 Nom 40%--60% 5.2 (s) 192 kHz -- -- 1.5 1.5 Nom 27%--47%* TTOACCLK (TMUX; STS-12 D4-12 mode) 1.73 (s) 576 kHz -- -- 1.5 1.5 Nom 43%--63%* 20.736 MHz -- -- 1.5 1.5 Nom 23%--43%* TTOACCLK (TMUX; STS-12 D1-3 mode) TTOACCLK (TMUX; STS-12 full access) 48.22 TTOACCLK (TMUX-STS-3 D1-3 mode) 5.2 (s) 192 kHz -- -- 1.5 1.5 Nom 48%--68%* TTOACCLK (TMUX-STS-3 D4-12 mode) 1.73 (s) 576 kHz -- -- 1.5 1.5 Nom 42%--62%* 192.9 5.184 MHz -- -- 1.5 1.5 Nom 23%--43%* TTOACCLK (TMUX-STS-3 full access) * Positive duty cycle. Agere Systems Inc. 57 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 Table 6-16. POAC Output Clocks Specifications Clock Name Period Frequency Accuracy (ppm) -- -- -- -- -- -- Jitter RPOACCLK (TMUX) RPOACCLK (STS1LT) RPOACCLK (SPEMPR) TPOACCLK (TMUX) TPOACCLK (STS1LT) TPOACCLK (SPEMPR) 1.73 (s) 1.73 (s) 1.73 (s) 1.73 (s) 1.73 (s) 1.73 (s) 576 kHz 576 kHz 576 kHz 576 kHz 576 kHz 576 kHz Accuracy (ppm) 44.736 MHz 20 34.368 MHz 20 51.84 MHz 20 Jitter -- -- -- -- -- -- Rise Fall (ns) (ns) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 Min/ Max Nom Nom Nom Nom Nom Nom Duty Cycle 40%--60% 40%--60% 40%--60% 40%--60% 40%--60% 40%--60% Table 6-17. DS3/E3/STS-1 Output Clocks Specifications Clock Name DS3RXCLKOUT [6:1](DS3) DS3RXCLKOUT [6:1](E3) DS3RXCLKOUT [6:1] (STS-1) Period (ns) 22.353 29.09 19.29 Frequency GR-253 G.783 GR-253 Rise (ns) 1.5 1.5 1.5 Fall (ns) 1.5 1.5 1.5 Min/ Max Nom Nom Nom Duty Cycle Rise Fall (ns) (ns) 1.5 1.5 Min/ Max Nom Duty Cycle Rise (ns) 1.5 1.5 Fall (ns) 1.5 1.5 Min/ Max Nom Nom Duty Cycle Rise Fall (ns) (ns) -- -- -- -- Min/ Max -- -- Duty Cycle 45%--55% 45%--55% 45%--55% Table 6-18. LOPOH Output Clock Specifications Clock Name LOPOHCLKOUT Period (ns) 51.44 Frequency 19.44 MHz Accuracy (ppm) 20 Jitter Accuracy (ppm) 20 20 Jitter Accuracy (ppm) 32 50 Jitter -- 45%--55% Table 6-19. NSMI Output Clocks Specifications Clock Name RXDATAEN NSMITXCLK Period (ns) 19.29 19.29 Frequency 51.84 MHz 51.84 MHz -- -- 45%--55% 45%--55% Table 6-20. Framer PLL Output Clocks Specifications Clock Name CG_PLLCLKOUT CG_PLLCLKOUT Period (ns) 647.66 488.28 Frequency 1.544 MHz 2.048 MHz GR-499 G.823 45%--55% 45%--55% Table 6-21. Shared Low-Speed Receive Line Input/Output Clocks Specifications Clock Name LINERXCLK (framer; DS1) LINERXCLK (framer; E1) LINERXCLK (M12) LINERXCLK (E12) LINERXCLK (VTMPR; DS1) LINERXCLK (VTMPR; E1) LINERXCLK (VTMPR; VC11) LINERXCLK (VTMPR; VC12) LINERXCLK (M23) 58 Period (ns) Frequency 647.66 488.28 647.66 488.28 647.66 488.28 600.96 446.42 158.42 1.544 MHz 2.048 MHz 1.544 MHz 2.048 MHz 1.544 MHz 2.048 MHz 1.664 MHz 2.24 MHz 6.312 MHz Accuracy (ppm) 32 50 32 50 32 50 20 20 30 Jitter -- -- -- -- -- -- -- -- -- Rise (ns) 10 10 10 10 10 10 10 10 10 Fall (ns) 10 10 10 10 10 10 10 10 10 Min/ Max Max Max Max Max Max Max Max Max Max Duty Cycle 45%--55% 45%--55% 45%--55% 45%--55% 45%--55% 45%--55% 45%--55% 45%--55% 45%--55% Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 6-21. Shared Low-Speed Receive Line Input/Output Clocks Specifications (continued) Clock Name LINERXCLK (E23) LINERXCLK (DJA; DS1) LINERXCLK (DJA; E1) LINERXCLK (TPG; DS1) LINERXCLK (TPG; E1) Period (ns) Frequency 118.37 647.66 488.28 647.66 488.28 8.448 MHz 1.544 MHz 2.048 MHz 1.544 MHz 2.048 MHz Accuracy (ppm) 30 32 50 32 50 Jitter -- -- -- -- -- Rise (ns) 10 10 10 10 10 Fall (ns) 10 10 10 10 10 Min/ Max Max Max Max Max Max Duty Cycle Rise (ns) 1.5 1.5 10 10 1.5 1.5 1.5 1.5 10 10 1.5 1.5 1.5 1.5 Fall (ns) 1.5 1.5 10 10 1.5 1.5 1.5 1.5 10 10 1.5 1.5 1.5 1.5 Min/ Max Nom Nom Max Max Nom Nom Nom Nom Max Max Nom Nom Nom Nom Duty Cycle Rise (ns) 3.5 3.5 1.5 1.5 3.5 Fall (ns) 3.5 3.5 1.5 1.5 3.5 Min/ Max Max Max Nom Nom Max Duty Cycle 45%--55% 45%--55% 45%--55% 45%--55% 45%--55% Table 6-22. Shared Low-Speed Transmit Line Input/Output Clocks Specifications Clock Name LINETXCLK (framer; DS1) LINETXCLK (framer; E1) LINETXCLK (M12) LINETXCLK (E12) LINETXCLK (VTMPR; DS1) LINETXCLK (VTMPR; E1) LINETXCLK (VTMPR; VC11) LINETXCLK (VTMPR; VC12) LINETXCLK (M23) LINETXCLK (E23) LINETXCLK (DJA; DS1) LINETXCLK (DJA; E1) LINETXCLK (TPG; DS1) LINETXCLK (TPG; E1) Period (ns) Frequency 647.66 488.28 647.66 488.28 647.66 488.28 600.96 446.42 158.42 118.37 647.66 488.28 647.66 488.28 1.544 MHz 2.048 MHz 1.544 MHz 2.048 MHz 1.544 MHz 2.048 MHz 1.664 MHz 2.24 MHz 6.312 MHz 8.448 MHz 1.544 MHz 2.048 MHz 1.544 MHz 2.048 MHz Accuracy (ppm) 32 50 32 50 32 50 20 20 30 30 32 50 32 50 Jitter Accuracy (ppm) 20 20 20 20 20 Jitter -- -- -- -- -- -- -- -- -- -- -- -- -- -- 45%--55% 45%--55% 45%--55% 45%--55% 45%--55% 45%--55% 45%--55% 45%--55% 45%--55% 45%--55% 45%--55% 45%--55% 45%--55% 45%--55% Table 6-23. NSMI Input/Output Clocks Specifications Clock Name NSMIRXCLK (framer) NSMIRXCLK (STS1LT) NSMIRXCLK (M13) NSMIRXCLK (E13) NSMIRXCLK (SPEMPR) Agere Systems Inc. Period (ns) Frequency 19.29 19.29 22.35 29.09 19.29 51.84 MHz 51.84 MHz 44.736 MHz 34.368 MHz 51.84 MHz -- -- -- -- -- 45%--55% 45%--55% 45%--55% 45%--55% 45%--55% 59 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 7 Microprocessor Interface Timing Note: To allow proper operation of the microprocessor interface upon device/board bring up, the recommended powerup sequence (listed in Section 3.6 Recommended Powerup Sequence, on page 37) should be followed. Specifically, to avoid potential bus contention issues, the IC3STATEN pin should be held low during boot up. 7.1 Synchronous Write Mode The synchronous microprocessor interface mode is selected when MPMODE (pin F6) = 1. In this mode, MPCLK used for the Ultramapper is the same as the microprocessor clock. Interface timing for the synchronous mode write cycle is given in Figure 7-1 and in Table 7-1, and for the read cycle in Figure 7-2 and in Table 7-2. T0 T1 T2 T3 Tn - 2 Tn - 1 Tn MPCLK tADDRVS tAPD tCSNVS tAPD ADDR[20:0] CSN tWS tAIPD ADSN tAPD tWS RWN tAPD tWS DATA[15:0] (INPUT) tDTNVPD tDTNIPD tADSNVDTF DTN Notes: MPCLK ADDR [20:0] CSN (Input) ADSN (Input) RWN (Input) DATA[15:0] DTN (Output) HIGH Z HIGH Z Input clock to Ultramapper MPU block. The address will be available throughout the entire cycle. Chip select is an active-low signal. Address strobe is active-low. ADSN must be one MPCLK clock period wide. The read (H) write (L) signal is always high except during a write cycle. Data will be available during cycle T1. Data transfer acknowledge is active-low for one clock and then driven high before entering a high-impedance state. (This is done with an I/O pad using the input as feedback to qualify the 3-state term.) DTN will become 3-stated when CSN is high. Typically, DTN is active for four or five MPCLK cycles after ADSN is low. Figure 7-1. Microprocessor Interface Synchronous Write Cycle--MPMODE Pin = 1 60 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 7-1. Microprocessor Interface Synchronous Write Cycle Specifications Symbol Parameter MPCLK 16 MHz Min--66* MHz Max Frequency tWS ADSN, RWN, DATA (write) Valid to MPCLK tAPD MPCLK to ADDR, RWN, DATA, CSN (write) Invalid tCSNVS CSN Valid to MPCLK tADDRVS ADDR Valid to MPCLK tAIPD MPCLK to ADSN Invalid tDTNVPD MPCLK to DTN Valid tDTNIPD MPCLK to DTN Invalid MPCLK TADSNVDTF ADSN Valid to DTN Falling Setup (Min) -- 6.7 -- 6 3.5 -- -- -- Hold (Min) -- -- 0 -- -- 0 -- -- Delay (Min) -- -- -- -- -- -- 2.5 2.5 -- -- -- Delay (Max) -- -- -- -- -- -- 12 12 -- Unit MHz ns ns ns ns ns ns ns ns * If DTN is used, then the maximum frequency for MPCLK is determined by the processor's setup specification for DTN. MPU maximum bus operating frequency = 1/(MPU DTN setup time + tDTNVPD). For example, an 8 ns setup time would limit MPCLK to 50 MHz for reliable DTN detection. DTN fall is variable, depending on the block selected for access and in some cases the state of the SONET frame. This interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. It should never exceed 35 MPCLK cycles. Certain registers in the VTMPR block have a very long acknowledge cycle (in the order of 32 MPCLK cycles). The reason for this is that those registers can also be accessed by the VTMPR lower-order path overhead interface as part of SONET overhead termination functions. Therefore the user must insert long enough delay or use the DTN signal to read/ write these registers correctly. Additionally, if the high-speed CDR is used, during initialization, enough time must be provided to allow the CDR to stabilize. If the CDR has not stabilized, it may take much longer than 35 MPCLK cycles for accesses to certain VTMPR registers (DTN return times on the order of several s). It is recommended that the user wait at least 10 ms after the CDR has been reset before attempting to access any VTMPR registers. CDR provisioning is accomplished via the UMPR_CLCR register. In addition to the above, the VT_RDY bit must be set before attempting any VTMPR register accesses. Agere Systems Inc. 61 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 7.2 Synchronous Read Mode T0 T1 T2 Tn - 4 Tn - 3 Tn - 2 Tn - 1 Tn MPCLK tAPD tAVS ADDR[20:0] tCSNSU CSN tADSNSU tSNIPD ADSN RWN tDNVPD tDNIPD tADSNVDTF DTN HIGH Z HIGH Z tDAIPD DATA[15:0] (OUTPUT) Notes: MPCLK ADDR [20:0] CSN (Input) ADSN (Input) RWN (Input) DTN (Output) DATA [15:0] Input clock to Ultramapper MPU block. The address will be available throughout the entire cycle, and must be stable before ADSN turns high. Chip select is an active-low signal. Address strobe is active-low. ADSN must be one MPCLK clock period wide. The read (H) write (L) signal is always high during the read cycle. Data transfer acknowledge on the host bus interface is initiated on T6. This signal is active for one clock, and then driven high before entering a high-impedance state. (This is done with an I/O pad using the input as feedback to qualify the 3-state term.) DTN will become 3stated when CSN is high. Typically, DTN is active four or five MPCLK cycles after ADSN is low. Read data is stable in Tn - 1. The data is guaranteed to be stable no later than the time at which DTN becomes active. Figure 7-2. Microprocessor Interface Synchronous Read Cycle--MPMODE Pin = 1 Table 7-2. Microprocessor Interface Synchronous Read Cycle Specifications Symbol Parameter MPCLK tAVS tAPD tCSNSU tADSNSU tSNIPD tDNVPD tDNIPD tDAIPD MPCLK 16 MHz Min--66* MHz Max Frequency ADDR Valid to MPCLK MPCLK to ADDR Invalid CSN Active to MPCLK ADSN Valid to MPCLK MPCLK to ADSN Inactive MPCLK to DTN Valid MPCLK to DTN Invalid MPCLK to DATA 3-State ADSN Valid to DTN Falling tADSNVDTF Setup (Min) -- 3.5 -- 6 6 -- -- -- -- -- Hold (Min) -- -- 0 -- -- 0 -- -- -- -- Delay (Min) -- -- -- -- -- -- 2.5 2.5 3.5 -- Delay (Max) -- -- -- -- -- -- 12 12 15 -- Unit MHz ns ns ns ns ns ns ns ns ns * If DTN is used, then the maximum frequency for MPCLK is determined by the processor's setup specification for DTN. MPU maximum bus operating frequency = 1/(MPU DTN setup time + tDNVPD). For example, an 8 ns setup time would limit MPCLK to 50 MHz for reliable DTN detection. DTN fall is variable, depending on the block selected for access and in some cases the state of the SONET frame. This interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. It should never exceed 35 MPCLK cycles. Certain registers in the VTMPR block have a very long acknowledge cycle (in the order of 32 MPCLK cycles). The reason for this is that those registers can also be accessed by the VTMPR lower-order path overhead interface as part of SONET overhead termination functions. Therefore the user must insert long enough delay or use the DTN signal to read/ write these registers correctly. Additionally, if the high-speed CDR is used, during initialization, enough time must be provided to allow the CDR to stabilize. If the CDR has not stabilized, it may take much longer than 35 MPCLK cycles for accesses to certain VTMPR registers (DTN return times on the order of several s). It is recommended that the user wait at least 10 ms after the CDR has been reset before attempting to access any VTMPR registers. CDR provisioning is accomplished via the UMPR_CLCR register. In addition to the above, the VT_RDY bit must be set before attempting any VTMPR register accesses. 62 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 7.3 Asynchronous Write Mode The asynchronous microprocessor interface mode is selected when MPMODE (pin F6) = 0. Interface timing for the asynchronous mode write cycle is given in Figure 7-3 and in Table 7-3, and for the read cycle in Figure 7-4 and in Table 7-4. Although this is an asynchronous interface, an MPCLK is still required. This clock can be different (asynchronous) from the MPU clock. Internal to the chip, RWN, ADSN, and DSN will be sampled by MPCLK. ADDR[20:0] tCSFDSF tAICSR CSN tAVADSF tADSRAI ADSN tAVDSF tDSNRAI DSN tRWFDSF tDSRRWR RWN tDSRDI tDVDSF DATA[15:0] (INPUT) tADSRDTR tCSRDT3 tCSFDTR tDSFDTF DTN HIGH Z HIGH Z Notes: ADDR [20:0] Address is asynchronously passed from the host bus to the internal bus. The address will be available throughout the entire cycle. ADDR must be held constant while ADSN and DSN are valid (low). CSN (Input) Chip select is an active-low signal. CSN must be held low (active) until ADSN and DSN are deasserted. ADSN (Input) Address strobe is active-low. ADSN must be stable for the entire period. ADSN and CSN may be connected and driven from the same source. DSN (Input) Data strobe is active-low. DATA [15:0] Write data is asynchronously passed from the host bus to the internal bus. Data will be available throughout the entire cycle. DATA must be held constant while DSN is valid (low). RWN (Input) The read/write signal should be high for a read cycle and low for a write cycle. It should always be held high, except during a write cycle. RWN must be held low (write) until DSN is deasserted (high). DTN (Output) Data transfer acknowledge (active-low). DTN is driven out of 3-state to inactive-high on the assertion of CSN. When the internal transaction is complete, DTN goes active-low. DTN is then driven high again when either ADSN or DSN is deasserted. DTN will become 3-stated when CSN is high. DTN fall is variable, depending on the block selected for access and in some cases the state of the SONET frame. This interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. In lab measurements, it has never exceeded 1000 ns. Figure 7-3. Microprocessor Interface Asynchronous Write Cycle--MPMODE Pin = 0 Agere Systems Inc. 63 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 Table 7-3. Microprocessor Interface Asynchronous Write Cycle Specifications Symbol Parameter Setup (Min) Hold (Min) Delay (Min) Delay (Max) Unit MPCLK tCSFDSF tAICSR tAVADSF tADSRAI tAVDSF tDSNRAI tRWFDSF tDSRRWR tDVDSF tDSRDI tCSFDTR tDSFDTF tADSRDTR tCSRDT3 MPCLK 16 MHz Min--66 MHz Max Frequency CSN Fall Setup and Hold to DSN Fall CSN Rise to ADDR Invalid ADDR Valid Setup and Hold to ADSN Fall ADSN Rise to ADDR Invalid ADDR Valid Setup and Hold to DSN Fall DSN Rise to ADDR Invalid RWN Fall Setup and Hold to DSN Fall DSN Rise to RWN Rise DATA Valid Setup and Hold to DSN Fall DSN Rise to DATA Invalid CSN Fall to DTN Rise DSN Fall to DTN Fall ADSN or DSN Rise to DTN Rise CSN Rise to DTN 3-State -- 0 -- 1.0 -- 0 -- 0 -- 0 -- -- -- -- -- -- -- 0 -- 1.42 -- 0 -- 0 -- 0 -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- 5.2 -- 2.9 2.9 -- -- -- -- -- -- -- -- -- -- -- 16.0 * 13.3 13 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns * Certain registers in the VTMPR block have a very long acknowledge cycle (in the order of 32 MPCLK cycles). The reason for this is that those registers can also be accessed by the VTMPR lower order path overhead interface as part of SONET overhead termination functions. Therefore, the user must insert a long enough delay or use the DTN signal to read/write these registers correctly. Additionally, if the high-speed CDR is used, during initialization, enough time must be provided to allow the CDR to stabilize. If the CDR has not stabilized, it may take much longer than 35 MPCLK cycles for accesses to certain VTMPR registers (DTN return times on the order of several s). It is recommended that the user wait at least 10 ms after the CDR has been reset before attempting to access any VTMPR registers. CDR provisioning is accomplished via the UMPR_CLCR register. In addition to the above, the VT_RDY bit must be set before attempting any VTMPR register accesses. 64 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 7.4 Asynchronous Read Mode ADDR[20:0] tAICSR tCSFDSF CSN tADSRAI tAVADSF ADSN tDSNRAI tAVDSF DSN RWN tCSFDTR tCSRDT3 tADSRDTR tDSFDTF DTN HIGH Z HIGH Z tDTVDV HIGH Z tADSRD3 HIGH Z DATA[15:0] Notes: ADDR [20:0] CSN (Input) ADSN (Input) DSN (Input) RWN (Input) DTN (Output) DATA [15:0] Address is asynchronously passed from the host bus to the internal bus. The address will be available throughout the entire cycle. Chip select is an active-low signal. Address strobe is active-low. Data strobe is active-low. The read (H) write (L) signal is always high during a read cycle. Data transfer acknowledge (active-low). DTN is driven out of 3-state to inactive-high on the assertion of CSN. When the internal transaction is complete, DTN goes active-low. DTN is then driven high again when either ADSN or DSN is deasserted. DTN will become 3-stated when CSN is high. 16-bit data bus. Figure 7-4. Microprocessor Interface Asynchronous Read Cycle--MPMODE Pin = 0 Agere Systems Inc. 65 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 Table 7-4. Microprocessor Interface Asynchronous Read Cycle Specifications Symbol Parameter Setup (Min) Hold (Min) Delay (Min) Delay (Max) Unit MPCLK MPCLK 16 MHz Min--66 MHz Max Frequency -- -- -- -- MHz 0 * -- -- ns tCSFDSF CSN Fall Setup and Hold to DSN Fall -- CSN Rise to ADDR Invalid -- 0 -- -- ns tAVADSF ADDR Valid Setup and Hold to ADSN Fall 1.0 -- -- -- ns tADSRAI ADSN Rise to ADDR Invalid -- 1.42 tAICSR tAVDSF ADDR Valid Setup and Hold to DSN Fall 0 -- -- -- ns -- -- ns tDSNRAI DSN Rise to ADDR Invalid -- 0 -- -- ns tCSFDTR CSN Fall to DTN Rise -- -- 5.2 16.0 ns tDSFDTF DSN Fall to DTN Fall -- 0 -- -- ns tADSRDTR ADSN or DSN Rise to DTN Rise -- -- 2.9 13.3 ns tCSRDT3 CSN Rise to DTN 3-State -- -- 2.9 13.0 ns tDTVDV DTN Valid to DATA Valid -- -- -- 0 ns tADSRD3 ADSN Rise to DATA 3-State -- -- 2.9 14 + MPCLK ns * CSN must be held low (active) until ADSN and DSN are deasserted. ADDR must be held constant while ADSN and DSN are valid (low). DTN fall is variable, depending on the block selected for access and in some cases, the state of the SONET frame. This interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. It should never exceed 35 MPCLK cycles. Certain registers in the VTMPR block have a very long acknowledge cycle (in the order of 32 MPCLK cycles). The reason for this is that those registers can also be accessed by the VTMPR lower-order path overhead interface as part of SONET overhead termination functions. Therefore the user must insert long enough delay or use the DTN signal to read/write these registers correctly. Additionally, if the high-speed CDR is used, during initialization, enough time must be provided to allow the CDR to stabilize. If the CDR has not stabilized, it may take much longer than 35 MPCLK cycles for accesses to certain VTMPR registers (DTN return times on the order of several s). It is recommended that the user wait at least 10 ms after the CDR has been reset before attempting to access any VTMPR registers. CDR provisioning is accomplished via the UMPR_CLCR register. In addition to the above, the VT_RDY bit must be set before attempting any VTMPR register accesses. DATA[15:0] is enabled by a retimed version of the ADSN. 66 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 8 Other Timing This interface may be used as either synchronous or asynchronous mode. Table 8-1. General-Purpose Inputs Specifications Name RSTN PMRST TDI and TMS Reference Async Async TCLK Edge Rising/Falling -- -- R Rise Time (ns) -- -- 5 Fall Time (ns) -- -- 5 Setup (ns) -- -- 19.5 Hold (ns) -- -- 6.4 Table 8-2. Miscellaneous Output Specifications Name RHSFSYNCN Reference Asynchronous Edge Rising/Falling -- Propagation Delay Min (ns) Max (ns) -- -- Table 8-3. General-Purpose Output Specifications Name Reference TDO TCLK Edge Rising/Falling F Propagation Delay Min (ns) Max (ns) 12.5 45 9 Hardware Design File References (IBIS, Spice, BSDL, etc.) Available upon request. Agere Systems Inc. 67 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 10 700-Pin PBGAM1T Diagrams * 2 oz option * Figure 10-1. 700-Pin PBGAM1T Physical Dimension 68 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Figure 10-2. Bottom View of 700-Pin PBGAM1T Balls Location Agere Systems Inc. 69 TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Hardware Design Guide, Revision 10 April 5, 2005 11 Ordering Information Table 11-1. Ordering Information Device Package Comcode TMXF846221BL-21 TMXF846221BL-3 L-TMXF846221BL-3* 700-pin PBGAM1T 700-pin PBGAM1T 700-pin PBGAM1T 700054129 700052305 700077978 * Pb-free/RoHS 70 Agere Systems Inc. Hardware Design Guide, Revision 10 April 5, 2005 12 Glossary AIS AMI APS ASM BER BLSR BOM Alarm indication signal Alternate mark inversion Automatic protection switch Associated signaling mode Bit error rate Bidirectional line switched ring Bit-oriented message BPV B8ZS CCI CDR CHI CMI CRC CRV DACS DJA ESF EXZ FCS FDL FEAC FEBE Bipolar violation Bipolar 8 zero substitution Common channel signaling Clock and data recovery Concentrated highway interface Coded mark inversion Cyclic redundancy check Coding rule violation Digital access cross connects Digital jitter attenuation Extended superframe Excessive zeros Frame check sequence Facility data link Far-end alarm and control Far-end block error Agere Systems Inc. TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 HDB3 HDLC LIU LOC LOF LOS LOPOH MCDR MRXC NSMI OOF PBGA POAC PRBS PRM QRSS RAI RDI REI SDH SEF TCM TOAC UDT High-density bipolar of order three High-level data link control Line interface unit Loss of clock Loss of frame Loss of signal Low-order path overhead Mate clock and data recovery Multirate cross connect Network serial multiplexed interface Out of frame Plastic ball grid array Path overhead access channel Pseudorandom bit sequence Performance report message Quasirandom signal source Remote alarm indicator Remote defect indication Remote error indication Synchronous digital hierarchy Severely errored frame Tandem connection monitoring Transport overhead access channels Unstructured data transport 71 Serializer/Deserializer (SERDES) Serial TMXF84622 Ultramapper Serial Interface the MACROsx DS3/E3/DS2/DS1/E1/DS0 622/155 Mbits/sforSONET/SDH Hardware DesignHardware Guide, Revision De10 sign Guide,April Revi-5, 2005 13 Change History 13.1 Changes to this Document Since Revision 9 On page 31, deleted STS1LT from the description. On page 39, added two rows to Table 4-3. Starting on page 55, updated the duty cycle in all tables in Section 6. Other changes that were made to this document are listed in Table 13-1. Table 13-1. Document Changes Change page 37 Change page 43 Change page 50 Change page 60 Change page 62 Change page 68 Change page 69 Change page 70 13.2 Navigating Through an Adobe Acrobat (R) Document If the reader displays this document in Acrobat Reader, clicking on any blue entry in the text will bring the reader to that reference point. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. Adobe Acrobat and Acrobat Reader are registered trademarks of Adobe Systems Incorporated. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: CHINA: (86) 21-54614688 (Shanghai), (86) 755 25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6741-9855, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere is a registered trademark of Agere Systems Inc. Agere Systems, the Agere logo, and Ultramapper are trademarks of Agere Systems Inc. Copyright (c) 2005 Agere Systems Inc. All Rights Reserved April 5, 2005 DS02-086BBAC-10 (Replaces DS02-086BBAC-9)