SEPTEMBER 2013
DSC-3210/11
1
©2013 Integrated Device Technology, Inc.
Features
◆◆
◆◆
◆64K x 16 advanced high-speed CMOS Static RAM
◆◆
◆◆
◆Equal access and cycle times
– Commercial : 12/15/20ns
– Industrial: 15/20ns
◆◆
◆◆
◆One Chip Select plus one Output Enable pin
◆◆
◆◆
◆Bidirectional data inputs and outputs directly TTL-
compatible
◆◆
◆◆
◆Low power consumption via chip deselect
◆◆
◆◆
◆Upper and Lower Byte Enable Pins
◆◆
◆◆
◆Commercial and industrial product available in 44-pin
Plastic SOJ package and 44-pin TSOP package
Description
The IDT71016 is a 1,048,576-bit high-speed Static RAM organized
as 64K x 16. It is fabricated using high-perfomance, high-reliability CMOS
technology. This state-of-the-art technology, combined with innovative
circuit design techniques, provides a cost-effective solution for high-speed
memory needs.
The IDT71016 has an output enable pin which operates as fast as 7ns,
with address access times as fast as 12ns. All bidirectional inputs and
outputs of the IDT71016 are TTL-compatible and operation is from a single
5V supply. Fully static asynchronous circuitry is used, requiring no clocks
or refresh for operation.
The IDT71016 is packaged in a JEDEC standard 44-pin Plastic SOJ
and 44-pin TSOP Type II.
Functional Block Diagram
Output
Enable
Buffer
Address
Buffers
Chip
Enable
Buffer
Write
Enable
Buffer
Byte
Enable
Buffers
OE
A0 - A15 Row / Column
Decoders
CS
WE
BHE
BLE
64K x 16
Memory
Array
Sense
Amps
and
Write
Drivers
16
Low
Byte
I/O
Buffer
8
8
8
8
I/O 8
I/O 15
I/O 7
I/O 0
3210 drw 01
High
Byte
I/O
Buffer
,
CMOS Static RAM
1 Meg (64K x 16-Bit) IDT71016S
6.42
2
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges
Pin Configurations
SOJ/TSOP
Top View
Truth Table (1)
Pin Descriptions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
I/O 7
NC
A12
A13
A14
A15
WE
I/O 6
I/O 5
I/O 4
V
SS
V
CC
I/O 3
I/O 2
I/O 1
I/O 0
CS
A0
A1
A2
A3
A4 44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A6
A7
OE
BHE
BLE
I/O 15
I/O 14
I/O 13
I/O 12
V
SS
V
CC
I/O 11
I/O 10
I/O 9
I/O 8
A8
A9
A10
A11
NC
A5
NC
SO44-1
SO44-2
3210 drw 02
,
A
0
- A
15
Address Inputs Input
CS Chip Select Input
WE Write Enable Input
OE Outp ut Enable Inp ut
BHE Hi g h B y te E na b le Inp ut
BLE Lo w Byte Enab le Input
I/O
0
- I/O
15
Data Inp ut/ Outp ut I/ O
V
CC
5. 0V Po we r P wr
V
SS
Ground Gnd
3210 tbl 01
NOTE:
1 . H = VIH, L = VIL, X = Don't care.
CS OE WE BLE BHE I/O
0
- I/O
7
I/O
8
- I/O
15
Function
H X X X X High-Z High-Z Deselected - Standby
L L H L H DATA OUT Hig h-Z Lo w B yte Re ad
L L H H L Hig h-Z DATA OUT Hig h Byte Re ad
L L H L L DATAOUT DATAOUT` Wo rd Read
L X L L L DATAIN DATAIN Word Write
L X L L H DATAIN Hig h-Z Low Byte Write
L X L H L High-Z DATAIN High Byte Write
L H H X X High-Z Hig h-Z Outputs Disabled
L X X H H Hig h-Z Hig h-Z Outputs Disabled
3210 tbl 02
6.42
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges
3
DC Electrical Characteristics(1)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC–0.2V)
Absolute Maximum Ratings(1)
Capacitance
(TA = +25° C, f = 1.0MHz, SOJ/TSOP Package)
Recommended DC Operating
Conditions
DC Electrical Characteristics
(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Range)
NOTE:
1. VIL (min.) = –1.5V for pulse width less than tRC/2, once per cycle.
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supply Voltage 4.5 5.0 5. 5 V
GND Ground 0 0 0 V
V
IH
Input H igh Volt age 2.2
____
V
DD
+0.5 V
V
IL
Input Low Volt age -0. 5
(1)
____
0.8 V
3210 tbl 05
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
Symbol Parameter(1) Conditions Max. Unit
C
IN
Input Capacit ance V
IN
= 3dV 6 pF
C
I/O
I/ O Capacitance V
OUT
= 3dV 7 pF
3210 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VCC + 0.5V.
Symbol Rating Value Unit
V
TERM
(2)
Te rminal Voltag e with
Res p e c t to GND -0.5 to +7.0 V
T
BIAS
Temperature
Under Bias -55 to +125
o
C
T
STG
Storage
Temperature -55 to +125
o
C
P
T
P o we r Di s s ipati o n 1. 25 W
I
OUT
DC Outp ut Curre nt 50 mA
3210 tbl 03
Symbol Parameter Test Conditions Min. Max. Unit
|I
LI
| Input Leakage Current V
CC
= M ax., V
IN
= GND to V
CC
___
5µA
|I
LO
| Out put Leakage Current V
CC
= M ax., CS = V
IH
, V
OUT
= GND t o V
CC
___
5µA
V
OL
Out put Low Volt age I
OL
= 8mA, V
CC
= Min.
___
0.4 V
V
OH
Out put H igh Voltage I
OH
= -4mA, V
CC
= M in. 2.4
___
V
3210 tb l 07
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing .
71016S12 71016S15 71016S20
Symbol Parameter Com'l. Com'l. Ind. Com'l. Ind. Unit
I
CC
Dy nami c Op e ra ting Curre nt
CS < V
IL
, Outp uts Ope n, V
CC
= Max., f = f
MAX
(2)
210 180 180 170 170 mA
I
SB
Stand b y P o we r Sup p ly Curre nt (TTL Lev e l)
CS > V
IH
, Outp uts Ope n, V
CC
= Max., F = f
MAX
(2)
60 50 50 45 45 mA
I
SB1
Standb y Power Supply Current (CMOS Level)
CS > V
HC
, Outputs Open, V
CC
= Max., f = 0
(2)
V
IN
< V
LC
or V
IN
> V
HC
10 10 10 10 10 mA
3210 tbl 08
Grade Temperature GND V
CC
Com m ercial 0°C to + 70°C 0V 5. 0V ± 1 0%
Industrial –40°C to + 85°C 0V 5. 0V ± 10%
3210 t bl 04
Recommended Operating
Temperature and Supply Voltage
6.42
4
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges
AC Test Conditions
Figure 1. AC Test Load Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
*Including jig and scope capacitance.
Figure 3. Output Capacitive Derating
AC Test Loads
1
2
3
4
5
6
7
20 40 60 80 100 120 140 160 180 200
Δt
AA,
t
ACS
(Typical, ns)
CAPACITANCE (pF)
8
3210 drw 05
•
•
•
•
•
•
•
,
3210 drw 04
480Ω
255Ω5pF*
DATA
OUT
5V
,
480Ω
255Ω30pF*
DATA OUT
5V
3210 drw 03
,
Input P ulse Lev els
Input R ise/ Fall Tim es
Input Tim ing Ref erence Lev els
Out put Reference Levels
AC Test Load
GND to 3.0V
1.5ns
1.5V
1.5V
See Figure 1, 2 and 3
3210 t bl 09
6.42
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges
5
Timing Waveform of Read Cycle No. 1(1,2,3)
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
AC Electrical Characteristics (VCC = 5.0V ± 10%, Commercial and Industrial Range)
DATA
OUT
ADDRESS
3210 drw 06
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALID
PREVIOUS DATA
OUT
VALID
,
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. 12ns commercial only.
71016S12
(2)
71016S15 71016S20
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
RE AD CYCL E
t
RC
Read Cy cle Time 12
____
15
____
20
____
ns
t
AA
Address Access Time
____
12
____
15
____
20 ns
t
ACS
Chip Select Access Time
____
12
____
15
____
20 ns
t
CLZ
(1)
Chip S ele ct Lo w to Output in Low-Z 4
____
5
____
5
____
ns
t
CHZ
(1)
Chip S ele ct Hig h to Output in Hig h-Z
____
6
____
6
____
8ns
t
OE
Outp ut E nab le Lo w to Outp ut Val id
____
7
____
8
____
10 ns
t
OLZ
(1)
Output Enable Lo w to Outp ut in Lo w-Z 0
____
0
____
0
____
ns
t
OHZ
(1)
Outp ut E na b le Hi g h to O utp ut in High -Z
____
6
____
6
____
8ns
t
OH
Output Ho ld fro m A d d re s s Chang e 4
____
4
____
5
____
ns
t
BE
B y te E nabl e L o w to O utp ut Va li d
____
7
____
8
____
10 ns
t
BLZ
(1)
B y te E nabl e L o w to Outp u t in Lo w-Z 0
____
0
____
0
____
ns
t
BHZ
(1)
By te Enab l e Hig h to Outp ut i n Hig h-Z
____
6
____
6
____
8ns
WR ITE C YCL E
t
WC
Write Cycle Time 12
____
15
____
20
____
ns
t
AW
Address Valid to End of Write 9
____
10
____
12
____
ns
t
CW
Chip Sele ct Low to End o f Write 9
____
10
____
12
____
ns
t
BW
B y te E nabl e L o w to E nd of W rite 9
____
10
____
12
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WR
Address Hold from End of Write 0
____
0
____
0
____
ns
t
WP
Write Pulse Width 9
____
10
____
12
____
ns
t
DW
Data Va li d to E n d o f Wr ite 7
____
8
____
10
____
ns
t
DH
Data Ho ld Tim e 0
____
0
____
0
____
ns
t
OW
(1)
Write Enable High to Output in Low-Z 1
____
1
____
1
____
ns
t
WHZ
(1)
Wri te E nab l e Low to Outp u t in Hig h -Z
____
6
____
6
____
8ns
3210 tb l 10
6.42
6
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges
Timing Wavefor m of Read Cycle No. 2(1)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and
data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
NOTES:
1. WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.
3. Transition is measured ±200mV from steady state.
ADDRESS
DATA
OUT
3210 drw 07
(3)
(3)
(3)
DATA VALID
t
AA
t
RC
t
OE
t
OLZ
t
CHZ
t
OHZ
OUT
(3)
t
ACS
(3)
t
BLZ
t
CLZ
(2)
t
BE
t
OH
t
BHZ
(3)
(2)
,
OE
CS
BHE,BLE
ADDRESS
CS
DATA
IN
3210 drw 08
(5)
(5)
(5)
DATA
IN
VALID
t
WC
t
AS
t
WHZ
(2)
t
CW
t
CHZ
t
OW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
PREVIOUS DATA VALID DATA VALID
BHE
,
BLE
t
BW
t
WP
(5)
t
BHZ
(3)
,
6.42
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges
7
Timing Wavefor m of Write Cycle No. 2 (CS Controlled Timing)(1,4)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and
data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4)
ADDRESS
CS
DATA
IN
3210 drw 9
DATA
IN
VALID
t
WC
t
AS (2)
t
CW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
BHE
,
BLE
t
BW
t
WP
,
ADDRESS
CS
DATA
IN
3210 drw 10
DATA
IN
VALID
t
WC
t
AS
(2)
t
CW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
BHE
,
BLE
t
BW
t
WP
,
6.42
8
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges
Ordering Information
S
Power
XX
Speed
XXX
Package
X
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Y
PH
400-mil SOJ (SO44-1)
400-mil TSOP Type II (SO44-2)
12
*
15
20
71016
Device
Type
Speed in nanoseconds
3210 drw 11
X
GGreen
Blank
8
Tube or Tray
Tape and Reel
X
*
Commercial temperature range only
6.42
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges
9
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
07/30/99: Updated to new format
080/5/99: Pg. 3 Expressed commercial and industrial ranges on DC Electrical table
Removed Icc, ISB, and ISB1 values for S12 industrial speed
Pg. 5 Expressed commercial and industrial ranges on AC Electrical table
Changed footnote #2 to commercial temperature only
Pg. 6 Revised footnotes on Write Cycle No.1 diagram
Pg. 7 Revised footnotes on Write Cycle No.2 and No.3 diagrams
Pg. 8 Removed SCD 2752 footnote
Added commercial only for 12ns speed
08/13/99: Pg. 9 Added Datasheet Document History
09/30/99: Pg. 3, 5, 8 Added 12ns industrial temperature speed grade offering
08/09/00: Not recommended for new designs
02/01/01: Removed "Not recommended for new designs"
01/30/04: Pg. 8 Added "Restricted hazardous substance device" to order information
01/30/06: Pg. 3 Updated Capacitance table to include TSOP
02/13/07: Pg. 8 Added N generation die step to data sheet ordering information
10/13/08: Pg. 8 Removed "IDT" from orderable part number
09/25/13: Pg. 1 Updated Commercial and Industrial speed grade offerings
Removed IDT reference to fabrication
Pg. 3 Removed Commercial TA information from the Absolute Maximum Ratings table
Removed Ind. temp values for the 12ns speed grade from the DC Elec Chars table
Pg. 5 Added the footnote annotation to the AC Elec Chars table and the footnote for 12ns commercial only
Pg. 8 Added T & R to, updated Restricted Hazardous Substance Device wording to "Green", added
annotation indicating "Commercial temperature range only" and removed Die Stepping indicator from
the ordering information
CORPORATE HEADQUARTERS for SALES:
6024 Silver Creek Valley Road 800-345-7015 or
San Jose, CA 95138 408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
sramhelp@idt.com
408-284-4532
