1999 Microchip Technology Inc. Preliminary DS30569A-page 1
Devices Included in this Data Sheet:
Microcontroller Core Features:
•High-performance RISC CPU
•Only 35 single word instructions to learn
•All single cycle instructions except for program
branches which are two cycle
•Operating speed:DC - 20 MHz clock input
DC - 200 ns instruction cycle
•2K x 14 words of FLASH Program Memory
128 x 8 bytes of Data Memory (RAM)
64 x 8 bytes of EEPROM Data Memory
•Pinout compatible to the PIC16CXXX 28 and 40-
pin devices
•Interrupt capability (up to 11 sources)
•Eight level deep hardware stack
•Direct, indirect and relative addressing modes
•Power-on Reset (POR)
•Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
•Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
•Programmable code-protection
•Power saving SLEEP mode
•Selectable oscillator options
•Low-power, high-speed CMOS FLASH/EEPROM
technology
•Fully static design
•In-Circuit Serial Programming (ICSP) via two
pins
•Single 5V In-Circuit Serial Programming capability
•In-Circuit Debugging via two pins
•Processor read/write access to program memory
•Wide operating voltage range: 2.0V to 5.5V
•High Sink/Source Current: 25 mA
•Commercial and Industrial temperature ranges
•Low-power consumption:
-< 1.6 mA typical @ 5V, 4 MHz
-20 µA typical @ 3V, 32 kHz
-< 1 µA typical standby current
Pin Diagram
Peripheral Features:
•Timer0: 8-bit timer/counter with 8-bit prescaler
•Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
•Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
•One Capture, Compare, PWM module
-Capture is 16-bit, max. resolution is 12.5 ns
-Compare is 16-bit, max. resolution is 200 ns
-PWM max. resolution is 10-bit
•10-bit multi-channel Analog-to-Digital converter
•Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI) with 9-bit address
detection
•Parallel Slave Port (PSP) 8-bits wide, with
external RD, WR and CS controls (40/44-pin only)
•Brown-out detection circuitry for
Brown-out Reset (BOR)
•PIC16F870 •PIC16F871
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5
RC4
RD3/PSP3
RD2/PSP2
MCLR/VPP/THV
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC16F871
PDIP
PIC16F870/871
28/40-Pin 8-Bit CMOS FLASH Microcontrollers
PIC16F870/871
DS30569A-page 2 Preliminary 1999 Microchip Technology Inc.
Pin Diagrams
PIC16F870
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP/THV
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5
RC4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
44
8
7
6
5
4
3
2
1
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
9
PIC16F871
RA4/T0CKI
RA5/AN4
RE0/RD/AN5
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CK1
NC
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
MCLR/VPP/THV
NC
RB7/PGD
RB6/PGC
RB5
RB4
NC
NC
RC6/TX/CK
RC5
RC4
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3
RC2/CCP1
RC1/T1OSI
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC16F871
37
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
MCLR/VPP/THV
NC
RB7/PGD
RB6/PGC
RB5
RB4
NC RC6/TX/CK
RC5
RC4
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3
RC2/CCP1
RC1/T1OSI
NC
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4
RA4/T0CKI
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3/PGM
PLCC
TQFP
DIP, SOIC, SSOP
1999 Microchip Technology Inc. Preliminary DS30569A-page 3
PIC16F870/871
Key Features
PICmicro™ Mid-Range Reference Manual (DS33023) PIC16F870 PIC16F871
Operating Frequency DC - 20 MHz DC - 20 MHz
Resets (and Delays) POR, BOR
(PWRT, OST) POR, BOR
(PWRT, OST)
FLASH Program Memory
(14-bit words) 2K 2K
Data Memory (bytes) 128 128
EEPROM Data Memory 64 64
Interrupts 10 11
I/O Ports Ports A,B,C Ports A,B,C,D,E
Timers 3 3
Capture/Compare/PWM modules 1 1
Serial Communications USART USART
Parallel Communications — PSP
10-bit Analog-to-Digital Module 5 input channels 8 input channels
Instruction Set 35 Instructions 35 Instructions
PIC16F870/871
DS30569A-page 4 Preliminary 1999 Microchip Technology Inc.
Table of Contents
1.0 Device Overv iew....................... ................. ................. ................. ................ ................. .. ......................................5
2.0 Memory Organization..........................................................................................................................................11
3.0 I/O Ports..............................................................................................................................................................27
4.0 Data EEPROM and FLASH Program Memory....................................................................................................39
5.0 Timer0 Module....................................................................................................................................................47
6.0 Timer1 Module....................................................................................................................................................51
7.0 Timer2 Module....................................................................................................................................................55
8.0 Capture/Compare/PWM Module.........................................................................................................................57
9.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ........................................63
10.0 Analog-to-Digital Converter (A/D) Module...........................................................................................................79
11.0 Special Features of the CPU...............................................................................................................................89
12.0 Instruction Set Summary...................................................................................................................................105
13.0 Development Support .......................................................................................................................................113
14.0 Electric al Chara cteris tic s................. ..... ................. ................. ................. ................. .........................................119
15.0 DC and AC Characteristics Graphs and Tables................................................................................................135
16.0 Packaging Information ......................................................................................................................................137
Index .......................................................................................................................................................................... 145
On-Line Support..........................................................................................................................................................151
Reader Response.......................................................................................................................................................152
Product Identification System......................................................................................................................................153
To Our Valued Customers
Most Current Data Sheet
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Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ens ure
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We appreciate your assistance in making this a better document.
1999 Microchip Technology Inc. Preliminary DS30569A-page 5
PIC16F870/871
1.0 DEVICE OVERVIEW
This document contains device-specific information.
Additional information may be found in the PICmicro™
Mid-Range Reference Manual, (DS33023), which may
be obtained from your local Microchip Sales Represen-
tative or downloaded from the Microchip website. The
Reference Manual should be considered a comple-
mentary docu ment to this dat a sheet, and is highly rec-
ommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
There are two devices (PIC16F870 and PIC16F871)
covered by this data sheet. The PIC16F870 device
comes in a 28-pin package and the PIC16F871 device
comes in a 40-pin package. The 28-pin device does not
have a Parallel Slave Port implemented.
The following two figures are device block diagrams
sor ted by pin number; 28-pin for Figure 1-1 and 40-pin
f or Figure 1-2. The 28-pin and 40-p in pinouts are liste d
in Table 1-1 and Table 1-2, respectively.
FIGURE 1-1: PIC16F870 BLOCK DIAGRAM
FLASH
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Coun ter
8 Level Stack
(13-bit)
RAM
File
Registers
Direct Addr 7
RAM Addr (1) 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
PORTA
PORTB
PORTC
RA4/T0CKI
RA5/AN4
RB0/INT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3
RC4
RC5
RC6/TX/CK
RC7/RX/DT
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
USART
CCP1
10-bit A/DTimer0 Timer1 Timer2
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
8
3
Data EEPROM
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
Device Program
FLASH Data Memory Data
EEPROM
PIC16F870 2K 128 Bytes 64 Bytes
In-Circuit
Debugger
Low-Voltage
Programming
PIC16F870/871
DS30569A-page 6 Preliminary 1999 Microchip Technology Inc.
FIGURE 1-2: PIC16F871 BLOCK DIAGRAM
FLASH
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
Direct Addr 7
RAM Addr (1) 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start- up Tim er
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
PORTA
PORTB
PORTC
PORTD
PORTE
RA4/T0CKI
RA5/AN4
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3
RC4
RC5
RC6/TX/CK
RC7/RX/DT
RD7/PSP7:RD0/PSP0
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
USART
CCP1
10-bit A/DTimer0 Timer1 Timer2
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
8
3
Data EEPROM
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
Device Program
FLASH Data Memory Data
EEPROM
PIC16F871 2K 128 Bytes 64 Bytes
In-Circuit
Debugger
Low-Voltage
Programming
Parallel Slave Port
1999 Microchip Technology Inc. Preliminary DS30569A-page 7
PIC16F870/871
TABLE 1-1: PIC16F870 PINOUT DESCRIPTION
Pin Name DIP
Pin# SOIC
Pin# I/O/P
Type Buffer
Type Description
OSC1/CLKIN 9 9 I ST/CMOS(3) Oscillator crystal input/external clock source input.
OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal
oscillator mode. In RC mode, the OSC2 pin outputs CLKO UT
which has 1/4 th e fre que ncy of OSC1 , and denot es th e instruc tion
cycle rate.
MCLR/VPP/THV 1 1 I/P ST Master cl ear (reset ) input or programming voltage input or high
voltage test mode control. This pin is an active low reset to the
device.
PORTA is a bi-directional I/O port.
RA0/AN0 2 2 I/O TTL RA0 can also be analog input0
RA1/AN1 3 3 I/O TTL RA1 can also be analog input1
RA2/AN2/VREF- 4 4 I/O TTL RA2 can also be analog input2 or negative analog reference
voltage
RA3/AN3/VREF+ 5 5 I/O TTL RA3 can also be analog input3 or positive analog reference
voltage
RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0 module. Output
is open drain type.
RA5/AN4 7 7 I/O TTL RA5 can also be analog input4
PORTB is a bi-directional I/O po rt. PORTB can be software
programmed for internal w eak pull-up on all inputs.
RB0/INT 21 21 I/O TTL/ST(1) RB 0 ca n al so be t he extern al interrupt pin.
RB1 22 22 I/O TTL
RB2 23 23 I/O TTL
RB3/PGM 24 24 I/O TTL/ST(1) RB 3 c a n al so be t he low vol ta ge pro gramm i ng inp ut
RB4 25 25 I / O TTL Inter rupt on chang e pin .
RB5 26 26 I / O TTL Inter rupt on chang e pin .
RB6/PGC 27 27 I/O TTL/ST(2) Interrupt on change pin or In-Circ uit Debu gger pin. Serial
programming clock.
RB7/PGD 28 28 I/O TTL/ST(2) Interrupt on change pin or In-Circ uit Debu gger pin. Serial
programming data.
PORTC is a bi-dir ectional I/O port.
RC0 /T1OSO/T1C KI 11 1 1 I/O ST RC0 c an al so be the Ti m e r1 osc i l lat o r ou tp u t or Ti m er 1 c l ock
input.
RC1/T1OSI 12 12 I/O ST RC1 c an also be the Timer1 oscil l ator input
RC2/CCP1 13 13 I/O ST RC2 c an also be the Capture 1 input/Compare1 out put/PWM1
output.
RC3 14 14 I/O ST
RC4 15 15 I/O ST
RC5 16 16 I/O ST
RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronou s Transmit or
Synchro n ous Cl ock.
RC7/RX/DT 18 18 I/O ST RC7 can als o be the USART Asynchronous Receive or
Synchro n ous Data.
VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins .
VDD 20 20 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/ou tput P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the exte rnal interrupt or LVP mode.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This bu ffer is a Schmitt Trigge r i nput when configured in RC oscillator mode and a CMOS input otherwise .
PIC16F870/871
DS30569A-page 8 Preliminary 1999 Microchip Technology Inc.
TABLE 1-2: PIC16F871 PINOUT DESCRIPTION
Pin N a me DIP
Pin# PLCC
Pin# QFP
Pin# I/O/P
Type Buffer
Type Description
OSC1/CLKIN 13 14 30 I ST/CMOS(4) Oscillator crystal input/external clock source input.
OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs CLK-
OUT which has 1/4 the frequency of OSC1, and denotes the
instruction cycle rate.
MCLR/VPP/THV 1 2 18 I/P ST Mas ter clear ( reset ) inp ut or pr og r amming v oltag e inpu t o r hig h
v oltage test mode control. This pin is an act ive low reset to the
device.
PORTA is a bi-directional I/O po rt.
RA0/AN0 2 3 19 I /O TTL RA0 can also be analog input0
RA1/AN1 3 4 20 I /O TTL RA1 can also be analog input1
RA2/AN2/VREF- 4 5 21 I /O TTL RA2 can also be analog input2 or negative an alog
refere nce volta g e
RA3/AN3/VREF+ 5 6 22 I/O TTL RA3 can also be analog input3 or positive analog
refere nce volta g e
RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/
counter. Output is open drain type.
RA5/AN4 7 8 24 I /O TTL RA5 can also be analog input4
PORTB is a bi-directional I/O port. POR TB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT 33 36 8 I/O TTL/ST(1) RB0 can also be t he external interrupt pin.
RB1 34 37 9 I/O TTL
RB2 35 38 10 I/O TTL
RB3/PGM 36 39 11 I/O TTL/ST(1) RB3 can also be the low vol tage programming inp ut
RB4 37 41 14 I/O TTL Interrupt on c hange pin.
RB5 38 42 15 I/O TTL Interrupt on c hange pin.
RB6/PGC 39 43 16 I/O TTL/ST(2) Interrupt on change pin or In-Circuit Debugger pin. Serial
programming clock.
RB7/PGD 40 44 17 I/O TTL/ST(2) Interrupt on change pin or In-Circuit Debugger pin. Serial
programming data.
PORTC is a bi-direction al I/O port.
RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a Timer1
clock input.
RC1/T1OSI 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input
RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3 18 20 37 I/O ST
RC4 23 25 42 I/O ST
RC5 24 26 43 I/O ST
RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
Legen d: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmit t Trigger input when configured as an external interrupt or LVP mode.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the P arallel Sla ve
Port mo de (fo r interfac in g to a mi c r op roc essor bus ) .
4: This bu ffer is a Schmitt Trigge r i nput when configured in RC oscillator mode and a CMOS input otherwise.
1999 Microchip Technology Inc. Preliminary DS30569A-page 9
PIC16F870/871
PORTD is a bi-direc tional I/O port or parallel s l ave port when
interfacing to a microproce ssor bus.
RD0/PSP0 19 21 38 I/O ST/TTL(3)
RD1/PSP1 20 22 39 I/O ST/TTL(3)
RD2/PSP2 21 23 40 I/O ST/TTL(3)
RD3/PSP3 22 24 41 I/O ST/TTL(3)
RD4/PSP4 27 30 2 I/O ST/TTL(3)
RD5/PSP5 28 31 3 I/O ST/TTL(3)
RD6/PSP6 29 32 4 I/O ST/TTL(3)
RD7/PSP7 30 33 5 I/O ST/TTL(3)
PORTE is a bi-directional I/O port.
RE0/RD/AN5 8 9 25 I/O ST/TTL(3) RE 0 can also be rea d cont rol f o r the par alle l sla v e port, or
analog input5.
RE1/WR/AN6 9 10 26 I/O ST/TTL(3) RE1 can also be write control for the parallel slave port, or
analog input6.
RE2/CS/AN7 10 11 27 I/O ST/TTL(3) RE2 can also be select control for the parallel slave por t,
or analog input7.
VSS 12,31 13,34 6,29 P — Ground reference for logic and I/O pins.
VDD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins.
NC — 1,17,28,
40 12,13,
33,34 — These pins are not internally connec ted. These pins should be
left unconnected.
TABLE 1-2: PIC16F871 PINOUT DESCRIPTION (CONTINUED)
Pin N a me DIP
Pin# PLCC
Pin# QFP
Pin# I/O/P
Type Buffer
Type Description
Legend: I = input O = output I/O = input/ou tput P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmit t Trigger input when configured as an external interrupt or LVP mode.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as gener al purpose I/O and a TTL input when used in the Parallel Slave
Port mo de (fo r interfac in g to a mi c r op roc essor bus ) .
4: This bu ffer is a Schmitt Trigge r i nput when configured in RC oscillator mode and a CMOS input otherwise .
PIC16F870/871
DS30569A-page 10 Preliminary 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. Preliminary DS30569A-page 11
PIC16F870/871
2.0 MEMORY ORGANIZATION
There are three memory blocks in each of these
PICmicro® MCUs. The Program Memory and Data
Memory have separate buses, so that concurrent
access can occur , and is detailed in this section. The
EEPROM data memory block is detailed in
Section 4.0.
Addit ional inf ormation on de vic e memory ma y be f oun d
in the PICmicro Mid-Range Reference Manual,
(DS33023).
2.1 Pr ogram Memory Organization
The PIC16F870/871 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. The PIC16F870/871 devices have 2K
x 14 words of FLASH program memory. Accessing a
location above the physically implemented address will
cause a wr ap arou nd.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-1: PI C16F87 0/8 71 PROGRAM
MEMORY MAP AND STACK
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1(STATUS<6>) and
RP0 (STATUS<5>) are the bank select bits.
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Functio n Regist ers . Abo v e the Special Functi on Re gis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some “high use” Special Function
Registers from one bank may be mirrored in another
bank for code reduction and quicker access.
2.2.1 GENERAL PURPOSE REGISTER FILE
The regi ster fi le can be accessed either di rectly, or indi-
rectly through the File Select Register FSR.
PC<12:0>
13
0000h
0004h
0005h
Stack Le vel 1
Stack Level 8
Reset Vector
Interrupt Vector
On-Chip
CALL, RETURN
RETFIE, RETLW
1FFFh
Stack Level 2
Program
Memory Page 0
07FFh
0800h
RP<1:0> Bank
00 0
01 1
10 2
11 3
Note: EEPR OM Data Memory description can be
found in Section 4.0 of this Data Sheet
PIC16F870/871
DS30569A-page 12 Preliminary 1999 Microchip Technology Inc.
FIGURE 2-2: PIC16F870/871 REGISTER FILE MAP
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
RCSTA
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PCON
PR2
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
7Fh FFh
Bank 0 Bank 1
File
Address
Indirect add r.(*) Indirect add r.(*)
PCL
STATUS
FSR
PCLATH
INTCON
PCL
STATUS
FSR
PCLATH
INTCON
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
17Fh 1FFh
Bank 2 Bank 3
Indirect addr.(*)
ADRESL
TMR0 OPTION_REG
PIR2 PIE2
ADRESH
ADCON0 ADCON1
General
Purpose
Register
General
Purpose
Register
1EFh
1F0h
accesses
A0h - BFh
16Fh
170h
accesses
70h-7Fh
TRISB
PORTB
96 Bytes
32 Bytes
10Ch
10Dh
10Eh
10Fh
110h
18Ch
18Dh
18Eh
18Fh
190h
EEDATA
EEADR EECON1
EECON2
EEDATH
EEADRH Reserved(1)
Reserved(1)
Unimplemented data memory locations, read as ’0’.
* Not a physical regi ster.
Note 1: These registers are reserved; maintain these registers clear.
2: These registers are not implemented on the PIC16F870.
120h 1A0h
accesses
70h-7Fh accesses
70h-7Fh
accesses
20h-7Fh
C0h
EFh
F0h
1C0h
1BFh
BFh
TXREG
RCREG
CCP1CON TXSTA
SPBRG
PORTD(2)
PORTE(2) TRISD(2)
TRISE(2)
File
Address
File
Address
File
Address
1999 Microchip Technology Inc. Preliminary DS30569A-page 13
PIC16F870/871
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2- 1.
The Special Function Registers can be classified into
two sets; core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
resets
(2)
Bank 0
00h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
02h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h(4) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
04h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA —— PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h(5) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
09h(5) PORTE — — — — —RE2RE1RE0---- -xxx ---- -uuu
0Ah(1,4) PCLATH ——— Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(3) ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
0Dh PIR2 ——— EEIF — — — — ---0 ---- ---0 ----
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h
14h
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
1Bh
1Ch
1Dh
1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/
DONE —ADON0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLAT H is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; alwa ys maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices , read as ‘0’.
PIC16F870/871
DS30569A-page 14 Preliminary 1999 Microchip Technology Inc.
Bank 1
80h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h(4) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
83h(4) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
84h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA —— PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h(5) TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h(5) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
8Ah(1,4) PCLATH ——— Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 PSPIE(3) ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
8Dh PIE2 ——— EEIE — — — — ---0 ---- ---0 ----
8Eh PCON — — — — — —PORBOR ---- --qq ---- --uu
8Fh —Unimplemented — —
90h —Unimplemented — —
91h
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h
94h
95h —Unimplemented — —
96h —Unimplemented — —
97h —Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
9Ah —Unimplemented — —
9Bh —Unimplemented — —
9Ch —Unimplemented — —
9Dh —Unimplemented — —
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 0--- 0000 0--- 0000
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
resets
(2)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessibl e. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; alwa ys maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices , read as ‘0’.
1999 Microchip Technology Inc. Preliminary DS30569A-page 15
PIC16F870/871
Bank 2
100h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
102h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
103h(4) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
104h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
105h —Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
107h —Unimplemented — —
108h —Unimplemented — —
109h —Unimplemented — —
10Ah(1,4) PCLATH ——— Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
10Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Ch EEDATA EEPROM data register xxxx xxxx uuuu uuuu
10Dh EEADR EEPROM address register xxxx xxxx uuuu uuuu
10Eh EEDATH —— EEPROM data register high byte xxxx xxxx uuuu uuuu
10Fh EEADRH ——— EEPROM address regis ter high byte xxxx xxxx uuuu uuuu
Bank 3
180h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
182h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
183h(4) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
184h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
185h —Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
187h —Unimplemented — —
188h —Unimplemented — —
189h —Unimplemented — —
18Ah(1,4) PCLATH ———Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
18Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
18Ch EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 x--- u000
18Dh EECON2 EEPROM control register2 (not a physical register) ---- ---- ---- ----
18Eh —Reserved maintain clear 0000 0000 0000 0000
18Fh —Reserved maintain clear 0000 0000 0000 0000
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
resets
(2)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLAT H is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; alwa ys maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices , read as ‘0’.
PIC16F870/871
DS30569A-page 16 Preliminary 1999 Microchip Technology Inc.
2.2.2.1 STATUS REGISTER
The STATUS Register contain s the arithmetic statu s of
the ALU, the RESET st atus an d the ba nk sel ect bits for
data me mo ry.
The STATUS Register can be the destination for any
instruction, as with any other register. If the STATUS
Regis ter is the dest ination f or an instructio n that aff ect s
the Z, DC or C bits, then the write to these three bits is
disab led . The se bi ts ar e set o r clea red a ccordi ng to the
device logi c. Fur t her more, the TO and PD bits are not
writable, therefore, the result of an instruction with the
STATUS Register as destination may be different than
inte nded .
For example, CLRF STATUS will cl ea r th e up p er- t hr ee
bits an d set the Z bi t. T his l ea ve s the STATUS reg ister
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bits from the STATUS Register.
For other instructions not affecting any status bits, see
the "Instruction Set Summary."
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
Note 1: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C R = Reada ble bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: IRP: Register Bank Sele ct bit (used f or ind irec t addressin g)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4: TO: Time-out bit
1 = After power-up, CLRWDT instr uction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3: PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By executio n of the SLEEP instruction
bit 2: Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
(for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of
the sec ond op erand. For rotate (RRF, RLF) instruction s, thi s b it is lo ade d w it h ei the r the hig h or l o w o r der
bit of the source register.
1999 Microchip Technology Inc. Preliminary DS30569A-page 17
PIC16F870/871
2.2.2.2 OPTION_REG REGISTER
The OPTIO N_REG R egister i s a read ab le and writab le
register , which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
abl e regist er kno wn als o as th e prescale r), the External
INT Inte rrupt, TMR0 and t he wea k pul l-ups on PO R TB .
REGISTER 2-2: OPTI ON_REG REGISTER (ADDRESS 81h, 181h)
Note: To achi eve a 1:1 pr escaler as signmen t fo r
the TMR0 register, assign the prescaler to
the Watchdog Timer.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readab le bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit7 bit0
bit 7: RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6: INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5: T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4: T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3: PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
PIC16F870/871
DS30569A-page 18 Preliminary 1999 Microchip Technology Inc.
2.2.2.3 INTCON REGISTER
The I NTCON Regi ster i s a rea dab le a nd w ritabl e regi s-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Por t change and External
RB0/INT pin interrupts.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
Note: Interrupt fl ag b its get s et wh en a n in terrupt
conditi on occ urs, regardless of the sta te of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit
W = Writable bit
U = Unimplem ented bit,
read as ‘0’
- n= Value at POR reset
bit7 bit0
bit 7: GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6: PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5: T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4: INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3: RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2: T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1: INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0: RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
1999 Microchip Technology Inc. Preliminary DS30569A-page 19
PIC16F870/871
2.2.2.4 PIE1 REGISTER
The PIE1 Register contains the individual enable bits
for the peripheral inter rupts.
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
PSPIE(1) ADIE RCIE TXIE CCP1IE TMR2IE TMR1IE R = Readable bit
W = Wr itable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6: ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5: RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disabl es the USART receive interrupt
bit 4: TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3: Unimplemented: Read as ‘0’
bit 2: CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1: PSPIE is reserved on the PIC16F870; always maintain this bit clear.
PIC16F870/871
DS30569A-page 20 Preliminary 1999 Microchip Technology Inc.
2.2.2.5 PIR1 REGISTE R
The PIR1 Register contains the individual flag bits for
the peripheral interr upts.
REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)
Note: Interrupt fl ag b its get s et wh en a n in terrupt
conditi on occ urs, regardless of the sta te of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt bits are clear prior to enabling an
interrupt.
R/W-0 R/W-0 R-0 R-0 U-0 R/W-0 R/W-0 R/W-0
PSPIF(1) ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF R = Readable bit
W = Writable bit
- n= Value at POR reset
bit7 bit0
bit 7: PSPIF(1): Parallel Slave Port Read/Wr ite Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6: ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5: RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
bit 4: TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
bit 7: Unimplemented: Read as ‘0’
bit 2: CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflo wed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: PSP IF is reserved on the PIC16F870; always maintain this bit clear.
1999 Microchip Technology Inc. Preliminary DS30569A-page 21
PIC16F870/871
2.2.2.6 PIE2 REGISTER
The PIE2 Register contains the individual enab le bit for
the EEPROM write operation interrupt.
REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh)
U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0
——— EEIE ——— — R = Readable bit
W = Writable bit
U = Unimplem ent ed bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-5: Unimplemented: Read as '0'
bit 4: EEIE: EEPROM Write Operation Interrupt Enable
1 = Enable EE Write Interrupt
0 = Disable EE Write Interrupt
bit 3-0: Unimplemented: Read as '0'
PIC16F870/871
DS30569A-page 22 Preliminary 1999 Microchip Technology Inc.
2.2.2.7 PIR2 REGISTE R
The PIR2 Register contains the flag bit for the
EEPROM write operation interrupt.
.
REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)
Note: Interrupt fl ag b its get s et wh en a n in terrupt
conditi on occ urs, regardless of the sta te of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0
——— EEIF ———— R = Readable bit
W = Writable bit
U = Unimplem ent ed bit,
read as ‘0’
- n= Value at POR reset
bit7 bit0
bit 7-5: Unimplemented: Read as '0'
bit 4: EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3-0: Unimplemented: Read as '0'
1999 Microchip Technology Inc. Preliminary DS30569A-page 23
PIC16F870/871
2.2.2.8 PCON REGISTER
The Power Control (PCON) Register contains flag bits
to allow differentiation between a Power-on Reset
(POR) , a Br own-ou t Rese t (B OR), a Watch-do g Rese t
(WDT) and an external MCLR Reset.
REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh)
Note: BOR is unknown on POR. It must be set by
the user and checked on subs eq uen t re sts
to see if BOR is clear, indicating a brown-
out has occurred. The BOR status bit is a
don’t care and is not predictable if the
brown-out circuit is disabled (by clearing
the BODEN bit in the configuration word).
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1
————— —PORBOR R = Readable bit
W = Writable bit
U = Unimplem ent ed bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-2: Unimplemented: Read as '0'
bit 1: POR: Power-on Reset Stat us bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0: BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occu rre d
0 = A Brown-out Reset occurred (must be set in s oftwa re after a Brown- out Reset occurs)
PIC16F870/871
DS30569A-page 24 Preliminary 1999 Microchip Technology Inc.
2.3 PCL and PCLATH
The Program Counter (PC) is 13-bits wide. The low
by te comes from the PCL Register, which is a reada ble
and writable register. The upper bits (PC<12:8>) are
not readable, but are indirectly writable through the
PCLATH register . On an y reset, the upper bits of the PC
will be cleared. Figure 2-3 shows the two situations for
the loading of the PC. The upper example in the figure
shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the fig-
ure shows ho w the PC is loaded during a CALL or GOTO
instruction (PCLATH< 4:3> → PCH).
FIGURE 2-3: LOADING OF PC IN
DIFFERENT SITUATIONS
2.3.1 COMPUTED GOTO
A comput ed GOTO i s a cc om pli sh ed by adding an offs et
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercis ed i f t he table location cros se s a PC L
memory boundary (each 256 byte block). Refer to the
application note,
“Implementing a Table Read"
(AN556).
2.3.2 STACK
The PIC16FXXX family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the stack pointer is
not readable or writable. The PC is PUSHed onto the
stack when a CALL instr ucti on is execute d or an int er-
rupt causes a branch . The stack is PO Ped in the event
of a RETURN,RETLW or a RETFIE instruction execu-
tion. PCLATH is not affected by a PUSH or POP opera-
tion.
The stac k operates as a circular b uffer . This means that
after the stac k has b een PU SHed e ight ti mes , th e nin th
push overwrites th e value that w as s tored fro m the firs t
push. The tenth pus h overwrites the sec ond pus h (an d
so on).
2.4 Program Memory Paging
The PIC16FXXX architecture is capable of addressing
a continuous 8K word block of program memory. The
CALL and GOTO instructions provide 11 bits of the
address , whic h allo ws branche s within any 2K pr ogram
memory page. Therefore, the 8K words of program
memory are broken into four pages. Since the
PIC16F872 has only 2K words of program memory or
one pa ge, ad ditional code i s not re quired to ensure that
the correct page is selected before a CALL or GOTO
instruction is executed. The PCLATH<4:3> bits should
alw a ys be maintai ned as z ero s. If a return from a CALL
instruction (or interrupt) is executed, the entire 13-bit
PC is popped off the stack. Manipulation of the
PCLATH is not required for the return instructions.
2.5 Indirect Addressing, INDF and FSR
Registers
The INDF Register is not a physical register. Address-
ing the INDF Register will cause indirect addressing.
Indirect addressing is possible by using the INDF Reg-
ister. Any instruction using the INDF Register actually
acces ses the register po inted to b y the File Sele ct Reg-
ister, FSR. Reading the INDF Register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF Register
indirec tly re sults i n a no-operation ( alth ou gh st atus bits
ma y b e affected). An e ff ec tiv e 9-bit ad dress is o btaine d
by concatenating the 8-bit FSR Register and the IRP bit
(STATUS< 7>), as shown in Figur e 2-4.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-1.
EXAMPLE 2-1: INDIRECT ADDRESSING
movlw 0x20 ;initialize pointer
movwf FSR ;to RAM
NEXT clrf INDF ;clear INDF register
incf FSR,F ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;no clear next
CONTINUE : ;yes continue
PC
12 8 7 0
5PCLATH<4:0>
PCLATH
Instruction with
ALU
GOTO,CALL
Opcode < 10:0 >
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
PCL as
Destination
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions that
occur from the execution of the CALL,
RETURN, RETLW and RETFIE instruc-
tions or the vectoring to an interrupt
address.
1999 Microchip Technology Inc. Preliminary DS30569A-page 25
PIC16F870/871
FIGURE 2-4: DIRECT/INDIRECT ADDRESSING
Note 1: For register file map detail see Figure 2-2.
Data
Memory(1)
Indirect AddressingDirect Addressing
bank select location select
RP1:RP0 6 0
from opcode IRP FSR register
70
bank select location select
00 01 10 11
Bank 0 Bank 1 Bank 2 Bank 3
FFh
80h
7Fh
00h
17Fh
100h
1FFh
180h
PIC16F870/871
DS30569A-page 26 Preliminary 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. Preliminary DS30569A-page 27
PIC16F870/871
3.0 I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Addit ion al information on I/O po rts ma y b e found in th e
PICmicro™ Mid-Range Reference Manual,
(DS33023).
3.1 PORTA and the TRISA Register
PORTA is a 6-bit wide bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA b it (=1 ) wi ll m ake t he corres pondi ng PORTA pi n
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISA bit (=0) will
mak e the c orresp onding POR TA pin an output (i. e., p ut
the contents of the output latch on the selected pin).
Reading the PORTA Register reads the status of the
pins , w h erea s writ in g to it wi ll write t o th e p ort latch. All
write operations are read-modify-write operations.
Theref ore, a write to a port implies that the port pins are
read, the value is modified and then written to the por t
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
Other PORTA pins are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 Register (A/D Control Register1).
The TRISA Register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA Register
are mai ntai ne d s et wh en us ing th em as an alo g i np uts.
EXAMPLE 3- 1: INITIALIZI NG PORTA
BCF STATUS, RP0 ;
BCF STATUS, RP1 ; Bank0
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0x06 ; Configure all pins
MOVWF ADCON1 ; as digital inputs
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as ’0’.
FIGURE 3-1: BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
FIGURE 3-2: BLOCK DIAGRAM OF RA4/
T0CKI PIN
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as '0'.
Data
Bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR
Port
WR
TRIS
Data Lat ch
TRIS Latch
RD TRIS
RD PORT
VSS
VDD
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
Analog
Input
Mode
TTL
Input
Buffer
To A/D Converter
Data
Bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
Input
Buffer
N
VSS
I/O pin(1)
TMR0 clock input
QD
Q
CK
QD
Q
CK
EN
QD
EN
Note 1: I/O pin has protection diodes to VSS only.
PIC16F870/871
DS30569A-page 28 Preliminary 1999 Microchip Technology Inc.
TABLE 3-1: POR TA FUNCTIONS
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit# Buffer Function
RA0/AN0 bit0 TTL Input/output or ana log input
RA1/AN1 bit1 TTL Input/output or ana log input
RA2/AN2 bit2 TTL Input/output or ana log input
RA3/AN3/VREF bit3 TTL Input/output or analog input or VREF
RA4/T0CKI bit4 ST Input/output or external clock input for Timer0
Output is open drain type
RA5/AN4 bit5 TTL Input/output or ana log input
Legend: TTL = TTL input, ST = Schmitt Trigger input
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all
othe r
resets
05h PORTA —— RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA —— PORTA Data Direction Register --11 1111 --11 1111
9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by
PORTA.
1999 Microchip Technology Inc. Preliminary DS30569A-page 29
PIC16F870/871
3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will mak e the corres ponding POR TB pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
Three pins of POR TB are multiple xed with the Low Volt-
age Programming function; RB3/PGM, RB6/PGC and
RB7/PGD. The alternate functions of these pins are
described in the Spec ia l Features Section.
Each o f the PO RTB pins h as a weak in ternal p ull -up. A
single control bit can turn on all the pu ll-ups. This is per-
formed by clea ring bi t R BPU (OPTION_REG<7 >). The
weak pu ll-up i s automa tically tur ned of f when the por t
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
FIGURE 3-3: BLOCK DIAGRAM OF
RB3:RB0 PINS
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause t his interrupt to occur (i.e . an y RB7:RB4 pin con-
figured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compar ed w ith th e o ld value latche d o n the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user , in th e interrupt service routine , can clear the inter-
rupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
This interrupt on mismatch feature, together with soft-
ware configurable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key-depression. Refer to the Embedded
Control Handbook,
“Implementing Wake-Up on Key
Stroke”
(AN552).
RB0/IN T is an external interru pt input pin and is confi g-
ured using the INTEDG bit (OPTION_REG<6>).
RB0/INT is discussed in detail in Section 11.10.1.
FIGURE 3-4: BLOCK DIAGRAM OF
RB7:RB4 PINS
Data Latch
RBPU(2) P
VDD
QD
CK
QD
CK
QD
EN
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
weak
pull-up
RD Port
RB0/INT
I/O
pin(1)
TTL
Input
Buffer
Schmitt Trigger
Buffer
TRIS Latch
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
RB3/PGM
Data Latch
From other
RBPU(2) P
VDD
I/O
QD
CK
QD
CK
QD
EN
QD
EN
Data Bus
WR Port
WR TRIS
Set RBIF
TRIS Latch
RD TRIS
RD Port
RB7:RB4 pi ns
weak
pull-up
RD Port
Latch
TTL
Input
Buffer
pin(1)
ST
Buffer
RB7:RB6 in serial programming mode Q3
Q1
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
PIC16F870/871
DS30569A-page 30 Preliminary 1999 Microchip Technology Inc.
TABLE 3-3: PORTB FUNCTIONS
TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit# Buffer Function
RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3/PGM bit3 TTL/ST(1) Input/output pin or programming pin in LVP mode. Internal software
programmable weak pull-up.
RB4 bit4 TTL Input/output pi n (with in terrupt on chang e). Internal so ftware prog ramm ab le
weak pul l-u p.
RB5 bit5 TTL Input/output pi n (with in terrupt on chang e). Internal so ftware prog ramm ab le
weak pul l-u p.
RB6/PGC bit6 TTL/ST(2) Input/output pin (with interrupt on change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming clock.
RB7/PGD bit7 TTL/ST(2) Input/output pin (with interrupt on change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This bu ffer is a Schmitt Trigger input when configured as the external interrupt or LVP mode.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
V alue on all
other
resets
06h, 106h PORTB RB7 RB6 R B5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h, 186h T RI SB PORTB Data Direction Register 1111 1111 1111 1111
81h, 181h O P TIO N_REG RB PU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
1999 Microchip Technology Inc. Preliminary DS30569A-page 31
PIC16F870/871
3.3 PORTC and the TRISC Register
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (=1) will make th e correspondin g PORTC pi n
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISC bit (=0) will
mak e the corresp onding PORT C pin an outpu t (i.e. , put
the contents of the output latch on the selected pin).
POR TC is m ultiple x ed with se ver al periphera l function s
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISC as
destina tion sh ould be a v oided. Th e user should ref er to
the corresponding peripheral section for the correct
TRIS bit settings.
FIGURE 3-5: P ORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
PORT/PERIPHERAL Select(2)
Data Bus
WR
PORT
WR
TRIS
RD
Data Latch
TRIS Latch
RD TRIS Schmitt
Trigger
QD
Q
CK
QD
EN
Peripheral Data Out 0
1
QD
Q
CK
P
N
VDD
VSS
PORT
Peripheral
OE(3)
P eripheral Input
I/O
pin(1)
Note 1: I/O pins have diode protection to VDD and VSS.
2: P ort/Peripher al select signal selects between port
data and peripheral output.
3: P eripher al OE (output enable) is only activated if
peri pheral select is active.
PIC16F870/871
DS30569A-page 32 Preliminary 1999 Microchip Technology Inc.
TABLE 3-5: PORTC FUNCTIONS
TABLE 3-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit# Buffer Type Fun ction
RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input
RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input
RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1
output
RC3 bit3 ST Input/output port pin
RC4 bit4 ST Input/output port pin
RC5 bit5 ST Input/output port pin
RC6/TX/CK bit6 ST Input/output port pin or USART Asynchronous Transmit or Synchro-
nous Clock
RC7/RX/DT bit7 ST Input/output port pin or USART Asynchronous Receive or Synchro-
nous Data
Legend: ST = Schmitt Trigger input
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all
other
resets
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged.
1999 Microchip Technology Inc. Preliminary DS30569A-page 33
PIC16F870/871
3.4 PORTD and TRISD Registers
This section is not applicable to the PIC16F870.
PORTD is an 8-bit port with Schmitt Tr igger input buff-
ers. Each pin is individually configurable as an input or
output.
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In th is mode, the in put bu ffe rs
are TTL.
FIGURE 3-6: PORTD BLOCK DIAGRAM (IN
I/O PORT MODE)
TABLE 3-7: PORTD FUNCTIONS
TABLE 3-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Data
Bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
Input
Buffer
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
QD
CK
QD
CK
EN
QD
EN
Name Bit# Buffer Type Function
RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel slave port bit0
RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1
RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel slave port bit2
RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3
RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel slave port bit4
RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel slave port bit5
RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel slave port bit6
RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel slave port bit7
Legend: ST = Schmitt Trigger input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Val ue on:
POR,
BOR
Value on all
other resets
08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
88h TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h TRISE IBF OBF IBOV PSPMODE —PORTE Data Direction Bits 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by PORTD.
PIC16F870/871
DS30569A-page 34 Preliminary 1999 Microchip Technology Inc.
3.5 PORTE and TRISE Register
This section is not applicable to the PIC16F870.
PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
I/O PORTE becomes control inputs for the micropro-
cessor port when bit PSPMODE (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs). Ensure ADC ON1 is c onfigured fo r digital I/O . In
this mode, the input buffers are TTL.
Register 3-1 shows the TRISE Register, which also
controls the parallel slave port operation.
PORTE pins are multiplexed with analog inputs. When
select ed as an analo g input, these pins will r ead as ’ 0’s .
TRISE control s the direction of th e RE pins, e v en when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
FIGURE 3-7: PORTE BLOCK DIAGRAM (IN
I/O PORT MODE)
REGISTER 3-1: TRISE REGISTER (ADDRESS 89h)
Note: On a Power-on Reset, these pins are con-
figured as analog inputs.
Data
Bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
input
buffer
QD
CK
QD
CK
QD
EN
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
IBF OBF IBOV PSPMODE — bit2 bit1 bit0 R = Readable bi t
W=Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
Parallel Slave Port Status/Control Bits
bit 7 : IBF: Input Buffer Full Status bit
1 = A word has been receiv ed and is waiting to be read by the CPU
0 = No word has been receiv ed
bit 6: OBF: Output Buffer F ull Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5: IBOV: Input Buffer Overfl ow Detect bit (in microprocessor mode)
1 = A write occurred when a prev iously input word has not been read (must be cleared in software)
0 = N o overflow o cc u rre d
bit 4: PSPMODE: Par allel Sl ave Port Mode Select bit
1 = Parallel slave port mode
0 = General purpose I/O mode
bit 3: Unimplemented: Read as ’0’
PORTE Data Direction Bits
bit 2: Bit2: Direction Control bit for pin RE2/CS/AN7
1 = Input
0 = Output
bit 1: Bit1: Direction Control bit for pin RE1/WR/AN6
1 = Input
0 = Output
bit 0: Bit0: Direction Control bit for pin RE0/RD/AN5
1 = Input
0 = Output
1999 Microchip Technology Inc. Preliminary DS30569A-page 35
PIC16F870/871
TABLE 3-9: PORTE FUNCTIONS
TABLE 3-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name Bit# Buffer Type Function
RE0/RD/AN5 bit0 ST/TTL(1) In put /out put port pin or rea d c on trol in put in parallel s lave port mode or
analog input:
RD
1 = Not a read operation
0 = Read operation. Reads PORTD register (if chip selected)
RE1/WR/AN6 bit1 ST/TTL(1) Input /out put port pin or w rite control input in para llel s la v e po rt mode or
analog input:
WR
1 = Not a write operation
0 = Write operation. Writes PORTD register (if chip selected)
RE2/CS/AN7 bit2 ST/TTL(1) Input/output port pin or chip select control input in parallel slave port
mode or analog input:
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Val ue on:
POR,
BOR
Value on all
other resets
09h PORTE — — — — —RE2RE1RE0---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSPMODE — P ORTE Data Direction Bits 0000 -111 0000 -111
9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
PIC16F870/871
DS30569A-page 36 Preliminary 1999 Microchip Technology Inc.
3.6 Parallel Slave Port
The Parallel Slave Port is not implemented on the
PIC16F870.
POR TD operat es as an 8-bit wid e Par allel Sla ve P ort or
microprocessor port when control bit PSPMODE
(TRISE<4>) is set. In slave mode, it is asynchronously
readab le and writab le by the e xternal world thro ugh RD
control input pin RE0/RD and WR control input pin
RE1/WR.
It can directly interface to an 8-bit microprocessor data
bus . Th e e xte rnal microproc esso r can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set). The A/D por t con-
figuration bits PCFG3:PCFG0 (ADCON1<3:0>) must
be set to configure pins RE2:RE0 as digital I/O.
There are actually two 8-bit latches. One for data-out
and one f o r data i nput. T he user writes 8-bi t data to the
PORTD data latch and reads data from the port pin
latch (note that they have the same address). In this
mode, t he TRIS D regist er is i gnored, since t he micro -
processor is controlling the direction of data flow.
A write to the PSP occurs when both the CS and WR
lines ar e f irs t de t ec ted l ow. When ei th er th e CS or WR
lines become high (le vel triggered), the Inp ut Buff er Full
(IBF) status flag bit (TRISE<7>) is set on the Q4 clock
cycle, following the next Q2 cycle, to signal the write is
complete (Figure 3-9). The interrupt flag bit PSPIF
(PIR1<7 >) i s also set on the same Q4 clock cycle. IBF
can onl y be cl eare d by reading the PORTD input latc h.
The Input Buffer Overflow (IBOV) status flag bit
(TRISE<5>) is set if a second write to the PSP is
attempted when the previous byte has not been read
out of the buffer.
A read from t he PSP occurs when both the CS and R D
lines are first detected low. The Output Buffer Full
(OBF) status flag bit (TRISE<6>) is cleared immedi-
ately (Figure 3-10) indicating that the PORTD latch is
wa iti ng t o be rea d by the ex ternal bus. When eith er th e
CS or RD pin becomes high (level triggered), the inter-
rupt flag bit PSPIF is set on the Q4 clock cycle, follow-
ing the next Q2 cycle, indicating that the read is
complete. OBF remains low until data is written to
PORTD by the user firmware.
When not in PS P mo de , the IBF an d O BF b its are hel d
clear. However, if flag bit IBOV was previously set, it
must be cleared in firmware.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF mus t be cleare d b y the u ser in firmware a nd the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7>).
FIGURE 3-8: PORTD AND PORTE BLOCK
DIAGRAM (P ARALLEL SLAVE
PORT)
Data Bus
WR
PORT
RD
RDx
QD
CK
EN
QD
EN
PORT
pin
One bit of PORTD
Set interrupt flag
PSPIF (PIR 1<7>)
Read
Chip Select
Write
RD
CS
WR
Note: I/O pin has protection diodes to VDD and VSS.
TTL
TTL
TTL
TTL
1999 Microchip Technology Inc. Preliminary DS30569A-page 37
PIC16F870/871
FIGURE 3-9: PARALLEL SLAVE PORT WRITE WAVEFORMS
FIGURE 3-10: PARALLEL SLAVE PORT READ WAVEFORMS
TABLE 3-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
08h PORTD Port data latch when written: Port pins when read xxxx xxxx uuuu uuuu
09h PORTE — — — — —RE2RE1RE0---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
0Ch PIR1 PSPIF ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
IBF
PSPIF
RD
OBF
PORTD<7:0>
PIC16F870/871
DS30569A-page 38 Preliminary 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. Preliminary DS30569A-page 39
PIC16F870/871
4.0 DATA EEPROM AND FLASH
PROGRAM MEMORY
The Data EEPR OM and FLASH Progr am Memory are
readab le an d writab le during normal oper atio n o v er the
entire VDD range. A bulk erase operation may not be
issued from user code (which includes removing code
prote ction). The data memory is not dire ctly m apped in
the register file space. Instead, it is indirectly
addressed through the Special Function Registers
(SFR).
There are six SFR s used to r ead an d write the progra m
and data EEPROM memory. These registers are:
• EECON1
• EECON2
• EEDATA
• EEDATH
• EEADR
• EEADRH
The EEPR OM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data f or read/write and EEADR holds the
address of the EEPROM lo cation being accessed. The
registers EEDATH and EEADRH are not used for data
EEPROM access. The PIC16F870/871 devices have
64 bytes of data EEPROM with an address range from
0h to 3Fh.
The EEPROM data memory is rated for high erase/
write cyc le s . The w rite tim e is co ntro lle d by an on-chi p
timer. The write t ime will v ary with v oltag e and temp er-
ature, as well as from chip-to-chip. Please refer to the
specifications for exact limits.
The program memory allows word reads and writes.
Program memory access allows for checksum calcula-
tion and c ali brat ion t able st orage. A byte or wor d wr it e
automatically erases the location and writes the new
data (erase before write). Writing to program memory
will cease oper ation until the write is comple te. The pro-
gram memory cannot be accessed during the write,
therefore code cann ot e xecute. During t he w rite op er a-
tion, the oscillator continues to clock the peripherals,
and therefore, they continue to operate. Interrupt
events will be detected and essentially “queued” until
the write is completed. When the write completes, the
next instruction in the pipeline is executed and the
branch to the interrupt ve ctor address will occur.
When interfacing to the program memory block, the
EEDATH:EEDATA registers form a two byte word,
which holds the 14-bit data for read/write. The
EEADRH:EEADR registers form a two byte word,
which holds the 13-bit address of the FLASH location
being acc essed. The PIC16F870/8 71 devi ces hav e 2K
words of program FLASH with an address range from
0h to 7FFh. The unused upper bits in both the EEDATH
and EEDATA registers all read as “0’s”.
The v alue written to progr am memory does not need to
be a valid instruction. Therefore, up to 14-bit numbers
can be stored in memory for use as calibration param-
eters, serial numbers, packed 7-bit ASCII, etc. Execut-
ing a program memory location containing data that
forms an invalid instruction results in a NOP.
4.1 EEADR
The addres s registers can addre ss up to a maxim um of
256 bytes of data EEPROM or up to a maximum of 8K
words of program FLASH. However, the PIC16F870/
871 have 64 bytes of data EEPROM and 2K words of
program FLASH.
When selecting a program address value, the MSByte
of the address is written to the EEADRH register and
the LSByte is written to the EEADR register. When
selecting a data address value, only the LSByte of the
address is written to the EEADR register.
On the PIC16F870/871 devices, the upper two bits of
the EEADR must always be cleared to prevent inad-
v ertent access to t he wro ng l oc atio n in da ta EEPROM.
This also applies to the program memory. The upper
five MSbits of EEADRH must always be clear during
program FLASH access.
4.2 EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the memory write sequence.
Control bit EEPGD determines if the access will be a
program or a data memory access. When clear, any
subsequent operations will operate on the data mem-
ory. Whe n set, any subseq uent op er ations will o pera te
on the program memory.
Control bits RD and WR initiate read and write opera-
tions, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at the
completion of the read or write operation. The inability
to clear the WR bit in software prevents the accidental
or premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On po wer-up , the W REN bit is clea r . The WRER R bit is
set when a write operation is interrupted by a MCLR
reset or a WDT ti me-out rese t during n ormal oper atio n.
In these situations, follow ing reset, the user can check
the WRERR bit and rewrite the location. The value of
the data and address registers and the EEPGD bit
remains unchanged.
Interrupt flag b it EEIF, in th e PI R2 re gis ter, i s set whe n
write is complete. It must be cleared in software.
PIC16F870/871
DS30569A-page 40 Preliminary 1999 Microchip Technology Inc.
REGISTER 4-1: EECON1 REGISTER (ADDRESS 18Ch)
R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/W-0 R/W-0
EEPGD ——— WRERR WREN WR RD R = Readable bit
W = Writable bit
U = Unimplem ented bit,
read as ‘0’
- n= Value at POR reset
bit7 bit0
bit 7: EEPGD: Program / Data EEPR OM Select bit
1 = Accesses Program memory
0 = Accesses data memory
(This bit cannot be changed while a read or write operation is in progress)
bit 6-4: Unimplemented: Read as '0'
bit 3: WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
(any M CLR reset or any WDT reset during normal operation)
0 = The write operation completed
bit 2: WREN: EEPROM Write Enable bit
1 = Allows write cycl es
0 = Inhibits write to the EEPROM
bit 1: WR: Write Control bit
1 = Initiates a write cycle. (The bit is cleared by hardware once write is complete.) The WR bit can only
be set (not cleared) in software.
0 = Write cycle to the EEPROM is complete
bit 0: RD: Read Control bit
1 = Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not cleared) in
software.
0 = Does not initiate an EEPROM read
1999 Microchip Technology Inc. Preliminary DS30569A-page 41
PIC16F870/871
4.3 Reading the Data EEPROM Memory
To read a data memory location, the user must write the
address to t he EEADR register, clear the EEPGD con-
trol bit (EECON1<7>) and then set control bit RD
(EECON1<0>). The data is available in the very next
instruction cycle of the EEDATA register, therefore it
can be read by the next instruction. EEDATA will hold
this value until another read operation or until it is writ-
ten to by the user (during a write operation).
EXAMPLE 4-1: DAT A EEPROM READ
BSF STATUS, RP1 ;
BCF STATUS, RP0 ;Bank 2
MOVLW DATA_EE_ADDR ;
MOVWF EEADR ;Data Memory Address to read
BSF STATUS, RP0 ;Bank 3
BCF EECON1, EEPGD ;Point to DATA memory
BSF EECON1, RD ;EEPROM Read
BCF STATUS, RP0 ;Bank 2
MOVF EEDATA, W ;W = EEDATA
4.4 Writing to the Data EEPROM Memory
To write an EEPROM data location, the address must
first be written to the EEADR regist er and the data writ-
ten to the EEDATA register. Then the sequence in
Example 4-2 must be f ollowed to initiate the write cycle.
EXAMPLE 4-2: DATA EEPROM WRITE
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware
After a write sequence has been initiated, clearing the
WREN bit will not aff ect the current write cycle. The WR
bit will be inhibit ed from being set unles s the WREN bit
is set. The WREN b it must be set on a previous instruc-
tion. Both WR an d WREN ca nno t be s et wi th the sam e
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardw are and the EEPR OM Write Complete
Interrupt Flag bi t (EEIF) is set. EEIF m ust be cleare d by
software.
BSF STATUS, RP1 ;
BCF STATUS, RP0 ; Bank 2
MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Data Memory Address to write
MOVLW DATA_EE_DATA ;
MOVWF EEDATA ; Data Memory Value to write
BSF STATUS, RP0 ; Bank 3
BCF EECON1, EEPGD ; Point to DATA memory
BSF EECON1, WREN ; Enable writes
BCF INTCON, GIE ; Disable Interrupts
MOVLW 55h ;
Required MOVWF EECON2 ; Write 55h
Sequence MOVLW AAh ;
MOVWF EECON2 ; Write AAh
BSF EECON1, WR ; Set WR bit to begin write
BSF INTCON, GIE ; Enable Interrupts
SLEEP ; Wait for interrupt to signal write complete
BCF EECON1, WREN ; Disable writes
PIC16F870/871
DS30569A-page 42 Preliminary 1999 Microchip Technology Inc.
4.5 Reading the FLASH Program Memory
A prog ram memory location ma y be read b y writing tw o
bytes of the address to the EEADR and EEADRH reg-
isters, setting the EEPGD control bit (EECON1<7>)
and then setting control bit RD (EECON1<0>). Once
the read control bit is set, the microcontroller will use
the next two instruction cycles to read the data. The
data is available in the EEDATA and EEDATH registers
after the second NOP instruction. Therefore, it can be
read as two bytes in the following instructions. The
EED ATA and EED ATH registers will hold t his v alue u ntil
another rea d operation or until it is written to b y the user
(during a write operation).
EXAMPLE 4-3: FLASH PROGRAM READ
BSF STATUS, RP1 ;
BCF STATUS, RP0 ; Bank 2
MOVLW ADDRH ;
MOVWF EEADRH ; MSByte of Program Address to read
MOVLW ADDRL ;
MOVWF EEADR ; LSByte of Program Address to read
BSF STATUS, RP0 ; Bank 3
BSF EECON1, EEPGD ; Point to PROGRAM memory
Required BSF EECON1, RD ; EEPROM Read
Sequence
NOP ; memory is read in the next two cycles after BSF EECON1,RD
NOP ;
BCF STATUS, RP0 ; Bank 2
MOVF EEDATA, W ; W = LSByte of Program EEDATA
MOVF EEDATH, W ; W = MSByte of Program EEDATA
1999 Microchip Technology Inc. Preliminary DS30569A-page 43
PIC16F870/871
4.6 Writing to the FLASH Program
Memory
When the PIC16F870/871 are fully code protected or
not code protected, a word of the FLASH program
memory may be written provided the WRT configura-
tion bit is set. If the PIC16F870/871 are partially code
protected, then a word of FLASH program memory
may be written if the word is in a non-code protected
segment of memory and the WRT configuration bit is
set. To write a FLASH program location, the first two
by tes of the address m ust be written to the EEADR and
EEADRH registers and two bytes of the data to the
EEDATA and EEDATH registers, set the EEPGD con-
trol bit (EECON1<7>), and then set control bit WR
(EECON1<1 >). The s equence in Examp le 4-4 must be
followed to initiate a write to program memory.
The microcontroller will then halt internal operations
during the next two instruction cycles for the TPEW
(parameter D133) in which the write takes place. This
is not SLEEP mode, as the clocks and peripherals will
continue to run. Therefore, the two instructions follow-
ing the “BSF EECON, WR” should be NOP instructions.
After the write cycle, the microcontroller will resume
operation with the 3rd instruction after the EECON1
write instruction.
EXAMPLE 4-4: FLASH PROGRAM WRITE
BSF STATUS, RP1 ;
BCF STATUS, RP0 ; Bank 2
MOVLW ADDRH ;
MOVWF EEADRH ; MSByte of Program Address to read
MOVLW ADDRL ;
MOVWF EEADR ; LSByte of Program Address to read
MOVLW DATAH ;
MOVWF EEDATH ; MS Program Memory Value to write
MOVLW DATAL ;
MOVWF EEDATA ; LS Program Memory Value to write
BSF STATUS, RP0 ; Bank 3
BSF EECON1, EEPGD ; Point to PROGRAM memory
BSF EECON1, WREN ; Enable writes
BCF INTCON, GIE ; Disable Interrupts
MOVLW 55h ;
Required MOVWF EECON2 ; Write 55h
Sequence MOVLW AAh ;
MOVWF EECON2 ; Write AAh
BSF EECON1, WR ; Set WR bit to begin write
NOP ; Instructions here are ignored by the microcontroller
NOP
; Microcontroller will halt operation and wait for
; a write complete. After the write
; the microcontroller continues with 3rd instruction
BSF INTCON, GIE ; Enable Interrupts
BCF EECON1, WREN ; Disable writes
PIC16F870/871
DS30569A-page 44 Preliminary 1999 Microchip Technology Inc.
4.7 Write Verify
Depen ding on th e applic ation, goo d progr amming prac-
tice may dictate that the value written to the memory
should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
Generally a write failure will be a bit which was written
as a ’1’, but re ads back as a ’0’ (due to lea kag e of f t he
bit).
4.8 Protection Against Spurious Write
4.8.1 EEPROM DATA MEMORY
Ther e are con dit ion s wh en t he device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power gl itch, or software mal function.
4.8.2 PROGRAM FLASH MEMORY
To protect against spurious writes to FLASH program
memory, the WRT bit in the configuration word may be
programmed to ‘0’ to prevent writes. The write initiate
sequen ce must als o be fol lowe d. WR T and the config u-
ration word cannot be programmed by user code, only
through the use of an external programmer.
4.9 Operation during Code Protect
Each reprogrammable memory block has its own code
protect mechanism. External Read and Write opera-
tions are disabled if either of these mechanisms are
enabled.
4.9.1 DATA EEPROM MEMORY
The mic rocontro ller it self c an both read a nd write to the
internal Data EEPROM, regardless of the state of the
code protect configuration bit.
When data mem ory is code protecte d (CONFIG<8>=0 )
any further external programming access of program
memory is disabled. To reenable programming access
to program memory, both bulk erase and removal of
code protection must be performed on program and
data memory.
4.9.2 PROGRAM FLASH MEMORY
The microcontroller can read and execute instructions
out of the internal FLASH p rog ram m emory, regardless
of the state of the code protect configuration bits. How-
ever, the WRT configuration bit and the code protect
bits have different effects on writing to program mem-
ory. Table 4-1 shows the various configurations and
status of reads and writes. To erase the WRT or code
protection bits in the configuration word requires that
the device be fully erased.
TABLE 4-1: READ/WRITE STATE OF INTERNAL FLASH PROGRAM MEMORY
Configuration Bits Memory Location Internal
Read Internal
Write ICSP Read ICSP Write
CP1 CP0 WRT
001All progr a m mem ory Yes Yes No No
000All progr a m mem ory Yes No No No
110All progr a m mem ory Yes No Yes Yes
111All progr a m mem ory Yes Yes Yes Yes
1999 Microchip Technology Inc. Preliminary DS30569A-page 45
PIC16F870/871
TABLE 4-2: REGISTERS ASSOCIATED WITH DATA EEPROM/PROGRAM FLASH
AddressNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Value on:
POR,
BOR
Value on
all other
resets
0Bh, 8Bh,
10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Dh EEADR EEPROM address register xxxx xxxx uuuu uuuu
10Fh EEADRH —————EEPROM address high xxxx xxxx uuuu uuuu
10Ch EEDATA EEPROM data resister xxxx xxxx uuuu uuuu
10Eh EEDATH — — EEPROM data resis ter high xxxx xxxx uuuu uuuu
18Ch EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 x--- u000
18Dh EECON2 EEPROM control resister2 (not a physical resister)
8Dh PIE2 ——— EEIE ————---0 ---- ---0 ----
0Dh PIR2 ——— EEIF ————---0 ---- ---0 ----
Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented read as ’0’. Shaded cells are not used by the
Timer1 module.
PIC16F870/871
DS30569A-page 46 Preliminary 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. Preliminary DS30569A-page 47
PIC16F870/871
5.0 T IMER0 MODULE
The Tim er0 module timer/count er has the f ollo wing f ea-
tures:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 5-1 is a block diagram of the Timer0 module and
the p r e s cal e r s ha red w i th th e W DT.
Additional information on the Timer0 module is available
in the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In timer mode, the Timer0 mod-
ule wi ll i nc rem ent eve ry instruct ion cy cl e (w it hou t pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
use r can wo rk around this by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
dis c ussed in detail in S ection 5.2.
The prescaler is mutually exclusively shared between
the Timer0 module and the watchdog timer. The pres-
caler is not re adab le o r writab le . Sec tion 5.3 details th e
oper at ion of the presca le r.
5.1 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows f rom FFh to 00h . This overflow se ts bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in s oftwa re b y th e Tim er0 mo dule interrupt s er-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP.
FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
RA4/T0CKI
T0SE
Pin
M
U
X
CLKOUT (= FOSC/4)
SYNC
2
Cycles TMR 0 r e g
8-bit Prescaler
8 - to - 1MUX
M
U
X
M U X
Watchdog
Timer
PSA
01
0
1
WDT
Time-out
PS2:PS0
8
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
PSA
WDT Enable bit
M
U
X
0
10
1
Data Bus
Set Flag Bit T0 IF
on Overflow
8
PSA
T0CS
PRESCALER
PIC16F870/871
DS30569A-page 48 Preliminary 1999 Microchip Technology Inc.
5.2 Using Timer0 with an External Clock
When no prescaler is used, the exter nal clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plishe d by sam pling the presca ler output on th e Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
5.3 Prescaler
There is only one prescaler available, which is mutually
exclusively shared between the Timer0 module and the
watchdog timer. A prescaler assignment for the Timer0
module means that there is no prescaler for the watch-
dog timer , and vi ce-versa. This prescaler is not readab le
or writable (see Figure 5-1).
The PSA and PS2:PS0 bits (OPTION_REG<3:0>) deter-
mine the prescaler assignment and prescale ratio .
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler . When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
REGISTER 5-1: OPTION_REG REGISTER
Note: Writing to TMR0, when the prescaler is
assigned to Timer0, will clear the prescaler
count, but will not change the prescaler
assignment.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPUINTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit
W = Writable bit
U = Unimplem ented bit,
read as ‘0’
- n = Value at POR reset
bit 7 bit 0
bit 7: RBPU
bit 6: INTEDG
bit 5: T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instr uction cycl e clock (CLKOUT)
bit 4: T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transi tion on T0 CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3: PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
Note: To a vo id an un intended de vice RESET, the in struction sequ ence s ho wn in the PICmicro™ Mid-Ran ge MCU
Family Reference Manual (DS33023) must be executed when changing the prescaler assignment from
Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
1999 Microchip Technology Inc. Preliminary DS30569A-page 49
PIC16F870/871
TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Valu e on:
POR,
BOR
Value on all
other resets
01h,101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
PIC16F870/871
DS30569A-page 50 Preliminary 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. Preliminary DS30569A-page 51
PIC16F870/871
6.0 T IMER1 MODULE
The T ime r1 m od ule is a 1 6-bi t ti mer/count er c ons is tin g
of two 8-bit registers (TMR1H and TMR1L), which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls ov er to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit TMR1IE (PIE1<0>).
Timer1 can operate in one of two modes:
•As a timer
•As a counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
In timer mode, Timer1 increments every instruction
cycle. In coun ter mo de, it in creme nts on every ri sing
edge of the external clock input.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR 1 ON (T1C O N<0>).
Timer1 a lso has an in ternal “reset input ”. This reset can
be generated by the CCP module (Section 8.0).
Register 6-1 shows the Timer1 control register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Additional infor mation on timer modules is available in
the PICmicro™ Mid-range MCU Family Reference
Manual (DS33023).
REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON R = Read able bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-6: Unimplemented: Read as '0'
bit 5-4: T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 P rescale value
10 = 1:4 P rescale value
01 = 1:2 P rescale value
00 = 1:1 P rescale value
bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillat or is enabled
0 = Oscillator is shut off (The oscillator inverter is turned off to eliminate power drain)
bit 2: T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1: TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0: TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
PIC16F870/871
DS30569A-page 52 Preliminary 1999 Microchip Technology Inc.
6.1 Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect since the internal clock is
always in sync.
6.2 Timer1 Counter Operation
Timer1 may operate in asynchronous or usynchronous
mode depending on the setting of the TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After
Timer1 is enabled in counter mode, the module must
first have a falling edge before the counter begins to
increment.
FIGURE 6-1: TIMER1 INCREMENTING EDGE
6.3 Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mod e, the time r increment s on ev ery rising edge of
clock input on pin RC1/T1OSI, when bit T1OSCEN is
set, or on pi n RC 0/ T1O SO/T1C KI , when bi t T1O SC EN
is cl eare d.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
caler stage is an asynchronous ripple-counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut off. The pres-
caler however will continue to increment.
FIGURE 6-2: TIMER1 BLOCK DIAGRAM
T1CKI
(Default high)
T1CKI
(Default low)
Note: Arrows indicate counter increments.
TMR1H TMR1L
T1OSC T1SYNC
TMR1CS T1CKPS<1:0> Q Clock
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
TMR1ON
on/off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
clock input
2
RC0/T1OSO/T1CKI
RC1/T1OSI(2)
Note 1: When the T1OSCEN bit is cleared, the inver te r is tur ned of f. This eliminates power drain.
2: For the PIC16F870/871, the Schmitt Trigger is not implemented in external clock mode.
Set flag bit
TMR1IF on
Overflow TMR1
(2)
1999 Microchip Technology Inc. Preliminary DS30569A-page 53
PIC16F870/871
6.4 Timer1 Operation in Asynchronous
Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in soft-
ware are needed to read/write the timer (Section 6.4.1).
In asynchronous counter mode, Timer1 can not be used
as a time-base for capture or compare operations.
6.4.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will guarantee a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself poses certain problems, since
the timer may overflow between the reads.
For w rites , it is recomm ended t hat the u se r s impl y stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires s ome c are . Exam ples
12-2 and 12-3 in the PICmicro™ Mid-Range MCU Fam-
ily Reference Manual (DS33023) show how to read and
write Timer1 when it is running in asynchronous mode .
6.5 Timer1 Oscillator
A crystal oscillator circuit is built-in betw een pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control b it T1OSCEN (T1CON<3>). The osc illa-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for use with a 32 kHz crystal. Table 6-1 shows the
capacitor selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 6-1: CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
6.6 Resetting Timer1 using CCP1 Trigger
Output
If the CCP1 module is configured in compare mode to
generate a “special event trigger” (CCP1M<3:0> =
1011), this signal will reset Timer1.
Timer1 must be configured for either timer or synchro-
niz ed counter m ode to tak e adv antage of th is f eature . If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the e v ent that a write to Timer1 coi ncides with a spe-
cial event trigger from CCP1, the write will take prece-
dence.
In this mode of oper ation, the CCPR1H:CC PR1L regis -
ter pair effectively becomes the period register for
Timer1.
6.7 Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H an d TMR 1 L reg isters a re not reset to 00h o n a
POR or any other reset except by the CCP1 special
event trigger.
T1CON regist er is reset t o 00h on a Pow er-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other resets, the register is
unaffected.
6.8 Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
Osc Type Freq C1 C2
LP 32 kHz 33 pF 33 pF
100 k Hz 15 pF 15 pF
200 k Hz 15 pF 15 pF
Thes e values are for design guidance only.
Crystals Tested:
32.768 kHz Epson C-001R 32.768K-A ± 20 PPM
100 kHz Epson C-2 100.0 0 KC-P ± 20 PPM
200 kHz STD XTL 200.000 kHz ± 20 PPM
Note 1: Higher capacitance increases the stability of
oscillator, but also increases the start-up time.
2: Since each resonator/crystal has its own charac-
teristics, the user should consult the resonator/
cry st al manufacturer for appropriate values of
ex ternal components.
Note: The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
PIC16F870/871
DS30569A-page 54 Preliminary 1999 Microchip Technology Inc.
TABLE 6-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,
18Bh
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TM R1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
1999 Microchip Technology Inc. Preliminary DS30569A-page 55
PIC16F870/871
7.0 T IMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mo de of the CCP m od ule (s). The T MR2 re g-
ister is readable and writable, and is cleared on any
device res et.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1: 0>).
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readab le and writable register . The PR2 register is ini-
tialized to FFh upon reset.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
Timer2 can be s hut off by clearing co ntrol b it T MR 2O N
(T2CON<2>) to minimize power consumption.
Register 7-1 shows the Timer2 control register.
Additional infor mation on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manu al (DS330 23).
7.1 Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (POR, MCLR reset, WDT reset
or BOR)
TMR2 is not cleared when T2CON is written.
7.2 Output of TMR2
The outpu t of TMR2 (bef ore th e postscaler) i s fed t o the
SSPort module, which optionally uses it to generate
shift clock.
FIGURE 7-1: TIMER2 BLOCK DIAGRAM
REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
Comparator
Sets flag
TMR2 reg
Postscaler
Prescaler
PR2 reg
2
FOSC/4
1:1 1:16
1:1, 1:4, 1:16
4
bit TMR2IF
to
T2OUTPS3:
T2OUTPS0
T2CKPS1:
T2CKPS0
EQ
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 R = Readable bit
W = Writab le bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: Unimplemented: Read as '0'
bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output P ostscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
0010 = 1:3 Postscale
•
•
•
1111 = 1:16 Post scale
bit 2: TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
PIC16F870/871
DS30569A-page 56 Preliminary 1999 Microchip Technology Inc.
TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
1999 Microchip Technology Inc. Preliminary DS30569A -page 57
PIC16F870/871
8.0 CAPTURE/COMPARE/PWM
MODULE
The C aptu re/C o mp are/ PWM (CC P) m od ule c on tain s a
16-bit register which can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM master/slave Duty Cycle register
Table 8-1 shows the resources used by the CCP mod-
ule. In the following sections, the operation of a CCP
module is described.
CCP1 Module:
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the oper ation of CCP1. The special e vent trigger is gen-
erated by a compare match and will reset Timer1 and
start an A/D conversion (if the A/D module is enabled).
Additional infor mation on CCP modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manu al (DS33023) and in Appl ication Note 594, “Usin g
the CCP Modules” (DS00594).
TABLE 8-1: CCP MODE - TIMER
RESOURCES REQUIRED
REGISTER 8-1: CCP1CON REGISTER (ADDRESS: 17h)
CCP Mode Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— CCP1X CCP1Y CCP1M3 CCP1 M2 CCP1M1 CCP1M0 R =Readab le bit
W =Writable bit
U = Unimple mented bit, rea d as ‘0’
- n = Value at PO R reset
bit7 bit0
bit 7-6: Unimp lemented: Read as ’0’
bit 5-4: CCP1<X:Y>: PWM Least Significant bits
Capture Mode : Unus ed
Compare Mode: Unused
PWM Mode: These bi ts are the two LSb s of t he P W M dut y c yc le. Th e e igh t M Sbs are found in CC PR 1L .
bit 3-0: CCP1M<3:0>: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mo de , clear output on match (CCP1IF bit is set)
1010 = C om pare m ode, g ene r ate so ftwa re i nte rrupt on match (C CP1IF bit i s se t, C CP pin is u naffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set, CCP1 pin is unaffected); CCP1 resets
TMR1 and starts an A/D conversion (if A/D module is enabled)
11xx = PWM mode
PIC16F870/871
DS30569A -page 58 Preliminary 1999 Microchip Technology Inc.
8.1 Capt ure Mo de
In Capture mode, CCPR1H:CCPR1L captures the
16-bit v alue of th e TMR1 register wh en an ev ent oc curs
on pin RC2/CCP1. An event is defined as:
• Every fal lin g edge
• Every rising edge
• Ev ery 4th rising edge
• Every 16th rising edge
An event is selected by control bits CCP1M<3:0>
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. The
interrupt flag must be cleared in software. If another
capture occurs before the value in register CCPR1 is
read, the old captured value will be lost.
8.1.1 CCP PIN CONFIGURATION
In Captu re m ode, the RC2/CCP1 pin s hou ld b e co nfig-
ured as an input by setting the TRISC<2> bit.
FIGURE 8-1: CAP TURE MODE OPERATION
BLOC K DIAGRAM
8.1.2 TIMER1 MODE SELECTION
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the c apture
feature. In asynchronous counter mode, the capture
operation may not work.
8.1.3 SOFTWARE INTERRUPT
When the capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
8.1.4 CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M<3 :0>. Whene ver the CCP modu le is turned off ,
or the CCP module is not in capture mode, the pres-
caler counter is cleared. Any reset will clear the pres-
caler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 8-1: CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF CCP1CON ;Turn CCP module off
MOVLW NEW_CAPT_PS;Load the W reg with
; the new precscaler
; move value and CCP ON
MOVWF CCP1CON ;Load CCP1CON with this
; value
Note: If the RC2/CCP1 pin is configured as an
output, a w rite to the port can cause a cap-
ture condition.
CCPR1H CCPR1L
TMR1H TMR1L
Set flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Q’s CCP1CON<3:0>
RC2/CCP1
Prescaler
÷ 1, 4, 16
and
edge detect
Pin
1999 Microchip Technology Inc. Preliminary DS30569A -page 59
PIC16F870/871
8.2 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. Wh en a match occurs, the RC2/CC P1 pin is:
• Driven high
•Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M<3:0> (CCP1CON<3:0>). At the same
time, interrupt flag bit CCP1IF is set.
FIGURE 8-2: COMPARE MODE OPERATION
BLOCK DIAGRAM
8.2.1 CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
8.2.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.2.3 SOFTWARE INTERRUPT MODE
When Generate S oftware Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set causing
a CCP interrupt (if enabled).
8.2.4 SPECIAL EVENT TRIGGER
In this mod e, an i nternal hardw a re trigger is g ener ated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 regi ster pair and s tarts an A/D co nv ers io n (i f th e
A/D module is enabled). This allows the CCPR1 regis-
ter to effectively be a 16-bit programmable period reg-
ister for Timer1.
.
8.3 PWM Mode (PWM)
In pulse width modulation mode, the CCP1 pin pro-
duces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiple xed with th e PORTC data latch, the
TRISC<2> bit must be cleared to make the CCP1 pin
an output.
Figure 8-3 shows a simp lified bloc k diagr am of the CCP
module in PWM mode.
F or a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 8.3.3.
FIGURE 8-3: SIMPLIFIED PWM BLOCK
DIAGRAM
Note: Clearing the CCP1CON register will force
the RC2/ CCP1 compare output lat ch to the
default low level. This is not the data latch.
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
ROutput
Logic
Special Ev ent Trigger
Set flag bit CCP1IF
(PIR1<2>)
match
RC2/CCP1
TRISC<2> CCP1CON<3:0>
Mode Select
Output Enable
Pin
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
Note: The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Note: Clear ing the CCP1CON regis ter will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
RQ
S
Duty Cycle Registers CCP1CON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
TRISC<2>
RC2/CCP1
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
PIC16F870/871
DS30569A -page 60 Preliminary 1999 Microchip Technology Inc.
A PWM output (Figure 8-4) has a time-base (period)
and a time that the output stay s high (duty cycle). The
frequency of the PWM is the inverse of the period (1/
period).
FIGURE 8-4: PWM OUTPUT
8.3.1 PWM PERIOD
The PWM pe riod is s pecifi ed b y writing to the PR2 reg -
ister. The PWM period can be calculated using the fol-
lowing formula:
When TMR2 is equal to PR2, the f ollowi ng three e vents
occur on the next increment cycle:
•TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cy cle is latched from CCPR1L into
CCPR1H
8.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
Tosc • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to do uble buffe r the PWM duty c yc le . Thi s do uble
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Maximum PWM resolution (bits) for a given PWM
frequency:
8.3.3 SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 register .
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale value and enab le Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation .
Note: The Timer2 postscaler (see Section 8.1) is
not used in the determination of the PWM
frequency. The postsc aler could b e used to
have a servo update rate at a different fre-
quency than the PWM output.
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
FOSC
4 • FPWM • TMR2 Prescale value
PR2 = — 1
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
log(FPWM
log(2)
FOSC )bits
=
Resolution
1999 Microchip Technology Inc. Preliminary DS30569A -page 61
PIC16F870/871
TABLE 8-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
TABLE 8-3: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all othe r
resets
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IFTMR2IF TMR1IF 0000 -000 0000 -000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IETMR2IE TMR1IE 0000 -000 0000 -000
87h TRI SC PORTC Data Direction Register 1111 1111 1111 1111
0Eh TMR 1L Holding register for the Least Sign ifica nt Byte of th e 16-bit TMR1 r egister xxxx xxxx uuuu uuuu
0Fh TMR1H Holding reg ister f or the Most Significan t Byte o f the 16-bit T MR 1 register xxxx xxxx uuuu uuuu
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h C CPR1L Capture/Comp are /PWM register 1 (LSB) xxxx xxxx uuuu uuuu
16h C CPR1H Capture/Comp are/PWM regis ter1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.
Note 1:The PSP is not implemented on the PIC16F870; alway s mainta in these bits clear.
Ad dres s Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on:
POR,
BOR
Value on
all othe r
resets
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
87h TRISC PORTC Data Dire ction Regi ster 1111 1111 1111 1111
11h TMR2 Timer2 module’ s register 0000 0000 0000 0000
92h PR2 Timer2 module’ s period register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Capture/Compare/PWM r egiste r1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Captur e/Co mpare/PWM r egiste r1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1:Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
PIC16F870/871
DS30569A -page 62 Preliminary 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. Preliminary DS30569A-page 63
PIC16F870/871
9.0 ADDRESS ABLE UNI VERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com-
muni cations I nterf ace or SCI ). The USAR T can b e con-
figured as a full duplex asynchronous system that can
comm un ic a te with periphe ral devices su ch as C RT ter-
minals and person al compu ters, or it can b e configure d
as a half dup lex synchro nou s sy s tem that c an co mmu-
nicate w it h periphe ral devices such as A/D or D /A in te-
grated circuits, serial EEPROMs etc.
The USART can be configured in the following modes:
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to
be set in order to configure pins RC6/TX/CK and
RC7/RX/DT as the Univ ersal Sync hronous Asynchro-
nous Receiver Transmitter.
The USART module also has a multi-processor com-
munication capability using 9-bit address detection.
REGISTER 9-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC — BRGH TRMT TX9D R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from exte rnal source)
bit 6: TX9: 9-bit Transmit Enable bit
1 = Sel ects 9 -bit transmission
0 = Sel ects 8 -bit transmission
bit 5: TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4: SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3: Unimplemented: Read as '0'
bit 2: BRGH: High Baud Rate Select bit
Asynchronous mode
1 = High speed
0 = Low speed
Synchronous mode
Unused in this mode
bit 1: TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0: TX9D: 9th bit of transmit data. Can be parity bit.
PIC16F870/871
DS30569A-page 64 Preliminary 1999 Microchip Technology Inc.
REGISTER 9-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: SPEN: Serial Port Enable bit
1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6: RX9: 9-bit Receive Enable bit
1 = Sel ects 9-bit reception
0 = Sel ects 8-bit reception
bit 5: SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - master
1 = Enables single receive
0 = Disables single receive
This bit is cl eared after reception is complete.
Synchronous mode - slave
Unused in this mode
bit 4: CREN: Continuous Receive Enable bit
Asynchronous mode
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3: ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1)
1 = Enables address detection, enable interrupt and load of the receive burffer when RSR<8> is set
0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit
bit 2: FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1: OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
bit 0: RX9D: 9th bit of received data (Can be parity bit)
1999 Microchip Technology Inc. Preliminary DS30569A-page 65
PIC16F870/871
9.1 USART Baud Rate Generator (BRG)
The BRG supports both the asynchronous and syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In synchronous mode, bit BRGH is ignored.
Table 9-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in master mode (internal clock).
Giv en the desired baud r ate and Fo sc, the neare st inte-
ger value for the SPBRG register can be calculated
using the formula in Table 9-1. From this, the error in
baud rate can be determined.
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
becaus e the FOSC/(16(X + 1)) eq uati on ca n red uc e th e
baud rate err or in some cases .
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a ti mer overflow be fore ou tput-
ting the new baud rate.
9.1.1 SAMPLING
The data on th e RC7/RX/DT pi n is sampled three ti mes
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
TABLE 9-1: BAUD RATE FORMULA
TABLE 9-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)
0
1(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1)) Baud Rate= FOSC/(16(X+1))
NA
X = value in SPBRG (0 to 255)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other
resets
98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG.
PIC16F870/871
DS30569A-page 66 Preliminary 1999 Microchip Technology Inc.
-
TABLE 9-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
BAUD
RATE
(K)
FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz
KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR
SPBRG
value
(decimal)
0.3------- --
1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129
2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64
9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15
19.2 19. 5 31 1.72 15 19.23 1 0.16 12 19.53 1 1.72 7
28.8 31.250 8.51 9 27.778 3.55 8 31.250 8.51 4
33.6 34.722 3.34 8 35.714 6.29 6 31.250 6.99 4
57.6 62.500 8.51 4 62.500 8.51 3 52.083 9.58 2
HIGH 1.221 - 255 0.977 - 255 0.610 - 255
LOW 312.500 - 0 250.000 - 0 156.250 - 0
BAUD
RATE
(K)
FOSC = 4 MHz FOSC = 3.6864 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal) KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3 0.300 0 207 0.301 0.33 185
1.2 1.202 0.17 51 1.216 1.33 46
2.4 2.404 0.17 25 2.432 1.33 22
9.6 8.929 6.99 6 9.322 2.90 5
19.2 20.833 8.51 2 18.643 2.90 2
28.8 31.250 8.51 1 - - -
33.6 - - - - - -
57.6 62.500 8.51 0 55.930 2.90 0
HIGH 0.244 - 255 0.218 - 255
LOW 62.500 - 0 55.930 - 0
TABLE 9-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
BAUD
RATE
(K)
FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz
KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR
SPBRG
value
(decimal)
0.3---------
1.2---------
2.4 - - - - - - 2.441 1.71 255
9.6 9.615 0.16 129 9.615 0.16 103 9.615 0.16 64
19.2 19.231 0.16 64 19.231 0.16 51 19.531 1.72 31
28.8 29.070 0.94 42 29.412 2.13 33 28.409 1.36 21
33.6 33.784 0.55 36 33.333 0.79 29 32.895 2.10 18
57.6 59.524 3.34 20 58.824 2.13 16 56.818 1.36 10
HIGH 4.883 - 255 3.906 - 255 2.441 - 255
LOW 1250.000 - 0 1000.000 0 625.000 - 0
BAUD
RATE
(K)
FOSC = 4 MHz FOSC = 3.6864 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal) KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3 - - - - - -
1.2 1.202 0.17 207 1.203 0.25 185
2.4 2.404 0.17 103 2.406 0.25 92
9.6 9.615 0.16 25 9.727 1.32 22
19.2 19.231 0.16 12 18.643 2.90 11
28.8 27.798 3.55 8 27.965 2.90 7
33.6 35.714 6.29 6 31.960 4.88 6
57.6 62.500 8.51 3 55.930 2.90 3
HIGH 0.977 - 255 0.874 - 255
LOW 250.000 - 0 273.722 - 0
1999 Microchip Technology Inc. Preliminary DS30569A-page 67
PIC16F870/871
9.2 USART Asynchronous Mode
In this mode, the USART uses standard non-return-to-
zero (NRZ) format (one sta rt bit, eigh t or nin e data b its,
and one stop bit). The most common data format is 8
bits. An on-chip, dedicated, 8-bit baud rate generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first. Th e USAR T’ s transmit ter and receive r are
functio nally in dependent , but use the s ame data fo rmat
and baud rate. The baud rate generator produces a
clock either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by
the hard ware , b ut can be implem ented in s oftw are (and
stored as the ninth data bit). Asynchronous mode is
stopped during SLEEP.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important elements:
• Baud Rate Ge nerat or
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
9.2.1 USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 9-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXRE G reg iste r tr ansfers t he data to th e TS R re giste r
(occurs in one TCY), the TXREG register is empty and
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
( PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE and cannot be cleared in soft-
wa re. It will reset onl y when ne w data is load ed into the
TXREG register . While flag bit TX IF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. Status bit TRMT
is a re ad onl y bit, w h ic h i s se t whe n the TSR r egi ste r i s
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR reg-
ister is empty.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure 9-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
tran sfer to the TXREG register w il l result in an i mm ed i-
ate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 9-3).
Clearing enable bit TXEN during a transmission will
cause the trans missio n to be aborted and will res et the
transmitter. As a result, the RC6/TX/CK pin will revert
to hi-impedance.
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can resul t in an immediate tran sf er of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
FIGURE 9-1: USA RT TR ANSMIT BLOCK DIAGRAM
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXI F is set when ena bl e bit TXEN
is set. TXIF is cleared by loading TXREG.
TXIF
TXIE
Interrupt
TXEN Baud Rate CLK
SPBRG
Baud Rate Generator TX9D
MSb LSb
Data Bus
TXREG register
TSR register
(8) 0
TX9
TRMT SPEN
RC6/TX/CK pin
Pin Buffer
and Control
8
• • •
PIC16F870/871
DS30569A-page 68 Preliminary 1999 Microchip Technology Inc.
Steps to follow when setting up an Asynchronous
Transmission:
1. In iti ali z e the SPBRG regis te r for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 9.1)
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit tr an sm is si on is d esi red , th en s et trans m it
bit TX9.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts trans-
mission).
FIGURE 9-2: ASYNCHRONOUS MASTER TRANSMISSION
FIGURE 9-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
TABLE 9-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
Resets
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG US ART Transmi t Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
Word 1 Stop Bit
Word 1
Transmit Shift Reg
Start Bit Bit 0 Bit 1 Bit 7/8
Write to TXRE G Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
TXIF b i t
(Transmit buffer
reg. empty flag)
TRMT bit
(Transmit shift
reg. empty flag)
Transmit Shift Reg.
Write to TXREG
BRG output
(shift clock)
RC6/TX/CK (pin)
TXIF bit
(interrupt reg. flag)
TRMT bit
(Transmit shift
reg. empty flag)
Word 1 Wor d 2
Word 1 Word 2
Start Bit Stop Bit Start Bit
Transmit Shift Reg.
Word 1 Word 2
Bit 0 Bit 1 Bit 7/8 Bit 0
Note: This timing diagram shows two consecutive transmissions.
1999 Microchip Technology Inc. Preliminary DS30569A-page 69
PIC16F870/871
9.2.2 USART ASYNCHRONOUS RECEIVER
The recei ver b loc k diagr am is sho wn in Figure 9-4. The
data is received on the RC7/RX/DT pin and drives the
data recovery block. The data recovery block is actually
a high speed shifter operating at x16 times the baud
rate, whereas the main receive serial shifter operates at
the bit rate or at FOSC.
Once asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver i s the receiv e (serial) shi ft reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transf erred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disab led by setting/clearing enab le bit RCIE (PIE1<5>).
Flag bit RCIF is a read only bit which is cleared by the
hardware. It is cleared when the RCREG register has
been read and is empty. The RCREG is a double buff-
ered register (i.e. it is a two deep FIFO). It is possible
for two bytes of data to be received and transferred to
the RCREG FIFO and a third byte to begin shifting to
the RSR register. On the detection of the STOP bit of
the third byte, if the RCREG register is still full, the ov er-
run error bit OERR (RCSTA<1>) will be set. The word
in the RSR will be lost. The RCREG register can be
read twice to retrieve the two bytes in the FIFO. Over-
run bit OERR has to be cleared in software. This is
done by resetting the receive logic (CREN is cleared
and then set). If bit OERR is set, transfers from the
RSR register to the RCREG register are inhibited, so it
is essential to clear error bit OERR if it is set. Framing
error bit FERR (RCSTA<2>) is set if a stop bit is
detected as c lea r. Bit FERR and the 9th rece ive bit are
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values, therefore it is essential for the user to read the
RCSTA register before reading RCREG register in
order not to l os e th e o ld FER R an d R X9 D information.
FIGURE 9-4: USART RECEVE BLOCK DIAGRAM
FIGURE 9-5: ASYNCHRONOUS RECEPTION
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR register
MSb LSb
RX9D RCREG Register FIFO
Interrupt RCIF
RCIE Data Bus
8
÷64
÷16
or Stop Start
(8) 710
RX9
• • •
Start
bit bit7/8
bit1bit0 bit7/8 bit0Stop
bit
Start
bit Start
bit
bit7/8 Stop
bit
RX (pin)
reg
Rcv buffer reg
Rcv shift
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
WORD 1
RCREG WORD 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffe r) is read after the third word,
causing the OERR (overrun) bit to be set.
PIC16F870/871
DS30569A-page 70 Preliminary 1999 Microchip Technology Inc.
Steps to follow when setting up an Asynchronous
Reception:
1. In iti ali z e the SPBRG regis te r for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 9.1).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, then set enable bit
RCIE.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag bit RCIF wi ll b e se t whe n rec eption is com -
plete and an interrupt will be gene rated if e nab le
bit RCIE is set.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during rece ption.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
TABLE 9-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Addr e s s N a m e B it 7 B it 6 B it 5 Bi t 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on:
POR,
BOR
Value on
all other
Resets
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
1999 Microchip Technology Inc. Preliminary DS30569A-page 71
PIC16F870/871
9.2.3 SETTING UP 9-BIT MODE WITH ADDRESS
DETECT
Steps to follow when setting up an Asynchronous
Reception with Address Detect Enabled:
• Initialize the SPBRG register for the appropriate
baud r ate . If a high sp eed baud rate is des ired, set
bit BRGH.
• Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
• If interrupts are desired, then set enable bit RCIE.
• Set bit RX9 to enable 9-bit reception.
• Set ADDEN to enable address detect.
• Enable the reception by setting enable bit CREN.
• Flag bit RCIF will be set when reception is com-
plete, and an interrupt will be generated if enable
bit RCIE was set.
• Read the RCSTA register to get the ninth bit and
determine if any error occurred during reception.
• Read the 8-bit received data by reading the
RCREG register, to determine if the device is
being addressed.
• If any error occurred, clear the error by clearing
enable bit CREN.
• If the device has been addressed, clear the
ADDEN bit to allow data bytes and address bytes
to be read i nto the rece iv e buff er, and in terrupt the
CPU.
FIGURE 9-6: USART RECEIVE BLOC K DIA GRAM
x64 B aud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR register
MSb LSb
RX9D RCREG Register FIFO
Interrupt RCIF
RCIE Data Bus
8
÷ 64
÷ 16
or Stop Start
(8) 710
RX9
• • •
RX9
ADDEN
RX9
ADDEN
RSR<8>
Enable
Load of
Receive
Buffer
8
8
PIC16F870/871
DS30569A-page 72 Preliminary 1999 Microchip Technology Inc.
FIGURE 9-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
FIGURE 9-8: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
TABLE 9-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Valu e o n:
POR,
BOR
Value on
all other
Resets
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receiv e Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
Start
bit bit1bit0 bit8 bit0Stop
bit
Start
bit bit8 Stop
bit
RC7/RX/DT (pin)
Load RSR
Read
RCIF
WORD 1
RCREG
Bit8 = 0, Data Byte Bit8 = 1, Address Byte
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(receive buffer) because ADDEN = 1.
Start
bit bit1bit0 bit8 bit0Stop
bit
Start
bit bit8 Stop
bit
RC7/RX/DT (pin)
Load RSR
Read
RCIF
WORD 1
RCREG
Bit8 = 1, Address Byte Bit8 = 0, Data Byte
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(receive buffer) because ADDEN was not updated and still = 0.
1999 Microchip Technology Inc. Preliminary DS30569A-page 73
PIC16F870/871
9.3 USART Synchronous Master Mode
In Sync hronous Maste r mode, t he data i s transmitte d in
a half-duplex manne (i.e., transmission and reception
do not occur at the same time). Whe n transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines respectively. The
Master mode in dicates that th e proces sor tran smits th e
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
9.3.1 USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 9-6. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXRE G reg iste r tr ansfers t he data to th e TS R re giste r
(occurs in one Tcycle), the TXREG is empty and inter-
rupt bit TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
wa re. It will reset only when ne w data is l oaded into th e
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
available to the user.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The firs t data bit wi ll be shi fted out on the ne xt a v ailab le
rising edge of the clock on the CK line. Data out is sta-
ble around the falling edge of the synchronous clock
(Figure 9-9). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 9-10). This is advantageous when slow
baud ra tes are selected , s inc e th e BRG is kept in res et
when bits TXEN, CREN and SREN are clear. Setting
enable bit TXEN will start the BRG, creating a shift
clock immediately. Normally, when transmission is first
started, the TSR register is empty, so a transfer to the
TXREG register will result in an immediate transfer to
TSR resulting in an empty TXREG. Back-to-back trans-
fers are possible.
Clearing enable bit TXEN during a transmission will
cause th e trans miss ion to be ab orted and will reset the
tra nsmit ter. The DT and CK pi ns wi ll revert to hi-impe d-
ance. If either bit CREN or bit SREN is set during a
transmission, the transmission is aborted and the DT
pin reverts to a hi-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic, however, is not
reset, although i t is disconnected from the pins . In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SR EN is set (to interrupt an on-going transm ission
and rece ive a single w ord), then a fter the sin gle word i s
received, bit SREN will be cleared and the serial port
will revert back to transmitting, since bit TXEN is still
set. The DT line will immediately switch from hi-imped-
ance receive mode to transmit and start driving. To
avoid this, bit TXEN should be cleared.
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register . This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written bef ore writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 9.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
PIC16F870/871
DS30569A-page 74 Preliminary 1999 Microchip Technology Inc.
TABLE 9-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
FIGURE 9-9: SYNCHRONOUS TRANSMISSION
FIGURE 9-10: SYNCHRONOUS TRANSMIS SION (THROUGH TXEN)
Addr e s s Name Bit 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other Resets
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
bit 0 bit 1 bit 7
WORD 1
Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4 Q1Q2 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3 Q4
bit 2 bit 0 bit 1 bit 7
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
(Interrupt flag)
TRMT
TXEN bit ’1’ ’1’
Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words
WORD 2
TRMT bit
Write word1 Write word2
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit0 bit1 bit2 bit6 bit7
TXEN b it
1999 Microchip Technology Inc. Preliminary DS30569A-page 75
PIC16F870/871
9.3.2 USART SYNCHRONOUS MASTER
RECEPTION
Once synchronous mode is selected, reception is
enab led by setting either enable bit SREN (RCSTA<5>)
or enable bit CREN (RCSTA<4>). Data is sampled on
the RC7/RX/DT pin on the falling edge of the clock. If
enable bit SREN is set, then only a single word is
received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
CREN tak es prec edence . After cloc king the last bit, the
received data in the Receive Shift Register (RSR) is
transf erred to the RCREG register (if it is empty). When
the transfer is complete, interrupt flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disab led by setting/clearing enab le bit RCIE (PIE1<5>).
Flag bit RCIF is a read only bit, which is reset by the
hardw are. In this case, it i s reset when t he RCREG reg-
ister has been read an d is empty. The RCREG is a dou-
ble buffered register (i.e., it is a two deep FIFO). It is
possible f or tw o b yte s of data to be received and tr an s-
ferred to the RCREG FIFO and a third byte to begin
shifting into the RSR register . On the cloc king of the last
bit of the third byte, if the RCREG register is still full,
then overrun error bit OERR (RCSTA<1>) is set. The
word in the RSR will be lost. The RCREG register can
be read twice to retrieve the two bytes in the FIFO. Bit
OERR has to be cleared in software (by clearing bit
CREN). If bit OERR is set, transfers from the RSR to
the RCREG are inhibited, so it is essential to clear bit
OERR if it is set. The ninth receive bit is buffered the
same way as the receive data. Reading the RCREG
register w ill load bit RX9 D with a ne w val ue, there for e it
is essential for the user to read the RCSTA register
before reading RCREG in order not to lose the old
RX9D information.
Steps to follow when setting up a Synchronous Master
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate. (Section 9.1)
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
7. Interrupt flag bit RCIF will be set when re ception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during rece ption.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
TABLE 9-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
FIGURE 9-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other Resets
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG US ART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
CREN bit
RC7/RX/DT pin
RC6/TX/CK pin
Write to
bit SREN
SREN b i t
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRG = '0'.
Q3Q4Q1Q2 Q3Q4 Q1Q2 Q3Q4Q2 Q1Q2Q3 Q4Q1Q2Q3 Q4 Q1 Q2Q3 Q4Q1Q2Q3 Q4 Q1Q2 Q3Q4Q1Q2Q3 Q4 Q1Q2Q3 Q4
’0’
bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
’0’
Q1Q2Q3Q4
PIC16F870/871
DS30569A-page 76 Preliminary 1999 Microchip Technology Inc.
9.4 USART Synchronous Slave Mode
Synchro nous s la v e mo de dif f ers fro m the M aster mod e
in the fact that the shift clock is supplied externally at
the RC6/T X/CK pin (instead of being supplied internally
in master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
9.4.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the synchronous master and slave
modes are identical except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register .
c) Flag bit TXIF will not be set.
d) When th e first wo rd has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
Steps to follow when setting up a Synchronous Slave
Transmission:
1. Enable the synchronou s slav e se rial port b y set-
ting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, then set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
9.4.2 USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the synchronous master and slave
modes is identical, except in the case of the SLEEP
mode. Bit SREN is a “don't care” in slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enab le bit RCIE bit is set, the interrupt gener ated
will wake the chip from SLEEP. If the global interrupt is
enabled, the progr am w i ll branch to the interrupt vector
(0004h).
Steps to follow when setting up a Synchronous Slave
Reception:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
5. Flag bit RCIF wi ll b e se t whe n rec eption is com -
plete and an interrupt will be generated, if
enable bit RCIE was set.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during rece ption.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
1999 Microchip Technology Inc. Preliminary DS30569A-page 77
PIC16F870/871
TABLE 9-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
TABLE 9-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Valu e o n:
POR,
BOR
Value on all
other Resets
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
Address Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other Resets
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h S PB RG B aud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870, always maintain these bits clear.
PIC16F870/871
DS30569A-page 78 Preliminary 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. Preliminary DS30569A-page 79
PIC16F870/871
10.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has five
inputs f o r the PIC16 F870 and ei ght f or the PIC16 F871.
The analog input charges a sample and hold capacitor .
The output of the sample and hold capacitor is the
input into the converter. The converter then generates
a digital result of this analog level via successive
approximation. The A/D con version of the analog input
signal results in a c orresponding 10-bit digital number.
The A/D module has high and low voltage reference
input that is software selectable to some combination
of VDD, VSS, RA2 or RA3.
The A/D conv erter has a un ique f eature of b eing able to
oper ate while the devic e is in SLEEP mode. To operate
in sleep, the A/D clock must be derived from the A/D’s
internal RC oscillator.
The A/D module has four registers. These registers
are: • A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register0 (ADCON0)
• A/D Control Register1 (ADCON1)
The ADCON0 register, shown in Register 10-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 10-2, configures the func-
tions of the por t pins. The port pins can be configured
as analog inputs (RA3 can also be the voltage refer-
ence) or as digital I/O.
Addition al inf ormation on us ing the A/D mo dul e c an b e
found in the PICmicro™ Mid-Range MCU Family Ref-
erence Manual (DS33023).
REGISTER 10-1: ADCON0 REGISTER (ADDRESS: 1Fh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON R = Readable bit
W = Wr itable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from an RC oscillation)
bit 5-3: CHS2:CHS0: Analog Channel Select bits
000 = channel 0, (RA0/AN0)
001 = channel 1, (RA1/AN1)
010 = channel 2, (RA2/AN2)
011 = channel 3, (RA3/AN3)
100 = channel 4, (RA5/AN4)
101 = channel 5, (RE0/AN5)(1)
110 = channel 6, (RE1/AN6)(1)
111 = channel 7, (RE2/AN7)(1)
bit 2: GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conv ersion in progress (setting this bit starts the A/D conversion)
0 = A/D conv ersion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete)
bit 1: Unimplemented: Read as '0'
bit 0: ADON: A/D On bit
1 = A/D converter mod ule is operating
0 = A/D converter mod ule is shutoff and consumes no operating current
Note 1: These channels are not av ailable on the PIC16F870.
PIC16F870/871
DS30569A-page 80 Preliminary 1999 Microchip Technology Inc.
REGISTER 10-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: ADFM: A/D Result format select
1 = Right Justified. 6 most significant bits of ADRESH are read as ‘0’.
0 = Left Justified. 6 least significant bits of ADRESL are read as ‘0’.
bit 6-4: Unimplemented: Read as ’0’
bit 3-0: PCFG3:PCFG0: A/D Port Configuration Control bits
A = Analog input
D = Digital I/O
Note 1: These channels are not available on the PIC16F870.
2: This column indicates the number of analog channels available as A/D inputs and the numer of analog channels
used as voltage refer ence inputs.
PCFG3:
PCFG0 AN7(1)
RE2 AN6(1)
RE1 AN5(1)
RE0 AN4
RA5 AN3
RA3 AN2
RA2 AN1
RA1 AN0
RA0 VREF+VREF-CHAN /
Refs(2)
0000 AAAAAAAAVDD VSS 8/0
0001 AAAAV
REF+AAARA3VSS 7/1
0010 DDDA A AAAV
DD VSS 5/0
0011 DDDAV
REF+AAARA3VSS 4/1
0100 DDDDADAAV
DD VSS 3/0
0101 DDDDV
REF+D A A RA3VSS 2/1
011x DDDDDDDDV
DD VSS 0/0
1000 AAAAV
REF+VREF-A A RA3RA2 6/2
1001 DDAAAAAAV
DD VSS 6/0
1010 DDAAV
REF+AAARA3VSS 5/1
1011 DDAAV
REF+VREF-A A RA3RA2 4/2
1100 DDDAV
REF+VREF-A A RA3RA2 3/2
1101 DDDDV
REF+VREF-A A RA3RA2 2/2
1110 DDDDDDDAV
DD VSS 1/0
1111 DDDDV
REF+VREF-D A RA3RA2 1/2
1999 Microchip Technology Inc. Preliminary DS30569A-page 81
PIC16F870/871
The ADRESH:ADRESL registers contain the 10-bit
result of th e A/D conversion. When the A/D co nv ersion
is complete, the result is loaded into this A/D result reg-
ister pair, the GO/DONE bit (ADCON0<2>) is cleared
and the A/D interrupt flag bi t ADIF is set. The b loc k dia-
gram of the A/D module is shown in Figure 10-1.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see Section 10.1. After this
acquisition time has elapsed, the A/D conversion can
be started. The following steps should be followed for
doing an A/D conversion:
1. Conf igure the A/D modul e:
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acqu is iti on tim e .
4. Start conversion:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result register pair
(ADRESH:ADRESL), clear bit ADIF if required.
7. For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
PIC16F870/871
DS30569A-page 82 Preliminary 1999 Microchip Technology Inc.
FIGURE 10-1: A/D BLOCK DIAGRAM
10.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 10-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impeda nc e varies o ver the device voltag e
(VDD), Figure 10-2. The maximum recommended
impedance for analog sources is 10 kΩ. As the
impedance is decreased, the acquisition time may be
decreased. After the analog input channel is selected
(changed), this acquisition must be done before the
conversion can be started.
To calculate the minimum acquisition time,
Equation 10-1 may be used. This equation assumes
that 1/2 LSb e rror is used (1024 step s f or the A/D). The
1/2 LS b er ror i s th e max imum erro r all o w ed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PICmicro™ Mid-Range Reference Manual
(DS33023).
(Input voltage)
VAIN
VREF+
(Reference
voltage)
VDD
PCFG3:PCFG0
CHS2:CHS0
RE2/AN7(1)
RE1/AN6(1)
RE0/AN5(1)
RA5/AN4
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
111
110
101
100
011
010
001
000
A/D
Converter
Note 1: Not available on PIC16F870.
VREF-
(Reference
voltage) VSS
PCFG3:PCFG0
1999 Microchip Technology Inc. Preliminary DS30569A-page 83
PIC16F870/871
EQUATION 10-1: ACQUISITION TIME
FIGURE 10-2: ANALOG INPUT MODEL
TACQ
TC
TACQ
=
=
=
=
=
=
=
=
Amplifier Settling Time +
Hold Capa cit or Ch argi ng Tim e +
Temper at ure Co eff ici en t
TAMP + TC + TCOFF
2µS + TC + [(Temperature -25°C)(0.05µS/°C)]
CHOLD (RIC + RSS + RS) In(1/2047)
- 120pF (1kΩ + 7kΩ + 10kΩ) In(0.0004885)
16.47µS
2µS + 16.47µS + [(50°C -25×C)(0.05µS/×C)
19.72µS
Note 1: The reference voltage (VREF) has no effect on the equation , since it cancels it self out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maxi mum reco mmended imp edance f or analog sourc es is 10 kΩ. This is requi red to meet the pin leak -
age specification.
4: After a conversion has completed, a 2.0TAD delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
CPIN
VA
RSANx
5 pF
VDD
VT = 0.6V
VT = 0.6V I LEAKAGE
RIC ≤ 1k
Sampling
Switch
SS RSS
CHOLD
= DAC capacitance
VSS
6V
Sampling Switch
5V
4V
3V
2V
5 6 7 8 91011
( kΩ )
VDD
= 120 pF
± 500 nA
Legend CPIN
VT
I LEAKAGE
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
v arious junctions
PIC16F870/871
DS30569A-page 84 Preliminary 1999 Microchip Technology Inc.
10.2 Selecting the A/D Conversion Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires a minimum 12TAD per 10-bit
conversion. The source of the A/D conversion clock is
software selected. The four possible options for TAD
are: •2T
OSC
•8TOSC
•32TOSC
• Internal RC oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) mus t be s ele cted t o ens ure a min imum TAD time
of 1.6 µs.
Table 10-1shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 10-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
10.3 Configuring Analog Port Pins
The ADCON1, and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bits
set (in put ). If the TR I S b it is c le ared ( outp ut), the di gita l
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
AD Clock Source (TAD) Maxim um De v ice Frequ enc y
Operation ADCS1:ADCS0 Max.
2TOSC 00 1.25 MHz
8TOSC 01 5 MHz
32TOSC 10 20 MHz
RC(1 , 2, 3) 11 Note 1
Note 1: The RC source has a typical TAD time of 4 µs but can vary between 2-6 µs.
2: When the device frequencies are greater than 1 MHz, the RC A/D conversion cloc k source is only recommended for sleep
operation.
3: For extended voltage devices (LC), please refer to the Electrical Specifications section.
Note 1: When reading the port register, any pin
configu red as an a nalog inpu t ch annel wil l
read as cleared (a low level). Pins config-
ured as dig ital input s wil l conver t an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
2: Analog levels on an y pin that is defined as
a digital input (including the AN7:AN0
pins), may cause the input buffer to con-
sume current that is out of the device
specifications.
1999 Microchip Technology Inc. Preliminary DS30569A-page 85
PIC16F870/871
10.4 A/D Conversions
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the par tially completed
A/D conversion sample. That is, the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is aborted, a 2TAD wait is
required before the next acquisition is started. After
this 2TAD wait, acquisition on the selected channel is
automatically started.
In Figure 10-3, after th e GO bit is set, the first time se g-
mant has a min imum of TCY and a maximu m of TAD.
FIGURE 10-3: A/D CONVERSION TAD CYCLES
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
TAD1TAD2TAD3TAD4TAD5 TAD6TAD7 TAD8TAD9
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
b9 b8 b7 b6 b5 b4 b3 b2
TAD10 TAD11
b1 b0
TCY to TAD
Conversion Starts
ADRES is loaded,
GO bit is cleared,
ADIF bit is set,
holding capacitor is connected to analog input.
PIC16F870/871
DS30569A-page 86 Preliminary 1999 Microchip Technology Inc.
10.4.1 A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits
wide. The A/D module gives the flexibility to left or right
justify the 10-bit result in the 16-bit result register. The
A/D Format Select bit (ADFM) controls this justifica-
tion. Figure 10-4 sho ws the oper ation of the A/D result
justification. The extra bits are loaded with ’0’s’. When
an A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general
purpose 8-bit registers.
10.5 A/D Operation During Sleep
The A/D mod ule can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
s wit ching no ise from the con v e rsion. Wh en the con ver-
sion is completed the GO/DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enab led, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
When the A/ D clo c k sou rce is a nother c loc k o ption (n ot
RC), a SLEEP instruction w ill cause the present con v er-
sion to b e aborted an d the A/D modul e to be turned off ,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
10.6 Effects of a Reset
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off, and any
con version is aborted.
The value that is in the ADRESH:ADRESL registers is
not modified for a Power-on Reset. The
ADRESH:ADRESL registers w ill contain unkno wn data
after a Power-on Reset.
FIGURE 10-4: A/D RESULT JUSTIFICATION
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To allow the con-
version to occur during SLEEP, ensure the
SLEEP instruction immediately follows the
instruction that sets the GO/DONE bit.
10-Bit Result
ADRESH ADRESL
0000 00
ADFM = 0
0
2 1 0 77
10-bit Result
ADRESH ADRESL
10-bit Result
0000 00
70 7 6 5 0
ADFM = 1
Right Justified Left Justified
1999 Microchip Technology Inc. Preliminary DS30569A-page 87
PIC16F870/871
TABLE 10-2: REGISTERS/BITS ASSOCIATED WITH A/D
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR,
BOR MCLR,
WDT
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 0000 00-0
9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
85h TRISA —— PORTA Data Direction Register --11 1111 --11 1111
05h PORTA —— PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
89h(1) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
09h(1) PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: These registers/bi ts are not a vailable on the PIC16F870.
PIC16F870/871
DS30569A-page 88 Preliminary 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. Preliminary DS30569A-page 89
PIC16F870/871
11.0 SPECIAL FEATURES OF THE
CPU
These d evic es hav e a hos t of fe atures inten ded to max-
imize system reliability, minimize cost through elimina-
tion of external components, provide power saving
oper at ing mod es and o ffer code protect ion . The se a r e:
• OSC Selection
• Reset
- Power-on Reset (POR)
- P o wer-up Tim er (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-Circuit Serial Programming
• Low Voltage In-Circuit Serial Programming
• In-Circuit Debugger
These devices have a watchdog timer, which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer neces sary delays on po wer-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chi p in rese t until th e crystal osci llator is stab le. Th e
other is the Pow er-u p Ti mer (PWRT), which provi des a
fixed delay of 72 ms (nominal) on power-up only. It is
designed t o k eep th e pa rt in reset w hile the po we r sup-
ply stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, Watchdog Timer Wake-up, or
through an interrupt. Sever al oscil lator opt ions are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
Additional inf ormation on speci al f eatures is av ailable in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
11.1 Configuration Bits
The con figur ati on bits c an be progr a mmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h -
3FFF h), whic h can be ac cessed on ly dur ing progra m-
ming.
PIC16F870/871
DS30569A-page 90 Preliminary 1999 Microchip Technology Inc.
REGISTER 11-1: CONFIGURATION WORD
CP1 CP0 DEBUG — WRT CPD LVP BODEN CP1 CP0 PWRTE WDTE F0SC1 F0SC0 Register: CONFIG
Address 2007h
bit13 bit0
bit 13-12:
bit 5-4: CP<1: 0 >: Flash Program Memory Code Protection bits (2)
11 = Code protection off
10 = Not supported
01 = Not supported
00 = Code protection on
bit 11: DEBUG: In-Circuit Debugger Mode
1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins.
0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger.
bit 10: Unimplemented: Read as ‘1’
bit 9: WRT: Flash Program Memory Write Enable
1 = Unprotected program memor y may be written to by EECON control
0 = Unprotected program memory may not be written to by EECON control
bit 8: CPD: Data EE Memory Code Protection
1 = Code protection off
0 = Data EEPROM memory cod e protected
bit 7: LVP: Low Voltage In-Circuit Serial Programming Enable bit
1 = RB3/PGM pin has PGM function, low voltage programming enabled
0 = RB3 is digital I/O, HV on MCLR must be used for programming
bit 6: BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3: PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE. Ensure
the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP<1:0> pairs have to be given the sam e value to enable the code protection scheme listed.
1999 Microchip Technology Inc. Preliminary DS30569A-page 91
PIC16F870/871
11.2 Oscillator Configurations
11.2.1 OSCILLATOR TYPES
The PIC16F870/871 can be operated in four different
oscill ato r mo de s . The use r c an p rog ram two co n fig ura-
tion bits (FOSC1 and FOSC0) to select one of these
four modes :
• LP Low Power Crystal
• XT Crystal/Resonator
• HS High Speed Crystal/Resonator
• RC Resistor/Capacitor
11.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 11-1). The
PIC16F870/871 oscillator design requires the use of a
par allel cut crystal. Use of a se ries cut c rystal may give
a frequency out of the crystal manufacturers specifica-
tions. When in XT, LP or HS modes, the device can
have an external clock source to drive the OSC1/
CLKIN pin (Figure 11-2).
FIGURE 11-1: CR YSTAL/CERAMI C
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
FIGURE 11-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
TABLE 11-1: CERAMIC RESONATORS
Note 1: See Table 11-1 and Table 11-2 for rec-
omme nded values of C1 and C2.
2: A series resistor (RS) may be required
for AT strip cut crystals.
3: RF varies with the crystal chosen.
C1(1)
C2(1)
XTAL
OSC2
OSC1
RF(3)
SLEEP
To
logic
PIC16F870/871
RS(2)
internal
OSC1
OSC2
Open
Clock from
ext. system PIC16F870/871
Ranges Tested:
Mode Freq OSC1 OSC2
XT 455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS 8.0 MHz
16.0 MHz 10 - 68 pF
10 - 22 pF 10 - 68 pF
10 - 22 pF
These values are for design guidance only. See
notes at bottom of page.
Resonators Used:
455 kHz Panasonic EFO-A455K04B ± 0.3%
2.0 MHz Murata Erie CSA2.00MG ± 0.5%
4.0 MHz Murata Erie CSA4.00MG ± 0.5%
8.0 MHz Murata Erie CSA8.00MT ± 0.5%
16.0 MHz Murata Erie CSA16.00MX ± 0.5%
All resonators used did not have built -in capacitors.
PIC16F870/871
DS30569A-page 92 Preliminary 1999 Microchip Technology Inc.
TABLE 11-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR 11.2.3 RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (REXT) and c apaci tor (CEXT) v alues , and th e ope rat-
ing temperature. In addition to this, the oscillator
frequency will var y from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
vari ation du e to to leranc e of exter nal R and C com po-
nents used. Figure 11-3 shows how the R/C combina-
tion is connected to the PIC16F870/871.
FIGURE 11-3: RC OSCILLATOR MODE
Osc Type Crystal
Freq Cap. Range
C1
Cap.
Range
C2
LP 32 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 200 kHz 47-68 pF 47-68 pF
1 MHz 15 pF 15 pF
4 MHz 15 pF 15 pF
HS 4 MHz 15 pF 15 pF
8 MHz 15-33 pF 15-33 pF
20 MHz 15-33 pF 15-33 pF
These values are for design guidance only.
See notes at bottom of page.
Crystals Used
32 kHz Epson C-001R32.768K-A ± 20 PPM
200 kHz STD XTL 200.000 kHz ± 20 PPM
1 MHz ECS ECS-10-13-1 ± 50 PPM
4 MHz ECS ECS-40-20-1 ± 50 PPM
8 MHz EPSON CA-301 8.000M-C ± 30 PPM
20 MHz EPSON CA-301 20.000M-C ± 30 PPM
Note 1: Higher cap ac ita nce increases th e stability
of osci llator but al so increases the start-up
time .
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external compo-
nents.
3: Rs may be required in HS mode, as well
as XT m o de, to avoid overdriv in g crystals
with low drive level specification.
4: When migrating from other PICmicro
devices, oscillator performance should be
verified.
OSC2/CLKOUT
Cext
Rext
PIC16F870/871
OSC1
FOSC/4
Internal
Clock
VDD
VSS
Recommended values: 3 kΩ ≤ Rext ≤ 100 kΩ
Cext > 20pF
1999 Microchip Technology Inc. Preliminary DS30569A-page 93
PIC16F870/871
11.3 Reset
The PIC16F870/871 differentiates between various
kinds of reset:
• Power-on Reset (POR)
•MCLR
reset during normal operation
•MCLR reset during SLEEP
• WDT Reset (during normal operation)
• WDT Wake-up (during SLEEP)
• Brown-out Reset (BOR)
Some registers are not affected in any reset condition.
Their statu s is unknown on POR and uncha nged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on the MCLR and
WDT Res et, on MCLR reset during SLEEP, and Brown-
out Reset (BOR). They are not affected by a WDT
Wake-up, which is viewed as the resumption of normal
oper ation. The T O and PD bits are s et or cleared diff er-
ently in different reset situations as indicated in
Table 11-4. These bits are used in software to deter-
mine the nature of the reset. See Table 11-6 for a full
description of reset states of all registers.
A simplifi ed b loc k diag ram of the on-ch ip res et circui t is
shown in Figure 11-4 .
These devices have a MCLR noise filter in the MCLR
reset path. The fil ter will detect and ignore small pulses.
It should be noted that a WDT Reset
does not drive
MCLR pin low.
FIGURE 11-4: SIMPLIFIED BLOCK DIAGRAM OF ON-C HIP RESET CIRCUIT
S
RQ
External
Reset
MCLR
VDD
OSC1
WDT
Module
VDD rise
detect
OST/PWRT
On-chip
RC OSC
WDT
Time-out
Power-on Reset
OST
10-bit Ripple counter
PWRT
Chip_Reset
10-bit Ripple counter
Reset
Enable OS T
Enable PWRT
SLEEP
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
Brown-out
Reset BODEN
(1)
PIC16F870/871
DS30569A-page 94 Preliminary 1999 Microchip Technology Inc.
11.4 Power-On Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, tie the MCLR pin directly
(or through a resistor) to VDD. This will eliminate exter-
nal R C co mp one nts u sua ll y n eeded to create a Power-
on Reset. A maximum rise time for VDD is specified.
See Electrical Specifications for details.
When the device starts normal operation (exits the
reset co ndi tion), device operati ng p ar am ete rs (voltage,
frequency, temperature,. ..) must be met to ensure oper-
ation. If these conditions are not met, the device must
be held in reset until the operating conditions are met.
Brown-out Reset may be used to meet the start-up con-
ditions. For additional information, refer to Application
Note, AN007, “Power-up Trouble Shooting”,
(DS00007).
11.5 Power-up Timer (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is ke pt in re set a s long as th e PWR T i s act ive. The
PWRT’s time delay allows VDD to rise to an acceptable
level. A configuration bit is provided to enable/disable
the PWRT.
The po wer-up tim e dela y will vary from chip to chip due
to VDD, temperature and process variation. See DC
parameters for details (TPWRT, parameter #33).
11.6 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWR T dela y i s ov er. This ens ures that t he crystal osci l-
lator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
11.7 Brown-Out Reset (BOR)
The conf iguration b it, BODEN, ca n enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(parameter #35, about 100µS), the brown-out situa-
tion will reset the device. If VDD falls below VBOR for
less than TBOR, a reset may not occur.
Once the brown-out occu rs, the d evice will remain in
brown-out reset until VDD rises above VBOR. The
power-up timer then keeps the device in reset for
TPWRT (parameter #33, about 72mS). If VDD should
fall below VBOR during TPWRT, the brown-out reset
process w ill restar t when VDD rises above VBOR with
the power-up timer reset. The power-up timer is
always enabled when the brown-out reset circuit is
enabled regardless of the state of the PWRT configu-
ration bit.
11.8 Time-out Sequence
On power-up, the time-out sequence is as follows: The
PWRT delay starts (if enabled) when a POR reset
occurs. Then OST starts counting 1024 oscillator
cycles when PWRT ends (LP, XT, HS). When the OST
ends, the device comes out of RESET.
If MCLR is kept low long enough, the time-outs will
expire. Bringing MCLR high wi ll begin exe cut ion im m e-
diately. This is useful for testing purposes or to synchro-
nize more than one PIC16CXX device operating in
parallel.
Table 11-5 shows the reset conditions for the STATUS,
PCON and PC registers, while Table 11-6 shows the
reset conditions for all the registers.
11.9 Power Control/Status Register
(PCON)
The Power Control/Status Register, PCON, has up to
two bits depending upon the device.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the use r and chec ke d on su bsequent resets t o see i f bit
BOR cleared, indicating a BOR occurred. The BOR bit
is a "don’t care" bit and is not nece ssarily pre dictab le if
the Brown-out Reset circuitry is disabled (by clearing
bit BODEN in the Configuration Word).
Bit1 is POR (P ower-on Reset Status bit). It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
1999 Microchip Technology Inc. Preliminary DS30569A-page 95
PIC16F870/871
TABLE 11-3: TIME-OUT IN VARIOUS SITUATIONS
TABLE 11-4: STATUS BITS AND THEIR SIGNIFICANCE
TABLE 11-5: RESET CONDITION FOR SPECIAL REGISTERS
Oscillator Configuration Power-up Brown-out Wake-up from
SLEEP
PWRTE = 0 P WRTE = 1
XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC
RC 72 ms —72 ms —
POR BOR TO PD
0x11Power-on Reset
0x0xIllegal, TO is set on POR
0xx0Illegal, PD is set on POR
1011Brown-out R eset
1101WDT Reset
1100WDT Wake-up
11uuMCLR Reset during normal operation
1110MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Condition Program
Counter STATUS
Register PCON
Register
Powe r-on Rese t 000h 0001 1xxx ---- --0x
MCLR Reset during normal operation 000h 000u uuuu ---- --uu
MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu
WDT Reset 000h 0000 1uuu ---- --uu
WDT Wake-u p PC + 1 uuu0 0uuu ---- --uu
Brown-out Reset 000h 0001 1uuu ---- --u0
Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu
Legend: u = unchanged, x = unkn own, - = unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
PIC16F870/871
DS30569A-page 96 Preliminary 1999 Microchip Technology Inc.
TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Devices Power-on Reset,
Brown-out Reset MCLR Resets
WDT Reset Wake-up via WDT or
Interrupt
W 870 871 xxxx xxxx uuuu uuuu uuuu uuuu
INDF 870 871 N/A N/A N/A
TMR0 870 871 xxxx xxxx uuuu uuuu uuuu uuuu
PCL 870 871 0000h 0000h PC + 1(2)
STATUS 870 871 0001 1xxx 000q quuu(3) uuuq quuu(3)
FSR 870 871 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 870 871 --0x 0000 --0u 0000 --uu uuuu
PORTB 870 871 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 870 871 xxxx xxxx uuuu uuuu uuuu uuuu
PORTD 870 871 xxxx xxxx uuuu uuuu uuuu uuuu
PORTE 870 871 ---- -xxx ---- -uuu ---- -uuu
PCLATH 870 871 ---0 0000 ---0 0000 ---u uuuu
INTCON 870 871 0000 000x 0000 000u uuuu uuuu(1)
PIR1 870 871 r000 -000 r000 -000 ruuu -uuu(1)
870 871 0000 -000 0000 -000 uuuu -uuu(1)
PIR2 870 871 ---0 ---- ---0 ---- ---u ----(1)
TMR1L 870 871 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 870 871 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 870 871 --00 0000 --uu uuuu --uu uuuu
TMR2 870 871 0000 0000 0000 0000 uuuu uuuu
T2CON 870 871 -000 0000 -000 0000 -uuu uuuu
CCPR1L 870 871 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H 870 871 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 870 871 --00 0000 --00 0000 --uu uuuu
RCSTA 870 871 0000 000x 0000 000x uuuu uuuu
TXREG 870 871 0000 0000 0000 0000 uuuu uuuu
RCREG 870 871 0000 0000 0000 0000 uuuu uuuu
ADRESH 870 871 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 870 871 0000 00-0 0000 00-0 uuuu uu-u
OPTION_REG 870 871 1111 1111 1111 1111 uuuu uuuu
TRISA 870 871 --11 1111 --11 1111 --uu uuuu
TRISB 870 871 1111 1111 1111 1111 uuuu uuuu
TRISC 870 871 1111 1111 1111 1111 uuuu uuuu
TRISD 870 871 1111 1111 1111 1111 uuuu uuuu
TRISE 870 871 0000 -111 0000 -111 uuuu -uuu
PIE1 870 871 r000 -000 r000 -000 ruuu -uuu
870 871 0000 0000 0000 0000 uuuu uuuu
PIE2 870 871 ---0 ---- ---0 ---- ---u ----
PCON 870 871 ---- --qq ---- --uu ---- --uu
PR2 870 871 1111 1111 1111 1111 1111 1111
TXSTA 870 871 0000 -010 0000 -010 uuuu -uuu
SPBRG 870 871 0000 0000 0000 0000 uuuu uuuu
ADRESL 870 871 xxxx xxxx uuuu uuuu uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depen ds
on condition, r = reserved maintain clear.
Note 1: One or more bits in INTCON, P IR1 and/or PIR2 will be a ffected (to caus e wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the inter-
rupt vector (0004h).
3: See Table 11-5 for reset value for specific condition.
1999 Microchip Technology Inc. Preliminary DS30569A-page 97
PIC16F870/871
FIGURE 11-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR N O T TI ED TO VDD): CASE 1
ADCON1 870 871 0--- 0000 0--- 0000 u--- uuuu
EEDATA 870 871 0--- 0000 0--- 0000 u--- uuuu
EEADR 870 871 xxxx xxxx uuuu uuuu uuuu uuuu
EEDATH 870 871 xxxx xxxx uuuu uuuu uuuu uuuu
EEADRH 870 871 xxxx xxxx uuuu uuuu uuuu uuuu
EECON1 870 871 x--- x000 u--- u000 u--- uuuu
EECON2 870 871 ---- ---- ---- ---- ---- ----
TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Devices Power-on Reset,
Brown-out Reset MCLR Resets
WDT Reset Wake-up via WDT or
Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = v a lu e depen ds
on condition, r = reserved maintain clear.
Note 1: One or more bits in INTCON, P IR1 and/or PIR2 will be a ffected (to caus e wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the inter-
rupt vector (0004h).
3: See Table 11-5 for reset value for specific condition.
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWR T TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWR T TIME-OUT
OST TIME-OU T
INTERNAL RESET
PIC16F870/871
DS30569A-page 98 Preliminary 1999 Microchip Technology Inc.
FIGURE 11-7: TIME-OUT SEQUENCE ON POWER -UP (MCLR N O T TIED TO VDD): CASE 2
FIGURE 11-8: SLOW RISE TIME (MC LR TIED TO VDD)
VDD
MCLR
INTERNAL POR
PWR T TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
0V 1V
5V
TPWRT
TOST
1999 Microchip Technology Inc. Preliminary DS30569A-page 99
PIC16F870/871
11.10 Interrupts
The PIC16F870/871 family has up to 11 sources of
interrupt. The interrupt control register (INTCON)
records individual interrupt requests in flag bits. It also
has individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared ) all in terrupts . W hen bit GIE is enab le d, and a n
interrupt’ s flag bit and mas k bit are set, the interrupt wil l
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enabl es interrupts.
The RB0/INT pin interrupt, the RB po rt change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the spe-
cial function regi sters, PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers, PIE1 and PIE2, and the peripheral
interrupt enab le bit i s co nta ine d i n speci al fu nction re g-
ister INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pu sh ed onto the sta ck and the PC is lo ade d
with 0004h. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive int errupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the s am e for one or two cy cl e instructions. I ndividua l
interrupt flag bits are set regardless of the status of
their corresponding mask bit or the GIE bit
FIGURE 11-9: INTERRUP T LOGIC
Note: Indiv idual interrupt flag bits are set, regard-
les s of the sta tus of the ir corre sponding
mask bit or the GIE bit.
PSPIF
PSPIE ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
T0IF
T0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake -up (If in SLEEP mode)
Interrupt to CPU
The following table shows w hich devices have which int errupts.
Device T0IF INTF RBIF PSPIF ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF EEIF
PIC16F870 Yes Yes Yes - Yes Yes Yes Yes Yes Yes Yes
PIC16F871 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
EEIF
EEIE
PIC16F870/871
DS30569A-page 100 Preliminary 1999 Microchip Technology Inc.
11.10.1 INT INTERRUPT
External interrupt on the RB0/INT pin is edge triggere d,
either rising, if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be clea red in s oftware i n the in terrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can w ake-up the proces sor from SLEE P, if bi t INTE wa s
set prior to goin g into SLEEP. The status of gl obal inter-
rupt enable bit GIE decides whether or not the proces-
sor b ra nch es t o t he in t errupt vector followin g wake-u p.
See Section 11.13 for details on SLEEP mode.
11.10.2 TMR0 INTERRUPT
An overf l ow (F F h → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 5.0)
11.10.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 3.2)
11.11 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on th e stack. Typicall y, users may wish to s ave ke y reg-
isters during an interrupt, (i.e., W register and STATUS
register). This will have to be implemented in software.
Since the upper 16 bytes of each bank are common in
the PIC16F870/871 devices, temporary holding regis-
ters W_TEMP, STATUS_TEMP and PCLATH_TEMP
should be placed in here. These 16 locations don’t
require banking and therefore, make it easier for con-
text save and restore. Example 11-1 can be used to
save and restore context for interrupts.
EXAMPLE 11-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF W_TEMP ;Copy W to TEMP register
SWAPF STATUS,W ;Swap status to be saved into W
CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3
MOVWF PCLATH_TEMP ;Save PCLATH into W
CLRF PCLATH ;Page zero, regardless of current page
:
:(ISR)
:
MOVF PCLATH_TEMP, W ;Restore PCLATH
MOVWF PCLATH ;Move W into PCLATH
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W
1999 Microchip Technology Inc. Preliminary DS30569A-page 101
PIC16F870/871
11.12 Wa tchdog Timer (WDT)
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external compo-
nents . T his RC os cilla tor is s epar ate from the R C osci l-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for ex ample, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (W atchdog Timer Reset). If the de vice is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer W ake-up). The T O bit in the STATUS register
will be cleared upon a Watchdog Timer time-out.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 11.1).
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
.
FIGURE 11-10: WATCHDOG TIMER BLOCK DIAGRAM
FIGURE 11-11: SUMMARY OF WATCHDOG TIMER REGISTERS
Note: The CLRWDT and SLEEP instructions clear
the WDT an d th e postsc al er, if as si gn ed to
the WDT, and pre vent it from timing out and
generating a device RESET condition.
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
presc al er ass ig nme nt is not changed.
Addr e s s Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2007h Config. bits (1) BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 11-1 for operation of these bits.
From TMR0 Clock Source
(Figure 5-1)
To TMR0 (Figure 5-1)
Postscaler
WDT Timer
WDT
Enable Bit
0
1M
U
X
PSA
8 - to - 1 MUX PS2:PS0
01
MUX PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
8
PIC16F870/871
DS30569A-page 102 Preliminary 1999 Microchip Technology Inc.
11.13 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
ke eps running , the PD bit (STATUS<3>) is cl ea red, th e
TO (STATUS<4>) bit is set, and the oscillator driver is
tur ned off. The I/O por ts maintain the status they had
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid s wi tc hin g c urre nts ca us ed by flo ati ng inputs. Th e
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
11.13.1 WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1. External reset input on MCLR pin.
2. Watchdog Timer wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change or some
Per ipheral Interrupts.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred and caused
wake-up.
The following peripheral interrupts can wake the device
from SLEEP:
1. PSP read or write.
2. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
3. CCP capture mode interrupt.
4. Special event trigger (Timer1 in asynchronous
mode using an external clock).
5. USART RX or TX (synchronous slave mode).
6. A/D conversion (when A/D clock source is RC).
7. EEPROM write operation completion
Other pe ripherals can not gener ate interrupts s ince dur-
ing SLEEP, no on-chip clocks are present.
When th e SLEEP inst ruction i s being e x ecuted, the ne xt
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corr esponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instr uct ion . If t he GIE bi t is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
ru pt ad dress (00 04h ). In ca ses wh ere the execution of
the instruction following SLEEP is not desirable, the
user shoul d have a NOP after the SLEEP instruction.
11.13.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and inte rrupt flag bit se t, one o f the f o llo wing w ill o ccur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruct ion will com -
plete as a NOP. Th erefore, the WDT and WDT
pos tscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleare d.
• If the interrupt occurs during or after the execu-
tion of a SLEEP instruction, the device wil l imme-
diately wake up from slee p. The SLEEP instruction
will be completely executed before the wake-up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instru ction executed , test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instr uc-
tion should be executed before a SLEEP instruction.
1999 Microchip Technology Inc. Preliminary DS30569A-page 103
PIC16F870/871
FIGURE 11-12: WAKE-UP FROM SLEEP THROUGH INTERRUPT
11.14 In-Circuit Debugger
When the DEBUG bit in the configuration word is pro-
grammed to a ’0’, the In-C ircuit Debugger funct ionali ty
is enab led. This function al lows sim ple debu gging func-
tions when used with MPLAB. When the microcontrol-
ler has th is feature enab l ed, som e o f t he res ourc es a re
not available for general use. Table 11-7 shows which
features are consumed by the background debugger.
TABLE 11-7: DEBUGGER RESOURCES
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, GND,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.
11.15 Pr ogram Verification/Code Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
11.16 ID Locations
F our memory locations (2000h - 200 3h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are read-
able and writable during program/verify. It is recom-
mended that only the 4 least significant bits of the ID
loc ation are used.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC PC+1 PC+2
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 1)
SLEEP
Processor in
SLEEP
Interrupt Latency
(Note 2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2 0004h 0005h
Dummy cycle
TOST(2)
PC+2
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine.
If GIE = ’0’, ex ec ution will continue in-line.
4: CLKOUT is not availabl e in these osc modes, but shown here for timing reference.
I/O pins RB6, RB7
Stack 1 level
Program Memory Address 0000h must be NOP
Last 100h words
Data Memory 0x070(0x0F0, 0x170, 0x1F0)
0x1 EB - 0x1EF
PIC16F870/871
DS30569A-page 104 Preliminary 1999 Microchip Technology Inc.
11.17 In-Circuit Serial Pr ogramming
PIC16F870/871 microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply d one with two l ine s for clock an d da ta and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
When using ICSP, the part must be supplied 4.5V to
5.5V if a bulk erase will be executed. This includes
reprogramming of the code protect both from an on-
state to off-state. For all other cases of ICSP, the par t
may be programmed at the normal operating voltages.
This mea ns c ali br ation v a lue s, unique us er IDs or us er
code can be reprogrammed or added.
For complete details of serial programming, please
refer to the In-Circuit Serial Programming (ICSP™)
Guide, (DS30277B).
11.18 Low Voltage ICSP Programming
The LVP bit of the configuration word enables low vo lt-
age ICSP programming. This mode allows the micro-
controller to be programmed via ICSP using a VDD
source in the operatin g vol tage range . This only me ans
that VPP does not have to be brought to VIHH, but can
instead be left at the normal operating voltage. In this
mode, the RB3/PGM pin is dedicated to the program-
ming function and ceases to be a general purpose I/O
pin. During programming, VDD is applied to the MCLR
pin. To enter progr am mi ng m od e , VDD m us t be applied
to the RB3/PGM provided the LVP bit is set. The LVP
bit defaults to on (‘1’) from the factor y.
If low-voltage programming mode is not used, the LVP
bit can b e progra mmed to a '0' an d RB3/PGM be comes
a digital I/O pin. Howe ver , the LVP bit ma y only be pro-
grammed when programming is entered with VIHH on
MCLR. The LVP bit can only be charged when using
high voltage on MCLR.
It should be noted, that once the LVP bit is programmed
to 0, only the high voltage programming mode is avail-
able and only high voltage programming mode can be
used to program the device.
When using low voltage ICSP, the part must be sup-
plied 4.5 V to 5 .5V if a b ulk erase w i ll b e execu ted. This
includes reprogramming of the code protect bits from
an on-state to off-state. For all other cases of low volt-
age ICSP, the part may be programmed at the normal
operating voltage. This means calibration values,
unique us er ID s or us er co de c an be repro gram med or
added.
Note 1: The high voltage programming mode is
alwa ys av ailable , regardless of the state of
the LVP bit, by apply ing VIHH to th e MCLR
pin.
2: While in low voltage ICSP mode, the RB3
pin can no longer be used as a general
purpose I/O pin.
1999 Microchip Technology Inc. Preliminary DS30569A-page 105
PIC16F870/871
12.0 INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
oper at ion of the instructio n. The PIC 16CXX ins tructio n
set summary in Table 12-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 12-1
shows the opcode field descriptions.
For byte-oriented instructions, ’f’ represents a file reg-
ister designator and ’d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The desti nation designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is
placed in the W registe r . If ’d ’ is one , the result i s placed
in the file register specified in the instruction.
For bit-oriented instructions, ’b’ represents a bit field
design ator whic h s el ec ts t he num ber of th e bit affected
by the operation, while ’f’ represents the number of the
file in which the bit is located.
For literal and control operations, ’k’ represents an
eigh t or e leven bi t constant or literal value.
TABLE 12-1: OPCODE FIELD
DESCRIPTIONS
The ins truction se t is hig hl y orthog on a l an d is group ed
into three basic categories:
•Byte-oriented operations
•Bit-oriented operations
•Literal and cont r ol operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In thi s case, t he execut ion takes t wo instruc tio n cycl es
with th e se co nd c y c le executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an osci llator frequ ency of 4 MHz, the normal instructio n
e xecution time i s 1 µs . If a con dition al test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
Table 12-2 lists the instructions recognized by the
MPASM assembler.
Figur e 12-1 shows the genera l fo rmats that th e instruc-
tions can have.
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 12-1: GENERAL FORMAT FOR
INSTRUCTIONS
A description of each instruction is available in the
PICmicro™ Mid-Range Reference Manual,
(DS33023).
Field Description
fRegister file address (0x00 to 0x7F)
WWorking regis ter (ac cum ul ator)
bBit address within an 8-bit file register
kLiteral field, constant data or label
xDon't care location (= 0 or 1)
The a ssembler will gener ate code w ith x = 0. It
is the recommended form of use for compati-
bility with all Microchip software tools.
dDestination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
PC Program Counter
TO Time-out bit
PD Power-down bit
Note: To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTION and TRIS instructions.
Byte-orient ed file register operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9 7 6 0
OPCODE b (BIT # ) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
PIC16F870/871
DS30569A-page 106 Preliminary 1999 Microchip Technology Inc.
TABLE 12-2: PIC16CXXX INSTRUCTION SET
Mnemonic,
Operands Description Cycles 14-Bit Opcode S tatus
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carr y
Rotate Right f through Carry
Subtract W from f
Swap nibb les in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Se t
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with liter al in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselv es. F or example, if the data latch is ’1’ f or a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is ex ec uted on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Addit ional inf ormation on the mid -range instruction set is available in the PICmicro™ Mid-Range MCU F amily
Reference Manual (DS33023).
1999 Microchip Technology Inc. Preliminary DS30569A-page 107
PIC16F870/871
12.1 Instruction Descriptions
ADDLW Add Literal and W
Syntax: [
label
] ADDLW k
Operands: 0 ≤ k ≤ 255
Operat ion: (W) + k → (W)
Status Affected: C, DC, Z
Description: The contents of the W register
are ad ded to the ei ght bit lite ral ’ k’
and the result is placed in the W
register.
ADDWF Add W and f
Syntax: [
label
] ADDWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) + (f) → (destination)
Status Affected: C, DC, Z
Description : Add the conte nts of the W regist er
with register ’f’. If ’d’ is 0, the result
is stored in the W register. If ’d’ is
1, the result is stored back in reg-
ister ’f’.
ANDLW AND Literal with W
Syntax: [
label
] ANDLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .AND. (k) → (W)
Status Affected: Z
Description: The contents of W register are
AND’ed with the eight bit literal
'k'. The result is placed in the W
register.
ANDWF AND W with f
Syntax: [
label
] ANDWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .AND. (f) → (destination)
Status Affected: Z
Description: AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W regi ster. If 'd ' is 1, th e resul t
is stored back in register 'f'.
BCF Bit Clear f
Syntax: [
label
] BCF f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: 0 → (f<b>)
Status Affected: None
Description: Bit 'b' in regi ster 'f' is cleared.
BSF Bit Set f
Syntax: [
label
] BSF f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: 1 → (f<b>)
Status Affected: None
Description: Bit 'b' in register 'f' is set.
PIC16F870/871
DS30569A-page 108 Preliminary 1999 Microchip Technology Inc.
BTFSS Bit Test f, Skip if Set
Syntax: [
label
] BTFSS f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Description: If bit ’b’ in register ’f’ is ’0’, the next
instructi on is executed.
If bit ’b’ is ’1’, then the next instruc-
tion is discarded and a NOP is exe-
cuted in stead making this a 2TCY
instruction.
BTFSC Bit Test, Skip if Clear
Syntax: [
label
] BTFSC f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: skip if (f<b>) = 0
Status Affected: None
Description: If bit ’b’ in register ’f’ is ’1’, the next
instruction is executed.
If bit ’b’, in register ’f’, is ’0’, the
next instruction is discarded, and
a NOP is e xe cuted ins tead, mak ing
this a 2TCY instruction.
CALL Call Subroutine
Syntax: [
label
] CALL k
Operands: 0 ≤ k ≤ 2047
Operation: ( PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected: None
Description: Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven bit immedi-
ate addre ss i s loaded int o PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALL is
a two cycle in structio n.
CLRF Clear f
Syntax: [
label
] CLRF f
Operands: 0 ≤ f ≤ 127
Operat ion: 00 h → (f)
1 → Z
Status Affected: Z
Description: The contents of register ’f’ are
cleared and the Z bit is set.
CLRW Clear W
Syntax: [
label
] CLRW
Operands: None
Operation: 00h → (W)
1 → Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z)
is se t.
CLRWDT Clear Watchdog Timer
Syntax: [
label
] CLRWDT
Operands: None
Operation: 00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Status Affected: TO, PD
Description: CLRWDT instruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT. Status
bits TO and PD are set.
1999 Microchip Technology Inc. Preliminary DS30569A-page 109
PIC16F870/871
COMF Complement f
Syntax: [
label
] COMF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) → (destination)
Status Affected: Z
Description: The contents of register ’f’ are
complemented. If ’d’ is 0, the
result is stored in W. If ’d’ is 1, the
result is stored back in register ’f’.
DECF Decrement f
Syntax: [
label
] DECF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - 1 → (destination)
Status Affected: Z
Description: Decrement register ’f’. If ’d’ is 0,
the result is stored in the W regis-
ter. If ’d’ is 1, the result is stored
back in register ’f’.
DECFSZ Decrement f, Skip if 0
Syntax: [
label
] DECFSZ f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation : (f) - 1 → (destination);
skip if result = 0
Status Affected: None
Description: The contents of register ’f’ are
decremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
then a NOP is executed instead
making it a 2TCY instruction.
GOTO Unconditional Branch
Syntax: [
label
] GOTO k
Operands: 0 ≤ k ≤ 2047
Operation: k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Status Affected: None
Description: GOTO is an unconditional branch.
The eleven bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a two
cycle instruction.
INCF Increment f
Syntax: [
label
] INCF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) + 1 → (destination)
Status Affected: Z
Description: The contents of register ’f’ are
incremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
INCFSZ Increment f, Skip if 0
Syntax: [
label
] INCFSZ f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operat ion: (f) + 1 → (destination),
skip if result = 0
Status Affected: None
Description: The contents of register ’f’ are
incremen ted. If ’ d’ is 0, th e result is
placed in the W register. If ’d’ is 1,
the result is placed back in regis-
ter ’f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0, a
NOP is executed instead making it
a 2TCY instruction.
PIC16F870/871
DS30569A-page 110 Preliminary 1999 Microchip Technology Inc.
IORLW Inclusive OR Literal with W
Syntax: [
label
] IORLW k
Operands: 0 ≤ k ≤ 255
Operat ion: (W) .OR. k → (W)
Status Affected: Z
Desc ription: The co ntents of the W register a re
OR’ed with the eight bit literal 'k'.
The result is placed in the W reg-
ister.
IORWF Inclusive OR W with f
Syntax: [
label
] IORWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .OR. (f) → (destination)
Status Affected: Z
Description: Inclusive OR the W register with
register 'f'. If 'd' is 0 the result is
placed in the W register. If 'd' is 1
the resu lt is pla ce d back in regis-
ter 'f'.
MOVF Move f
Syntax: [
label
] MOVF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) → (destinati on )
Status Affected: Z
Description: The contents of register f are
mov ed to a destination dependant
upon the status of d. If d = 0, des-
tination is W register. If d = 1, the
destinat ion is f ile registe r f itself . d
= 1 is useful to test a file register
since status flag Z is affected.
MOVLW Move Literal to W
Syntax: [
label
] MOVLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W)
Status Affected: None
Description: The eight bit literal 'k' is loaded
into W register. The don’t cares
will assemble as 0’s.
MOVWF Move W to f
Syntax: [
label
] MOVWF f
Operands: 0 ≤ f ≤ 127
Operat ion: (W) → (f)
Status Affected: None
Description: Mov e da ta from W reg ister to re g-
ister 'f'.
NOP No Operation
Syntax: [
label
] NOP
Operands: None
Operation: No operation
Status Affected: None
Description: No operation.
1999 Microchip Technology Inc. Preliminary DS30569A-page 111
PIC16F870/871
RETFIE Return from Interrupt
Syntax: [
label
] RETFIE
Operands: None
Operation: TOS → PC,
1 → GIE
Status Affected: None
RETLW Return with Literal in W
Syntax: [
label
] RETLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W);
TOS → PC
Status Affected: None
Description: The W register is loaded with the
eight bit literal ’k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two cycle instruction.
RETURN Return from Subroutine
Syntax: [
label
] RETURN
Operands: None
Operation: T OS → PC
Status Affected: None
Description: Return from subrout ine. The stac k
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two cycle
instruction.
RLF Rotate Left f through Carry
Syntax: [
label
] RLF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ’f’ are
rotated one bit to the left through
the Carry Flag. If ’d’ is 0, the
result is placed in the W register.
If ’ d’ is 1, the result is s tored ba c k
in register ’f’.
RRF Rotate Right f through Carry
Syntax: [
label
] RRF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ’f’ are
rotated one bit to the right through
the Carry Flag. If ’ d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
SLEEP
Syntax: [
label
]SLEEP
Operands: None
Operation: 00h → WDT,
0 → WDT prescaler,
1 → TO,
0 → PD
Status Affected: TO, PD
Description: The pow er-down statu s bit, PD is
cleared. Time-out status bi t, TO
is set. Watchdog Timer and its
prescaler are cleare d.
The proc essor is put i nto SLEEP
mode wi th the oscillator stopped.
Register fC
Register fC
PIC16F870/871
DS30569A-page 112 Preliminary 1999 Microchip Technology Inc.
SUBLW Subtract W from Literal
Syntax: [
label
]SUBLW k
Operands: 0 ≤ k ≤ 255
Operation: k - (W) → (W)
Status Affected: C, DC, Z
Description: The W regis ter is su btracted (2’s
complement method) from the
eight bit literal 'k'. The result is
placed i n the W regist er.
SUBWF Subtract W from f
Syntax: [
label
]SUBWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - (W) → (destination)
Status Affected: C, DC, Z
Description: Subtract (2’s complement method)
W register from register 'f'. If ' d' is 0,
the result is stored in the W regis-
ter. If 'd' is 1, the result is stored
back in register 'f'.
SWAPF Swap Nibbles in f
Syntax: [
label
] SWAPF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Status Affected: None
Description: The upper and lower nibbles of
register 'f' are exchanged. If 'd' is
0, the result is placed in W regis-
ter . If 'd' is 1, the result is pl aced in
register 'f'.
XORLW Exclusive OR Literal with W
Syntax: [
label
]XORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .XOR. k → (W)
Status Affected: Z
Description: The contents of the W register
are XOR’ed with the eight bit lit-
eral 'k'. The result is placed in
the W register.
XORWF Exclusive OR W with f
Syntax: [
label
] XORWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .XOR. (f) → (destination)
Status Affected: Z
Description: Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
1999 Microchip Technology Inc. Preliminary DS30569A-page 113
PIC16F870/871
13.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full r an ge of hardw are and softw are d e velopment to ols:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASM Assembler
- MPLAB-C17 and MPLAB-C18 C Compilers
- MPLINK/MPLIB Linker/Librarian
• Simulators
- MPLAB-SIM Software Simulator
•Emulators
- MPLAB-ICE Real-Time In-Circuit Emulator
- PICMASTER®/PICMASTER-CE In-Circui t
Emulator
-ICEPIC™
• In-Circuit Debugger
- MPLAB-ICD for PIC16F877
• Device P rogrammers
-PRO MATE
II Universal Programmer
- PICSTART Plus Entry-Level Prototype
Programmer
• Low-Cost Demonstration Boards
- SIMICE
- PICDEM-1
- PICDEM-2
- PICDEM-3
- PICDEM-17
- SEEVAL
-KEELOQ
13.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a Windows-based applica-
tion which contains:
• Multiple functionality
-editor
- simulator
- programmer (sold separately)
- emulator (sold separately)
• A full featured editor
• A project manager
• Customizable tool bar and key mapping
• A status bar
• On-line help
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
proje ct information)
• Debug using:
- source files
- absolute listing f ile
- object code
The ability to use MPLAB with Microchip’s simulator,
MPLAB-SIM, allo w s a con si ste nt pl atform and the abi l-
ity to easily switch from the cost-effective simulator to
the full featured emulator with minimal retraining.
13.2 MPASM Assembler
MPASM is a full f eatured univ ersal m acro assem bler f or
all PICmicro MCU’s. It can produce absolute code
directly in the form of HEX files for device program-
mers, or it can generate relocatable objects for
MPLINK.
MPASM has a command line interface and a Windows
shell and c an be u sed a s a stand alone appli catio n o n a
Windows 3.x or greater system. MPASM generates
relocatable object files, Intel standard HEX files, MAP
files to detail memory usage and symbol reference, an
absolute LST fil e which con tains so urce lines an d ge n-
erated machine code, and a COD file for MPLAB
debugging.
MPASM f ea ture s includ e:
• MPASM and MPLINK are integrated into MPLAB
projects.
• MPASM allows user defined macros to be created
for streamlined assembly.
• MPASM allows conditional assembly for multi pur-
pose source files.
• MPASM directi ve s allo w comple te control ov er th e
assem b l y proces s .
13.3 MPLAB- C17 and MPLAB- C18
C Compilers
The MPLAB-C 17 and MPLAB -C18 Code De v elop ment
Systems are complete ANSI ‘C’ compilers and inte-
grated development environments for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrol-
lers, respectively. These compilers provide powerful
integration capabilities and ease of use not found with
other co mpi le rs .
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
PIC16F870/871
DS30569A-page 114 Preliminary 1999 Microchip Technology Inc.
13.4 MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and
MPLAB-C17 and MPLAB-C18. It can link relocatable
objects from assembly or C source files along with pre-
compiled libraries using directives from a linker script.
MPLIB is a librarian for pre-compiled code to be used
with MPLINK. When a routine from a library is called
from another source file, only the modules that cont ains
that routine will be linked in with the application. This
allows l arg e li brarie s t o b e use d e ffi ci en tl y i n ma ny dif -
ferent applications. MPLIB manages the creation and
modification of library files.
MPLINK features include:
• MPLINK works with MPASM and MPLAB-C17
and MPLAB-C18.
• MPLINK allows all memory areas to be defined as
sections to provide link-time flexibility.
MPLIB features include:
• MPLIB makes linkin g ea sier becau se singl e li br ar-
ies can be included instead of many smaller files.
• MPLIB hel ps k ee p code m aintai nab le b y grou pin g
related modules together.
• MPLIB commands allow libraries to be created
and modules to be added, listed, replaced,
deleted, or extracted.
13.5 MPLAB-SIM Software Simulator
The MPLAB-SIM Software Simulator allows code
development in a PC host environment by simulating
the PICmicro series microcontrollers on an instruction
level. On any given in struct ion, th e data areas ca n be
examined or modified and stimuli can be applied from
a file or user-defined key press to any of the pins. The
e xecution can be perf ormed in singl e step, e xecute until
break, or trace mode.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Soft-
ware Simulator offers the flexibility to develop and
deb ug code outside of the laboratory enviro nment mak-
ing it an excellent multi-project software development
tool.
13.6 MPLAB-ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
inte nded to provi de t he pr oduc t developm ent en gin eer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). Software control of
MPLAB-ICE is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal architecture of the MPLAB-ICE
allows expansion to support new PICmicro microcon-
trollers.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced fea-
tures that are generally found on more expensive devel-
opment tools. The PC platf orm and Microsoft® Windows
3.x/95/98 en vironment w ere chosen to best mak e these
features available to you, the end user.
MPLAB-ICE 2000 is a full-featured emulator system
with enhanced trace, trigger, and data monitoring fea-
tures. Both systems use the same processor modules
and will operate across the full operating speed range
of the PICmicro MCU.
13.7 PICMASTER/PICMASTER CE
The PICMASTER system from Microchip Technolog y is
a full-featured, professional quality emulator system.
This flexible in-circuit emulator provides a high-quality,
universal platform for emulating Microchip 8-bit
PICmicro microcontrollers (MCUs). PICMASTER sys-
tems are sold worldwide, with a CE compliant model
available for European Union (EU) countries.
13.8 ICEPIC
ICEPIC is a lo w-cost in-circ uit emula tion solution f o r the
Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X, and PIC16CXXX fam ilies of 8-bit on e-time-
progr amma b le (OTP) microcontrollers. The modula r
system can suppo rt different subsets of PIC16C5X or
PIC16CXXX products through the use of
interchangeab le persona lity modules or daughter
boards. The em ulator is capable of emulatin g withou t
target application circuitry being present.
13.9 MPLAB-ICD In-Circuit Debugger
Microc hip’s In-C ircuit Deb ugger , MPLAB-ICD, is a pow -
erful, low-cost run-time development tool. This tool is
based on the flash PIC16F877 and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXXX family. MPLAB-ICD utilizes the
In-Circuit Debugging capability built into the
PIC16F8 7X. This f eature, alon g with Microchip’ s In-C ir-
cuit Serial Programming protocol, offers cost-effective
in-circuit flash programming and debugging from the
graphical user interface of the MPLAB Integrated
Development Environment. This enables a designer to
de velop and deb ug so urce c ode b y w atchi ng v ariab l es,
single-stepping and setting break points. Running at
full speed enables testing hardware in real-time. The
MPLAB-ICD is also a programmer for the flash
PIC16F87X family.
1999 Microchip Technology Inc. Preliminary DS30569A-page 115
PIC16F870/871
13.10 PRO MATE II Universal Programmer
The PRO MATE II Universal Programmer is a full-fea-
ture d programme r capable of operati ng in stand -alo ne
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for instructions and error messages,
keys to enter commands and a modular detachable
socket assembly to suppor t various package types. In
stand-al on e m ode the PRO MATE II can read , verify or
program PICmicro devices. It can also set code-protect
bits in this mode.
13.11 PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient.
PICSTA RT Plus su pp orts all PI Cmicr o devices wi th up
to 40 pins. Larger pin count devices such as the
PIC16C92X, and PIC17C76X may be supported with
an adapter socket. PICSTART Plus is CE compliant.
13.12 SIMICE Entry-Level
Hardware Simulator
SIMICE is an entry-level hardware development sys-
tem designed to operate in a PC-based environment
with Microchip’s simulator MPLAB-SIM. Both SIMICE
and MPLAB-SIM run under Microchip Technology’s
MPLAB Integrated Development Environment (IDE)
software. Specifically, SIMICE provides hardware sim-
ulation for Microchip’s PIC12C5XX, PIC12CE5 XX, an d
PIC16C5X families of PICmicro 8-bit microcontrollers.
SIMICE works in conjunction with MPLAB-SIM to pro-
vide non- real-time I/O port emulation. SIMICE enables
a developer to run simulator code for driving the target
system . In addition, the target system can provi de input
to the simulator code. This capability allows for simple
and interactive debugging without having to manually
generate MPLAB-SIM stimulus files. SIMICE is a valu-
able debugging tool for entry-level system develop-
ment.
13.13 PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and downl o a d t h e
firmware to the emulator for testing. Additional proto-
type area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
13.14 PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-Plus , and easil y test firmw are .
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional ha rdware and connectin g it to the mic rocontroll er
soc ket (s). Some of the f eatures include a RS-232 int er-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
usage of th e I2C bu s and separ ate hea ders f or connec -
tion to an LCD module and a keypad.
13.15 PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microc ont roll ers wi th a LCD Mo dul e . All the ne ces -
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PI CDE M-3 bo ar d, on a PRO MATE II pro gram-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firm-
ware. Addit ional protot ype a rea has been provided to
the us er for adding ha rdware and con necti ng it to the
microcontroller sock et(s). Some of the f eatures i nclude
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a k e y pad. Als o pro vide d on th e PICDEM -3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the w e ek . Th e P I CD EM-3 provides an add i-
tional RS-232 interface and Windows 3.1 software for
showing the demulti plex ed LCD signals on a PC . A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
PIC16F870/871
DS30569A-page 116 Preliminary 1999 Microchip Technology Inc.
13.16 PICDEM-17
The PICDEM-17 is an evaluation board that demon-
strates the capabilities of several Microchip microcon-
trollers, including PIC17C752, PIC17C756,
PIC17C762, and PIC17C766. All necessary hardware
is incl uded to run bas ic demo prog rams, which are su p-
plied on a 3.5-inch disk. A programmed sample is
includ ed, and the us er ma y eras e it an d prog ram it wi th
the other sample programs using the PRO MATE II or
PICSTART Plus device programmers and easily debug
and test the sample code . In additio n, PICDEM-17 su p-
ports down-loa ding of progr ams to and e xec uting out of
e xt ernal FLASH memory on board. The PICD EM -17 i s
also usab le with th e MPL AB-ICE or PI CMASTER em u-
lator, and all of the sample programs can be run and
modified using either emulator. Additionally, a gener-
ous prototype area is available for user hardware.
13.17 SEEV AL Evaluation and Programming
System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes ever ything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off analy sis a nd relia bility calc ulatio ns . The tota l kit ca n
significantly reduce time-to-market and result in an
optimized system.
13.18 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microc hips HCS Secure D ata Product s. The HC S ev al-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
1999 Microchip Technology Inc. Preliminary DS30569A-page 117
PIC16F870/871
TABLE 13-1: DEVELOPMENT TOOLS FROM MICR OCHIP
PIC12CXXX
PIC14000
PIC16C5X
PIC16C6X
PIC16CXXX
PIC16F62X
PIC16C7X
PIC16C7XX
PIC16C8X
PIC16F8XX
PIC16C9XX
PIC17C4X
PIC17C7XX
PIC18CXX2
24CXX/
25CXX/
93CXX
HCSXXX
MCRFXXX
MCP2510
Software Tools
MPLAB Integrated
Development Envi ronment
á
á
á
á
á
á
á
á
á
á
á
á
á
á
MPLAB C17 Compiler
á
á
MPLAB C18 Compiler
á
MPASM/MPLINK
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
Emulators
MPLAB-ICE
á
á
á
á
á
á
**
á
á
á
á
á
á
á
á
PICMASTER/PICMASTER-CE
á
á
á
á
á
á
á
á
á
á
á
ICEPIC Low-Cost
In-Circuit Emulator
á
á
á
á
á
á
á
á
Debugger
MPLAB-ICD In-Circuit
Debugger
á
*
á
*
á
Programmers
PICSTARTPlus
Low-Cost Universal Dev. Kit
á
á
á
á
á
á
**
á
á
á
á
á
á
á
á
PRO MATE II
Universal Programmer
á
á
á
á
á
á
**
á
á
á
á
á
á
á
á
á
á
Demo Boards and Eval Kits
SIMICE
á
á
PICDEM-1
á
á
á
†
á
á
PICDEM-2
á
†
á
†
á
PICDEM-3
á
PICDEM-14A
á
PICDEM-17
á
KEELOQ® E valua tion K it
á
KEELOQ Transp on de r Kit
á
microID™ Progra mmer’s Kit
á
125 kHz microID Developer’s Kit
á
125 kHz Anticollision microID
Developer’s Kit
á
13.56 MHz Anticollision microID
Developer’s Kit
á
MCP2510 CAN Developer’s Kit
á
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB-ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77
** Contact Microchip Technology Inc. for availability date.
†Development tool is available on select devices.
PIC16F870/871
DS30569A-page 118 Preliminary 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. Preliminary DS30569A-page 119
PIC16F870/871
14.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.................................................................................................................-55 to +125°C
Storage temperature.............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4)..........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V
Voltage on MCLR with respect to VSS (Note 2).............................................................................................0 to +13.25V
Voltage on RA4 with respect to Vss..................................................................................................................0 to +8.5V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current i nto VDD pin..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................± 20 mA
Maximu m out put current sunk by any I/O pin................. ..... ...... ............................ ............................ . .....................25 mA
Maximu m out put current so urced b y an y I/O pin ........................................................ .......................... ..................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3)....................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3) ..............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3)..................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3).............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
2: Volta ge spik es belo w VSS at the M CLR pin, induc ing currents greater than 80 mA, ma y cause latch-up . Thus ,
a series resistor of 50 -100Ω shoul d be used whe n applying a “lo w” le v el to the MCL R pin, rath er tha n pullin g
this pin directly to VSS.
3: PORTD and PORTE are not implemented on the 28-pin devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
de vic e. Th is is a s tress r ating o nly and functional oper atio n of the device at those or an y o ther cond itions abo v e t hose
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
PIC16F870/871
DS30569A-page 120 Preliminary 1999 Microchip Technology Inc.
FIGURE 14-1: PIC16FXXX VOLTA GE-FREQUENCY GRAPH
FIGURE 14-2: PIC16LFXXX VOLTAGE-FREQUENCY GRAPH
Frequency
Voltage
6.0 V
5.5 V
4.5 V
4.0 V
2.0 V
20 MHz
5.0 V
3.5 V
3.0 V
2.5 V
Frequency
Voltage
6.0 V
5.5 V
4.5 V
4.0 V
2.0 V
5.0 V
3.5 V
3.0 V
2.5 V
Equation 1: FMAX = (6.0 MHz/V) (VDDAPPMIN - 2.0 V) + 4 MHz; VDDAPPMIN = 2.0V - 3.0V
Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
4 MHz 10 MHz
Note 2: FMAX has a maximum frequency of 10MHz.
20 MHz
Equation 1Equation 2
Equation 2: FMAX = (10.0 MHz/V) (VDDAPPMIN - 3.0 V) + 10 MHz; VDDAPPMIN = 3.0V - 4.0V
1999 Microchip Technology Inc. Preliminary DS30569A-page 121
PIC16F870/871
14.1 DC Characteristics: PIC16F870/871 (Industrial)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C≤ TA ≤ +85°C for industrial
Param
No. Characteristic Sym Min Typ† Max Units Conditions
D001
D001A Su ppl y Voltage VDD 4.0
4.5
VBOR*
-
-
-
5.5
5.5
5.5
V
V
V
XT, RC and LP osc configuration
HS osc configuration
BOR enabled, Fmax = 14MHz (Note 7)
D002* RAM Data Retention
Volta ge (N ote 1) VDR -1.5-V
D003 VDD start voltage to
ensure in ternal Power-on
Reset signal
VPOR -VSS - V See section on Power-on Reset for details
D004* VDD rise rate to ensure
internal Power-on Reset
signal
SVDD 0.05 - - V/ms See section on Power-on Reset for details
D005 Brown-out Reset Voltage VBOR 3 .7 4. 0 4.35 V BODEN bit in configur ati on word enabled
D010
D013
Supply Current (Note 2,5) IDD -
-
1.6
7
4
15
mA
mA
XT, RC osc config urati on
FOSC = 4 MHz, VDD = 5.5V (Note 4)
HS osc configuration
FOSC = 20 MHz, VDD = 5.5V
D015* Brown-out Reset Current
(Not e 6) ∆IBOR -85200µA BOR enabled VDD = 5.0V
D020
D021
D021A
Power-down Current
(Not e 3,5) IPD -
-
-
10.5
1.5
1.5
42
16
19
µA
µA
µA
VDD = 4.0V, WDT enabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -0°C to +70°C
VDD = 4.0V, WDT disabled, -40°C to +85°C
D023* Brown-out Reset Current
(Not e 6) ∆IBOR -85200µA BOR enabled VDD = 5.0V
Legend: * T hese parameters are characterized but not tes ted.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 o sc il lat or (w he n e nabled) adds approxim ate ly 20 µA to the specific ati on . Th is v al ue is from c ha ra cte r-
ization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
PIC16F870/871
DS30569A-page 122 Preliminary 1999 Microchip Technology Inc.
14.2 DC Characteristics: PIC16LF870/871 (Commercial, Industrial)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Ope rating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Characteristic Sym Min Typ† Max Units Conditions
D001 S upply Voltage VDD 2.0 - 5.5 V LP, XT, RC osc configuration (DC - 4 MHz)
D002* RAM Da ta Retention
Voltage (Note 1) VDR -1.5- V
D003 VDD start voltage to
ensure i nternal Power-o n
Reset si gna l
VPOR -VSS - V See secti on on Power- on Re set for details
D004* VDD rise rate to ensure
internal Power-on Reset
signal
SVDD 0.05 - - V/ms See sectio n on Power-o n Rese t for details
D005 Brown-out Reset Voltage VBOR 3.7 4.0 4.35 V BODEN bit in configuration word enabled
D010
D010A
Supply Current (Note 2,5) IDD -
-
0.6
20
2.0
35
mA
µA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
LP osc configu ration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D015* Brown-out Reset Current
(Note 6) ∆IBOR -85200µA BOR enabled VDD = 5.0V
D020
D021
D021A
Power-down Current
(Note 3,5) IPD -
-
-
7.5
0.8
0.9
30
4.5
5
µA
µA
µA
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
D023* Brown-out Reset Current
(Note 6) ∆IBOR -85200µA BOR enabled VDD = 5.0V
Legend: * T hese parameters are characterized but not tes ted.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note1: This is the limit to which VDD can be lowered without losing RAM data.
2: The sup ply c urre nt i s m ai nl y a function of the op erating v ol tag e and fr equ enc y. Other factors such a s I/ O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
1999 Microchip Technology Inc. Preliminary DS30569A-page 123
PIC16F870/871
14.3 DC Characteristics: PIC16F870/871 (Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Operating voltage VDD range as described in DC spec Section 14.1 and
Section 14.2.
Param
No. Characteristic Sym Min Typ† Max Units Conditions
Input Low Voltage
I/O ports VIL
D030 with TTL buffer VSS - 0.15VDD V For entire VDD range
D030A VSS -0.8VV4.5V ≤ VDD ≤ 5.5V
D031 with Schmitt Trigger buffer VSS -0.2VDD V
D032 MCLR, OSC1 (in RC mode) VSS -0.2VDD V
D033 OSC1 (in XT, HS and LP) VSS -0.3VDD VNote1
Ports RC3 and RC 4
D034 with Schmitt Trigger buffer VSS -0.3VDD V For entire VDD range
D034A with SMBus -0.5 - 0.6 V for VDD = 4.5 to 5.5V
Input High Voltage
I/O ports VIH -
D040 with TTL buffer 2.0 - VDD V4.5V ≤ VDD ≤ 5.5V
D040A 0.25VDD
+ 0.8V -VDD V For entire VDD range
D041 with Schmitt Trigger buffer 0.8VDD -VDD V For entire VDD range
D042 MCLR 0.8VDD -VDD V
D042A OSC1 (XT, HS and LP) 0.7VDD -VDD VNote1
D043 OSC1 (in RC mode) 0.9VDD -VDD V
Ports RC3 and RC 4
D044 with Schmitt Trigger buffer 0.7VDD -VDD V For entire VDD range
D044A with SMBus 1.4 - 5.5 V for VDD = 4.5 to 5.5V
D070 PORTB weak pull-up current IPURB 50 250 400 µAVDD = 5V, VPIN = VSS
Input Leakage Current
(Notes 2, 3)
D060 I/O ports IIL --±1µAVss ≤ VPIN ≤ VDD, Pin at hi-imped-
ance
D061 MCLR, RA4/T0CKI - - ±5µAVss ≤ VPIN ≤ VDD
D063 OSC1 - - ±5µAVss ≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
Output Low Voltage
D080 I/O ports VOL --0.6VIOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
Output High Volta ge
D090 I/O ports (Note 3) VOH VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
D092 OSC2/CLKOUT (RC osc config) VDD - 0.7 - - V IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F870/871 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
PIC16F870/871
DS30569A-page 124 Preliminary 1999 Microchip Technology Inc.
D150* Open-Drain High Voltage VOD - - 8.5 V RA4 pin
--
Capacitive Loading Specs on
Output Pins
D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes when exter-
nal clock is used to drive OSC1.
D101
D102 All I/O pins and OSC2 (in RC
mode) SCL, SDA in I2C mode CIO
CB-
--
-50
400 pF
pF
Data EEPROM Memory
D120 Endurance ED100K - - E/W 25°C at 5V
D121 VDD for read /write VDRW Vmin - 5.5 V Using EECON to read/write
Vmin = min operating voltage
D122 Erase/write cycle time TDEW -48ms
Program FLASH Memory
D130 Endurance EP1000 - - E/W 25°C at 5V
D131 VDD for read VPR Vmin - 5.5 V Vmin = min operating voltage
D132a VDD for erase/write Vmin - 5.5 V using EECON to read/write,
Vmin = min operating voltage
D133 Erase/Write cycle time TPEW -48ms
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Operating voltage VDD range as described in DC spec Section 14.1 and
Section 14.2.
Param
No. Characteristic Sym Min Typ† Max Units Conditions
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F870/871 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
1999 Microchip Technology Inc. Preliminary DS30569A-page 125
PIC16F870/871
14.4 Timing Parameter Symbology
The timing parameter symbols have been created fol-
lowing one of the following formats:
FIGURE 14-3: LOAD CONDITIONS
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
TFFrequency TTime
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppercase letters and t heir meanings:
SFFall PPeriod
HHigh RRise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-impedance
I2C only
AA ou tput access High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO STOP condition
STA START condition
VDD/2
CL
RL
Pin Pin
VSS VSS
CL
RL= 464Ω
CL= 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on the PIC16F870.
Load condition 1 Load condition 2
PIC16F870/871
DS30569A-page 126 Preliminary 1999 Microchip Technology Inc.
FIGURE 14-4: EXTERNAL CLOCK TIMING
OSC1
CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
1
23344
TABLE 14-1: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
FOSC External CLKIN Frequency
(Note 1) DC — 4 MHz XT and RC osc mode
DC — 4 MHz HS osc mode (-04)
DC — 20 M Hz HS osc mode (-20)
DC — 200 kHz LP osc mode
Oscillator Frequency
(Note 1) DC — 4 MHz RC osc mode
0.1 — 4 MHz XT osc mode
4
5—
—20
200 MHz
kHz HS osc mode
LP osc mode
1TOSC External CLKIN Period
(Note 1) 250 — — ns XT and RC osc mode
250 — — ns HS osc mode (-04)
50 — — ns HS osc mode (-20)
5— —µs LP osc mode
Oscillator Period
(Note 1) 250 — — ns RC osc mode
250 — 10,000 ns XT osc mode
250 — 250 ns HS osc mode (-04)
50 — 250 ns HS osc mode (-20)
5— —µs LP osc mode
2TCY Instruction Cycle Time
(Note 1) 200 TCY DC ns TCY = 4/F OSC
3TosL,
TosH External Clock in (OSC1) High
or Low Time 100 — — ns XT oscillator
2.5 — — µs LP oscillator
15 — — ns HS oscillator
4TosR,
TosF External Clock in (OSC1) Rise
or Fall Time — — 25 ns XT oscillator
— — 50 ns LP oscillator
— — 15 ns HS oscillator
Legend: † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note1: Instruction c yc le pe riod (TCY) equals four time s the in put osc ill ato r ti me -bas e period. All s pe ci fied values ar e
based on ch ar acteriza tion d ata for that pa rticular o scil lator t ype u nder s tanda rd ope ratin g con dition s w ith th e
de vic e e x ec uting code . Excee ding the se specifi ed lim its ma y res ult in an un stab le os cilla tor oper ati on and/o r
higher than expected cu rrent consum ption . All d e vic es a re tes ted to op erate at "m in." v alue s with an external
clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is
"DC" (no clo ck) for all devices.
1999 Microchip Technology Inc. Preliminary DS30569A-page 127
PIC16F870/871
FIGURE 14-5: CLKOUT AND I/O TIMING
TABLE 14-2: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
10* TosH2ckL OSC1↑ to CLKOUT↓ — 75 200 ns Note 1
11* TosH2ckH OSC1↑ to CLKOUT↑ — 75 200 ns Note 1
12* Tc kR CLKOUT rise time — 35 100 ns Note 1
13* TckF CLKOUT f all time — 35 100 ns Note 1
14* Tc kL2ioV CLKOUT ↓ to Port out valid — — 0.5TCY + 20 ns Note 1
15* TioV2ckH Port in valid before CLKOUT ↑ T
OSC + 200 — — ns Note 1
16* TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns Note 1
17* TosH2ioV OSC1↑ (Q1 cycle) to
Port out valid — 100 255 ns
18* TosH2ioI OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
Standard (F) 100 — — ns
Extended (LF) 200 — — ns
19* TioV2osH Port input vali d to OSC1↑ (I/O in setup time) 0 — — ns
20* TioR Port output rise time Standard (F) — 10 40 ns
Extended (LF) — — 145 ns
21* TioF Port output fall time Standard (F) — 10 40 ns
Extended (LF) — — 145 ns
22††* Tinp INT pin high or low time TCY ——ns
23††* Trbp RB7:RB4 change INT high or low time TCY ——ns
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
Note: Refer to Figure 14-3 for load conditions.
OSC1
CLKOUT
I/O Pin
(input)
I/O Pin
(output)
Q4 Q1 Q2 Q3
10
13 14
17
20, 21
19 18
15
11
12 16
old value new v alue
PIC16F870/871
DS30569A-page 128 Preliminary 1999 Microchip Technology Inc.
FIGURE 14-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND P OWER-UP
TIMER TIMING
FIGURE 14-7: BROWN-OUT RESET TIMING
TABLE 14-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
30 TmcL MCLR Pulse Width (low) 2 ——
µsVDD = 5V, -40°C to +85°C
31* Twdt Watchdog Timer Time-out P eriod
(No Prescaler) 71833msV
DD = 5V, -40°C to +85°C
32 Tost Oscillation Start-up Timer Period — 1024 TOSC ——TOSC = OSC1 period
33* Tpwrt Power up Timer Period 28 72 132 ms VDD = 5V, -40°C to +85°C
34 TIOZ I/O Hi-impedance from MC LR Low
or Watchdog Timer Reset ——2.1
µs
35 TBOR Brown-out Reset pulse width 100 — — µsVDD ≤ VBOR (D005)
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O Pins
34
Note: Refer to Figure 14-3 for load conditions.
VDD VBOR
35
1999 Microchip Technology Inc. Preliminary DS30569A-page 129
PIC16F870/871
FIGURE 14-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 14-4: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
40* Tt0H T0CKI High Pulse Widt h No Prescaler 0.5TCY + 20 — — ns Must also meet
parameter 42
With Prescaler 10 — — ns
41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
parameter 42
With Prescaler 10 — — ns
42* Tt0P T0CKI Pe r i od No Prescaler TCY + 40 — — n s
With Prescaler Greater of:
20 or TCY + 40
N
— — ns N = prescale val ue
(2, 4, ..., 256)
45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
Standard(F)15——ns
Extended(LF)25——ns
Asynchronous Standard(F)30——ns
Extended(LF)50——ns
46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
Standard(F)15——ns
Extended(LF)25——ns
Asynchronous Standard(F)30——ns
Extended(LF)50——ns
47* Tt1P T1CKI input period Synchronous Standard(F) Greater of:
30 OR TCY + 40
N
— — ns N = prescale val ue
(1, 2, 4, 8)
Extended(LF) Greater of:
50 OR TCY + 40
N
N = presca le value
(1, 2, 4, 8)
Asynchronous Standard(F)60——ns
Extended(LF)100——ns
Ft1 Timer1 oscillator input frequency r ange
(oscillator enabled by setting bit T1OSCEN) DC — 200 kHz
48 TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc — 7Tos c —
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 14-3 for load conditions.
46
47
45
48
41
42
40
RA4/T0CKI
RC0/T1OSO/T1CKI
TMR0 o r
TMR1
PIC16F870/871
DS30569A-page 130 Preliminary 1999 Microchip Technology Inc.
FIGURE 14-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1)
TABLE 14-5: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1)
Param
No. Sym Characteristic Min Typ† Max Units Conditions
50* TccL CCP1 input
low time No Prescaler 0.5TCY + 20 ——ns
With Prescal er Standard(F)10 — — ns
Extended(LF)20——ns
51* TccH CCP1 input
high time No Prescaler 0.5TCY + 20 — — ns
With Prescal er Standard(F)10——ns
Extended(LF)20——ns
52* TccP CCP1 input period 3TCY + 40
N— — ns N = prescale
value (1,4 or 16)
53* TccR CCP1 output rise time Standard(F) — 10 25 ns
Extended(LF) — 25 50 ns
54* TccF CCP1 output fall time Standard(F) — 10 25 ns
Extended(LF) — 25 45 ns
* These parameters are character ized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated.
These parameters are for design guidance only and are not tested.
Note: Refer to Figure 14-3 for load conditions.
RC2/CCP1
(Capture Mode)
50 51
52
53 54
RC2/CCP1
(Compare or PWM Mode)
1999 Microchip Technology Inc. Preliminary DS30569A-page 131
PIC16F870/871
FIGURE 14-10: PARALLEL SLAVE PORT TIMING (PIC16F871 ONLY)
TABLE 14-6: PARALLEL SLAVE PORT REQUIREMENTS (PIC16F871 ONLY)
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
62 TdtV2wrH Data in valid before WR↑ or CS↑ (setup time) 20
25 —
——
—ns
ns Extended
Range Only
63* TwrH2dtI WR↑ or CS↑ to data–in invalid (hold time) Standard(F)20——ns
Extended(LF)35——ns
64 TrdL2dtV RD↓ and CS↓ to data–out valid —
——
—80
90 ns
ns Extended
Range Only
65 TrdH2dtI RD↑ or CS↓ to data–out invalid 10 — 30 ns
* Thes e parameters are character ized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 14-3 for load conditions.
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65
PIC16F870/871
DS30569A-page 132 Preliminary 1999 Microchip Technology Inc.
FIGURE 14-11: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 14-7: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 14-12: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 14-8: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
120 TckH2dtV SYN C XMIT (M AST E R &
SLAVE)
Cloc k high to data out valid
Standard(F)— — 80 ns
Extended(LF) — — 100 ns
121 Tckrf Cloc k out rise time and fall time
(Master Mode) Standard(F)——45ns
Extended(LF)——50ns
122 Td trf Data out rise time and fall time S tanda rd(F)——45ns
Extended(LF)——50ns
†: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
125 TdtV2ckL SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time) 15 ——ns
126 TckL2dtl Data hold after CK ↓ (DT hold time) 15 — — ns
†: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 14-3 for load conditions.
121 121
122
RC6/TX/CK
RC7/RX/DT
Pin
Pin
120
Note: Refer to Figure 14-3 for load conditions.
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
1999 Microchip Technology Inc. Preliminary DS30569A-page 133
PIC16F870/871
TABLE 14-9: PIC16F870/871 (INDUSTRIAL)
PIC16LF870/871 (INDUSTRIAL)
Param
No. Sym Characteristic Min Typ† Max Units Conditions
A01 NRResolution — — 10-bits bit VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A03 EIL Integral linearity error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A04 EDL Differential linearity error — — < ± 1 LS b VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A06 EOFF Offset error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A07 EGN Gain error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10 — Monotonicity(3) — guaranteed — — VSS ≤ VAIN ≤ VREF
A20 VREF Reference voltage (VREF+ - VREF-) 2.0V — VDD + 0.3 V Ab solute minimum electr ical
spec. to ensure 10-bit
accuracy.
A21 VREF+ Reference voltage High VDD - 2.5V VDD + 0.3V V M ust me et spec. A20
A22 VREF- Reference voltage low VSS - 0.3V VREF+ - 2.0V V M ust me et spec. A20
A25 VAIN Analog input voltage VSS - 0.3 — V REF + 0.3 V
A30 ZAIN Recommended impedance of
analog voltage source — — 10.0 kΩ
A40 IAD A/D conversion cur-
rent (VDD)Standard(F) — 220 — µA Ave rage current consump-
tion when A/D is on.
(Note 1)
Extended(LF)— 90 — µA
A50 IREF VREF input current (Note 2) 10
—
—
—
1000
10
µA
µA
During VAIN acquisition.
Based on diff erential of
VHOLD to VAIN to charge
CHOLD, see Section 10.1.
During A/D Conversion cycle
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes.
PIC16F870/871
DS30569A-page 134 Preliminary 1999 Microchip Technology Inc.
FIGURE 14-13: A/D CONVERSION TIMING
TABLE 14-10: A/D CONVERSION REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
130 TAD A/ D clock period Standard(F)1.6 ——
µsTOSC based, VREF ≥ 3.0V
Extended(LF)3.0——
µsT
OSC based, VREF ≥ 2.0V
Standard(F) 2.0 4.0 6.0 µs A/D RC Mode
Extended(LF) 3.0 6.0 9.0 µs A/D RC Mode
131 TCNV Conversion time (not including S/H time)
(Note 1) —12TAD
132 TACQ Acquisition time Note 2
10*
40
—
—
—
µs
µs The minimum time is the ampli-
fier settling time. This may be
used if the "new" input voltage
has not changed by more than 1
LSb (i.e., 20.0 mV @ 5.12V)
from the last sampled voltage
(as stated on CHOLD).
134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is
selected as RC , a time of TCY is
added before the A/D clock
star ts. This allows the SLEEP
instruction to be execut ed.
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§ This specification ensured by design.
Note 1: ADRES regist er may be read on the following TCY cycle.
2: See Section 10.1 for min conditions.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(TOSC/2)(1)
987 210
Note 1: If th e A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction t o be execut ed.
1 TCY
. . . . . .
1999 Microchip Technology Inc. Preliminary DS30569A-page 135
PIC16F870/871
15.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TA BLES
The graphs and tables provided in this section are for
design guidance and are not tested.
In some graphs or tables, the data presented are out-
side speci fied operating range (i.e., outside specifie d
VDD range). This is for information only and devices
are ensured to operate properly only within the speci-
fied rang e .
The data presented in this section is a statis tical sum-
mary of data collected on units from different lots over
a period of time and matrix samples. ’Typical’ repre-
sents the me an of the distribution at 25°C . ’ Max’ or ’m in’
represents (mean + 3σ) or (mean - 3σ) respectively,
where σ is st an dard deviati on, over the whol e t empe r-
ature range.
Graphs and Tables not available at this time.
PIC16F870/871
DS30569A-page 136 Preliminary 1999 Microchip Technology Inc.
NOTES:
1999 Microchip Technology Inc. Preliminary DS30569A-page 137
PIC16F870/871
16.0 PACKAGING INFORMATION
16.1 Package Marking Information
28-Lead SOIC
YYWWNNN
Example
PIC16F870-I/SO
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead PDIP (Skinny DIP) Example
PIC16F870-I/SP
9910SAA
9910SAA
Legend: MM...M Microchip part number information
XX...X Customer specific information*
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Microc hip part number cannot be marke d on one lin e, it w ill
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
28-Lead SSOP
YYWWNNN
Example
PIC16F870-I/SS
9910SAA
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16F870/871
DS30569A-page 138 Preliminary 1999 Microchip Technology Inc.
Package Marking Information (Cont’d)
XXXXXXXXXXXXXXXXXX
AABBCDE
40-Lead PDIP Example
PIC16F871-I/P
9912SAA
44-Lead TQFP
XXXXXXXXXX
AABBCDE
XXXXXXXXXX
Example
-I/PT
PIC16F871
44-Lead PLCC Example
PIC16F871
-I/L
9911HAT
9903SAT
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
XXXXXXXXXX
XXXXXXXXXX
1999 Microchip Technology Inc. Preliminary DS30569A-page 139
PIC16F870/871
28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
*Controlling Para meter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-150
Drawing No. C04-073
10501050Mold Draft Angle Bottom 10501050
α
Mold Draft Angle Top 0.380.320.25.015.013.010BLead Width 203.20101.600.00840
φ
F oot Angle 0.250.180.10.010.007.004
c
Lead Thickness 0.940.750.56.037.030.022LFoot Length 10.3410.2010.06.407.402.396DOverall Length 5.385.255.11.212.207.201E1Molded Package Width 8.107.857.59.319.309.299EOverall Width 0.250.150.05.010.006.002A1Standoff 1.831.731.63.072.068.064A2Molded Package Thickness 1.981.851.73.078.073.068AOverall Height 0.65.026
p
Pitch 2828
n
Number of Pin s MAXNOMMINMAXNOMMINDimen sion Li mit s MILLIMETERS*INCHESUnits
2
1
D
p
n
B
E1
E
L
β
c
φ
α
A2
A1
A
β
PIC16F870/871
DS30569A-page 140 Preliminary 1999 Microchip Technology Inc.
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
1510515105
β
Mold Draft Angle Bottom 1510515105
α
Mold Draft Angle Top 10.928.898.13.430.350.320eBOverall Row Spacing 0.560.480.41.022.019.016BLower Lead Width 1.651.331.02.065.053.040B1Upper Lead Width 0.380.290.20.015.012.008
c
Lead Thickness 3.433.303.18.135.130.125LTip to Seating Plane 35.1834.6734.161.3851.3651.345DOverall Length 7.497.246.99.295.285.275E1Molded Package Width 8.267.877.62.325.310.300EShoulder to Shou lder Width 0.38.015A1Base to Seating Plane 3.433.303.18.135.130.125
A2
Molded Package Thickness 4.063.813.56.160.150.140ATop to Seating Plane 2.54.100
p
Pitch 2828
n
Number of Pin s MAXNOMMINMAXNOMMINDimen si on Limi t s MILLIMETERSINCHES*Units
2
1
D
n
E1
c
eB
β
E
α
p
L
A2
B
B1
A
A1
Notes:
JEDEC Equivalent: MO-095
Drawing No. C04-070
*Controlling Parameter
Dimension D and E1 do n ot include mol d flash or protrusions. Mold fl ash or protrus ions shall no t exc eed
.010” (0.254mm) per side.
1999 Microchip Technology Inc. Preliminary DS30569A-page 141
PIC16F870/871
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
Foot Angle Top φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.330.280.23.013.011.009
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 18.0817.8717.65.712.704.695DOverall Length 7.597.497.32.299.295.288E1Molded Package Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff 2.392.312.24.094.091.088A2Molded Package Thickness 2.642.502.36.104.099.093AOver all Height 1.27.050
p
Pitch 2828
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
L
c
β
45°
h
φ
A2
α
A
A1
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254 mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
PIC16F870/871
DS30569A-page 142 Preliminary 1999 Microchip Technology Inc.
40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)
1510515105
β
Mold Draft Angle Bottom 1510515105
α
Mold Draft Angle Top 17.2716.5115.75.680.650.620eBOverall Row Spacing 0.560.460.36.022.018.014BLower Lead Width 1.781.270.76.070.050.030B1Upper Lea d Wid th 0.380.290.20.015.012.008
c
Lead Thickness 3.433.303.05.135.130.120LTip to Seating Plane 52.4552.2651.942.0652.0582.045DOverall Length 14.2213.8413.46.560.545.530E1Molded Package Width 15.8815.2415.11.625.600.595EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 4.063.813.56.160.150.140A2Molded Package Thickness 4.834.454.06.190.175.160ATop to Seating Plane 2.54.100
p
Pitch 4040
n
Number of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
A2
1
2
D
n
E1
c
βeB
E
α
p
L
B
B1
A
A1
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
1999 Microchip Technology Inc. Preliminary DS30569A-page 143
PIC16F870/871
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
*Controlling Parameter
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
1.140.890.64.045.035.025CHPin 1 Corner Chamfer
1.00.039
(F)
Footprint (Reference)
(F)
A
A1 A2
α
E
E1
#leads=n1
p
B
D1 D
n
1
2
φ
c
βL
Units INCHES MILLIMETERS*
Dimension Limits MIN NOM MAX MIN NOM MAX
Numb er of Pin s n44 44
Pitch p.031 0.80
Overall Height A .039 .043 .047 1.00 1.10 1.20
Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05
Standoff A1 .002 .004 .006 0.05 0.10 0.15
Foot Length L .018 .024 .030 0.45 0.60 0.75
Foot Angle φ03.5 7 03.5 7
Overall Width E .463 .472 .482 11.75 12.00 12.25
Overall Length D .463 .472 .482 11.75 12.00 12.25
Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10
Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10
Pins per Side n1 11 11
Lead Thickness c.004 .006 .008 0.09 0.15 0.20
Lead Width B .012 .0 15 .017 0.30 0.38 0.44
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
CH x 45°
PIC16F870/871
DS30569A-page 144 Preliminary 1999 Microchip Technology Inc.
44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
CH2 x 45°CH1 x 45°
10501050
β
Mold Draft Angle Bottom 10501050
α
Mold Draft Angle Top 0.530.510.33.021.020.013B0.810.740.66.032.029.026B1Upper Lead Width 0.330.270.20.013.011.008
c
Lead Thickness
1111n1Pi ns per Side
16.0015.7514.99.630.620.590D2Footprint Length 16.0015.7514.99.630.620.590E2Footpri nt Width 16.6616.5916.51.656.653.650D1Molded Package Length 16.6616.5916.51.656.653.650E1Molded Package Width 17.6517.5317.40.695.690.685DOverall Length 17.6517.5317.40.695.690.685EOverall Width 0.250.130.00.010.005.000CH2Corner Chamfer (others) 1.271.141.02.050.045.040CH1Corner Chamfer 1 0.860.740.61.034.029.024A3Side 1 Chamfer Height 0.51.020A1Standoff A2Molded Pac kage Thickness 4.574.394.19.180.173.165AOverall Height
1.27.050
p
Pitch 4444
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
β
A2
c
E2
2
D
D1
n
#leads=n1
E
E1
1
α
p
A3
A
35°
B1
B
D2
A1
.145 .153 .160 3.68 3.87 4.06
.028 .035 0.71 0.89
Lower Lead Width
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-048
PIC16F870/871
1999 Microchip Technology Inc. Preliminary DS30569A-page 145
INDEX
A
A/D ..................................................................................... 79
ADCON0 Register ......................................................79
ADCON1 Register ......................................................80
ADIF bit ......... ................... ....................... ...................81
Analog Input Model Block Diagram ............................83
Analog Port Pins ......................................7, 8, 9, 35, 36
Block Diag ram ........ .............. ................... ............... ....82
Configuring Analog Port Pins .....................................84
Configuring the Interrupt ............................................81
Configuring the Module ..............................................81
Conversio n Clo ck ................. ............... ........... ............84
Conversions ...............................................................85
Delays ........................................................................ 83
Effects of a Reset .......................................................86
GO/DONE bit .............................................................81
Internal Sampling Switch (Rss) Impedence ...............82
Operation During Sleep .............................................86
Sampling Requirements .......................... .... ....... .. .. ....82
Source Impedence ....... .... .... ......... .... .... .... ......... .... ....82
Time Dela ys ......... .................. ................... .................83
Absolute Maximum Ratings .............................................119
ADRES Register s ........................................................13, 79
Application Notes
AN552 (Implementing Wake-up on Key Strokes
Using PIC16CXXX) ....................................................29
AN556 (Table Reading Using PIC16CXX) .................24
Architecture
PIC16F870 Block Diagram ..........................................5
PIC16F871 Block Diagram ..........................................6
Assembler
MPASM Assembler ..................................................113
B
Banking, Data Memory ................................................11, 16
Block Diagrams
A/D ............................................................................. 82
Analog Input Model . ...................................................83
Capture ...................................................................... 58
Compare ....................................................................59
PWM ..........................................................................59
Timer0/WDT Prescaler ..............................................47
Timer2 ........................................................................55
USART Recei ve ......... .......... ............... ................... ....69
USART Transmit .................... ................... .................67
BOR.
See
Brown-out Reset
BRGH bit ............................................................................65
Brown-out Reset (BOR) ...................................89, 93, 95, 96
BOR Status (BO R Bit) ........ ....................... .................23
C
Capture/Compare/PWM
Capture
Block Diag ram ............... ................... .................58
CCP1CON Registe r .................. ............... ..........57
CCP1IF .............................................................. 58
Mode ..................................................................58
Prescaler ............................................................58
CCP Timer Resources ...............................................57
Compare
Block Diag ram ............... ................... .................59
Mode ..................................................................59
Software Interrupt Mode ....................................59
Special Event Trigger ........................................59
Special Trigger Output of CCP1 ........................ 59
Section ....................................................................... 57
Special Event Trigger and A/D Conversions ............. 59
Capture/Compare/PWM (CCP)
CCP1
RC2/CCP1 Pin ................................................. 7, 8
CCP2
RC1/T1OSI/CCP2 Pin ..................................... 7, 8
PWM Block Diagram ................................................. 59
PWM Mode ................ ............. .... .... ............. .... ...... .... 59
CCP1CON ......................................................................... 15
CCP1M0 bit ....................................................................... 57
CCP1M1 bit ....................................................................... 57
CCP1M2 bit ....................................................................... 57
CCP1M3 bit ....................................................................... 57
CCP1X bit .......................................................................... 57
CCP1Y bit .......................................................................... 57
CCP2CON ......................................................................... 15
CCPR1H Register .................................................. 13, 15, 57
CCPR1L Register ........................................................ 15, 57
CCPR2H Register .............................................................. 15
CCPR2L Register .............................................................. 15
Code Examples
Indirect Addressing .................................................... 24
Code Protection ......................................................... 89, 103
Computed GOTO ............................................................... 24
Configuration Bits .............................................................. 89
D
Data Memor y ............. ................... ................... .................. 1 1
Bank Select (RP1:RP0 Bits) ................................ 11, 16
General Purpose Registers ....................................... 11
Register File Map ...... ............... ................... .............. 12
Special Function Registers ........................................ 13
DC Characteristics ........................................................... 121
Development Support ...................................................... 113
Device Overview .................................................................. 5
Direct Add ressing ........ ................... ................... ................ 25
E
Electrical Characteristics ................................................. 119
Errata ................................................................................... 4
F
Firmware Instructions ...................................................... 105
FSR Register ................................................... 13, 14, 15, 24
I
I/O Ports ..... ............... ....................... ....................... .......... 27
ID Locations ............................................................... 89, 103
In-Circuit Serial Programming (ICSP) ........................ 89, 104
INDF .................................................................................. 15
INDF Register ........................................................ 13, 14, 24
Indirect Addressing ...................................................... 24, 25
FSR Register ............................................................. 11
Instruction Format ............................................................ 105
Instruction Set .................................................................. 105
ADDLW .................................................................... 107
ADDWF ................................................................... 107
ANDLW .................................................................... 107
ANDWF ................................................................... 107
BCF ......................................................................... 107
BSF .......................................................................... 107
BTFSC ..................................................................... 108
BTFSS ..................................................................... 108
CALL ........................................................................ 108
CLRF ....................................................................... 108
PIC16F870/871
DS30569A-page 146 Preliminary 1999 Microchip Technology Inc.
CLRW ......................................................................108
CLRWDT ..................................................................108
COMF ......................................................................109
DECF .......................................................................109
DECFSZ ...................................................................109
GOTO ......................................................................109
INCF .........................................................................109
INCFSZ ....................................................................109
IORLW .....................................................................110
IORWF .....................................................................110
MOVF .......................................................................110
MOVLW ...................................................................110
MOVWF ...................................................................110
NOP .........................................................................110
RETFIE ....................................................................111
RETLW ....................................................................111
RETURN ..................................................................111
RLF ..........................................................................111
RRF ..........................................................................111
SLEEP .....................................................................111
SUBLW ....................................................................112
SUBWF ....................................................................112
SWAPF ....................................................................112
XORLW .................................................................... 112
XORWF ....................................................................112
Summary Ta b l e ... ............... ................... ...................106
INTCON .............................................................................15
INTCON Register ...............................................................18
GIE Bi t ......... .............. ............................ .....................18
INTE Bit .......................... ....................... .....................18
INTF Bit ........... ....................... ................... .................18
PEIE Bi t ................................ ....................... ...............18
RBIE Bit .....................................................................18
RBIF Bit ................................................................18, 29
T0IE Bit ......... ................... ................... .......................18
T0IF Bit ......... ....................... ................... ...................18
Internal Sampling Switch (Rss) Impedence . ......................82
Interrupt Sources ..........................................................89, 99
Block Diag ram ........... ............... ................... ...............99
Interrupt on Change (RB7:RB4 ) ......................... .......29
RB0/INT Pin, External ......................................7, 8, 100
TMR0 Overflow ........................................................100
USART Receive/Transmit Complete .........................63
Interrupts, Context Saving During ....................................100
Interrupts, Enable Bits
Global Interrupt Enable (GIE Bit) .........................18, 99
Interrupt on Change (RB7:RB4) Enable
(RBIE Bit) ...........................................................18, 100
Peripheral Interrupt Enable (PEIE Bit) .......................18
RB0/INT Enable (INTE Bit) ........................................18
TMR0 Overflow Enable (T0IE Bit) ..............................18
Interrupts, Flag Bits
Interrupt on Change (RB7:RB4) Flag
(RBIF Bit) .....................................................18, 29, 100
RB0/INT Flag (INTF Bit) .............................................18
TMR0 Overflow Flag (T0IF Bit) ..........................18, 100
K
KeeLoq Evaluation and Programming Tools .................116
L
Loading of PC ............. .. .... ..... .. .. .. .. .. .. .... ..... .. .. .. .. .. .. .. ....... ..24
M
Master Clear (MCLR) ....................................................... 7, 8
MCLR Reset, Normal Operation .................... 93, 95, 96
MCLR Reset, SLEEP ..................................... 93, 95, 96
Memory Organization
Data Memor y ............. ................... ................... ..........11
Program Memory ....................................................... 11
MPLAB Integrated Development Environment Software . 113
O
OPCODE Field Desc r i p tions ..................... ............... ........ 105
OPTION ............................................................................. 15
OPTION_R EG Re g i ster ................. ................... ................. 1 7
INTEDG Bit ....... ................... ....................... ............... 17
PS2:PS0 Bits ............................................................. 17
PSA Bit ...................................................................... 17
RBPU Bit ...... ................... ....................... ................... 17
T0CS Bit .................................................................... 17
T0SE Bit ... ................... ................... ................... ........ 17
OSC1/CLKIN Pin ............................................................. 7, 8
OSC2/CLKOUT Pin .........................................................7, 8
Oscillato r Configurat ion . .............................................. 89, 91
HS ........................................................................91, 95
LP ........................................................................ 91, 95
RC ................................................................. 91, 92, 95
XT ........................................................................91, 95
Oscillator, WDT ................................................................ 101
Output of TMR2 ................................................................. 55
P
Packaging ........................................................................ 137
Paging, Program Memory ............................................ 11, 24
Parallel Slave Port (PSP) ......................................... 9, 33, 36
Block Diagram ...........................................................36
RE0/RD/AN5 Pin ............................................. 9, 35, 36
RE1/WR/AN6 Pin ............................................. 9, 35, 36
RE2/CS/AN7 Pin .............................................. 9, 35, 36
Read Waveforms ....................................................... 37
Select (PSPMODE Bit) .................................. 33, 34, 36
Write Waveforms ....................................................... 37
PCL Register ................................................... 13, 14, 15, 24
PCLATH Register ............................................ 13, 14, 15, 24
PCON Register ...................................................... 15, 23, 94
BOR Bit ...................................................................... 23
POR Bit ...................................................................... 23
PIC16F876 Pinout Description ............................................ 7
PICDEM-1 Low-Cost PICmicr o Demo Board .................. 115
PICDEM-2 Low-Cost PIC16CXX Demo Board ................ 115
PICDEM-3 Low-Cost PIC16CXX X Demo Board ............. 115
PICSTART Plus Entry Level Development System ...... 115
PIE1 Register ............................................................... 15, 19
PIE2 Register ............................................................... 15, 21
Pinout Descriptions
PIC16F870 .................................................................. 7
PIC16F871 .................................................................. 8
PIR1 Register .................................................................... 20
PIR2 Register .................................................................... 22
POP ................................................................................... 24
PORTA ......................................................................7, 8, 15
Analog Port Pins ...................................................... 7, 8
Initialization ................................................................ 27
PORTA Register ........................................................ 27
RA3,RA0 and RA5 Port Pins ..................................... 27
RA4/T0CKI Pin .................................................. 7, 8, 27
RA5/AN4 Pin ...........................................................7, 8
TRISA Register .......................................................... 27
PIC16F870/871
1999 Microchip Technology Inc. Preliminary DS30569A-page 147
PORTA Register ................................................................13
PORTB .......................................................................7, 8, 15
PORTB Register ........................................................29
Pull-up Enable (RBPU Bit) .............. ................... ........17
RB0/INT Edge Select (INTEDG Bit) . ..........................17
RB0/INT Pin, External ......................................7, 8, 100
RB3:RB0 Port Pins ....................................................29
RB7:RB4 Interrupt on Change .................................100
RB7:RB4 Interrupt on Change Enable
(RBIE Bit) ...........................................................18, 100
RB7:RB4 Interrupt on Change Flag
(RBIF Bit) .....................................................18, 29, 100
RB7:RB4 Port Pins ....................................................29
TRISB Register ..........................................................29
PORTB Register ................................................................13
PORTC ......................................................................7, 8, 15
Block Diag ram ........ .............. ................... ............... ....31
PORTC Register ........................................................31
RC0/T1OSO/T1CKI Pin ...........................................7, 8
RC1/T1OSI/CCP2 Pin ..............................................7, 8
RC2/CCP1 Pin .........................................................7, 8
RC3 Pin ....................................................................7, 8
RC4 Pin ....................................................................7, 8
RC5 Pin ....................................................................7, 8
RC6/TX/CK Pin ..................................................7, 8, 64
RC7/RX/DT Pin ............................................7, 8, 64, 65
TRISC Register ....................................................31, 63
PORTC Register ................................................................13
PORTD ....................................................................9, 15, 36
Block Diag ram ........ .............. ............... ................... ....33
Parallel Slave Port (PSP) Function ............................33
PORTD Register ........................................................33
TRISD Register ................ ............... ................... ........33
PORTD Register ................................................................13
PORTE ...........................................................................9, 15
Analog Port Pins ..............................................9, 35, 36
Block Diag ram ........ .............. ................... ............... ....34
Input Buffer Full Status (IBF Bit) ................................34
Input Buffer Overflow (IBOV Bit) ................................34
Output Buffer Full Status (OBF Bit) ............................34
PORTE Register ........................................................34
PSP Mode Select (PS PMODE Bit) ................33, 34, 36
RE0/RD/AN5 Pin ..............................................9, 35, 36
RE1/WR/AN6 Pin .............................................9, 35, 36
RE2/CS/AN7 Pin ..............................................9, 35, 36
TRISE Register ..........................................................34
PORTE Register ................................................................13
Postscaler, WDT
Assignment (PS A Bit) .......... ................... ...................17
Rate Select (PS2:PS0 Bits) .......................................17
Power-down Mode.
See
SLEEP
Power-on Reset (POR) ..............................89, 93, 94, 95, 96
Oscillator Start-up Timer (OST) ...........................89, 94
POR Status (PO R Bit) ........ ....................... .................23
Power Control (PCON) Register ................................94
Power-down (PD Bit) ...........................................16, 93
Power-up Timer (PWRT) .....................................89, 94
Time-o ut (TO Bit) .................................................16, 93
Time-out Sequence on Power-up ........................97, 98
PR2 .................................................................................... 15
PR2 Register ................................................................14, 55
Prescaler, Timer0
Assignment (PS A Bit) .......... ................... ...................17
Rate Select (PS2:PS0 Bits) .......................................17
PRO MA TE II Universal Programmer ...........................115
Product Identification System ..........................................193
Program Counter
Reset Conditions ......................................... .... .. .... .... 95
Program Memory ............................................................... 11
Interrupt Vector .......................................................... 11
Paging ................................................................. 11, 24
Program Memory Map ............................................... 11
Reset Vector .............................................................. 11
Program Verification ........................................................ 103
Programming Pin (VPP) ................................................... 7, 8
Programming, Device Instructions ................................... 105
PUSH ................................................................................. 24
R
RAM.
See
Data Memory
RCREG .............................................................................. 15
RCSTA Register .......................................................... 15, 64
CREN Bit ................. ................... ................... ............ 64
FERR Bit .................................................................... 64
OERR Bit ................................................................... 64
RX9 Bit ...................................................................... 64
RX9D Bit ........................... .................. ................... .... 64
SPEN Bit .............................................................. 63, 64
SREN Bit ........... ................... ................... .................. 64
Register File ............. ................... .............. ................... ...... 11
Register File Map ............................................................... 12
Registers
FSR Summary ........................................................... 15
INDF Summary .......................................................... 15
INTCON Summary .................................................... 15
OPTION Summary .................................................... 15
PCL Summary ........................................................... 15
PCLATH Summary .... ................... ................... .......... 15
PORTB Summary ...................................................... 15
STATUS Sum mary .... ................... ....................... ...... 15
TMR0 Summary ........................................................ 15
TRISB Summary ........................................................ 15
Reset ........................................................................... 89, 93
Block Diag ram ............. ............... ............... ................ 93
Reset Conditions for All Registers ............................. 96
Reset Conditions for PCON Register ........................ 95
Reset Conditions for Program Counter ..................... 95
Reset Conditions for STATUS Register .................... 95
S
SEEVAL Evaluation and Programming System ........... 116
SLEEP ................................................................. 89, 93, 102
Softwar e Simulat or ( MP L AB-SIM) ...... ............... .............. 114
SPBRG .............................................................................. 15
SPBRG Register ................................................................ 14
Special Features of the CPU ............................................. 89
Special Function Registers ................................................ 13
Special Function Register Summary ......................... 13
Speed, Operating ................................................................ 1
Stack .................................................................................. 24
Overflows ................................................................... 24
Underflow .................................................................. 24
STATUS Register ........................................................ 15, 16
C Bit ........................................................................... 16
DC Bit ........................................................................ 16
IRP Bit ......... ....................... ................... .................. .. 16
PD Bit .................................................................. 16, 93
RP1:RP0 Bits ....... ............... ................... .................... 16
TO Bit .................................................................. 16, 93
Z Bit ............... ....................... ................... .................. 16
PIC16F870/871
DS30569A-page 148 Preliminary 1999 Microchip Technology Inc.
T
T1CKPS0 bit ......................................................................51
T1CKPS1 bit ......................................................................51
T1CON ............................................................................... 15
T1CON Register ...........................................................15, 51
T1OSCEN bit .....................................................................51
T1SYNC bit ....................... ................... ................... ...........51
T2CKPS0 bit ......................................................................55
T2CKPS1 bit ......................................................................55
T2CON Register ...........................................................15, 55
TAD ..................................................................................... 84
Timer0
Clock Source Edge Select (T0SE Bit) ........................17
Clock Source Select (T0CS Bit) .................................17
Overflow Enable (T0IE Bit) ........................................18
Overflow Flag (T0IF Bit) .....................................18, 100
Overflow Inte r rup t .......... ................... .................. .....100
RA4/T0CKI Pin, External Clock ...............................7, 8
Timer1 ................................................................................ 51
RC0/T1OSO/T1CKI Pin ...........................................7, 8
RC1/T1OSI/CCP2 Pin ..............................................7, 8
Timers
Timer0
External Clock ....................................................48
Interrupt ..............................................................47
Prescaler ............................................................48
Prescaler Block Diagram ...................................47
Section ............................................................... 47
T0CKI .................................................................48
Timer1
Asynchronous Counter Mode ............................53
Capacitor Selection ..................................... .......53
Operation in Timer Mode ...................................52
Oscillator ............................................................ 53
Prescaler ............................................................53
Resetting of Timer1 Registers ...........................53
Resetting Timer1 using a CCP Trigger Output . .53
Synchronized Counter Mode .............................52
T1CON ...............................................................51
TMR1H ...............................................................53
TMR1L ...............................................................53
Timer2
Block Diag ram ........ .............. ................... ...........55
Postscaler ..........................................................55
Prescaler ............................................................55
T2CON ...............................................................55
Timing Diagrams
A/D Conversion ............ .............. ................... ...........134
Brown-out Reset ......................................................128
Capture/Compare/PWM ...........................................130
CLKOUT and I/O ......................................................127
Power-up Timer ................... ................... ............... ..128
Reset ........................................................................128
Start- u p Timer ....... ................... ................... .............128
Time-out Sequence on Power-up ........................97, 98
Timer0 ...................................................................... 129
Timer1 ...................................................................... 129
USART Asynch ronous Mas ter Transm ission .............68
USART Asynchronous Reception ..............................69
USART Synchronous Receive .................................132
USART Synchronous Reception ................................75
USART Synchronous Tran smiss ion ..................74, 132
USART, Asynchronous Reception .............................72
Wake-up from SLEEP via Interrupt ..........................103
Watchdog Timer ............... .. .... .. .. .... ....... .. .... .. .. .... .....128
TMR0 .................................................................................15
TMR0 Register ................................................................... 13
TMR1CS bit ................... ................... .................. ............... 51
TMR1H ..............................................................................15
TMR1H Register ................................................................ 13
TMR1L ............................................................................... 15
TMR1L Register ................................................................. 13
TMR1ON bit ....................................................................... 51
TMR2 ................................................................................. 15
TMR2 Register ................................................................... 13
TMR2ON bit ....................................................................... 55
TOUTPS0 bit ..................................................................... 55
TOUTPS1 bit ..................................................................... 55
TOUTPS2 bit ..................................................................... 55
TOUTPS3 bit ..................................................................... 55
TRISA ................................................................................ 15
TRISA Register .................................................................. 14
TRISB ................................................................................ 15
TRISB Register .................................................................. 14
TRISC ................................................................................ 15
TRISC Regist e r ......... ............... ............... ................... ........ 14
TRISD ................................................................................ 15
TRISD Regist e r ......... ............... ............... ................... ........ 14
TRISE ................................................................................ 15
TRISE Register ............................................................ 14, 34
IBF Bit .................. ....................... ........................... .... 34
IBOV Bit ..................................................................... 34
OBF Bit ................ ....................... ................... ............ 34
PSPMODE Bit ................................................ 33, 34, 36
TXREG ..............................................................................15
TXSTA ............................................................................... 15
TXSTA Register ................................................................. 63
BRGH Bit ................................................................... 63
CSRC Bit ....................... ....................... ................... .. 63
SYNC Bit ................... ................... .............. ............... 63
TRMT Bit ....................................................................63
TX9 Bit ....................................................................... 63
TX9D Bit .................................................................... 63
TXEN Bit .................. ....................... ....................... .... 63
U
Universal Synchronous Asynchronous Receiver
Transmitter (USART)
Asynchronous Receiver
Setting Up Reception ......................................... 71
Timing Dia g ram ......... ................... ............... ...... 72
USART ............................................................................... 63
Asynchronous Mode .................................................. 67
Receive Block Diagram ..................................... 71
Asynchronous Receiver ............................................. 69
Asynchronous Receptio n ........................................... 70
Asynchronous Tra nsmit ter ......................................... 67
Baud Rate Generator (BRG) ..................................... 65
Baud Rate Formula ........................................... 65
Baud Rates, Asynchronous Mode (B RG H=0) ... 6 6
High Baud Rate Select (BRGH Bit) ................... 63
Sampling ............................................................ 65
Clock Source Select (CSRC Bit) ................................ 63
Continuous Receive Enable (CREN Bit) .................... 64
Framing Error (FERR Bit) .......................................... 64
Mode Select (SYNC Bit) ............................................ 63
Overrun Error (OERR Bit) .......................................... 64
RC6/TX/CK Pin ........................................................ 7, 8
RC7/RX/DT Pin ........................................................ 7, 8
RCSTA Regist e r .............. ................... ................... .... 64
Receive Block Diagram ............................................. 69
Receive Data, 9th bit (RX9D Bit) ............................... 64
PIC16F870/871
1999 Microchip Technology Inc. Preliminary DS30569A-page 149
Receive Enable, 9-bit (RX9 Bit) .................................64
Serial Port Enable (SPEN Bit) ..............................63, 64
Single Receive Enable (SREN Bit) ............................64
Synchronous Master Mode ........................................73
Synchronous Master Reception .................................75
Synchronous Master Transmission ............................73
Synchronous Slave Mode ........................................ ..76
Transmit Block Diagram .............................................67
Transmit Data, 9th Bit (TX9D) ....................................63
Transmit Enable (TXEN Bit) .................. .... .. ....... .. .... ..63
Transmit Enable, Nine-bit (TX9 Bit) ...........................63
Transmit Shift Register Status (TRMT Bit) .................63
TXSTA Register ......................................................... 63
W
Wake-up from SLEEP ................................................89, 102
Interrupts ..............................................................95, 96
MCLR Reset ................ ................... ............... ............96
Timing Dia g r a m .............. ............... ................... ........103
WDT Reset .............. ................... .............. .................96
Watchdog Timer (WDT) .............................................89, 101
Block Diag ram ........ .............. ................... ............... ..101
Enable (WDTE Bit) ...................................................101
Programming Considerations ..................................101
RC Oscillator ............................................................101
Time-o u t Pe riod ................................ .......................101
WDT Reset, Normal Operation ......................93, 95, 96
WDT Reset, SLEEP .......................................93, 95, 96
WWW, On-Line Support ......................................................4
1999 Microchip Technology Inc. Preliminary DS30569A-page 151
PIC16F870/871
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The we b site is used b y Mic rochi p as a mean s to mak e
files and infor mation easily available to customers. To
vie w the site , the user must ha v e access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
•Device Errata
• Job Postings
• Micro chip C onsultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Sys-
tems, technical information and more
• Listing of seminars and events
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-786-7302 for the rest of the world.
Trademarks: The Microchip name, logo, PIC, PICmicro,
PICSTART, PICMASTE R, PRO MATE and MPLAB are regis-
tered trademarks of Microchip Technology Incorporated in
the U.S .A. and other countries.
Flex
ROM and
fuzzy
LAB are
trademarks and SQTP is a service mark of Microc hip in the
U.S.A.
All other trademarks mentioned herein are the property of
their respective companies.
991103
PIC16F870/871
DS30569A-page 152 Preliminary 1999 Microchip Technology Inc.
READER RESPONSE
It is our i ntention to provide you w ith the bes t d ocu me nta tion poss ible to ensure suc ce ssf ul us e of your Microchip pro d-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
To: Technical Publications Manager
RE: Reader Response Total Pages Sent
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (_____ _) ____ ___ __ - _____ ___ _
DS30569A
PIC16F870/871
PIC16F870/871
1999 Microchip Technology Inc. Preliminary DS30569A-page 153
PIC16F870/871 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
PART NO. -X /XX XXX
PatternPackageTemperature
Range
Device
Device PIC16F870, PIC16F870T ;VDD range 4.0V to 5.5V
PIC16F871, P IC16F871T ;VDD r ange 4.0V to 5.5V
PIC16LF870X, PIC16LF870T;VDD range 2.0V to 5.5V
PIC16LF871X, PIC16LF871T;VDD range 2.0V to 5.5V
F = Normal VDD limits
LP = Extended VDD limits
T = In Tape and Reel - SOIC, SSOP, TQFP and
PLCC packages only.
Temperature Rang e blank(3) = 0
°C to 70°C (Commercial)
I= -40
°C to +85°C (Industrial)
Package PQ = MQFP (Metric PQFP)
PT = TQFP (Thin Quad Flatpack)
SO = SOIC
SP = Skinny plastic dip
SS = SSOP
P=PDIP
L=PLCC
Pattern QTP, Code or Special Requirements
(blank otherwis e )
Examples:
a) PIC16F870-I/SP 301 = Industrial temp., PDIP
package, 20 MHz, normal VDD limits, QTP pat-
tern #301.
b) PIC16F871-I/PT = Industrial temp., TQFP
package, 20 MHz, Extended VDD limits.
c) PIC16F871-I/P = Industrial temp., PDIP pack-
age, 20 MHz, nor m al VDD limit s.
d) PIC16LF870-I/SS = Industrial temp., SSOP
package, DC - 20MHz , ext ended VDD limits.
Data Sheets
Products supported b y a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Cor porate Literature Center U.S. FAX: (480) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
PIC16F870/871
DS30569A-page 154 Preliminary 1999 Microchip Technology Inc.
NOTES:
PIC16F870/871
1999 Microchip Technology Inc. Preliminary DS30569A-page 155
NOTES:
2002 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is intended through sug gestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microc hip Technology Incorporated with respect
to the accuracy or use of such inf orm ation, or inf ringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
nology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexRO M, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code ho pp in g
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Note the following details of the code protection feature on PICmicro® MCUs.
•The PICmicro family meets the specifications contained in the Microchip Data Sheet.
•Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
•Microchip is willing to work with the customer who is concerned about the integrity of their code.
•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
•Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter , please contact the local sales office nearest to you.
2002 Microchip Technology Inc.
M
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