LTC4418 Dual Channel Prioritized PowerPath Controller FEATURES DESCRIPTION Selects Highest Priority Supply from Two Inputs nn Blocks Reverse and Cross Conduction Currents nn Wide Operating Voltage Range: 2.5V to 40V nn -42V Protection Against Reverse Connection nn 60V Tolerant V1, V2 Inputs nn Adjustable Input Validation Time nn Fast Switchover Minimizes Output Voltage Droop nn Low 26A Operating Current nn 1.5% Input Overvoltage/Undervoltage Protection nn Adjustable Overvoltage/Undervoltage Hysteresis nn Cascadable for Additional Input Supplies nn 20-Lead 4mm x 4mm QFN Package The LTC(R)4418 connects one of two valid power supplies to a common output based on priority and validity. Priority is defined by pin assignment, with V1 assigned the higher priority and V2 the lower priority. A power supply is defined as valid when its voltage has been within its overvoltage (OV) and undervoltage (UV) window continuously for at least the configured validation time. If the highest priority valid input falls out of the OV/UV window, the channel is immediately disconnected and the other valid input is connected to the common output. Multiple LTC4418s, as well as triple channel LTC4417s, can be cascaded to provide switchover between more than two inputs. nn The LTC4418 incorporates fast non-overlap switching circuitry to prevent both reverse and cross conduction while minimizing output droop. The gate driver includes a 6V clamp to protect external MOSFETs. A controlled soft-start feature minimizes start-up inrush current. Open drain VALID outputs indicate the input supplies have been within their OV/UV window for the duration of the validation time. The validation time can be disabled or adjusted using an external capacitor. APPLICATIONS Industrial Handheld Instruments High Availability Systems nn Battery Backup Systems nn Servers and Computer Peripherals nn nn All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION M1 5V SYS FDS4465 M2 + M3 12V WALL ADAPTER FDS4465 1.25A MAX OUTPUT M4 V2 2V/DIV 47nF 100nF V1 VS1 470nF G1 698 VS2 13.8V BAT46WJ VOUT G2 VOUT 1M 100k UV1 60.4k 100k V1 2V/DIV VALID1 OV1 VALID2 226k LTC4418 INTVCC 1M EN UV2 33.2k 5V ILOAD = 1.25A COUT = 82F CAS V2 2ms/DIV 4418 TA01b SHDN OV2 78.7k Priority Switching from V1 to V2 82F GND HYS 255k TMR 1nF 4418 TA01a 100nF Rev A Document Feedback For more information www.analog.com 1 LTC4418 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) Supply Voltages V1, V2...................................................... -42V to 60V VOUT....................................................... -0.3V to 42V VS1, VS2................................................. -0.3V to 60V Voltage from V1, V2 to VOUT........................ -84V to 60V Voltage from VS1, VS2 to G1, G2................-0.3V to 7.5V Input Voltages EN, SHDN............................................... -0.3V to 60V OV1, OV2, UV1, UV2, TMR....................... -0.3V to 6V HYS.......................................................... -0.3V to 1V INTVCC................................................... -0.3V to 6.2V Output Voltages VALID1, VALID2....................................... -0.3V to 60V CAS........................................................... -0.3V to 6V Input Currents OV1, OV2, UV1, UV2, HYS, TMR, INTVCC, EN, SHDN............................................. -3mA Output Currents VALID1, VALID2, CAS............................... -2mA/+5mA Operating Ambient Temperature Range LTC4418C................................................. 0C to 70C LTC4418I..............................................-40C to 85C Storage Temperature Range................... -65C to 150C ORDER INFORMATION V2 V1 EN SHDN HYS TOP VIEW 20 19 18 17 16 15 VOUT TMR 1 14 VS1 UV1 2 GND 21 OV1 3 UV2 4 13 G1 12 VS2 11 G2 8 VALID2 GND 9 10 INTVCC 7 CAS 6 VALID1 OV2 5 UF PACKAGE 20-LEAD (4mm x 4mm) PLASTIC QFN TJMAX = 150C, JA = 47C/W, JC = 4.5C/W EXPOSED PAD (PIN 21), PCB GND CONNECTION OPTIONAL http://www.linear.com/product/LTC4418#orderinfo LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4418CUF#PBF LTC4418CUF#TRPBF 4418 20-Lead (4mm x 4mm) Plastic QFN 0C to 70C LTC4418IUF#PBF LTC4418IUF#TRPBF 4418 20-Lead (4mm x 4mm) Plastic QFN -40C to 85C Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2 Rev A For more information www.analog.com LTC4418 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Unless otherwise noted, V1 = VS1 = 12V and/or V2 = VS2 = 12V, VOUT = 12V, HYS = GND, CAS = Open, G1 = G2 = Open. (Notes 1, 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Start-Up V1, V2, VOUT V1, V2, VOUT Operating Supply Range l 2.5 VINTVCC INTVCC Voltage l 2.5 40 V 3.3 4 V ITOT Total Supply Current (Sum of IVOUT, IV1, IV2, IVS1, IVS2) l l 26 22 52 44 A A IVOUT VOUT Supply Current l 17 34 A IV1, IV2 V1, V2 Supply Current (Note 3) VOUT = 0V, EN = 0V VOUT = 0V, SHDN = 0V l l l 1.4 21 13 2.8 42 26 A A A IVS1, IVS2 VS Supply Current Channel ON Channel OFF l l 5.7 1.8 11.4 3.6 A A Open Clamp Voltage (VS - VG) VOUT = 11V, G1 = G2 = Open l 6.2 6.7 V SHDN = 0V Gate Control VG 5.4 VG(SOURCE) Sourcing Clamp Voltage (VS - VG) VOUT = 11V, I = -10A l 5.8 6.6 7 V VG(SINK) Sinking Clamp Voltage (VS - VG) VOUT = 11V, I = 10A l 4.5 5.2 6 V IG(DN) Gate Pull-Down Current VG = 3V, VS Floating l 28 60 120 VG(OFF) Gate Off Threshold (VS - VG) VS1 = VS2 = 2.8V, VOUT = 11V, Gate Rising l 0.2 0.3 0.4 V RG(OFF) Gate Off Resistance V1 or V2 = 12V, IG = -10mA l 8 16 28 VREV Reverse Voltage Threshold Measure (V1 or V2) - VOUT Falling l 75 125 185 mV tG(SWITCHOVER) Break-Before-Make Time VOUT = 11V, CGATE = 10nF (Note 4) l 1 2.7 4 s tP(SHDN) Gate Turn-Off Delay from SHDN VOUT = 11V, Falling Edge SHDN to G1 = VS1-3V or G2 = VS2 - 3V, CGATE = 10nF l 0.3 0.7 1.4 s tP(EN) Gate Turn-On/Off Delay from EN VOUT = 11V, Rising/Falling EN Edge to G1 = VS1-3V or G2 = VS2 - 3V, CGATE = 10nF l 0.3 0.7 1.4 s tSS Soft-Start Timeout VOUT = 2V l 20 35 70 ms VVALID(OL) VALID Output Low Voltage I = 1mA, V1 or V2 = 2.5V, VOUT = 0V l 0.23 0.5 V VCAS(OH) CAS Output High Voltage I = -1A, V1, V2, VOUT > 2.5V, UV = OV = EN = 0V l 2.7 3.5 V VCAS(OL) CAS Output Low Voltage I = 1mA, V1 or V2 = 2.5V, VOUT = 0V l 60 150 mV ICAS CAS Pull-Up Current SHDN = 0V, CAS = 1V l -10 -20 -40 A tCAS(EN) CAS Delay from VG(OFF) VOUT = 11V l 0.3 0.7 1.4 s VEN(TH) EN Threshold Voltage EN Rising, VOUT = 11V l 0.6 1 1.4 V VSHDN(TH) SHDN Threshold Voltage SHDN Rising l 0.6 1 1.4 VSHDN_EN(HYS) SHDN, EN Threshold Hysteresis ICTRL SHDN, EN Pull-Up Current SHDN = EN = 0V l ILEAK SHDN, EN, VALID1, VALID2, CAS Leakage Current SHDN = EN = VALID1 = VALID2 = 40V, CAS = 5.5V l mA Input/Output Pins 1.6 130 -1.5 -3.2 V mV -5.5 A 1 A Rev A For more information www.analog.com 3 LTC4418 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Unless otherwise noted, V1 = VS1 = 12V and/or V2 = VS2 = 12V, VOUT = 12V, HYS = GND, CAS = Open, G1 = G2 = Open. (Notes 1, 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 1.015 V OV, UV Protection Circuitry VTH OV/UV Comparator Threshold VOUT = 11V, OV Rising, UV Falling l 0.985 1 VHYS(INT) OV/UV Comparator Hysteresis VOUT = 11V l 15 30 ILEAK OV/UV Leakage Current OV = 1.015V, UV = 0.985V l IEXT External Hysteresis Current Into/Out of UV/OV Pins IHYS = -400nA IHYS = -4A l l 40 470 VHYS HYS Voltage IHYS = -4A l ITMR TMR Pull-Up Current TMR Pull-Down Current Timer On, VTMR 600mV Timer On, VTMR 1.6V tVALID OV, UV Validation Time tVALID(OFF) 45 mV 10 nA 50 500 60 530 nA nA 480 500 520 mV l l -1 1 -2 2 -3.5 3.5 A A TMR = VINTVCC CTMR = 1nF l l 2 9 3.5 16 7 32 s ms VALID Off Delay from OV/UV Fault UV or OV 10% Overdrive, Measure VALID1 or VALID2 Rising Edge l 2 3.5 7 s VTH(TMROFF) TMR Disable Voltage Threshold Measure VINTVCC-VTMR, Rising Edge l 50 100 180 mV VTH(TMRHYS) TMR Disable Voltage Hysteresis Validation Timer 120 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive; all voltages are referenced to GND unless otherwise specified. 4 mV Note 3: Specification represents the diode-OR'd current of V1 or V2 input supplies. Current is split evenly if both supplies are equal. Note 4: UV1 or UV2 driven below VTH. Time is measured from respective rising edge G1 crossing VS1 - 3V or G2 crossing VS2 - 3V to next valid priority falling edge G1 crossing VS1 - 3V or G2 crossing VS2 - 3V. Rev A For more information www.analog.com LTC4418 TYPICAL PERFORMANCE CHARACTERISTICS Total Enabled Supply Current vs Supply Voltage Total Shutdown Supply Current vs Supply Voltage 25C 30 -45C 20 15 10 ALL SUPPLY VS AND VOUT PINS CONNECTED TOGETHER 5 0 10 20 30 SUPPLY VOLTAGE (V) 25 20 -45C 10 0 10 20 30 SUPPLY VOLTAGE (V) 18 GATE FALLING SLEW RATE (V/s) VG (V) 6.0 OPEN 5.5 5.0 IG = 10A 0 25 50 TEMPERATURE (C) 75 V1 = 40V 16 V1 = 12V 12 V1 = 24V 8 6 V1 = 5V 4 2 0 25 50 TEMPERATURE (C) 75 3.0 0 0.5 1 1.5 2 2.5 GATE VOLTAGE (V) 3 3.5 V1 = 5V 8 4 V1 = 2.7V 0 -50 100 -25 0 25 50 TEMPERATURE (C) 75 Valid Delay Off Time vs Temperature 7 6 V1 = 3V V1 = 12V 2.5 V1 = 40V 2.0 1.5 -50 100 4418 G06 VALID DELAY TIME (s) 10 t G(SWITCHOVER) (s) GATE PULL-DOWN CURRENT (mA) 3.5 -45C V1 = 12V, 24V, 40V 12 Break Before Make Time vs Temperature V1/V2 = 12V VOUT = 11.7V VS1/VS2 = FLOATING V1 = V2 CGATE = 10nF 4418 G05 100 25C 16 V1 = 2.7V -25 40 4418 G03 V1 = V2 CGATE = 10nF 10 Gate Pull-Down Current vs Gate Voltage 90C 30 Gate Rising Slew Rate vs Temperature 4418 G04 0.1 0 -40 -30 -20 -10 0 10 20 V2 VOLTAGE (V) 40 14 0 -50 100 1 IV2 IV1 ALL SUPPLY VS AND VOUT PINS CONNECTED TOGETHER Gate Falling Slew Rate vs Temperature IG = -10A IVS1+IVS2 4418 G02 7.0 -25 10 5 5 Gate Drive Voltage vs Temperature 4.5 -50 15 15 4418 G01 6.5 IVOUT 25C 0 40 V1 = VS1 = VS2 = VOUT = 12V 90C GATE RISING SLEW RATE (V/s) 25 20 IV1-V2-VOUT(EN) (A) TOTAL SUPPLY CURRENT (A) TOTAL ENABLE SUPPLY CURRENT (A) 90C 35 0.01 IV1, IV2, IVOUT vs V2 Supply Voltage 30 40 0 TA = 25C, unless otherwise noted. 5 4 3 V1 = V2 CGATE = 10nF -25 0 25 50 TEMPERATURE (C) 75 100 4418 G08 4418 G07 2 -50 -25 0 25 50 TEMPERATURE (C) 75 100 4418 G09 Rev A For more information www.analog.com 5 LTC4418 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, unless otherwise noted. Validation Time vs TMR Capacitance OV, UV Threshold vs Temperature 1.04 10k OV, UV Hysteresis Current Configuration 500 V1/2 = 12V 1.03 VTH (V) 1.01 1.00 VTH 0.99 0.98 400 1k IEXT (nA) VALIDATION DELAY (ms) UV RISING THRESHOLD 1.02 100 10 300 200 100 0.97 0.96 -50 OV FALLING THRESHOLD -25 0 25 50 TEMPERATURE (C) 75 1 0.1 100 1 4418 G10 4.0 INTVCC vs Input Voltage (V1, V2, VOUT) 10 CTMR (nF) VVALID(OL) (V) 2.0 1.5 0.6 32 3000 4000 4418 G12 VOUT V1 2V/DIV 0.4 0.2 16 24 INPUT VOLTAGE (V) 2000 IHYS (nA) V2 2V/DIV -45C 40 0 0 1 2 3 4 PULL-UP CURRENT (mA) 5 4418 G14 4418 G13 VOUT Switching from Lower to Higher Voltage with Inrush Current Limiting Circuitry VOUT Switching from Higher to Lower Voltage Reverse Voltage Blocking V2, VOUT 5V/DIV V2 4V/DIV V2 2V/DIV V1 5V/DIV VOUT VOUT 2V/DIV 4418 G15 5ms/DIV CTMR = 1nF COUT = 120F ILOAD = 1A -40A PCH FDS4685 V1/V2 = 12V VOUT = 12V 0.5 8 1000 Deglitched Connection 25C 2.5 0 0 4418 G11 90C 0.8 1.0 V1 = +15V V1 4V/DIV V1 2V/DIV IV2 10A/DIV 500s/DIV COUT = 120F ILOAD = 2A -20V PCH FDS4465 6 0 1.0 3.0 0 1k VALID1, VALID2 Pull-Down Strength 3.5 INTVCC (V) 100 4418 G16 V1 = -15V 50s/DIV RS = 475 CS = 47nF COUT = 120F ILOAD = 2A -20V PCH FDS4465 4418 G17 2ms/DIV 4418 G18 -40V PCH FDD4685 COUT = 10F ILOAD = 1A Rev A For more information www.analog.com LTC4418 PIN FUNCTIONS TMR (Pin 1): Validation Timer. Attach an external capacitor between TMR and GND of at least 100pF to set a Validation Time of 16ms/nF for both channels. Connect TMR to INTVCC to set a minimum validation time of 3.5s (Fast Mode). Do not leave open. UV1, UV2 (Pins 2, 4): Undervoltage Comparator Inputs. Falling voltages below 1V (VTH) trigger an undervoltage event, invalidating the respective input supply channel. Connect UV1 and UV2 to a resistive divider between the respective V1 and V2 and ground to achieve the desired undervoltage threshold. The comparator hysteresis can be set internally to VHYS(INT) or set externally via the HYS pin. Connect unused pins to ground. OV1, OV2 (Pins 3, 5): Overvoltage Comparator Inputs. Rising voltages above 1V (VTH) signal an overvoltage event, invalidating the respective input supply channel. Connect OV1 and OV2 to an external resistive divider from its respective V1 and V2 to achieve the desired overvoltage threshold. The comparator hysteresis can be set internally to VHYS(INT) or set externally via the HYS pin. Connect unused pins to ground. VALID1, VALID2 (Pins 6, 7): Valid Channel Indicator Outputs. VALID1 and VALID2 are 40V rated, open drain outputs that pull low when the respective V1 and V2 are within the OV/UV window for at least the configured validation time and release when the respective V1 and V2 are outside the OV/UV window. Connect a resistor between VALID1 and VALID2 and a desired supply, which may be V1, V2 or VOUT, to provide the pull-up. Leave open when not used. GND (Pin 8, Exposed Pad Pin 21): Device Ground. Exposed pad may be left open or connected to device ground. CAS (Pin 9): Cascade Output. Digital output used for cascading multiple LTC4418s and/or LTC4417s. Connect CAS to EN of another LTC4417/LTC4418 to increase the number of multiplexed input supplies. CAS is pulled up to INTVCC by an internal 20A current source (ICAS) to indicate when all inputs are invalid, the external P-channel MOSFETs are determined to be off, and EN is above VEN(TH). CAS also pulls high when SHDN is driven below VSHDN(TH). CAS is pulled low when any input supply is within the OV/UV window for at least the configured validation time and SHDN is above its threshold. CAS also pulls low when EN is driven below VEN(TH). CAS can be pulled up to voltages as high as 5.5V, independent of the input supply voltages. Leave open if not used. INTVCC (Pin 10): Internal Low Voltage Supply Decoupling Output. Do not connect an external load current to INTVCC. Connect a 0.1F capacitor from this pin to GND. G1, G2 (Pins 13, 11): P-Channel MOSFET Gate Drive Outputs. G1 and G2 are used to control external P-channel MOSFETs. When driven low, G1 and G2 are clamped 6.2V (VG) below their corresponding VS1 and VS2. Connect G1 and G2 to external P-channel MOSFET gate pins. VS1, VS2 (Pins 14, 12): External P-Channel MOSFET Common Source Connection. The gate drivers use VS1 and VS2 to monitor the common source connection of the external P-channel MOSFETs. Connect VS1 and VS2 to the respective common source connection of the P-channel MOSFETs. Connect to ground when channel is not used. See Applications Information section for bypass capacitor recommendations. VOUT (Pin 15): Output Voltage Supply and Sense. VOUT is an output voltage sense pin used to prevent any input supply from connecting to the output if the output voltage is not below the input supply voltage by at least 125mV (VREV). During normal operation, VOUT powers most of the internal circuitry when its voltage exceeds 2.475V. See Applications Information section for bypass capacitor recommendations. V2 (Pin 16): Lower Priority Input Supply. When V2 is within its user defined OV/UV window for the configured validation time, it is connected to VOUT via its external P-channel MOSFETs only if V1 does not meet its OV/UV requirements. Connect V2 to ground when channel is not used. See Applications Information for bypass capacitor recommendations. V1 (Pin 17): Higher Priority Input Supply. When V1 is within its user defined OV/UV window for the configured validation time, it is connected to VOUT via its external P-channel MOSFETs. See Applications Information for bypass capacitor recommendations. Rev A For more information www.analog.com 7 LTC4418 PIN FUNCTIONS EN (Pin 18): Channel Enable Input. EN is a 40V input that allows the user to quickly connect and disconnect channels without resetting the OV/UV Validation timer. This feature is essential in cascading applications. When below 1V (VEN(TH)), both external P-channel MOSFETs are driven off by pulling G1 and G2 to their respective VS1 and VS2. When above VEN(TH), the highest valid priority channel is connected to the output. EN is pulled to INTVCC with a 3.2A current source (ICTRL) and can be pulled up externally to a maximum voltage of 40V. Connect to INTVCC when not used. SHDN (Pin 19): Shutdown Input. Driving SHDN below VSHDN(TH) turns off all external P-channel MOSFETs, disables the OV/UV comparators and resets the validation 8 timers used to validate V1 and V2. CAS is pulled high to allow lower priority LTC4417/LTC4418s in a cascaded system to provide power to VOUT. Driving SHDN above 1V (VSHDN(TH)) allows channels to validate and connect. SHDN is pulled high to INTVCC with a 3.2A current source (ICTRL) and can be pulled up externally to a maximum voltage of 40V. Connect to INTVCC when not used. HYS (Pin 20): OV/UV Comparator Hysteresis Input. Connecting HYS to ground sets a fixed hysteresis (VHYS(INT)) for the OV and UV comparators. Connecting a resistor, RHYS, between HYS and ground disables the internal hysteresis and sets a 63mV/RHYS hysteresis current which is sourced from each OV1 and OV2 and sunk into each UV1 and UV2 pin. Connect to GND if not used. Rev A For more information www.analog.com LTC4418 BLOCK DIAGRAM INTVCC 3.2A INTVCC SHDN VOUT + - 1V V1 DISABLE GATEDRIVERS AND RESET VALIDATION TIMER INTVCC 3.2A EN INTVCC REGULATOR 20A INTVCC + - 1V V2 INTVCC DISABLE GATEDRIVERS CAS TMR HYS GND OSCILLATOR HYSTERESIS IEXT UV1 EXT HYS UV UV2 PRIORITIZED NONOVERLAP CONTROL LOGIC + - INT HYS IEXT UV 1.03V VALIDATION TIMER 1V 970mV INTVCC OV IEXT CH1 VALID 125mV HOLD CH OFF REV + - +- VOUT V1 V2 + - OV OV1 OV2 EXTERNAL SWITCH ON VGS + - VS1 +- 6.2V 300mV VS2 G1 VALID1 GATE DRIVER VALID2 G2 CHANNEL 1 CHANNEL 2 4418 BD Rev A For more information www.analog.com 9 LTC4418 TIMING DIAGRAM G2 G1 VALID2 VALID1 UV2 UV1 EN SHDN tVALID tVALID(OFF) tG(SWITCHOVER) tP(EN) tP(EN) tP(SHDN) 4418 TD 10 Rev A For more information www.analog.com LTC4418 OPERATION The LTC4418 is an intelligent 40V dual channel PowerPathTM switch that automatically connects one of two input supplies to a common output based on a channel's priority and validity. Channel 1 is defined to be higher priority than Channel 2 regardless of voltage levels. A channel's validity is user defined by a set of undervoltage (UV) and overvoltage (OV) comparators biased with a resistive divider off of the channel's input. Connection is made by enhancing external back-to-back P-channel MOSFETs. Unlike a diode-OR, which always passes the highest supply voltage to the output, the LTC4418 lets one use a higher supply as a secondary for backup power. During normal operation the LTC4418 continuously monitors V1 and V2 through its respective UV and OV pins using precision overvoltage and undervoltage comparators. An input supply is defined valid when the voltage remains in the OV/UV window for at least the validation time, (tVALID). If the input supply connected to V1 falls out of the OV/UV window and remains outside for at least 3.5s (tVALID(OFF)) the channel is disconnected. V2 is then connected to the common output if it is within its OV/UV window. The LTC4418 always connects the higher priority V1 supply if it becomes valid regardless of the status of V2. VALID1 and VALID2 pull low to indicate when the V1 and V2 input supplies are valid. Hysteresis on the UV and OV inputs can be configured to be a fixed 3% or made adjustable. Connecting the HYS pin to ground sets the hysteresis on both channels to be 3% of the monitored voltage. Connecting a resistor, RHYS, between HYS and ground forces 63mV/RHYS current out of OV1 and OV2 and into UV1 and UV2 in order to create hysteresis when outside their respective OV/UV windows. The configuration of HYS affects both channels. During channel transitions, monitoring circuitry prevents cross conduction between input supplies and reverse conduction from VOUT using a break-before-make architecture. The VGS comparator monitors the disconnecting channel's gate pin voltage (G1 or G2). When the gate voltage is 300mV (VG(OFF)) from its common source connection (VS1 or VS2), the VGS comparator latches the output to indicate the channel is off and allows the other valid priority input supply to connect to VOUT, preventing cross conduction between channels. To prevent reverse conduction from VOUT to V1 and V2 during channel switchover, the REV comparator monitors the connecting input supply (V1 or V2) and VOUT. The REV comparator delays the connection until the output voltage droops lower than the input voltage by 120mV (VREV). Once activated, the LTC4418 gate driver pulls G1 or G2 down to 6.2V (VG) below its respective VS1 or VS2 with a strong pull-down current. After turning on, the gate driver holds the gates of the external P-channel MOSFETs at VG with a small pull-down current. To minimize inrush current at start-up, the gate driver soft-starts the first input supply to connect to VOUT at a rate of approximately 4V/ ms terminating when any channel disconnects or 35ms elapses. Once slew rate control has terminated, the gate driver returns to normal gate driving operation. When EN is driven above 1V (VEN(TH)) the highest valid priority input supply is connected to VOUT. When EN is driven below VEN(TH) all channels are disconnected from VOUT and the LTC4418 continues to monitor the OV and UV pins indicating status with VALID1 and VALID2. When SHDN is pulled below 1V (VSHDN(TH)) all channels are disconnected, OV and UV comparators are disabled and both channel validation timers are reset. A SHDN low to high transition reactivates soft-start, provided VOUT drops below 2.3V before SHDN is high. VOUT dropping below 1.7V also reactivates soft-start. When additional supplies need to be prioritized the part can work in conjunction with other LTC4417s and/or LTC4418s where the CAS pin of the highest priority controller is connected to the EN of the lower priority controller. If VOUT is allowed to fall below 1.7V, the next connecting input supply is soft-started. The LTC4418 has its own internally generated 3.3V rail (INTVCC) that provides power to internal circuits of the part. The INTVCC rail is prioritized such that supply current comes from one of three prioritized sources (V1, V2 or VOUT). An external capacitor must be connected between the INTVCC pin and GND to hold up the internal rail in the event of transients such as input supply shorts. Rev A For more information www.analog.com 11 LTC4418 APPLICATIONS INFORMATION PowerPath controllers are designed to connect one of several input supplies to a common output based on their priority and validity. The highest priority supply may not necessarily be the highest in voltage. While the application appears simple at first glance there are a few issues that must be accounted for when building an application. One issue is input supply inrush current during a channel switchover that occurs when charging a low ESR output capacitor. Inrush current dissipates significant power in the external P-channel MOSFETs. It also causes input voltage droop due to the input power supply's source impedance and the parasitic impedance of connectors, cables and PCB traces. Input supply voltage droop can cause UV faults that trigger a phenomenon called motor-boating, where the input supply repeatedly connects and disconnects from the output. Motor-boating can lead to component damage or undesirable/erratic circuit behavior. Another issue is output voltage droop which occurs during the break-before-make time of a switchover between channels. Ideally, there would be no disruption of the output voltage during a switchover. However, load current discharges the output capacitor during the break-beforemake time resulting in output voltage droop. To ensure minimum output voltage droop, a large value, low ESR capacitor is used to ride through this dead time. There is a trade-off between inrush current and output voltage droop. The following sections describe these challenges in more detail and explain component selection to properly manage them. Note that input supply voltages denoted by "SYS" are not hot-swappable, all other input supplies are hot-swappable. DEFINING OPERATION RANGE The operation range for each LTC4418 channel is defined by an OV/UV window. An input supply must remain inside the OV/UV window for the OV/UV validation time, tVALID, to become valid and connect to the output. Both OV and UV thresholds include hysteresis which reduces the operating window as shown in Figure 1. For example, V1 supply voltage must be greater than UVHYS to exit the UV fault. If an OV fault occurs, the V1 supply voltage must return to a voltage lower than the OVHYS voltage to exit the OV fault. 12 OV OVHYS REDUCED OPERATING WINDOW OV/UV WINDOW UVHYS UV V1 UV1 FAULT OV1 FAULT V1 VALID1 4418 F01 Figure 1. OV and UV Thresholds and Hysteresis Voltage The OV/UV window for each input supply is set by a resistive divider connected from the input supply to GND. The most important consideration when setting the resistive divider values for the OV/UV window is to provide enough hysteresis to allow for input supply voltage droop due to inrush and load current during switchover. In addition to input supply droop take into consideration: 1. Tolerance of the Input Supply 2. 1.5% OV/UV Comparator Threshold Error 3. Tolerance of External Resistive Divider 4. Max ILEAK OV/UV Pin Leakage Currents Hysteresis for the OV and UV comparators is set via the HYS pin. Two options are available. Connecting a resistor, RHYS, between HYS and GND, as shown in Figure 2, sets the hysteresis current IHYS that is sunk into UV1 and UV2 and sourced out of OV1 and OV2. The value of RHYS is calculated with: RHYS = 63mV I EXT Choose RHYS to limit the hysteresis current in the range 50nA to 500nA. Connecting HYS to GND, as shown in Figure 3, selects an internal 30mV fixed hysteresis, resulting in 3% of the input supply range. Rev A For more information www.analog.com LTC4418 APPLICATIONS INFORMATION V1 INPUT SUPPLY R10 R12 R9 R11 R8 T-RESISTIVE CONNECTION R5 UV1 OV1 R7 V1 LTC4418 R3 VOUT UV UV1 UV1 R6 RP IHYS/8 R2 VALID1 1V OV1 R4 VALIDATION TIMER INTVCC DUALRESISTIVE CONNECTION IHYS/8 OV1 ALTERNATE INDEPENDENT HYSTERESIS M1 1V OV IHYS HYS R1 RHYS GND 124k TO 1.24M 4418 F02 Figure 2. Adjustable External OV/UV Hysteresis V1 INPUT SUPPLY V1 R3 UV1 UV RP 1V CUVF VOUT LTC4418 VALID1 1.03V OPTIONAL FILTER CAPACITOR VALIDATION TIMER M1 R2 M2 1V OV 0.97V OPTIONAL DISCONNECT R1 OV1 HYS GND 4418 F03 Figure 3. 3% Internal Hysteresis with Optional Filter Capacitor and Manual Disconnect MOSFET Rev A For more information www.analog.com 13 LTC4418 APPLICATIONS INFORMATION Refer to the Design Example for an explanation of the Three-Resistor configuration for setting OV/UV thresholds and hysteresis. Independent OV and UV hysteresis values are available by separating the single string resistive dividers R1, R2 and R3, shown in Figure 2, into two resistive strings, R4-R5 and R6-R7. In such a configuration, the top resistor defines the amount of hysteresis and the bottom resistor defines the threshold. RTOP and RBOT are calculated using: R TOP = RBOT = Desired Hysteresis I EXT (OV/UV Threshold) - 1 When large independent hysteresis voltages are required, a resistive T structure can be used to define hysteresis values, also shown in Figure 2. After the desired OV and UV thresholds are set with resistors R8 through R10, R11 and R12 are calculated using: R8 * [OVHYS - IEXT * (R9 + R10)] R12 = (R8 + R9) * [UVHYS - IEXT * R10] The LTC4418 drives external P-channel MOSFETs to conduct or block load current between an input supply and load. When selecting external P-channel MOSFETs, the key parameters to consider are: 1. On-Resistance (RDS(ON)) 2. Absolute Max Drain-Source Breakdown Voltage (BVDSS(MAX)) 3. Threshold Voltage (VGS(TH)) IEXT * (R8 + R9 + R10) 4. SOA IEXT * (R8 + R9 + R10) where OVHYS, UVHYS are the desired OV and UV hysteresis voltage magnitudes at V1 through V2, and IEXT is the programmed hysteresis current. The LTC4418 has an OV/UV fault filter time of tVALID(OFF). Add a filter capacitor, CUVF, between the OV or UV pin and GND to extend the fault filter time and ride through transients as shown in Figure 3. By extending the filter time, the detection of a valid UV condition will also be delayed. To tailor the filter time delays individually, separate the single resistive divider into two resistive dividers. When selecting resistor values, take into consideration board leakage and OV/UV pin leakage and their affect on threshold accuracy. 14 A connected input supply can be manually disconnected by artificially creating a UV fault. An example is shown in Figure 3. When N-channel MOSFET, M2, is turned on, the UV1 pin is pulled below 1V. The LTC4418 then disconnects V1 and connects the next highest valid priority to VOUT. Alternatively, the VALID2 can be connected directly to UV1 to swap priority to Channel 2, as shown in Figure 12. Connect TMR to INTVCC to ensure quick switchover to channel 1 when channel 2 becomes invalid. SELECTING EXTERNAL P-CHANNEL MOSFETS R TOP R11= PRIORITY REASSIGNMENT The on-resistance of each P-channel MOSFET should be sufficiently low when conducting the maximum load current to minimize voltage drop and power dissipation. External P-channel MOSFET devices may be paralleled to decrease resistance and decrease power dissipation of each paralleled MOSFET. The clamped gate drive output is 4.5V (minimum) from the common source connection. Select logic level or lower threshold external MOSFETs to ensure adequate overdrive. For applications with input supplies lower than the clamp voltage, choose external MOSFETs with thresholds sufficiently lower than the input supply voltage to guarantee full enhancement. Rev A For more information www.analog.com LTC4418 APPLICATIONS INFORMATION It is imperative that external P-channel MOSFET devices never exceed their BVDSS(MAX) rating in the application. Switching inductive supply inputs with low value input and/or output capacitances may require additional precautions; see Transient Supply Protection section for more information. In normal operation, the external P-channel MOSFET devices are either fully on, dissipating relatively low power, or off, dissipating no power. However, during slew-rate controlled startup or switchover from a lower to a higher voltage with inrush current, significant power may be dissipated in the external P-channel MOSFETs. The external MOSFETs must satisfy the Safe Operating Area (SOA) curve for these conditions. A list of suggested P-channel MOSFETs is shown in Table 1. Use procedures outlined in this section and the SOA curves in the chosen MOSFET manufacturer's data sheet to verify suitability for the application. Table 1. Listed of Suggested P-Channel MOSFETs MOSFET APP MAX OP VOLTAGE VTH(MAX) VGS(MAX) VDS(MAX) Si4465ADY 5V -1V 8V -8V Si4931DY 10V -1V 8V -12V IRF7220 10V -0.6V 12V -12V IRF7325* 10V -0.9V 8V -12V FDS4465 18V -1.5V 8V -20V FDMS6673BZ FDS6675 AO4803A* Si4909DY* SUD50P04-23 Si7463ADP FDD4685/FDS4685 Si7461DP FDMC5614P SUD50P06-15 FDD5614P FDS9958 SUD50P08-25L Si7469DP FDS8935 Si7489DP 28V 28V 28V 36V 36V 36V 36V 40V 40V 40V 40V 40V 40V 40V 40V 40V -3V -3V -2.5V -2.5V -3V -3V -3V -3V -3V -3V -3V -3V -3V -3V -3V -3V 25V 20V 20V 20V 20V 20V 20V 20V 20V 20V 20V 20V 20V 20V 20V 20V -30V -30V -30V -40V -40V -40V -40V -60V -60V -60V -60V -60V -80V -80V -80V -100V RDS(ON) () 0.009 at -4.5V 0.011 at -2.5V 0.018 at -4.5V 0.022 at -2.5V 0.012 at -4.5V 0.02 at -2.5V 0.024 at -4.5V 0.033 at -2.5V 0.0085 at -4.5V 0.010 at -2.5V 0.0125 0.02 0.074 0.034 0.0117 0.0135 0.035 0.019 0.135 0.02 0.13 0.135 0.029 0.029 0.247 0.047 *Dual P-channel MOSFETs in a single package. Rev A For more information www.analog.com 15 LTC4418 APPLICATIONS INFORMATION SELECTING VOUT CAPACITANCE INRUSH CURRENT AND INPUT VOLTAGE DROOP To ensure there is minimal droop at the output, select a low ESR capacitor large enough to ride through the dead time between channel switchover. A low ESR bulk capacitor will reduce IR drops to the output voltage while the load current is sourced from the capacitor. When connecting a higher voltage supply to a lower voltage output, significant inrush current can occur while charging an output capacitor with low ESR. Inrush current during a switchover can cause two issues, (1) P-channel MOSFETs are subjected to damaging power dissipation and (2) an undesirable UV fault from significant input voltage droop also known as motor-boating. Motor-boating is specifically a concern when the UVHYS threshold for the input supply connected to V1 is higher in voltage than the OV/ UV window of the input supply connected to V2. Motorboating is prevented through inrush current limiting and ensuring that there is a proper amount of hysteresis to accommodate the expected input supply voltage droop. At a minimum hysteresis should provide enough margin for the input supply voltage to droop due to inrush and load current during switchover. Select the OV/UV operation range appropriately. To calculate the value of the load capacitor that will ride through the break-before-make time, tG(SWITCHOVER) during a normal switchover use: COUT I LOAD(MAX) * tG(SWITCHOVER) VOUT(DROOP) - ESR * I LOAD(MAX) where ILOAD(MAX) is the maximum load current drawn and VOUT(DROOP) is the maximum acceptable amount of voltage droop at the output. This equation assumes no inrush current limiting circuitry is required. If inrush current limiting is necessary then a modified equation for the minimum COUT calculation is used: COUT ( I LOAD * tG(SWITCHOVER) + 0.79 * R S * CS VOUT(DROOP) - ESR * I LOAD ) 1. Max IINRUSH through the supply source resistance, RSRC can cause a UV condition. The selection of RS and COUT is iterative. Initially, the minimum COUT is calculated by approximating: 0.79 * RS * CS = 15s Once RS is determined, the selection of COUT should be checked by substituting the values of RS and CS into the equation above to ensure the condition is satisfied. See the Inrush Current and Input Voltage Droop section. For conditions where V1/2 supplies are rapidly disconnected or may be shorted then it is appropriate to add the VALID1/2 Off Delay from OV/UV Fault (tVALID(OFF)) to tG(SWITCHOVER) in the previous equations. Note that there is a trade-off between larger COUT and tolerating higher inrush current. COUT ( I LOAD * tG(SWITCHOVER) + t VALID(OFF) + 0.79 * R S * CS 16 VOUT(DROOP) - ESR * I LOAD Inrush current limiting is necessary in situations where one or more of these conditions apply: ) 2. Peak inrush current violates the maximum pulsed drain current (IDM) of the external P-channel MOSFETs. 3. Large voltage differential between input supplies or the configured OV/UV thresholds between input supplies. 4. Small or unknown source impedance. 5. Large output capacitance. In order to check maximum expected inrush current use: Max IINRUSH = (Max V1 or V2) - VOUT(MIN) R SRC + ESR COUT + 2 * RDS(ON) Where ESRCOUT is the ESR of the output capacitor and RDS(ON) is the channel resistance of the selected P-channel MOSFETs. The maximum voltage differential is determined from the higher supply's OV threshold and the lower supply's UV threshold minus VOUT droop. Rev A For more information www.analog.com LTC4418 APPLICATIONS INFORMATION With the LTC4418, inrush current can be reduced by slew rate limiting the output voltage. The gate driver can be configured to slew rate limit the output voltage with a resistor, capacitor and Schottky diode, as shown in Figure 4. The series resistor, RS, and capacitor, CS, are inrush current limiting components, while the Schottky diode, DS, provides a fast turn off path when G1 is pulled to VS1. Choose CS to be at least ten times the external P-channel MOSFET's reverse transfer capacitance, CRSS(MAX), and CVS to be ten times CS. Alternatively, CRSS(MAX) itself can be used in place of CS, where its value is taken at the minimum VDS voltage. M1 V1/2 M2 VOUT CIN COUT CS CVS DS BAT54 RS VS1/2 G1/2 VOUT LTC4418 4418 F04 Figure 4. Inrush Current Limiting Components With a desired COUT and inrush current target the value of RS is: RS ( VG(SINK) - VGS ) * COUT CS * IINRUSH where VG(SINK) is the LTC4418's sink clamp voltage and VGS is the external P-channel's gate to source voltage when driving the load and inrush current. The output load current ILOAD is neglected for simplicity. When inrush current limiting, ensure power dissipation does not exceed the manufacturer's SOA for the chosen external P-channel MOSFET. GATE DRIVER When turning a channel on, the LTC4418 pulls the common gate connection (G1 and G2) down with a strong low impedance pull-down. See IG(DN) in the Electrical Characteristics table. VS1 and VS2 voltages lower than 5V will result in lower gate slew rates, see the Typical Performance Characteristics curves for more detail. After turning a channel on the gate driver holds down G1 or G2 with a small pull-down current sufficient to maintain the VG clamp voltage. Clamping the G1 and G2 voltage prevents any overvoltage stress on the gate to source oxide of the external P-channel MOSFETs. When turning a channel off, the gate driver pulls the common gate to the common source with a switch having an on-resistance of RG(OFF), to facilitate a quick turn-off. To minimize inrush current at start-up, the gate driver soft-starts the gate drive of the first input to connect to VOUT. The gate pin is regulated to create an approximately 4V/ms slew rate on VOUT. Logic level P-channel MOSFETs with thresholds below 1V will result in faster soft-start slew rates on VOUT. Slew rate control is terminated when any channel disconnects or a time period 35ms has elapsed. Once soft-start has terminated, the gate driver operates normally. A SHDN low to high transition reactivates soft-start, provided VOUT drops below 2.3V before SHDN is high. VOUT drooping below 1.7V also reactivates soft-start. SELECTING VALIDATION TIME The validation time is adjustable allowing greater flexibility when validating input supplies over a variety of applications. The validation time, tVALID, is adjusted by connecting a capacitor, CTMR, between the TMR pin and ground. The value of this capacitor is determined by: C TMR = t VALID 16ms /nF It is not recommended to leave the TMR pin open, instead connect the pin to INTVCC to engage "Fast Mode" operation where tVALID is reduced to approximately 3.5s typical. The accuracy of the validation time is affected by capacitor leakage (the nominal charging current is specified by ITMR) and capacitor tolerance. A low leakage ceramic capacitor is recommended. Rev A For more information www.analog.com 17 LTC4418 APPLICATIONS INFORMATION TRANSIENT SUPPLY PROTECTION REVERSE VOLTAGE PROTECTION The LTC4418's abrupt switching due to OV or UV faults can create large transient overvoltage events with inductive input supplies, such as supplies connected by a long cable. At times the transient overvoltage condition can exceed twice the nominal voltage resulting in damage to the system. It is imperative that external P-channel MOSFET devices do not exceed their single pulse avalanche energy specification (EAS) in unclamped inductive applications and input voltages to the LTC4418 never exceed the Absolute Maximum Ratings. The LTC4418 is designed to withstand reverse voltages applied to V1 and V2 with respect to VOUT up to -84V. This allows VOUT to operate at or near its maximum operating voltage, 42V with V1/V2 at a -42V reverse voltage. The large reverse voltage rating protects input supplies and downstream devices connected to VOUT against high reverse voltage connections of -42V (absolute maximum) with margin. Select P-channel MOSFETs with BVDSS(MAX) ratings capable of handling any anticipated reverse voltages between VOUT and V1 or V2. Ensure transient voltage suppressors (TVS) connected to reverse connection protected inputs (V1 and V2) are bidirectional and input capacitors are rated for the negative voltage. See Typical Performance Characteristics for voltage waveforms illustrating this feature. To minimize inductive voltage spikes, use wider and/or heavier trace plating. Transient voltage suppressors (TVS) should be placed on supply pins, V1 and V2 where inductive transients beyond the 60V absolute maximum rating are expected. When selecting transient voltage suppressors, ensure the reverse standoff voltage (VR) is equal to or greater than the application operating voltage, the peak pulse current (IPP) is higher than the peak transient voltage divided by the source impedance, the maximum clamping voltage (VCLAMP) at the rated IPP is less than the absolute maximum ratings and BVDSS of all the external P-channel MOSFETs. See Figure 5. The LTC4418's absolute maximum voltage rating for V1 and V2 allow it to withstand supplyside inductive voltage spikes up to 60V. A range of TVS diode specifications can be used accommodating VRWM ratings up to 36V and VCLAMP ratings up to 60V. INPUT PARASITIC INDUCTANCE M1 V1/2 RSN OR TVS REVERSE CURRENT BLOCKING When switching channels from higher voltages to lower voltages, the REV comparator verifies the VOUT voltage is below the connecting channel's voltage by 120mV before the new channel is allowed to connect to VOUT. VOUT is allowed to decay at a slew rate determined by the load current divided by the load capacitance. This ensures little to no reverse conduction occurs during switching. OUTPUT PARASITIC INDUCTANCE M2 VOUT CVIN COUT OR TVS CLOAD CSN SNUBBER VS1/2 G1/2 VOUT LTC4418 4418 F05 Figure 5. Transient Voltage Suppression 18 Rev A For more information www.analog.com LTC4418 APPLICATIONS INFORMATION DISABLING ALL CHANNELS WITH EN AND SHDN Driving EN below 1V turns off all external P-channel MOSFETs but does not interrupt input supply monitoring or reset the validation timers. Driving EN above 1V enables the highest valid priority channel to connect to VOUT. This feature is essential in cascading applications. For applications where EN could be driven below ground, limit the current from EN with a 10k resistor. Forcing SHDN below 0.8V turns off all external P-channel MOSFETs, disables all OV and UV comparators and resets all validation timers. VALID1 and VALID2 release high to indicate all inputs are invalid, regardless of the input supply condition. The LTC4418 is required to revalidate the input supplies before connecting the inputs to VOUT. For applications where SHDN could be driven below ground, limit the current from SHDN with a 10k resistor. If EN or SHDN are not used then each can be connected to INTVCC. the input from the output before the output is dragged below the operating voltage of the LTC4418. Placing a bypass capacitor from INTVCC to GND keeps the internal rail of the LTC4418 from collapsing due to these types of transients. To prevent damage to the LTC4418 and associated devices in the event of an input or output short, it may be necessary to protect the input and output pins as shown in Figure 5. Protect the input pins with either unidirectional or bidirectional TVS and VOUT with a unidirectional TVS. In situations where VOUT has the potential to get pulled below ground place a reverse Schottky diode from VOUT to GND or a small series resistance with the VOUT pin to limit current. An input and output capacitor between 0.1F and 10F with intentional or parasitic series resistance will aid in dampening voltage spikes. CASCADING INPUT SUPPLY AND VOUT SHORTS Input shorts can cause high current slew rates. Coupled with series parasitic inductances in the input and output paths, potentially destructive transients may appear at the input and output pins. If the short occurs on an input that is not powering VOUT, the impact to the system is benign due to the P-channel MOSFETs having reverse block capability. If a short occurs on an input that is powering VOUT, the issue is compounded by high conduction current and low impedance connection to the output via the P-channel MOSFETs. Once the LTC4418 blocks the high input short current, V1 and V2 may experience large negative voltage spikes while the output may experience large positive voltage spikes. If VOUT is shorted there will be an input supply UV fault due to its low impedance connection. If the UV threshold is high enough and the short resistive enough, the LTC4418 will disconnect the input. If the other input supply is valid it will attempt to connect. Rapid switching between supplies may occur if tVALID is configured to be too short in duration or in Fast Mode. The fast change in current may force the output below GND, while the input will increase in voltage. If UV thresholds are set close to the minimum operating voltage of the LTC4418, it may not disconnect The LTC4418 is cascadable and can work in conjunction with the LTC4417 to prioritize three or more input supplies. When cascading multiple LTC4418s, connect VOUT pins together and connect each LTC4418 CAS pin to the next lower priority LTC4418's EN pin. See Figure 6. The first LTC4418 to validate an input will soft-start the common output. Once the output is above 2.5V, power will be drawn from VOUT by the other LTC4418 regardless of its supply connections. When the master LTC4418 wants to connect one of its input supplies to the VOUT, it simultaneously initiates a channel turn on and pulls its CAS pin low to force the slave LTC4418 to disconnect its channels. A small amount of reverse conduction may occur in this case. The amount of cross conduction will depend on the total turn-on delay of the master channel compared with the turn-off delay of the slave channel. Care should be taken to ensure the connection between CAS and EN is as short as possible, to minimize the capacitance and hence the turn-off delay of the slave channel. When all of the inputs to the master LTC4418 are invalid, the master confirms that all its inputs are disconnected from VOUT before releasing CAS. CAS is pulled to the INTVCC rail with a 20A current source, allowing the slave Rev A For more information www.analog.com 19 LTC4418 APPLICATIONS INFORMATION + 1ST PRIORITY SUPPLY M1 VOUT COUT M2 M7 M8 4TH PRIORITY SUPPLY 2 SUPPLIES MASTER 2 SUPPLIES SLAVE 2ND PRIORITY SUPPLY M3 VS1 DISABLE ALL CHANNELS SHDN MASTER EN G2 M4 VS2 LTC4418 MASTER M5 G2 VS5 VOUT CAS VOUT CAS TO EN CONNECTION SHDN 3RD PRIORITY SUPPLY M6 EN G6 VS7 G8 LTC4418 SLAVE SHDN 4418 F06 Figure 6. Cascaded Application LTC4418 to connect its highest valid priority channel to VOUT. Confirmation that all channels are off before the slave is allowed to connect its channel to VOUT prevents cross conduction from occurring. Driving the master LTC4418's EN low forces both master and slave to disconnect all channels from the common output and continue monitoring the input supplies. Driving the master LTC4418's SHDN low places it in a reset state where all of its channels are disconnected and CAS is pulled high with a 20A current source, allowing the slave LTC4418 to become the master and connect its highest valid priority channel to the common output. DESIGN EXAMPLE In this example, the LTC4418 prioritizes between 5V and 12V supplies for a 1.25A system as shown in Figure 7. Power is only sourced from the 12V supply when the 5V supply is invalid. The 12V supply has a 20m source resistance (RSRC) and the ambient conditions of the system are between 25C and 85C. The design must accommodate 2.5% tolerance on the 5V supply and a 20 10% tolerance on the 12V supply and limit the VOUT droop to 500mV during switchover. The load capacitor is assumed to be an electrolytic with a minimum ESR (ESRCOUT) of 25m at 25C. Determining OV/UV Windows For the 5V V1 supply, 2.5% tolerance sets an operational window of 4.875V to 5.125V. In order to accommodate this voltage range the OV/UV thresholds must allow for desired hysteresis, external resistive divider error and comparator threshold error. For the 5V V1 supply, an additional 2.5% error is included for margin which means that the OV/UV window must accommodate 4.75V to 5.25V range. For 5% external hysteresis or 250mV, set the UV1 = 4.5V and OV1 = 5.5V. For the 12V V2 supply, taking into account supply tolerance and a margin for error sources the operational window is 10.2V to 13.78V. Since external hysteresis is used, channel 2 also has 250mV of hysteresis (2.1%). The OV/UV thresholds are UV2 = 9.95V and OV2 = 14.03V. These thresholds determine the maximum possible differential voltage between supplies at switchover. Rev A For more information www.analog.com LTC4418 APPLICATIONS INFORMATION M1 5V SYS + 12V WALL ADAPTER INPUT IMPEDANCE: 20m FDS4465 M2 + CIN1 10F M3 + CV2 100nF CS 47nF CVS1 100nF R3 1M R2 53.6k R1 232k R5 33.2k R4 78.7k M4 CIN2 10F CV1 100nF R6 1M FDS4465 VOUT 1.25A COUT 82F 25m ESR VS1 V1 RS 698 CVS2 470nF G1 VS2 G2 VALID2 OV1 LT3060-3.3 R7 100k VOUT VALID1 UV1 DS BAT46WJ R8 100k V1 INVALID V2 INVALID CAS LTC4418 INTVCC V2 EN UV2 SHDN OV2 GND TMR HYS 4418 F07 RHYS 255k CHANNEL 1 2 UV THRESHOLD 4.5V 9.95V OV THRESHOLD 5.5V 14.13V 250mV HYSTERESIS 250mV INRUSH LIMIT - 12A VALIDATION DELAY 16ms 16ms VOUT DROOP MAX CTMR 1nF CINTVCC 100nF 500mV Figure 7. Design Example Schematic 5V/12V System Rev A For more information www.analog.com 21 LTC4418 APPLICATIONS INFORMATION P-Channel MOSFET Selection Using the list of suggested P-channel MOSFETs in Table 1 as a guideline, the FDS4465 (Max VDS = -20V, RDS(ON) = 8.5m) is appropriate for this application. When selecting external MOSFETs the following items are relevant: 1. MAX VDS 2. RDS(ON) 3. IDM Based on these calculations, the target inrush current for the V2 PowerPath switches is 12A. Now the appropriate values for output capacitance and inrush current limiting components are determined. The first step is to calculate the minimum required output capacitance, COUT, to satisfy the desired output voltage droop, 500mV. Assume the inrush current limiting components, RS and CS, add 15s to the switchover time. COUT 4. CRSS (Maximum) 5. VGS (At IINRUSH + ILOAD Current) 6. SOA Inrush Current Component Selection The UV2 threshold for V2 is larger than the OV/UV window of V1. This means that there could be significant inrush current during switchover from V1 to V2. There are two inrush current issues to address: 1. Avoid damaging the P-channel MOSFETs by violating their IDM specification 2. Prevent UV faults on channel 2 from V2 input droop The maximum inrush current occurs when switching to the V2 supply which has a maximum voltage of 14.03V. The minimum voltage of VOUT is 4.5V if V1 is at its UV threshold. For these conditions, the maximum inrush current through the P-channel MOSFETs is: MAX IINRUSH = = V2(MAX) - VOUT(MIN) R SRC + ESR COUT + 2 * RDS(ON) 14.03V - 4.5V 0.02 + 0.025 + 0.17 = 154A The 154A worst case inrush current far exceeds the 50A IDM spec of the FDS4465. The worst case condition for generating a UV fault on Channel 2 is if V2 is just above UVHYS threshold of 10.2V. Given the input impedance of 20m, the maximum tolerable inrush current is: Tolerable IINRUSH = 22 UVHYS2 R SRC = 250mV 0.02 = 12.5A ( ILOAD * tG(SWITCHOVER) + 15s ) VOUT(DROOP) - ESR COUT * ILOAD 1.25A * (2.7s + 15s) 500mV - 1.25A * 25m 47F For aluminum electrolytic capacitors add at least 20%. For margin, choose 82F for COUT for this application. The inrush current limiting components must now be determined. Information from the FDS4465 data sheet required is VGS at IINRUSH + ILOAD which is 1.25V at approximately 12A and the maximum value of CRSS which is 4000pF. The minimum value of CS is 10 * CRSS or 40nF so a 47nF CS value is selected. Next calculate RS using the maximum specification for VG(SINK): RS (VG(SINK) - VGS ) * COUT CS * IINRUSH(TARGET) (6V - 1.25V) * 82F 47nF * 12A 690.6 where the closest 1% value is 698. With the inrush current limiting components known, the desired output capacitance is checked with the equation: COUT ( ILOAD * tG(SWITCHOVER) + 0.79 * R S * CS VOUT(DROOP) - ESR * ILOAD ) 1.25A * (2.7s + 0.79 * 698 * 47nF) 500mV - 25m 71.54F The selected 82F output capacitance is therefore suitable. A typical value for CVS1 and CVS2 is 0.1F. For the situation where inrush current limiting components are used, so CVS2 is chosen to be 0.47F. Rev A For more information www.analog.com LTC4418 APPLICATIONS INFORMATION External P-Channel MOSFET Power Dissipation The SOA of the P-channel MOSFET should be checked to ensure it is not violated. Worst case channel turn on time for the V2 power path occurs for the same condition used to determine inrush current limiting components for a maximum inrush current of 12A. ( V2(MAX) - VOUT(MIN) ) * COUT dt = = 12A = 62s R2 = Setting Operational Range The 5V supply has a 2.5% operational window in this example. The thresholds chosen give an additional 2.5% margin in each direction. Instead of using the internal fixed 150mV (or 3%) hysteresis, the higher priority 5V supply is set for 250mV hysteresis using an external hysteresis current (IEXT) of 250nA. The resistive divider will be configured as a Three-Resistive network. First select an appropriate RHYS value: 63mV 250nA 63mV 255k = 247nA R3 is calculated from: R3 = Desired Hysteresis IEXT = 1 * + 1 * 1M = 233.7k 5.5V ( 4.5V / 1V ) - 1 1V 250mV 247nA = 1012k where the closest 1% value is 1000k. = R3 (UV1 / VTH ) - 1 1M (4.5V / 1V) - 1 - R1 - 232k = 53.7k where the closest 1% value is 53.6k. The actual UV threshold is: UV1= VTH * R1+ R2 + R3 = 4.5V R1+ R2 UV1HYS = R3 * I EXT = 1M * 247nA = 247mV Likewise, the actual OV threshold is: OV1= VTH * R1+ R2 + R3 R1 OV1HYS = (R2 + R3) * I EXT = 5.54V = (113k + 1M) * 247nA = 260mV The values of R4 through R6 are calculated similarly using the configured hysteresis current. If internal hysteresis is desired, the resistor values for a Three-Resistive network can be determined by initially selecting resistive divider current and using it to determine R1-R3 or RSUM. The choice of resistive divider values should take into consideration board and OV/UV pin leakages. The hysteresis thresholds are calculated by: = 252k where the closest 1% value is 255k. IEXT = = R2 can be calculated from: Checking the Maximum Safe Operating Area plot in the FDS4465 data sheet shows that it must withstand 12A at 10V worst case (120W) for 62s. The SOA plot for the FDS4465 shows that it can conduct 50A at 10V (1kW) for 100s satisfying the requirement. The Maximum Safe Operating Area plot can also be checked with regard to the soft-start power dissipation. RHYS = V 1 R1= TH * + 1 * R 3 OV1 (UV1 / VTH ) - 1 where the closest 1% value is 232k. IINRUSH(TARGET) (14.05V - 4.5V) * 82F Next, calculate R1 from: UV(Risin g) = UV(Fallin g) = ( VTH + VHYS(INT) ) * RSUM R1+ R2 ( VTH + VHYS(INT) ) * RSUM R1 Rev A For more information www.analog.com 23 LTC4418 APPLICATIONS INFORMATION Dual 28V System with Kelvin Sense Connection Through Connector Using internal hysteresis in this application would result in 130mV UV hysteresis and 170mV OV hysteresis for V1. Likewise, the V2 OV/UV window would result in 300mV UV hysteresis and 420mV OV hysteresis. The dual 28V supply system in Figure 13 includes a backplane connector with a kelvin sense. The supply pin and resistive divider network for each channel are connected to the kelvin sense. A rapid disconnection of one of the input supplies from the backplane causes an immediate UV fault since the time constant at V1/2 and the respective OV/UV pins is much shorter than at the output. Without a kelvin sense connection the input supply must discharge down to its UV threshold over a period of time before switchover. Both input supplies include transient voltage suppression diodes (SMBJ36CA) rated for 36V operation and a clamping voltage of 58V. Layout Consideration High current applications demand careful attention to trace resistances. Sheet resistance of 1oz copper is ~530 per square. Keep high current traces short with minimum trace widths of 0.02" per Amp to ensure traces stay at a reasonable temperature. Using 0.03" per Amp or wider is recommended. To improve noise immunity, place OV/UV resistive dividers as close to the LTC4418 as possible. Transient voltage suppressors should be located as close to the input connector as possible with short wide traces to GND. Figure 8 shows a partial layout that addresses these issues. FROM V1 INPUT SOURCE M1 D S G G S D M2 TO OUTPUT FROM V2 INPUT SOURCE M3 D S G G S D M4 CV1 CS1 CV2 SHDN EN V1 V2 RHYS 0.03" PER AMPERE HYS DS1 20 19 18 17 16 RS1 CTMR TMR 1 R5 UV2 4 13 G1 12 VS2 OV2 5 11 G2 6 7 8 9 10 INTVCC R4 14 VS1 GND 21 OV1 3 CAS R6 R2 GND R1 15 VOUT UV1 2 VALID2 R3 VALLID1 TRANSIENT VOLTAGE SUPPRESSOR CVS2 CVS1 CINTVCC GND GND 4418 F08 NOTE: NOT TO SCALE Figure 8. LTC4418 Layout Example 24 Rev A For more information www.analog.com LTC4418 TYPICAL APPLICATIONS 5V 2.5% SYS A IMPUT IMPEDANCE: 25m M1 + Si4465DY M2 CIN1 10F M3 + R3 1.15M R2 82.5k R1 255k R5 82.5k R4 255k VOUT 1.5A MAX M4 CS2 47nF CV1 100nF R6 1.15M Si4465DY CIN2 10F CVS1 470nF CV2 100nF CIN3 82F 25m ESR DS1 BAT46WJ RS1 422 5V 2.5% SYS B IMPUT IMPEDANCE: 25m + CS1 47nF VS1 V1 CVS2 470nF G1 RS2 422 VS2 G2 VALID2 OV1 R7 100k VOUT VALID1 UV1 DS2 BAT46WJ R8 100k SYSA INVALID SYSB INVALID CAS LTC4418 INTVCC V2 EN UV2 SHDN OV2 GND TMR HYS 4418 F09 RHYS 210k CHANNEL 1 2 UV THRESHOLD 4.4V 4.4V OV THRESHOLD 5.85V 5.85V 350mV HYSTERESIS 350mV INRUSH LIMIT 25A 25A VALIDATION DELAY 16ms 16ms VOUT DROOP MAX CTMR 1nF CINTVCC 100nF 400mV Figure 9. Dual 5V System Rev A For more information www.analog.com 25 LTC4418 TYPICAL APPLICATIONS M1 5V USB + IRF7325 M2 + CIN1 10F INPUT IMPEDANCE: 900m 4x AA BATTERIES M3 IRF7325 COUT 33F 30m ESR VOUT 500mA MAX M4 VBAT CVS1 0.1F CV1 0.1F R3 402k R2 30.9k R1 90.9k CV2 0.1F R6 402k R7 562k R5 76.8k R8 105k R4 78.7k VS1 V1 CVS2 0.1F G1 VS2 G2 VALID1 UV1 VALID2 OV1 R9 1M VOUT R10 1M V1 INVALID V2 INVALID CAS LTC4418 INTVCC V2 EN UV2 OV2 SHDN GND TMR HYS 4418 F10 RHYS 255k CHANNEL 1 2 UV THRESHOLD 4.3V 3.6V OV THRESHOLD 5.76V 7.1V HYSTERESIS 100mV 600mV (UV) 300mV (OV) INRUSH LIMIT - - VALIDATION DELAY 16ms VOUT DROOP MAX CTMR 1nF CINTVCC 100nF 16ms 500mV Figure 10. 5V USB and AA Alkaline Battery Backup 26 Rev A For more information www.analog.com LTC4418 TYPICAL APPLICATIONS M1 12V SYS + FDS4685 M2 + CIN1 39F FDS4685 M3 24V SYS INPUT IMPEDANCE: 30m + CS 6.8nF CIN2 39F CVS1 100nF R3 634k R2 23.2k R1 49.9k R6 634k R5 11.8k R4 23.2k V1 VS1 RS 1.96k CVS2 220nF CVS1 100nF CV2 100nF M4 VOUT 2A MAX COUT 39F 30m ESR G1 VS2 G2 VALID2 OV1 12V INVALID 24V INVALID EN UV2 SHDN GND TMR HYS 4418 F11 RHYS 158k 1 2 UV THRESHOLD 9.67V 19.17V OV THRESHOLD 14.17V 28.84V HYSTERESIS 250mV 250mV INRUSH LIMIT - 8A VALIDATION DELAY 16ms VOUT DROOP MAX R8 1M INTVCC V2 CHANNEL R7 1M CAS LTC4418 OV2 LT3060-3.3 VOUT VALID1 UV1 DS BAT46WJ CTMR 1nF CINTVCC 100nF 16ms 1.2V Figure 11. 12V System with 24V Backup Supply Rev A For more information www.analog.com 27 LTC4418 TYPICAL APPLICATIONS FDD4685 M1 24V SYS A INPUT IMPEDANCE: 30m + M2 CIN1 47F RS1 133 24V SYS B INPUT IMPEDANCE: 30m VOUT 1A MAX COUT 10F 120m ESR DS1 BAT46WJ FDD4685 M3 + + CS1 6.8nF M4 CS2 6.8nF CIN2 47F CV2 100nF CV1 100nF R3 1.87M R2 34.8k R1 68.1k V1 VS1 RS2 133 CVS2 68nF CVS1 68nF G1 VS2 VALID2 OV1 R7 100k CH PRIORITY SWAP INTVCC EN SHDN OV2 R4 68.1k V1 INVALID LT3060-3.3 LTC4418 UV2 R5 34.8k VOUT VALID1 UV1 V2 R6 1.87M G2 DS2 BAT46WJ GND HYS TMR 4418 F12 RHYS 158k CHANNEL 1 2 UV THRESHOLD 19.17V 19.17V OV THRESHOLD 29V 29V HYSTERESIS 750mV 750mV INRUSH LIMIT 50A 50A VALIDATION DELAY 3.5s VOUT DROOP MAX CINTVCC 100nF 3.5s 2.4V CH PRIORITY IS SWAPPED - FAST MODE REQUIRED Figure 12. Dual 24V System with Priority Swapped 28 Rev A For more information www.analog.com LTC4418 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC4418#packaging for the most recent package drawings. UF Package 20-Lead Plastic QFN (4mm x 4mm) (Reference LTC DWG # 05-08-1710 Rev A) 0.70 0.05 4.50 0.05 3.10 0.05 2.45 0.05 2.00 REF 2.45 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 0.10 0.75 0.05 R = 0.05 TYP R = 0.115 TYP 19 20 0.40 0.10 PIN 1 TOP MARK (NOTE 6) 1 2.00 REF 4.00 0.10 PIN 1 NOTCH R = 0.20 TYP OR 0.35 x 45 CHAMFER BOTTOM VIEW--EXPOSED PAD 2.45 0.10 2 2.45 0.10 (UF20) QFN 01-07 REV A 0.200 REF 0.00 - 0.05 0.25 0.05 0.50 BSC NOTE: 1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-1)--TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE REVISION HISTORY REV DATE DESCRIPTION A 04/18 Updated specification conditions: RG(OFF), tSS, ITMR PAGE NUMBER 3, 4 Rev A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 29 LTC4418 TYPICAL APPLICATION CONNECTOR 1 CONNECTOR 2 SUD50P06 M2 TVS1 SMBJ36CA + CS1 47nF RS1 243 KELVIN VOUT 3.5A COUTB 22F 50V 170m ESR COUTA + 22F 50V 170m ESR DS1 BAT46WJ SUD50P06 M3 M4 CONNECTOR 3 28V BACKUP INPUT IMPEDANCE: 30m M1 CONNECTOR 4 28V SYS INPUT IMPEDANCE: 30m TVS2 SMBJ36CA CV1 100nF 100V CV2 100nF 100V KELVIN CS2 47nF CVS1 470nF 100V VS1 G1 V1 R3 1.33M CVS2 470nF 100V R7 100k VOUT VALID2 OV1 R1 42.2k G2 VALID1 UV1 R2 20k DS2 BAT46WJ RS2 243 VS2 LT3060-3.3 R8 100k V1 INVALID V2 INVALID LTC4418 INTVCC V2 R6 1.33M EN UV2 R5 20k SHDN OV2 R4 42.2k HYS GND TMR 4418 F13 CHANNEL 1 2 UV THRESHOLD 22.4V 22.4V OV THRESHOLD 33V 33V HYSTERESIS 3% OV/UV 3% OV/UV INRUSH LIMIT 10A 10A VALIDATION DELAY 16ms 16ms VOUT DROOP MAX CTMR 1nF CINTVCC 100nF 2.8V Figure 13. Dual 28V System with Kelvin Sense Connection Through Connector RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC4411 2.6A Low Loss Ideal Diode in ThinSOTTM Internal 2.6A P-Channel, 2.6V to 5.5V, 40A IQ, SOT-23 Package LTC4412 36V Low Loss PowerPath Controller in ThinSOT 2.5V to 36V, P-Channel, 11A IQ SOT-23 Package LTC4415 Dual 4A Ideal Diodes with Adjustable Current Limit Dual Internal P-Channel, 1.7V to 5.5V, MSOP-16 and DFN-16 Packages LTC4416 36V Low Loss Dual PowerPath Controller for Large PFETs 3.6V to 36V, 35A IQ MSOP-10 Package LTC4417 3-Channel Prioritized PowerPath Controller Triple P-Channel Controller, 2.5V to 36V, SSOP-24 and QFN-24 Packages LTC4419/ LTC4420 18V Dual Input Micropower PowerPath Prioritizer Internal P-Channel, 1.8V to 18V, 3.6A IQ, DFN-12 and MSOP-12 Packages LTC4355 Positive High Voltage Ideal Diode-OR Dual N-Channel, 9V to 80V, SO-16, MSOP-16 and DFN-14 Packages LTC4359 Ideal Diode Controller with Reverse Input Protection N-Channel, 4V to 80V, MSOP-8 and DFN-6 Packages 30 Rev A D16838-0-4/18(A) www.analog.com For more information www.analog.com ANALOG DEVICES, INC. 2017-2018