MOSEL VITELIC
1
V53C517405A
4M X 4 EDO PAGE MODE
CMOS DYNAMIC RAM
V53C517405A Rev. 1.1 March 1998
V53C517405A 50 60
Max. RAS Access Time, (t
RAC
) 50 ns 60 ns
Max. Column Address Access Time, (t
CAA
) 25 ns 30 ns
Min. Extended Data Out Page Mode Cycle Time, (t
PC
) 20 ns 25 ns
Min. Read/Write Cycle Time, (t
RC
) 84 ns 104 ns
Features
■
4M x 4-bit organization
■
EDO Page Mode for a sustained data rate
of 50 MHz
■
RAS access time: 50, 60, 70 ns
■
Low power dissipation
■
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh, Hidden Refresh
■
Refresh Interval: 2048 cycles/32 ms
■
Available in 24/26-pin 300 mil SOJ,
and 24/26-pin 300 mil TSOP-II
■
Single +5 V
±
10% Power Supply
■
TTL Interface
Description
The V53C517405A is a 4,194,304 x 4 bit high-
performance CMOS dynamic random access
memory. The V53C517405A offers Page mode
operation with Extended Data Output. The
V53C517405A has a symmetric address, 11-bit row
and 11-bit column.
All inputs are TTL compatible. EDO Page Mode
operation allows random access up to 2048 x 4 bits,
within a page, with cycle times as short as 20ns.
These features make the V53C517405A ideally
suited for a wide variety of high performance
computer systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline Access Time (ns) Power Temperature
MarkK T 50 60 Std.
0
°
C to 70
°
C•••• • Blank
2
MOSEL VITELIC
V53C517405A
V53C517405A Rev. 1.1 March 1998
VCC
I/O1
I/O2
WE
RAS
NC
A10
A0
A1
A2
A3
VCC
VSS
I/O4
I/O3
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
5
6
8
9
10
11
12
1
2
3
424
23
22
21
19
18
17
16
15
13 14
511740502-02
26
25
Pin Names
A
0
–A
10
Row, Column Address Inputs
RAS Row Address Strobe
CAS Column Address Strobe
WE Write Enable
OE Output Enable
I/O
1
–I/O
4
Data Input, Output
V
CC
+5V Supply
V
SS
0V Supply
NC No Connect
Description Pkg. Pin Count
SOJ K 24/26
TSOP-II T 24/26
24/26 Pin Plastic SOJ /TSOP-II
PIN CONFIGURATION
Top View
MOSEL VITELIC
V53C517405A
3
V53C517405A Rev. 1.1 March 1998
Absolute Maximum Ratings*
Operating temperature range ..................0 to 70
°
C
Storage temperature range ............... -55 to 150
°
C
Input/output voltage.......-0.5 to min (V
CC
+0.5, 7) V
Power supply voltage ............................-1.0V to 7V
Power dissipation ..........................................1.0 W
Data out current (short circuit)......................50 mA
*
Note:
Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Capacitance*
T
A
= 25
°
C, V
CC
= 5 V
±
10%, V
SS
= 0 V, f = 1 MHz
*Note:
Capacitance is sampled and not 100% tested.
Symbol Parameter Min. Max. Unit
C
IN1
Address Input — 5 pF
C
IN2
RAS, CAS, WE, OE — 7 pF
C
OUT
Data Input/Output — 7 pF
Block Diagram
No. 2 Clock
Generator
Data In
Buffer Data Out
Buffer
Column
Address
Buffers (11)
Refresh
Controller
Row
Decoder
Refresh
Counter (11)
No. 1 Clock
Generator
Voltage Down
Generator
Row
Address
Buffers (11)
11
4
I/O1 I/O2 I/O3I/O4
4
OE
11
11 11
4
2048
VCC
VCC (internal)
2048
x4
Memory Array
2048 x 2048 x 4
Sense Amplifier
I/O Gating
Column
Decoder
A0
CAS
WE
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
RAS
11
511740500-03
4096 x 4
4
V53C517405A Rev. 1.1 March 1998
MOSEL VITELIC
V53C517405A
DC and Operating Characteristics
(1-2)
T
A
= 0
°
C to 70
°
C, V
CC
= 5 V
±
10%, V
SS
= 0 V, t
T
= 2ns, unless otherwise specified.
Symbol Parameter Access
Time
V53C517405A
Unit Test Conditions NotesMin. Typ. Max.
I
LI
Input Leakage Current
(any input pin) –10 10
µ
A V
SS
≤
V
IN
≤
V
CC
+ 0.5V 1
I
LO
Output Leakage Current
(for High-Z State) –10 10
µ
A V
SS
≤
V
OUT
≤
V
CC
+ 0.5V
RAS, CAS at V
IH
other input
≥
V
SS
1
I
CC1
V
CC
Supply Current,
Operating 50 80 mA t
RC
= t
RC
(min.) 2, 3, 4
60 70
I
CC2
V
CC
Supply Current,
TTL Standby 2 mA RAS, CAS at V
IH
other inputs
≥
V
SS
I
CC3
V
CC
Supply Current,
RAS-Only Refresh 50 80 mA t
RC
= t
RC
(min.) 2, 4
60 70
I
CC4
V
CC
Supply Current,
EDO Page Mode
Operation
50 35 mA Minimum Cycle 2, 3, 4
60 30
I
CC5
V
CC
Supply Current,
during CAS-before-RAS
Refresh
50 120 mA 2, 4
60 110
70 100
I
CC6
V
CC
Supply Current,
CMOS Standby 1.0 mA RAS
≥
V
CC
– 0.2 V,
CAS
≥
V
CC
– 0.2 V
other input
≥
V
SS
1
V
CC
Power Supply Voltage 4.5 5.0 5.5 V
V
IL
Input Low Voltage –0.5 0.8 V 1
V
IH
Input High Voltage 2.4 V
CC
+0.5 V 1
V
OL
Output Low Voltage 0.4 V I
OL
= 4.2 mA 1
V
OH
Output High Voltage 2.4 V I
OH
= –5 mA 1
5
MOSEL VITELIC
V53C517405A
V53C517405A Rev. 1.1 March 1998
AC Characteristics
(5, 6)
T
A
= 0 to 70 ˚C,V
CC
= 5 V
±
10 %, t
T
= 2 ns
# Symbol Parameter
-50 -60
Unit Notemin. max. min. max.
Common Parameters
1 t
RC
Random read or write cycle time 84 – 104 – ns
2 t
RP
RAS precharge time 30 – 40 – ns
3 t
RAS RAS pulse width 50 10k 60 10k ns
4 tCAS CAS pulse width 8 10k 10 10k ns
5 tASR Row address setup time 0 – 0 – ns
6 tRAH Row address hold time 8 – 10 – ns
7 tASC Column address setup time 0 – 0 – ns
8 tCAH Column address hold time 8 – 10 – ns
9 tRCD RAS to CAS delay time 12 37 14 45 ns
10 tRAD RAS to column address delay 10 25 12 30 ns
11 tRSH RAS hold time 13 15 – ns
12 tCSH CAS hold time 40 50 – ns
13 tCRP CAS to RAS precharge time 5 – 5 – ns
14 tTTransition time (rise and fall) 1 50 1 50 ns 7
15 tREF Refresh period – 32 – 32 ms
Read Cycle
16 tRAC Access time from RAS – 50 – 60 ns 8, 9
17 tCAC Access time from CAS – 13 – 15 ns 8, 9
18 tCAA Access time from column address – 25 – 30 ns 8,10
19 tOEA OE access time – 13 – 15 ns
20 tRAL Column address to RAS lead time 25 – 30 – ns
21 tRCS Read command setup time 0 – 0 – ns
22 tRCH Read command hold time 0 – 0 – ns 11
23 tRRH Read command hold time referenced to RAS 0 – 0 – ns 11
24 tCLZ CAS to output in low-Z 0 – 0 – ns 8
25 tOFF Output buffer turn-off delay 0 13 0 15 ns 12
26 tOEZ Output turn-off delay from OE 0 13 0 15 ns 12
27 tDZC Data to CAS low delay 0 – 0 – ns 13
28 tDZO Data to OE low delay 0 – 0 – ns 13
29 tCDD CAS high to data delay 10 – 13 – ns 14
30 tODD OE high to data delay 10 – 13 – ns 14
6
V53C517405A Rev. 1.1 March 1998
MOSEL VITELIC
V53C517405A
Write Cycle
31 tWCH Write command hold time 8 – 10 – ns
32 tWP Write command pulse width 8 – 10 – ns
33 tWCS Write command setup time 0 – 0 – ns 15
34 tRWL Write command to RAS lead time 8 – 10 – ns
35 tCWL Write command to CAS lead time 8 – 10 – ns
36 tDS Data setup time 0 – 0 – ns 16
37 tDH Data hold time 8 – 10 – ns 16
Read-modify-Write Cycle
38 tRWC Read-write cycle time 113 – 138 – ns
39 tRWD RAS to WE delay time 64 – 77 – ns 15
40 tCWD CAS to WE delay time 27 – 32 – ns 15
41 tAWD Column address to WE delay time 39 – 47 – ns 15
42 tOEH OE command hold time 10 – 13 – ns
EDO Page Mode Cycle
43 tPC EDO page mode cycle time 20 – 25 – ns
44 tCP CAS precharge time 8 – 10 – ns
45 tCPA Access time from CAS precharge – 27 – 32 ns 7
46 tCOH Output data hold time 5 – 5 – ns
47 tRASP RAS pulse width in EDO mode 50 200k 60 200k ns
48 tRHPC CAS precharge to RAS Delay 27 – 32 – ns
49 tOES OE setup time prior to CAS 5 – 5 ns
EDO Page Mode Read-modify-Write Cycle
50 tPRWC EDO page mode read-write cycle time 58 – 68 – ns
51 tCPWD CAS precharge to WE 41 – 49 – ns
CAS-before-RAS Refresh Cycle
52 tCSR CAS setup time 10 – 10 – ns
53 tCHR CAS hold time 10 – 10 – ns
54 tRPC RAS to CAS precharge time 5 – 5 – ns
55 tWRP Write to RAS precharge time 10 – 10 – ns
56 tWRH Write hold time referenced to RAS 10 – 10 – ns
AC Characteristics
(5, 6)
TA = 0 to 70 ˚C,VCC = 5 V ± 10 %, tT = 2 ns
# Symbol Parameter
-50 -60
Unit Notemin. max. min. max.
7
MOSEL VITELIC
V53C517405A
V53C517405A Rev. 1.1 March 1998
CAS-before-RAS Counter Test Cycle
57 tCPT CAS precharge time 35 – 40 – ns
Test Mode
61 tWTS Write command setup time 10 – 10 – ns
62 tWTH Write command hold time 10 – 10 – ns
63 tCHRT CAS hold time 30 – 30 – ns
64 tRAHT RAS hold time in test mode 30 – 30 – ns
AC Characteristics
(5, 6)
TA = 0 to 70 ˚C,VCC = 5 V ± 10 %, tT = 2 ns
# Symbol Parameter
-50 -60
Unit Notemin. max. min. max.
8
V53C517405A Rev. 1.1 March 1998
MOSEL VITELIC
V53C517405A
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC5 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
4) Address can be changed once or less while RAS = VIL. In case of I CC4 it can be changed once or less during a EDO
page mode cycle
5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be
a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum
of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 2 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured
between VIH and VIL.
8) Measured with the specified current load and 100 pF at VOL = 0.8 V and V OH = 2.0 V. Access time is determined by
the latter of tRAC, tCAC, tCAA,tCPA, tOEA . tCAC is measured from tristate.
9) Operation within the t RCD (max.) limit ensures that t RAC (max.) can be met. t RCD (max.) is specified as a reference point
only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC.
10) Operation within the t RAD (max. ) limit ensures that t RAC (max.) can be met. t RAD (max.) is specified as a reference point
only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tCAA.
11) Either tRCH or tRRH must be satisfied for a read cycle.
12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not referenced
to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last.
13) Either tDZC or tDZO must be satisfied.
14) Either tCDD or tODD must be satisfied.
15) tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit
(high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.), the cycle
is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions
is satisfied, the condition of I/O (at access time) is indeterminate.
16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-
write cycles.
9
MOSEL VITELIC
V53C517405A
V53C517405A Rev. 1.1 March 1998
Waveforms of Read Cycle
Row
Column
Row
Valid Data Out
RAS
CAS
Address
WE
OE
I/O
(Inputs)
I/O
(Outputs)
VIH
VIL
tRAS
tRC
tCSH
tRAD
tCAS
tRP
tRAH
tCRP
tRSH
tRCD
tRAL
tASR tCAH
tASC tASR
tRCH
tRRH
tRCS
tCAA
tOEA
tCLZ
tCAC
tOEZ
tODD
tCDD
tOFF
tDZC
tDZO
tRAC
Hi ZHi Z
“H” or “L”
WL1
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
10
V53C517405A Rev. 1.1 March 1998
MOSEL VITELIC
V53C517405A
Waveforms of Write Cycle (Early Write)
RAS
CAS
Address
WE
OE
I/O
(Inputs)
I/O
(Outputs)
.
tRAS
Valid Data In
Hi Z
Column RowRow
“H” or “L”
WL2
tRC tRP
tCSH
tRCD tRSH
tCAS
tCRP
tRAL
tRAD
tASR tASC tCAH tASR
tCWL
tRAH tWCS
tWP
tWCH
tRWL
tDH
tDS
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
11
MOSEL VITELIC
V53C517405A
V53C517405A Rev. 1.1 March 1998
Waveforms of Write Cycle (OE Controlled Write)
Valid Data
tRWL
tWP
tOEH
tCWL
Row
“H” or “L”
Hi-Z
Hi-Z
Column
Row
tASC
tRAD tRAL
tCAH
tRAH
RAS
CAS
Address
WE
OE
I/O
(Inputs)
I/O
(Outputs)
tCAS
tRSH
tRCD
tASR tASR
WL3
VIH
VIL
VOH
VOL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tRC
tRAS tRP
tCSH tCRP
tODD
tDZO
tDZC
tDH
tDS
tOEZ
tCLZ
tOEA
12
V53C517405A Rev. 1.1 March 1998
MOSEL VITELIC
V53C517405A
Waveforms of Read-Write (Read-Modify-Write) Cycle
RowRow
tRWC
I/O
(Outputs)
I/O
(Inputs)
OE
WE
Column
Valid
Data in
Data
Out
t
RAC
“H” or “L”
RAS
CAS
Address
WL4
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOL
VOH
tRAS tRP
tCSH
tRCD tRSH
tCAS tCRP
tASR
tCAH
tASC
tRAH
tASR
tRAD tAWD tCWD
tRWD
tCWL
tRWL
tWP
tOEH
tCAA tOEA
tRCS
tDS
tDH
tDZO
tDZC
tCLZ
tCAC tODD
tOEZ
13
MOSEL VITELIC
V53C517405A
V53C517405A Rev. 1.1 March 1998
Waveforms of EDO Page Mode Read Cycle
t
RP
Column 2
Row
Data Out
RAS
I/O
WE
Address
CAS
VIH
VIL
“H” or “L”
OE
tRASP
(Output) Data Out
Column N
Column 1
Data Out
12N
WL5
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
tRHPC
tRCD
tCRP
tPC
tCAS tCP tCAS
tRSH
tCAS
tCRP
tCRH tRAL
tASR tRAH tASC tCAH tASC tCAH tASC tCAH
tRAD
tRCS
tRRH
tRCH
tCAC
tCAA
tCPA
tOES tCPA
tCAA tOFF
tOEA
tRAC
tCAC
tCAA
tCLZ
tCOH tCOH
tOEZ
tCAC
14
V53C517405A Rev. 1.1 March 1998
MOSEL VITELIC
V53C517405A
Waveforms of EDO Page Mode Early Write Cycle
Column 1 Column 2
Row
Addr
Data In N
Data In 2
Data In 1
Column N
RAS
I/O (Input)
WE
Address
CAS
“H” or “L”
OE
tRASP
WL8
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
tRCD tRHPC
tRP
tCRP tPC
tCAS tCP tCAS tCAS
tCRP
tRSH
tRAL
tCAH
tASC
tCAH
tASC
tCAH
tCSH
tASC
tRAH
tASR
tRAD tCWL
tWCH
tWP
tWCS
tWP tWP
tWCH tWCH
tWCS tWCS
tCWL tCWL
tRWL
tDS tDH tDH
tDS tDH
tDS
15
MOSEL VITELIC
V53C517405A
V53C517405A Rev. 1.1 March 1998
Waveforms of EDO Page Mode Late Write and Read-Modify-Write Cycle
tODD
RAS
CAS
WE
OE
Address
I/O
(Inputs)
I/O
(Outputs)
Data In Data In Data In
Data
Out Out
Data
Data
Out
Row
Column
Column
Row Column
WL17
tRASP
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tPRWC
tCSH
tRCD tCAS tCAS tCAS
tRSH
tRP
tCRP
tASR
tRAL
tCAH
tASC
tCAH
tASC
tCAH
tASC
tRAD
tRAH
tASR
tRWL
tCWL
tCPWD
tCWD
tCWL
tCWD
tCPWD
tCWL
tCWD
tRWD
tRCS
tAWD
tCAA
tOEA
tAWD
tOEA
tWP tWP
tAWD tWP
tRAC
tDZO
tCAC
tDZC tCLZ
tODD
tOEZ
tDS
tDH
tOEH
tDZC
tCPA
tCAA
tCLZ
tODD
tOEZ
tDS
tDH
tDZC
tCPA
tCLZ
tOEH tCAC
tCAA
tDS
tDH
tOEH
tOEA
16
V53C517405A Rev. 1.1 March 1998
MOSEL VITELIC
V53C517405A
Waveforms of RAS Only Refresh Cycle
Row
Row
HI-Z
Address
RAS
CAS
I/O
(Outputs)
“H” or “L” WL9
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tRC
tRAS tRP
tCRP
tRPC
tASR
tASR
tRAH
17
MOSEL VITELIC
V53C517405A
V53C517405A Rev. 1.1 March 1998
Waveforms of CAS-before-RAS Refresh Cycle
tRC
HI-Z
“H” or “L”
RAS
I/O
(Outputs)
I/O
(Inputs)
OE
WE
CAS
WL10
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tRAS tRP
tRP
tRPC tCSR
tCP tCHR tRPC
tCRP
tWRP
tWRH
tOEZ
tCDD
tODD
tOFF
18
V53C517405A Rev. 1.1 March 1998
MOSEL VITELIC
V53C517405A
Waveforms of Hidden Refresh Read Cycle
RAS
I/O
(Outputs)
I/O
(Inputs)
OE
WE
Address
CAS
“H” or “L”
Valid Data Out
Row
Column
Row
HI-Z
WL11
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tRC tRC
tRAS tRP tRAS tRP
tRCD tRSH
tCHR tCRP
tRAD tASC
tRAH
tASR tCAH
tWRP
tWRH tASR
tRRH
tRCS
tCAA
tOEA
tDZC
tDZO
tCDD
tODD
tOFF
tOEZ
tCAC
tCLZ
tRAC
19
MOSEL VITELIC
V53C517405A
V53C517405A Rev. 1.1 March 1998
Waveforms of Hidden Refresh Early Write Cycle
RAS
I/O
(Output)
I/O
(Input)
WE
Address
CAS
“H” or “L”
tRC
Row Row
Valid Data
HI-Z
Column
WL12
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tRAS
tRP
tRCD tRSH
tRC
tRAS tRP
tCRP
tCHR
tRAD
tRAH
tASR
tASC
tCAH tASR
tWCS tWCH
tWP
tWRP tWRH
tDS tDH
20
V53C517405A Rev. 1.1 March 1998
MOSEL VITELIC
V53C517405A
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
tRAS
RAS
I/O
(Inputs)
OE
WE
Address
CAS
I/O
(Outputs)
I/O
(Outputs)
I/O
(Inputs)
WE
OE
Column Row
Data Out
Data In
HI-Z
Read Cycle:
Write Cycle:
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tRP
tCSB tCHR tCP tRSH
tCAS
tRAL
tCAH
tASC tASR
tWRP tCAA tRRH tRCH
tCAC
tRCS tOEA
tWRH
tDZC
tDZO tCLZ
tCDD
tODD tOFF
tOEZ
tWRP tWCS
tWRH
tRWL
tCWL
tWCH
tDH
tDS
21
MOSEL VITELIC
V53C517405A
V53C517405A Rev. 1.1 March 1998
Waveforms of Test Mode Entry
I/O
(Outputs)
I/O
(Inputs)
OE
WE
CAS
RAS
“H” or “L”
HI-Z
Address Row
WL15
HI-Z
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tRP tRC
tRAS tRP
tRPC
tCP tCSR tCHRT tRPC tCRP
tASR tRAHT
tWTS tWTH
tODD
tCDD
tOEZ
tOFF
22
V53C517405A Rev. 1.1 March 1998
MOSEL VITELIC
V53C517405A
Test Mode
As the V53C517405A is organized internally as
1M x 16-bits, a test mode cycle using 4:1 compres-
sion can be used to improve test time. Note that in
the 4M x 4 version the test time is reduced by 1/4 for
a N test pattern.
In a test mode “write” the data from each I/O pin is
written into four 1M blocks simultaneously (all “1” s
or all “0” s). In test mode “read” each I/O output is
used for indicating the test mode result. If the inter-
nal four bits are equal, the I/O would indicate a “1”.
If they were not equal, the I/O would indicate a “0”.
The WCBR cycle (WE, CAS before RAS) puts the
device into test mode. To exit from test mode, a
“CAS before RAS refresh”, “RAS only refresh” or
“Hidden refresh” can be used.Refresh during test
mode operation can be performed by normal read
cycles or by WCBR refresh cycles.
Row addresses A0 through A9 have to kept high
to perform a testmode entry cycle. All other address-
es are don’t care.
Block Diagram in Test Mode
Normal
Test
Vcc
Vss
I/O 3
Normal
Test
Vcc
Vss
I/O 2
Normal
Test
Vcc
Vss
I/O 1
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
I/O 4
I/O 3
I/O 2
I/O 1
Normal
Test
Normal
Normal
Normal
Test
Test
Test
A0C,A1C
A0C,A1C
A0C,A1C
A0C,A1C
A0C,A1C
A0C,A1C
A0C,A1C
A0C,A1C
Normal
Test
Vcc
Vss
I/O 4
23
MOSEL VITELIC
V53C517405A
V53C517405A Rev. 1.1 March 1998
Package Diagrams
24/26-pin 300 mil SOJ
24/26-pin 300 mil TSOP-II
Index Marking Units in inches [mm]
30°
26 21 1419
1 6 138
A
Does not include plastic or metal protrusion of 0.15 max. per side
0.020 [0.5] 0.315 min
[0.8] min
0.6 [15.24]
0.680 -0.009
[17.27 -0.25]
0.104 ± 0.003
[2.64 ± 0.1]
0.148 -0.020
[3.75 -0.5]
0.008 +0.003
[0.2 +0.1]
0.335 [0.85] Max
0.305 -0.009
[7.75 -0.25]
0.340 -0.009
[8.63 -0.25]
0.268 ±0.008
[6.8 ±0.2]
1
M
0.020 -0.003
[0.51 -0.1]0.007 [0.18] 24x
M
.05 [1.27]
B
[0.003] 0.1
0.009 [0.25] A
0.009 [0.25] B
0.007 [0.18] B
1
1
26 14
1 13
0.4 +0.12
–0.1
0.016 +0.005
–0.004
0.006 +0.003
–0.004
0.15 +0.08
–0.09
5° max.
0.008 [0.2] 24x
M
Unit in inches [mm]
0.006 ±0.002
[0.15±0.05]
0.05 [1.27]
0.039 ± 0.002
[1.0 ± 0.05] 0.3 ± 0.005
[7.62 ± 0.13]
0.363 ± 0.008
[9.22 ± 0.2]
0.050 max
[1.27 max]
0.004 [0.1]
0.680±0.005
[17.27±0.13]
Does not include plastic or metal protrusion of 0.15 max. per side
1
1
0.024 -0.008
[0.6 -0.2]
MOSEL VITELIC
WORLDWIDE OFFICES V53C517405A
© Copyright 1998, MOSEL VITELIC Inc. 3/98
Printed in U.S.A.
MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
U.S. SALES OFFICES
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
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