DATA SHEET MOS INTEGRATED CIRCUIT PD44323362 32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 1M-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE Description The PD44323362 is a 1,048,576 words by 36 bits synchronous static RAM fabricated with advanced CMOS technology using Full-CMOS six-transistor memory cell. The PD44323362 is suitable for applications which require high-speed, low voltage, high-density memory and wide bit configuration, such as cache and buffer memory. The PD44323362 is packaged in a 119-pin PLASTIC BGA (Ball Grid Array). Features * Fully synchronous operation * HSTL Input / Output levels * Fast clock access time: 2.0 ns / 250 MHz * Asynchronous output enable control: /G * Byte write control: /SBa (DQa1 to DQa9), /SBb (DQb1 to DQb9), /SBc (DQc1 to DQc9), /SBd (DQd1 to DQd9) * Common I/O using three-state outputs * Internally self-timed write cycle * Late write with 1 dead cycle between Read-Write * User-configurable outputs: Controlled impedance outputs or push-pull outputs * Boundary scan (JTAG) IEEE 1149.1 compatible * 2.5 0.125 V (Chip) / 1.4 to 1.9 V (I/O) supply * 119 bump BGA package, 1.27 mm pitch, 14 mm x 22 mm * Sleep mode: ZZ (Enables sleep mode, active high) Ordering Information Part number PD44323362F1-C40-FJ1 <R> <R> Access time Clock frequency Package 2.0 ns 250 MHz 119-pin PLASTIC BGA PD44323362F1-C40-FJ1-A Remark Products with -A at the end of the part number are lead-free products. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. M16379EJ5V0DS00 (5th edition) Date Published February 2006 NS CP(K) Printed in Japan The mark <R> shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. 2002 PD44323362 Pin Configuration /xxx indicates active low signal. 119-pin plastic BGA Top View Bottom View A B C D E F G H J K L M N P R T U 1 2 3 4 5 6 7 7 6 5 4 3 2 1 1 2 3 4 5 6 7 7 6 5 4 3 2 1 VDDQ SA12 SA9 NC SA5 SA2 VDDQ A VDDQ SA2 SA5 NC SA9 SA12 VDDQ NC SA18 SA16 SA19 SA15 SA17 NC B NC SA17 SA15 SA19 SA16 SA18 NC NC SA13 SA10 VDD SA6 SA3 NC C NC SA3 SA6 VDD SA10 SA13 NC DQc8 DQc9 VSS ZQ VSS DQb9 DQb8 D DQb8 DQb9 VSS ZQ VSS DQc9 DQc8 DQc6 DQc7 VSS /SS VSS DQb7 DQb6 E DQb6 DQb7 VSS /SS VSS DQc7 DQc6 VDDQ DQc5 VSS /G VSS DQb5 VDDQ F VDDQ DQb5 VSS /G VSS DQc5 VDDQ DQc3 DQc4 /SBc NC /SBb DQb4 DQb3 G DQb3 DQb4 /SBb NC /SBc DQc4 DQc3 DQc1 DQc2 VSS NC VSS DQb2 DQb1 H DQb1 DQb2 VSS NC VSS DQc2 DQc1 VDDQ VDD VREF VDD VREF VDD VDDQ J VDDQ VDD VREF VDD VREF VDD VDDQ DQd1 DQd2 VSS K VSS DQa2 DQa1 K DQa1 DQa2 VSS K VSS DQd2 DQd1 DQd3 DQd4 /SBd /K /SBa DQa4 DQa3 L DQa3 DQa4 /SBa /K /SBd DQd4 DQd3 VDDQ DQd5 VSS /SW VSS DQa5 VDDQ M VDDQ DQa5 VSS /SW VSS DQd5 VDDQ DQd6 DQd7 VSS SA0 VSS DQa7 DQa6 N DQa6 DQa7 VSS SA0 VSS DQd7 DQd6 DQd8 DQd9 VSS SA1 VSS DQa9 DQa8 P DQa8 DQa9 VSS SA1 VSS DQd9 DQd8 NC SA14 M1 VDD M2 SA4 NC R NC SA4 M2 VDD M1 SA14 NC NC NC SA11 SA8 SA7 NC ZZ T ZZ NC SA7 SA8 SA11 NC NC VDDQ TMS TDI TCK TDO NC VDDQ U VDDQ NC TDO TCK TDI TMS VDDQ 2 Data Sheet M16379EJ5V0DS PD44323362 Pin Name and Functions Pin name Description Function VDD Core Power Supply Supplies power for RAM core VSS Ground VDDQ Output Power Supply VREF Input Reference K, /K Main Clock SA0 to SA19 Synchronous Address Input DQa1 to DQd9 Synchronous Data Input / Output /SS Synchronous Chip Select Logically selects SRAM /SW Synchronous Byte Write Enable Write command /SBa Synchronous Byte "a" Write Enable Write DQa1 to DQa9 /SBb Synchronous Byte "b" Write Enable Write DQb1 to DQb9 /SBc Synchronous Byte "c" Write Enable Write DQc1 to DQc9 /SBd Synchronous Byte "d" Write Enable Write DQd1 to DQd9 /G Asynchronous Output Enable Asynchronous input ZZ Asynchronous Sleep Mode Enables sleep mode, active high ZQ Output Impedance Control M1, M2 Mode Select NC No Connection TMS Test Mode Select (JTAG) TDI Test Data Input (JTAG) TCK Test Clock Input (JTAG) TDO Test Data Output (JTAG) Supplies power for output buffers Selects operation mode Note Note This device only supports Single Differential Clock, R/R Mode. (R/R stands for Registered Input / Registered Output.) Data Sheet M16379EJ5V0DS 3 PD44323362 Late Write Block Diagram SA0 to SA19 K Address register K /K /K Mux Write address register /SS /SS Write clock genelator /SW /SW /SBa /SBa Write control logic /SBb /SBb /SBc /SBc /SBd /SBd DQ 4 /G ZZ ZZ Read comp. Data Data in out Mux Data in register /G Memory array Output Register Data Sheet M16379EJ5V0DS PD44323362 Programmable Impedance / Power Up Requirements An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow for the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between 175 ohm and 350 ohm. Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in supply voltage and temperature. The impedance update of the output driver occurs only when the SRAM is in high impedance. Write and Deselect operations will synchronously switch the SRAM into and out of high impedance, therefore, triggering an update. Power up requirements for the SRAM are that VDD must be powered before or simultaneously with VDDQ followed by VREF; inputs should be powered last. The limitation on VDDQ is that it must not exceed VDD during power up. In order to guarantee the optimum internally regulated supply voltage, the SRAM requires 4096 clock cycles of power-up time after VDD reaches its operating range. And CID impedance is not updated during the clock stopped. Sleep Mode Sleep Mode is enabled by switching asynchronous signal ZZ High. When the SRAM is in Sleep Mode, the output will go to a high impedance state and the SRAM will draw standby current. SRAM data will be preserved and a recovery time (tZZR) is required before the SRAM resumes normal operation. And CID impedance is not updated during the sleep mode. Data Sheet M16379EJ5V0DS 5 PD44323362 Synchronous Truth Table ZZ /SS /SW /SBa /SBb /SBc /SBd Mode DQa1 to DQa9 DQb1 to DQb9 DQc1 to DQc9 DQd1 to DQd9 Power L H x x x x x Not selected High-Z High-Z High-Z High-Z Active L L H x x x x Read Dout Dout Dout Dout Active L L L L L L L Write Din Din Din Din Active L L L L H H H Write Din High-Z High-Z High-Z Active L L L H L L L Write High-Z Din Din Din Active H x x x x x x Sleep Mode High-Z High-Z High-Z High-Z Standby Remark x : Don't care Output Enable Truth Table Mode /G DQ Read L Dout Read H High-Z Sleep (ZZ = H) x High-Z Write (/SW = L) x High-Z Deselect (/SS = H) x High-Z Mode Select (I/O) Notes Note 1 M1 M2 VSS VDD Mode Single Differential Clock (K, /K), R/R Mode Note 2 1. This device only supports Single Differential Clock, R/R Mode. Mode Select Pins (M1, M2) are to be tied to either VDD or VSS. 2. R/R: Registered Input / Registered Output Mode Select (Output Buffer) ZQ IZQ x RQ VDD Notes Mode Controlled impedance push-pull output buffer mode 1 Push-pull output buffer mode 2 1. See figure. ZQ 2. See figure. VDD ZQ 6 Note Data Sheet M16379EJ5V0DS PD44323362 Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Symbol Condition MIN. TYP. MAX. Unit Note VDD -0.5 +3.0 V 1 VDDQ -0.5 +3.0 V 1 Input voltage VIN -0.5 VDD + 0.3 (3.0 V MAX) V 1 Input / Output voltage VI/O -0.5 VDD + 0.3 (3.0 V MAX) V 1 Junction temperature Tj 5 110 C Storage temperature Tstg -55 +125 C Output supply voltage Note 1. -1.0 V MIN. (Pulse width 10% Tcyc) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (Tj = 5 to 110 C) Parameter MIN. TYP. MAX. Unit VDD 2.375 2.5 2.625 V Output buffer supply voltage VDDQ 1.4 1.9 V Input reference voltage VREF 0.68 0.95 V Low level input voltage VIL VREF - 0.1 V High level input voltage VIH VDDQ + 0.3 V MAX. Unit Core supply voltage Symbol Conditions -0.3 Note VREF + 0.1 Note -1.0 V MIN. (Pulse width 10% Tcyc) Recommended AC Operating Conditions (Tj = 5 to 110 C) Parameter Symbol Conditions MIN. TYP. Input reference voltage VREF (RMS) -5% +5% V Low level input voltage VIL -0.3 VREF - 0.2 V High level input voltage VIH VREF + 0.2 VDDQ + 0.3 V MAX. Unit Capacitance (TA Note = 25 C, f = 1 MHz) Parameter Note Symbol Test conditions Input capacitance CIN VIN = 0 V 6 pF Input / Output capacitance CI/O VI/O = 0 V 7 pF Clock input capacitance Cclk Vclk = 0 V 7 pF Note TA = Operating ambient temperature Remark These parameters are sampled and not 100% tested. Data Sheet M16379EJ5V0DS 7 PD44323362 DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input leakage current ILI VIN = 0 to VDD -5 +5 A DQ leakage current ILO VI/O = 0 to VDDQ, /SS = VIH or /G = VIH -5 +5 A Operating supply current ICC VIN = VIH or VIL, /SS = VIL, ZZ = VIL, 550 mA 250 mA 150 mA 300 mA MAX. Unit VSS VDDQ/2 V VDDQ/2 VDDQ V cycle = 250 MHz, IDQ = 0 mA Quiescent active power ICC2 supply current Sleep mode power supply VIN = VIH or VIL, /SS = VIL, ZZ = VIL, Cycle = 4 MHz, IDQ = 0 mA ISBZZ current ZZ = VIH, All other inputs = VIH or VIL, Cycle = DC, IDQ = 0 mA Power supply standby ISBSS current VIN = VIH or VIL, /SS = VIH, ZZ = VIL, Cycle = 250 MHz, IDQ = 0 mA Output Voltage on Controlled Impedance Push-Pull Output Buffer Mode (VZQ = IZQ x RQ) Parameter Low level output voltage Symbol VOL Conditions MIN. IOL = (VDDQ/2) / (RQ/5) 15% TYP. @VOL = VDDQ / 2 (175 < RQ < 350 ) High level output voltage VOH IOH = (VDDQ/2) / (RQ/5) 15% @VOH = VDDQ / 2 (175 < RQ < 350 ) Output Voltage on Push-Pull Output Buffer Mode (VZQ = VDD) Parameter Symbol Conditions MIN. TYP. MAX. Unit Low level output voltage VOL IOL = +4 mA - 0.3 V High level output voltage VOH IOH = -4 mA VDDQ - 0.3 - V 8 Data Sheet M16379EJ5V0DS PD44323362 AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Characteristics Test Conditions (TA Note = 0 to 70 C, VDD = 2.375 to 2.625 V, VDDQ = 1.5 V) Parameter Symbol Conditions Unit High level input voltage VIH 1.25 V Low level input voltage VIL 0.25 V Input reference voltage VREF 0.75 V Input rise time TR 0.5 ns Input fall time TF 0.5 ns Input and output timing reference level Cross point Note TA = Operating ambient temperature Remark Parameter tested with RQ = 250 and VDDQ = 1.5 V. Input waveform (rise and fall time = 0.5 ns (20 to 80%)) 1.25 V VTT or VDDQ / 2 0.25 V Output waveform VTT or VDDQ / 2 Data Sheet M16379EJ5V0DS 9 PD44323362 Read and Write Cycle Parameter Symbol MIN. MAX. Unit Clock cycle time tKHKH 4.0 - ns Clock phase time tKHKL / tKLKH 1.5 - ns Address tAVKH 0.5 - ns Write data tDVKH Write enable tWVKH Chip select tSVKH Address tKHAX 0.5 - ns Write data tKHDX Write enable tKHWX Chip select tKHSX Setup times Hold times Note Clock access time tKHQV - 2.0 ns 1 K high to Q change tKHQX 0.5 - ns 2 /G low to Q valid tGLQV - 2.0 ns 1 /G low to Q change tGLQX 0.5 - ns 2 /G high to Q High-Z tGHQZ 1.0 2.0 ns 2 K high to Q High-Z (/SW) tKHQZ 1.0 2.5 ns 2 K high to Q High-Z (/SS) tKHQZ2 1.0 2.5 ns 2 K high to Q Low-Z tKHQX2 0.7 - ns /G high Pulse width tGHGL 4.0 - ns 3 /G high to K high tGHKH 1.0 - ns 3 K high to /G low tKHGL 2.5 - ns 3 Sleep mode recovery tZZR 2 - Cycle 4 Sleep mode enable tZZE - 2 Cycle 4 Notes 1. See figure. (VTT = 0.75 V, RQ = 250 ) VTT 50 Zo = 50 DQ (Output) 2. See figure. (VTT = 0.75 V, RQ = 250 ) VTT 50 DQ (Output) 5 pF 3. Controlled impedance push-pull output buffer mode only. 4. /SS must be 'high' before sleep mode entry. 10 Data Sheet M16379EJ5V0DS Read Operation /K K tKHAX tKHKH tKHKL tKLKH tAVKH Address a b c d e f g h i j tKHQZ2 tKHQX2 k tKHSX tSVKH Data Sheet M16379EJ5V0DS /SS tKHWX tWVKH /SW tGHGL /G tGLQX tGHQZ DQ Qb Qa Qc tGLQV High-Z Qe Qf Qg High-Z Qi tKHQX tKHQV PD44323362 11 12 Write Operation /K K tKHAX tKHKH tKHKL tKLKH tAVKH Address l m n o p q r s t u v tKHSX tSVKH /SS Data Sheet M16379EJ5V0DS tKHWX tWVKH /SW tGHKH tKHGL /G tGLQX tGHQZ DQ tGLQV Ql Dn High-Z tKHQZ Qo Qp Qq tKHQX2 Ds High-Z Qt tDVKH tKHDX PD44323362 Sleep Mode /K K Address a b c d e f g h i j l k /SS Data Sheet M16379EJ5V0DS /ZZ tZZR tZZE DQ Qa Qb Qc High-Z Qj PD44323362 13 PD44323362 JTAG Specifications The PD44323362 supports a limited set of JTAG functions as in IEEE standard 1149.1. Test Access Port (TAP) Pins Pin name Pin assignments TCK 4U TMS 2U Description Test Clock Input. All input are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. Test Mode Select. This is the command input for the TAP controller state machine. Test Data Input. This is the input side of the serial registers placed between TDI and TDO. TDI 3U The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction. TDO Remark 5U Test Data Output. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP. JTAG DC Characteristics (Tj = 5 to 110 C) Parameter Symbol Conditions MIN. TYP. MAX. Unit JTAG input high voltage VIH 2.2 VDD + 0.3 (3.0 V MAX) V JTAG input low voltage VIL -0.3 +0.5 V JTAG output high voltage VOH IOH = -8 mA 2.4 - V JTAG output low voltage VOL IOL = 8 mA - 0.4 V 14 Data Sheet M16379EJ5V0DS Note PD44323362 JTAG AC Test Conditions (Tj = 5 to 110 C) Input waveform (rise / fall time = 1 ns (20 to 80%)) VDD VDD / 2 Test Points VDD / 2 VDD / 2 Test Points VDD / 2 0V Output waveform Output load (VTT = 1.5 V) VTT Z0 = 50 50 TDO Data Sheet M16379EJ5V0DS 15 PD44323362 JTAG AC Characteristics (Tj = 5 to 110 C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Clock cycle time (TCK) tTHTH 100 - ns Clock phase time (TCK) tTHTL / tTLTH 40 - ns Setup time (TMS / TDI) tMVTH / tDVTH 10 - ns Hold time (TMS / TDI) tTHMX / tTHDX 10 - ns tTLQV - 20 ns TCK low to TDO valid (TDO) JTAG Timing Diagram tTHTH TCK tMVTH tTHTL tTLTH TMS tTHMX tDVTH TDI tTHDX TDO 16 Data Sheet M16379EJ5V0DS tTLQV Note PD44323362 Scan Register Definition (1) Register name Description The instruction register holds the instructions that are executed by the TAP controller when it is moved Instruction register into the run-test/idle or the various data register state. The register can be loaded when it is placed between the TDI and TDO pins. The instruction register is automatically preloaded with the IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state. The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test Bypass register data to be passed through the RAMs TAP to another device in the scan chain with as little delay as possible. The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the ID register controller is put in capture-DR state with the IDCODE command loaded in the instruction register. The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR state. The boundary register, under the control of the TAP controller, is loaded with the contents of the RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to activate the Boundary register boundary register. The Scan Exit Order tables describe which device bump connects to each boundary register location. The first column defines the bit's position in the boundary register. The shift register bit nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the input or I/O at the bump and the third column is the bump number Scan Register Definition (2) Register name Bit size Unit Instruction register 3 bit Bypass register 1 bit ID register 32 bit Boundary register 70 bit ID Register Definition ID [31:28] vendor revision no. ID [27:12] part no. ID [11:1] vendor ID no. ID [0] fix bit XXXX 0000 0000 0011 1100 00000010000 Data Sheet M16379EJ5V0DS 1 17 PD44323362 SCAN Exit Order Bit no. Signal name Bump ID Bit no. Signal name Bump ID 1 M2 5R 36 SA16 3B 37 SA18 2B 18 2 SA1 4P 38 SA9 3A 3 SA8 4T 39 SA10 3C 4 SA4 6R 40 SA13 2C 5 SA7 5T 41 SA12 2A 6 ZZ 7T 42 DQc9 2D 7 DQa9 6P 43 DQc8 1D 8 DQa8 7P 44 DQc7 2E 9 DQa7 6N 45 DQc6 1E 10 DQa6 7N 46 DQc5 2F 11 DQa5 6M 47 DQc4 2G 12 DQa4 6L 48 DQc3 1G 13 DQa3 7L 49 DQc2 2H 14 DQa2 6K 50 DQc1 1H 15 DQa1 7K 51 /SBc 3G 16 /SBa 5L 52 ZQ 4D 17 /K 4L 53 /SS 4E 18 K 4K 54 SA19 4B 19 /G 4F 20 /SBb 5G 55 NC 4H 21 DQb1 7H 56 /SW 4M 22 DQb2 6H 57 /SBd 3L 23 DQb3 7G 58 DQd1 1K 24 DQb4 6G 59 DQd2 2K 25 DQb5 6F 60 DQd3 1L 26 DQb6 7E 61 DQd4 2L 27 DQb7 6E 62 DQd5 2M 28 DQb8 7D 63 DQd6 1N 29 DQb9 6D 64 DQd7 2N 30 SA2 6A 65 DQd8 1P 31 SA3 6C 66 DQd9 2P 32 SA6 5C 67 SA11 3T 33 SA5 5A 68 SA14 2R 34 SA17 6B 69 SA0 4N 35 SA15 5B 70 M1 3R Data Sheet M16379EJ5V0DS PD44323362 JTAG Instructions Instructions Description EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented in this device. EXTEST Therefore this device is not 1149.1 compliant. respond to an all zeros instruction, as follows. Nevertheless, this RAMs TAP does With the EXTEST (000) instruction loaded in the instruction register the RAM responds just as it does in response to the SAMPLE instruction, except the RAM output are forced to high impedance any time the instruction is loaded. The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The IDCODE IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. The BYPASS instruction is loaded in the instruction register when the bypass register is placed between BYPASS TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Sample is a Standard 1149.1 mandatory public instruction. When the sample instruction is loaded in the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable SAMPLE input will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins. This functionality is not Standard 1149.1 compliant. If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive SAMPLE-Z drive state (high impedance) and the boundary register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state. JTAG Instruction Cording IR2 IR1 IR0 Instruction Note 0 0 0 EXTEST 1 0 0 1 IDCODE 0 1 0 SAMPLE-Z 0 1 1 BYPASS 1 0 0 SAMPLE 1 0 1 BYPASS 1 1 0 BYPASS 1 1 1 BYPASS 1 Note 1. TRISTATE all data drivers and CAPTURE the pad values into a SERIAL SCAN LATCH. Data Sheet M16379EJ5V0DS 19 PD44323362 TAP Controller State Diagram 1 Test-Logic-Reset 0 1 0 1 Run-Test / Idle 1 Select-IR-Scan Select-DR-Scan 0 0 1 1 Capture-IR Capture-DR 0 0 0 Shift-DR 0 Shift-IR 1 1 1 1 Exit1-DR Exit1-IR 0 0 0 Pause-DR 0 Pause-IR 1 1 0 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 Update-IR 0 1 0 Disabling The Test Access Port It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a 1k resistor. TDO should be left unconnected. 20 Data Sheet M16379EJ5V0DS Test Logic Operation (Instruction Scan) TCK TMS Run-Test/Idle Update-IR Exit1-IR Shift-IR Exit2-IR Pause-IR Exit1-IR Shift-IR Capture-IR New Instruction IDCODE Instruction Register state Select-IR-Scan Select-DR-Scan Run-Test/Idle Output Inactive TDO Test-Logic-Reset TDI Data Sheet M16379EJ5V0DS Controller state PD44323362 21 22 Test Logic (Data Scan) TCK TMS Test-Logic-Reset Select-IR-Scan Select-DR-Scan Run-Test/Idle Update-DR Exit1-DR Shift-DR Exit2-DR Pause-DR Exit1-DR Shift-DR IDCODE Instruction Instruction Register state Capture-DR Select-DR-Scan Run-Test/Idle TDI Data Sheet M16379EJ5V0DS Controller state TDO Output Inactive PD44323362 PD44323362 Package Drawing 119-PIN PLASTIC BGA (14x22) w S B E ZD 4-C1.05 E1 ZE B 7 6 5 4 3 2 1 A D1 D U T RPNML K J HGF EDCB A INDEX MARK w S A (UNIT:mm) A 25 y1 A2 S S y e S b x M A1 S AB ITEM D DIMENSIONS E 22.000.20 D1 12.00 E1 19.50 w 0.30 e 1.27 A 2.060.30 A1 0.600.10 A2 1.46 b 0.750.15 x 0.15 y 0.15 y1 0.35 ZD 3.19 ZE Data Sheet M16379EJ5V0DS 14.000.20 0.84 P119F1-127-FJ1 23 PD44323362 Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the PD44323362. Type of Surface Mount Device PD44323362F1-FJ1 <R> : 119-pin plastic BGA PD44323362F1-FJ1-A : 119-pin plastic BGA 24 Data Sheet M16379EJ5V0DS PD44323362 Revision History Edition/ Date Page Type of Location Description (Previous edition This edition) This Previous revision edition edition 5th edition/ p.1 p.1 Addition Ordering Information Lead-free products have been added Feb. 2006 p.24 p.24 Addition Recommended Soldering Lead-free products have been added Conditions Data Sheet M16379EJ5V0DS 25 PD44323362 [MEMO] 26 Data Sheet M16379EJ5V0DS PD44323362 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet M16379EJ5V0DS 27 PD44323362 * The information in this document is current as of February, 2006. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1