32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM
1M-WORD BY 36-BIT
HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
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DATA SHEET
MOS INTEGRATED CIRCUIT
μ
PD44323362
Document No. M16379EJ5V0DS00 (5th edition)
Date Published February 2006 NS CP(K)
Printed in Japan The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
2002
Description
The
μ
PD44323362 is a 1,048,576 words by 36 bits synchronous static RAM fabricated with advanced CMOS
technology using Full-CMOS six-transistor memory cell.
The
μ
PD44323362 is suitable for appl ications which require hi gh-speed, low voltage, high-de nsity memory and wide
bit configuration, such as cache and buffer memory.
The
μ
PD44323362 is packaged in a 119-pin PLASTIC BGA (Ball Grid Array).
Features
• Fully synchronous operation
• HST L Input / Output levels
• Fast clock access time: 2.0 ns / 250 MHz
• Asynchronous output enable control: /G
• Byte write control: /SBa (DQa1 to DQa9), /SBb (DQb1 to DQb9), /SBc (DQc1 to DQc9), /SBd (DQd1 to DQd9)
• Common I/O using three-state outputs
• Internall y self-timed write cycle
• Late write with 1 dead cycle between Read-Write
• User-configura ble o utputs: Co ntrolled impedance outputs or push-pull o utputs
• Boundary scan (JTAG) IEEE 1149.1 compatible
• 2.5 ± 0.125 V (Chip) / 1.4 to 1.9 V (I/O) supply
• 119 bump BGA package, 1.27 mm pitch, 14 mm × 22 mm
• Sleep mode: ZZ (Enables sleep mode, active high)
Ordering Information
Part number Access time Clock frequency Package
μ
PD44323362F1-C40-FJ1 2.0 ns 250 MHz 119-pin PLASTIC BGA
μ
PD44323362F1-C40-FJ1-A
Remark Products with -A at the end of the part number are lead-free products.
<R>
<R>
2 Data Sheet M16379EJ5V0DS
μ
PD44323362
Pin Configuration
/xxx indicates active low signal.
119-pin plastic BGA
123445671234567
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Top View Bottom View
1 2 3 4 5 6 7 7 6 5 4 3 2 1
VDDQ SA12 SA9 NC SA5 SA2 VDDQ A VDDQ SA2 SA5 NC SA9 SA12 VDDQ
NC SA18 SA16 SA19 SA15 SA17 NC B NC SA17 SA15 SA19 SA16 SA18 NC
NC SA13 SA10 VDD SA6 SA3 NC C NC SA3 SA6 VDD SA10 SA13 NC
DQc8 DQc9 VSS ZQ VSS DQb9 DQb8 D DQb8 DQb9 VSS ZQ VSS DQc9 DQc8
DQc6 DQc7 VSS /SS VSS DQb7 DQb6 E DQb6 DQb7 VSS /SS VSS DQc7 DQc6
VDDQ DQc5 VSS /G VSS DQb5 VDDQ F VDDQ DQb5 VSS /G VSS DQc5 VDDQ
DQc3 DQc4 /SBc NC /SBb DQb4 DQb3 G DQb3 DQb4 /SBb NC /SBc DQc4 DQc3
DQc1 DQc2 VSS NC VSS DQb2 DQb1 H DQb1 DQb2 VSS NC VSS DQc2 DQc1
VDDQ VDD VREF VDD VREF VDD VDDQ J VDDQ VDD VREF VDD VREF VDD VDDQ
DQd1 DQd2 VSS K VSS DQa2 DQa1 K DQa1 DQa2 VSS K VSS DQd2 DQd1
DQd3 DQd4 /SBd /K /SBa DQa4 DQa3 L DQa3 DQa4 /SBa /K /SBd DQd4 DQd3
VDDQ DQd5 VSS /SW VSS DQa5 VDDQ M VDDQ DQa5 VSS /SW VSS DQd5 VDDQ
DQd6 DQd7 VSS SA0 VSS DQa7 DQa6 N DQa6 DQa7 VSS SA0 VSS DQd7 DQd6
DQd8 DQd9 VSS SA1 VSS DQa9 DQa8 P DQa8 DQa9 VSS SA1 VSS DQd9 DQd8
NC SA14 M1 VDD M2 SA4 NC R NC SA4 M2 VDD M1 SA14 NC
NC NC SA11 SA8 SA7 NC ZZ T ZZ NC SA7 SA8 SA11 NC NC
VDDQ TMS TDI TCK TDO NC VDDQ U VDDQ NC TDO TCK TDI TMS VDDQ
3
Data Sheet M16379EJ5V0DS
μ
PD44323362
Pin Name and Functions
Pin name Description Function
VDD Core Power Supply Supplies power for RAM core
VSS Ground
VDDQ Output Power Supply Supplies power for output buffers
VREF Input Reference
K, /K Main Clock
SA0 to SA19 Synchronous Address Input
DQa1 to DQd9 Synchronous Data Input / Output
/SS Synchronous Chip Select Logically selects SRAM
/SW Synchronous Byte Write Enable Write command
/SBa Synchronous Byte "a" Write Enable Write DQa1 to DQa9
/SBb Synchronous Byte "b" Write Enable Write DQb1 to DQb9
/SBc Synchronous Byte "c" Write Enable Write DQc1 to DQc9
/SBd Synchronous Byte "d" Write Enable Write DQd1 to DQd9
/G Asynchronous Output Enable Asynchronous input
ZZ Asynchronous Sleep Mode Enables sleep mode, active high
ZQ Output Impedance Control
M1, M2 Mode Select Selects operation mode Note
NC No Connection
TMS Test Mode Select (JTAG)
TDI Test Data Input (JTAG)
TCK Test Clock Input (JTAG)
TDO Test Data Output (JTAG)
Note This device only supports Single Differential Clock, R/R Mo de.
(R/R stands for Registered Input / Registered Output.)
4 Data Sheet M16379EJ5V0DS
μ
PD44323362
Late Write Block Diagram
K
/SBa
K
/K
/SS
/SW
/SBa
/SBb
/SBc
/SBd
Data
in
register
Write
control
logic
Address
register
Write address
register
Read
comp.
Memory
array
Data
in
Data
out
Mux
Output
Register
/SW
/SBc
/SBb
DQ
/SBd
/G
/K
/SS
SA0 to SA19
Mux
ZZ
Write
clock
genelator
/G
ZZ
5
Data Sheet M16379EJ5V0DS
μ
PD44323362
Programmable Impedance / Power Up Requirements
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow for the SRAM to
adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by
the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between 175
ohm and 350 ohm. Periodic readjustment of the output driver impedance is necessary as the impedance is greatly
affected by drifts in supply vol tage and temperature. T he impedanc e update of the outp ut driver occur s only when the
SRAM is in high impedance. W rite and Deselect operations will sync hronously switch the SRAM into and out of hig h
impedance, therefore, triggering an update. Power up requirements for the SRAM are that VDD must be powered
before or simultaneously with VDDQ follo wed by VREF; inputs should be powered last. The limitation on VDDQ is that it
must not exceed VDD during power up. In order to guarantee the optimum internally regulated supply voltage, the
SRAM requires 4096 clock cycles of po wer-up time after VDD reaches its operating ra nge. And CID impedance is not
updated during the clock stopped.
Sleep Mode
Sleep Mode is enabled by switching asynchronous signal ZZ High. When the SRAM is in Sleep Mode, the output
will go to a high impedance state and the SRAM will draw standby current. SRAM data will be preserved and a
recovery time (tZZR) is required before the SRAM resumes normal operation. And CID impedance is not updated
during the sleep mode.
6 Data Sheet M16379EJ5V0DS
μ
PD44323362
Synchronous Truth Table
ZZ /SS /SW /SBa /SBb /SBc /SBd Mode DQa1 to DQa9 DQb1 to DQb9 DQc1 to DQc9 DQd1 to DQd9 Power
L H × × × × × Not selected High-Z High-Z High-Z High-Z Active
L L H × × × × Read Dout Dout Dout Dout Active
L L L L L L L Write Din Din Din Din Active
L L L L H H H Write Din High-Z High-Z High-Z Active
L L L H L L L Write High-Z Din Din Din Active
H × × × × × × Sleep Mode High-Z High-Z High-Z High-Z Standby
Remark × : Don't care
Output Enable Truth Table
Mode /G DQ
Read L Dout
Read H High-Z
Sleep (ZZ = H) × High-Z
Write (/SW = L) × High-Z
Deselect (/SS = H) × High-Z
Mode Select (I/O) Note 1
M1 M2 Mode
VSS VDD Single Differential Clock (K, /K), R/R Mode Note 2
Notes 1. T his device only supp orts Single Differential Clock, R/R Mode. Mode Select Pins (M1, M2) are to be tied
to either VDD or VSS.
2. R/R: Registered Input / Registered Output
Mode Select (Output Buffer)
ZQ Mode Note
IZQ × RQ Controlled impedance push-pull output buffer mode 1
VDD Push-pull output buffer mode 2
Notes 1. See figure.
ZQ
2. See figure.
ZQ
VDD
7
Data Sheet M16379EJ5V0DS
μ
PD44323362
Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol Condition MIN. TYP. MAX. Unit Note
Supply voltage VDD –0.5 +3.0 V 1
Output supply voltage VDDQ –0.5 +3.0 V 1
Input voltage VIN –0.5 VDD + 0.3 (3.0 V MAX) V 1
Input / Output voltage VI/O –0.5 VDD + 0.3 (3.0 V MAX) V 1
Junction temperature Tj 5 110 °C
Storage temperature Tstg –55 +125 °C
Note 1. −1.0 V MIN. (Pulse width 10% Tcyc)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (Tj = 5 to 110 °C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Core supply voltage VDD 2.375 2.5 2.625 V
Output buffer supply voltage VDDQ 1.4 1.9 V
Input reference voltage VREF 0.68 0.95 V
Low level input voltage VIL –0.3
Note VREF – 0.1 V
High level input voltage VIH VREF + 0.1 VDDQ + 0.3 V
Note −1.0 V MIN. (Pulse width 10% Tcyc)
Recommended AC Operating Conditions (Tj = 5 to 110 °C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input reference voltage VREF (RMS) –5% +5% V
Low level input voltage VIL –0.3 VREF – 0.2 V
High level input voltage VIH VREF + 0.2 VDDQ + 0.3 V
Capacitance (TA Note = 25 °C, f = 1 MHz)
Parameter Note Symbol Test conditions MAX. Unit
Input capacitance CIN VIN = 0 V 6 pF
Input / Output capacitance CI/O VI/O = 0 V 7 pF
Clock input capacitance Cclk Vclk = 0 V 7 pF
Note TA = Operating ambient temperature
Remark These parameters are sampled and not 100% tested.
8 Data Sheet M16379EJ5V0DS
μ
PD44323362
DC Characteristics (Recommended Operating Conditions Unless Otherwise No ted)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input leakage current ILI VIN = 0 to VDD –5 +5
μ
A
DQ leakage current ILO VI/O = 0 to VDDQ, /SS = VIH or /G = VIH –5 +5
μ
A
Operating supply current ICC VIN = VIH or VIL, /SS = VIL, ZZ = VIL, 550 mA
cycle = 250 MHz, IDQ = 0 mA
Quiescent active power ICC2 VIN = VIH or VIL, /SS = VIL, ZZ = VIL, 250 mA
supply current Cycle = 4 MHz, IDQ = 0 mA
Sleep mode power supply ISBZZ ZZ = VIH, All other inputs = VIH or VIL, 150 mA
current Cycle = DC, IDQ = 0 mA
Power supply standby ISBSS VIN = VIH or VIL, /SS = VIH, ZZ = VIL, 300 mA
current Cycle = 250 MHz, IDQ = 0 mA
Output Voltage on Controlled Impedance Push-Pull Output Buffer Mode (VZQ = IZQ × RQ)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Low level output voltage VOL IOL = (VDDQ/2) / (RQ/5) ± 15% VSS VDDQ/2 V
@VOL = VDDQ / 2 (175 Ω < RQ < 350 Ω)
High level output voltage VOH IOH = (VDDQ/2) / (RQ/5) ± 15% VDDQ/2 VDDQ V
@VOH = VDDQ / 2 (175 Ω < RQ < 350 Ω)
Output Voltage on Push-Pull Output Buffer Mode (VZQ = VDD)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Low level output voltage VOL IOL = +4 mA – 0.3 V
High level output voltage VOH IOH = –4 mA VDDQ – 0.3 – V
9
Data Sheet M16379EJ5V0DS
μ
PD44323362
AC Characteristics (Recommended Operating Co nditions Unless Otherwise Noted )
AC Characteristics Test Conditions (TA Note = 0 to 70 °C, VDD = 2.375 to 2.625 V, VDDQ = 1.5 V)
Parameter Symbol Conditions Unit
High level input voltage VIH 1.25 V
Low level input voltage VIL 0.25 V
Input reference voltage VREF 0.75 V
Input rise time TR 0.5 ns
Input fall time TF 0.5 ns
Input and output timing reference level Cross point
Note TA = Operating ambient temperature
Remark Parameter tested with RQ = 250 Ω and VDDQ = 1.5 V.
Input waveform (rise and fall time = 0.5 ns (20 to 80%))
V
TT
or V
DD
Q / 2
1.25 V
0.25 V
Output waveform
V
TT
or V
DD
Q / 2
10 Data Sheet M16379EJ5V0DS
μ
PD44323362
Read and Write Cycle
Parameter Symbol MIN. MAX. Unit Note
Clock cycle time tKHKH 4.0 – ns
Clock phase time tKHKL / tKLKH 1.5 – ns
Setup times Address tAVKH 0.5 – ns
Write data tDVKH
Write enable tWVKH
Chip select tSVKH
Hold times Address tKHAX 0.5 – ns
Write data tKHDX
Write enable tKHWX
Chip select tKHSX
Clock access time tKHQV – 2.0 ns 1
K high to Q change tKHQX 0.5 – ns 2
/G low to Q valid tGLQV – 2.0 ns 1
/G low to Q change tGLQX 0.5 – ns 2
/G high to Q High-Z tGHQZ 1.0 2.0 ns 2
K high to Q High-Z (/SW) tKHQZ 1.0 2.5 ns 2
K high to Q High-Z (/SS) tKHQZ2 1.0 2.5 ns 2
K high to Q Low-Z tKHQX2 0.7 – ns
/G high Pulse width tGHGL 4.0 – ns 3
/G high to K high tGHKH 1.0 – ns 3
K high to /G low tKHGL 2.5 – ns 3
Sleep mode recovery tZZR 2 – Cycle 4
Sleep mode enable tZZE – 2 Cycle 4
Notes 1. See figure. (VTT = 0.75 V, RQ = 250 Ω)
DQ (Output)
Zo = 50 Ω
50 Ω
V
TT
2. See figure. (VTT = 0.75 V, RQ = 250 Ω)
DQ (Output)
5 pF
50 Ω
VTT
3. Controlled impedance push-p ull output buffer mode only.
4. /SS must be 'high' before sleep mode entry.
11
Data Sheet M16379EJ5V0DS
μ
PD44323362
a
Qa Qc Qe Qf Qg
bcde fghijk
Qi
t
KHAX
t
AVKH
t
KHKH
t
KHKL
t
KLKH
t
KHSX
t
SVKH
t
WVKH
t
KHWX
t
GHQZ
t
GHGL
t
GLQX
t
GLQV
t
KHQZ2
t
KHQV
t
KHQX
t
KHQX2
Read Operation
/K
K
Address
/SS
/SW
/G
DQ Qb High-Z High-Z
12 Data Sheet M16379EJ5V0DS
μ
PD44323362
l
Ql Qo Qp Qq
mnopqr s t uv
t
KHAX
t
AVKH
t
KHKH
t
KHKL
t
KLKH
t
KHSX
t
SVKH
t
WVKH
t
KHWX
t
GLQX
t
GHKH
t
GLQV
t
KHQZ
t
KHDX
t
DVKH
t
KHQX2
Write Operation
/K
K
Address
/SS
/SW
/G
DQ Dn QtDs
t
GHQZ
t
KHGL
High-Z High-Z
13
Data Sheet M16379EJ5V0DS
μ
PD44323362
a
Qa Qc
bcde fghijk
tZZE tZZR
Sleep Mode
/K
K
Address
/SS
/ZZ
DQ Qb
l
Qj
High-Z
14 Data Sheet M16379EJ5V0DS
μ
PD44323362
JTAG Specifications
The
μ
PD44323362 supports a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name Pin assignments Description
TCK 4 U Test Clock Input. All input are captured on the rising edge of T CK and all outputs propagate
from the falling edge of TCK.
TMS 2 U Test Mode Select. This is the command input for the TAP controller state machine.
TDI 3 U Test Data Input. This is the input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by the state of the TAP controller
state machine and the instruction that is currently loaded in the TAP instruction.
TDO 5 U Test Data Output . Output changes in response t o the falling edge of TCK. This is the output
side of the serial registers placed between TDI and TDO.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (Tj = 5 to 110 °C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit Note
JTAG input high voltage VIH 2.2 VDD + 0.3 (3.0 V MAX) V
JTAG input low voltage VIL –0.3 +0.5 V
JTAG output high voltage VOH IOH = –8 mA 2.4 – V
JTAG output low voltage VOL IOL = 8 mA – 0.4 V
15
Data Sheet M16379EJ5V0DS
μ
PD44323362
JTAG AC Test Conditions (Tj = 5 to 110 °C)
Input waveform (rise / fall time = 1 ns (20 to 80%))
V
DD
/ 2 Test Points
V
DD
V
DD
/ 2
0 V
Output waveform
V
DD
/ 2 Test Points V
DD
/ 2
Output load (VTT = 1.5 V)
TDO
Z0 = 50 Ω
50 Ω
V
TT
16 Data Sheet M16379EJ5V0DS
μ
PD44323362
JTAG AC Characteristics (Tj = 5 to 110 °C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit Note
Clock cycle time (TCK) tTHTH 100 – ns
Clock phase time (TCK) tTHTL / tTLTH 40 – ns
Setup time (TMS / TDI) tMVTH / tDVTH 10 – ns
Hold time (TMS / TDI) tTHMX / tTHDX 10 – ns
TCK low to TDO valid (TDO) tTLQV – 20 ns
JTAG Timing Diagram
tTHTH
tTLQV
tTLTHtTHTLtMVTH
tTHDX
tDVTHtTHMX
TCK
TMS
TDI
TDO
17
Data Sheet M16379EJ5V0DS
μ
PD44323362
Scan Register Definition (1)
Register name Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller when it is moved
into the run-test/idle or the various data register state. The register can be loaded when it is placed
between the TDI and TDO pins. The instruction register is automatically preloaded with the IDCODE
instruction at power-up whenever the controller is placed in test-logic-reset state.
Bypass register The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test
data to be passed through the RAMs TAP to another device in the scan chain with as little delay as
possible.
ID register The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the
controller is put in capture-DR state with the IDCODE command loaded in the instruction register. The
register is then placed between the TDI and TDO pins when the controller is moved into shift-DR state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents of the RAMs
I/O ring when the controller is in capture-DR state and then is placed between the TDI and TDO pins
when the controller is moved to shift-DR state. Several TAP instructions can be used to activate the
boundary register. The Scan Exit Order tables describe which device bump connects to each boundary
register location. The first column defines the bit’s position in the boundary register. The shift register bit
nearest TDO (i.e., first to be shift ed out) is defined as bit 1. The second column is the name of the i nput
or I/O at the bump and the third column is the bump number
Scan Register Definition (2)
Register name Bit size Unit
Instruction register 3 bit
Bypass register 1 bit
ID register 32 bit
Boundary register 70 bit
ID Register Definition
ID [31:28] vendor revision no. ID [27:12] part no. ID [11:1] vendor ID no. ID [0] fix bit
XXXX 0000 0000 0011 1100 00000010000 1
18 Data Sheet M16379EJ5V0DS
μ
PD44323362
SCAN Exit Order
Bit no. Signal name Bump ID Bit no. Signal name Bump ID
1 M2 5R 36 SA16 3B
37 SA18 2B
2 SA1 4P 38 SA9 3A
3 SA8 4T 39 SA10 3C
4 SA4 6R 40 SA13 2C
5 SA7 5T 41 SA12 2A
6 ZZ 7T 42 DQc9 2D
7 DQa9 6P 43 DQc8 1D
8 DQa8 7P 44 DQc7 2E
9 DQa7 6N 45 DQc6 1E
10 DQa6 7N 46 DQc5 2F
11 DQa5 6M 47 DQc4 2G
12 DQa4 6L 48 DQc3 1G
13 DQa3 7L 49 DQc2 2H
14 DQa2 6K 50 DQc1 1H
15 DQa1 7K 51 /SBc 3G
16 /SBa 5L 52 ZQ 4D
17 /K 4L 53 /SS 4E
18 K 4K 54 SA19 4B
19 /G 4F
20 /SBb 5G 55 NC 4H
21 DQb1 7H 56 /SW 4M
22 DQb2 6H 57 /SBd 3L
23 DQb3 7G 58 DQd1 1K
24 DQb4 6G 59 DQd2 2K
25 DQb5 6F 60 DQd3 1L
26 DQb6 7E 61 DQd4 2L
27 DQb7 6E 62 DQd5 2M
28 DQb8 7D 63 DQd6 1N
29 DQb9 6D 64 DQd7 2N
30 SA2 6A 65 DQd8 1P
31 SA3 6C 66 DQd9 2P
32 SA6 5C 67 SA11 3T
33 SA5 5A 68 SA14 2R
34 SA17 6B 69 SA0 4N
35 SA15 5B
70 M1 3R
19
Data Sheet M16379EJ5V0DS
μ
PD44323362
JTAG Instructions
Instructions Description
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction
register, whatever length it may be in the device, is loaded with all logic 0s. EXTES T is not implemented
in this device. Therefore this device is not 1149.1 compliant. Nevertheless, this RAMs TAP does
respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the
instruction register the RAM responds just as it does in response to the SAMPLE instruction, except the
RAM output are forced to high impedance any time the instruction is loaded.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in
capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The
IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in
the test-logic-reset state.
BYPASS The BYPASS instruction is loaded in the instruction register when the bypass register is placed between
TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board
level scan path to be shortened to facilitate testing of other devices in the scan path.
SAMPLE
Sample is a Standard 1149.1 mandatory public instruction. When the sample instruction is loaded in the
instruction register, moving the TAP controller into the capture-D R state loads the data in the RAMs input
and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the
TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input
buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable
input will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The
RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring
contents into the boundary scan register. Moving the controller to shift-DR state then places the
boundary scan register between the TDI and TDO pins. This functionality is not Standard 1149.1
compliant.
SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive
drive state (high impedance) and the boundary register is connected between TDI and TDO when the
TAP controller is moved to the shift-DR state.
JTAG Instruction Cording
IR2 IR1 IR0 Instruction Note
0 0 0 EXTEST 1
0 0 1 IDCODE
0 1 0 SAMPLE-Z 1
0 1 1 BYPASS
1 0 0 SAMPLE
1 0 1 BYPASS
1 1 0 BYPASS
1 1 1 BYPASS
Note 1. TRISTATE all data drivers and CAPTURE the pad values into a SERIAL SCAN LATCH.
20 Data Sheet M16379EJ5V0DS
μ
PD44323362
TAP Controller State Diagram
Test-Logic-Reset
Run-Test / Idle Select-DR-Scan
Capture-DR Capture-IR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR Update-IR
Exit2-IR
Pause-IR
Exit1-IR
Shift-IR
Select-IR-Scan
0
0
0
1
0
1
1
0
0
1
0
1
1
0
0
0
0
10 10
11 1
0
1
1
0
1
0
11
Disabling The Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with
normal operation of the device, TCK must be tied to VSS to preclude mid level inp uts.
TDI and TMS are desig ned so an undriven input will produce a respons e identical to the application of a logic 1, and
may be left unconnected. But they may also be tied to VDD through a 1k Ω resistor.
TDO should be left unconnected.
21
Data Sheet M16379EJ5V0DS
μ
PD44323362
Test Logic Operation (Instruction Scan)
TCK
Controller
state
TDI
TMS
TDO
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Shift-IR
Exit1-IR
Update-IR
Run-Test/Idle
IDCODE
Instruction
Register state New Instruction
Output Inactive
22 Data Sheet M16379EJ5V0DS
μ
PD44323362
Test Logic (Data Scan)
Controller
state
TDI
TMS
TDO
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Shift-DR
Exit1-DR
Update-DR
Test-Logic-Reset
Instruction
Instruction
Register state IDCODE
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Output Inactive
TCK
23
Data Sheet M16379EJ5V0DS
μ
PD44323362
Package Drawing
ITEM DIMENSIONS
D
E
D1
E1
w
e
A
A1
A2
b
x
y
y1
ZD
ZE
14.00±0.20
22.00±0.20
2.06±0.30
0.60±0.10
12.00
0.30
19.50
1.27
0.35
3.19
0.84
1.46
0.15
0.75±0.15
0.15
(UNIT:mm)
P119F1-127-FJ1
SwA
SwB
ZE
ZD
A
B
7
6
5
4
3
2
1
ABCDEFGHJKLMNPRTU
E1
E
S
25°
e
xbAB
M
φφ
S
A
A2
A1
y1 S
S
y
D1
INDEX MARK
4–C1.05
D
119-PIN PLASTIC BGA (14x22)
24 Data Sheet M16379EJ5V0DS
μ
PD44323362
Recommended Soldering Conditions
Please consult with our sales offices for soldering c onditions of the
μ
PD44323362.
Type of Surface Mount Device
μ
PD44323362F1-FJ1 : 119-pin plastic BGA
μ
PD44323362F1-FJ1-A : 119-pin plastic BGA
<R>
25
Data Sheet M16379EJ5V0DS
μ
PD44323362
Revision History
Edition/ Page Type of Location Description
Date This Previous revision (Previous edition → This edition)
edition edition
5th edition/ p.1 p.1 Addition Ordering Information Lead-free products have been added
Feb. 2006 p.24 p.24 Addition Recommended Soldering Lead-free products have been added
Conditions
26 Data Sheet M16379EJ5V0DS
μ
PD44323362
[MEMO]
27
Data Sheet M16379EJ5V0DS
μ
PD44323362
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
μ
PD44323362
The information in this document is current as of February, 2006. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
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Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
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customers or third parties arising from the use of these circuits, software and information.
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customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
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redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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(Note)
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defined above).
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M8E 02. 11-1
