Reliability of Hitachi IC Memories - Hitachi Semiconductor

Reliability of Hitachi IC Memories

1. Structure

IC memory devices are classified as NMOS type, CMOS type, and Bi-CMOS type. There are advantages to it's

circuit design, layout pattern, degree of integration, and manufacturing process.

All Hitachi memories are produced using standardized design, manufacturing, and inspection techniques.

Reliability, a key factor in Hitachi IC design and usage, is enhanced by Test Element Group (TEG) evaluation. This

approach ensures the best possible application of our experience and knowledge at every step of IC development.

IC memories consist of memory cells which are circuit patterns arranged within a device at very high density.

Examples of memory cell circuitry of MOS memories are shown in Table 1.

The dies of IC memories are encapsulated in various packages. The most common packages are plastic and cerdip.

Plastic packages are widely used in many different types of equipment. Cerdip packaging is especially suitable in

equipment requiring high reliability. Surface mount packages, such as the plastic leaded chip carrier (PLCC) and

small outline package (SOP) have been developed for high density applications.

Hitachi has developed new techniques of IC packaging, thus achieving high levels of reliability. Hitachi plastic IC

packages have been improved to match the performance of other hermetically sealed packages.

Table 2 illustrates the appearance and relative sizes of various Hitachi IC packages.

Table 1 Basic Memory Cell Circuit of IC Memories

Classification Dynamic RAM Static RAM EPROM

Example of basic

cell circuit

Reliability of Hitachi IC Memories

Table 2 IC Memory Package Outline

• Cerdip

22 pin 24 pin 28 pin 28 pin with Lid

32 pin with Lid 40 pin with Lid

• Plastic DIP

18 pin 20 pin 24 pin 24 pin

28 pin 28 pin 28 pin

32 pin 40 pin 42 pin

Reliability of Hitachi IC Memories

Table 2 IC Memory Package Outline (cont)

• Zigzag-in-line Plastic

20 pin 24 pin 24 pin

28 pin 40 pin

• SOP

28/32 pin 48 pin 32 pin

20 pin 24 pin 28 pin 32 pin

44 pin 52 pin 68 pin

• SOJ

20/26/28/32 pin 40 pin

Reliability of Hitachi IC Memories

2. Reliability

Hitachi IC memory reliability test results are listed below.

2.1 Reliability Test Data of Hi-BiCMOS Memory

Hi-BiCMOS memory is a recently developed design, based on the latest fine process technologies. Hi-BiCMOS

memory offers a combination of the best features of other, earlier devices—the low power consumption and high

integrity of CMOS devices, plus the high speed and high drive capability of bipolar circuits.

The reliability test data for HM67S3632BP (32k × 36 bits) is listed in Tables 3 and 4.

In normal use, Hi-BiCMOS memory reliability is affected by some limitations based on the circuit composition.

Besides the normal constraints of CMOS and bipolar device design, Hi-BiCMOS memory should not be used in

applications involving deformed or slow signal waveforms that may cause latch-up or other malfunctions. For

further information, refer to the detailed specifications on the data sheet for each Hi-BiCMOS device.

Table 3 Results of HM67S3632BP (BGA119pin) Tests (1)

Test Item Test condition Samples Total test time Failure Failure rate

High temperature operation Ta = 105°C, 4.7 V 240 2.4 × 1050 3.8 × 10–6

6000 1.4 × 1050 6.4 × 10–6

Moisture endurance Ta = 85°C,

RH = 85%, 4.7 V 240 2.4 × 1050 4.2 × 10–6

Pressure cooker 121°C, 100%RH 200 2.0 × 1050 5.0 × 10–5

Table 4 Results of HM67S3632BP (BGA119pin) Tests (2)

Test Item Test condition Samples Failure

Temperature cycling –55°C to +150°C 100 cycles 200 0

Soldering heat 240°C, 10 seconds (reflow) 600 0

Thermal shock –65°C to +150°C, 15 cycles 45 0

Reliability of Hitachi IC Memories

2.2 Reliability Test Data of MOS Memory

2.2.1 MOS DRAM and SRAM Tests

Tables 5, 6, and 7 show the reliability test data on 4-Mbit DRAMs (HM514100/HM514400), 16-Mbit DRAMs

(HM5116100/HM5116400), and 1-Mbit SRAM (HM628128 and HM624256). The life test is performed at high

temperature and high voltage to evaluate product reliability using many samples. For all failures identified in the

manufacturing process, the data is analyzed in great detail to improve the quality and reliability of both the process

and the finished product.

Table 5 Reliability Data on 4M DRAM

HM514100AS/HM514400AS

Series (SOJ) HM514100AZ/HM514400AZ

Series (ZIP)

Test Item Test

Condition Sam-

ples Total

Test

Time

Fail-

ures Failure

RateNote

(1/h)

Sam-

ples Total

Test

Time

Fail-

ures Failure

RateNote

(1/h)

Remarks

High- 125˚C/5.5 V 823 8.2×1050 1.12×10–6 —— —— *

temperature 125˚C/7 V 2514 8.3×1051* 2.43×10–6 1100 1.5×1050 6.22×10–6 Oxide film

operation 150˚C/7 V 151 1.5×1050 6.09×10–6 — — — — failure × 1

Moisture

endurance 85˚C 85% RH

5.5 V 317 3.2×1050 2.90×10–6 300 3×1050 3.07×10–6

Pressure

cooker 121˚C/100%

RH 100 3×1040 3.07×10–5 100 3×1040 3.07×10–5

Note: Confidence level 60%

HM514100AT/HM514400AT

Series (TSOP)

Test Item Test

Condition Sam-

ples Total

Test

Time

Fail-

ures Failure

RateNote

(1/h)

High- 125˚C/5.5 V — — — —

temperature 125˚C/7 V 1100 1.5×1050 6.22×10–6

operation 150˚C/7 V — — — —

Moisture

endurance 85˚C 85% RH

5.5 V 300 3.0×1050 3.07×10–6

Pressure

cooker 121˚C/100%

RH 100 3.0×1040 3.07×10–5

Note: Confidence level 60%

Reliability of Hitachi IC Memories

Table 6 Reliability Data on 16M DRAM

HM5116100J/HM5116400J

Series (SOJ) HM5116100TT/HM5116400TT

Series (TSOP)

Test Item Test

Condition Sam-

ples Total

Test

Time

Fail-

ures Failure

RateNote

(1/h)

Sam-

ples Total

Test

Time

Fail-

ures Failure

RateNote

(1/h)

Remarks

High- 125˚C/7.0 V 12436 5.97×1050 1.68×10–6 22 4.40×1040 2.27×10–5 *

temperature 125˚C/7.5 V 5235 2.51×1051* 3.98×10–6 — — — — Oxide film

operation 125˚C/7 V 500 1.00×1060 1.00×10–6 — — — — failure × 1

Moisture

endurance 85˚C 85%

RH5.5 V 306 6.12×1050 1.63×10–6 129 2.58×1060 3.88×10–6

Pressure

cooker 121˚C/100%

RH 130 3.90×1040 2.56×10–5 38 1.14×1040 8.77×10–5

Note: Confidence level 60%

HM5116100Z/HM5116400Z

Series (ZIP)

Test Item Test

Condition Sam-

ples Total

Test

Time

Fail-

ures Failure

RateNote

(1/h)

High- 125˚C/7.0 V — — — —

temperature 125˚C/7.5 V — — — —

operation 125˚C/7 V 129 2.58×1050 3.88×10–6

Moisture

endurance 85˚C 85%

RH 5.5 V 129 2.58×1050 3.88×10–6

Pressure

cooker 121˚C/100%

RH 38 1.14×1040 8.77×10–5

Note: Confidence level 60%

Table 7 Reliability Data on 1M CMOS SRAM

HM624256 (SOJ) HM628128FP (SOP)

Test Item Test

Condition Sam-

ples Total

Test

Time

Fail-

ures Failure

RateNote

(1/h)

Sam-

ples Total

Test

Time

Fail-

ures Failure

RateNote

(1/h)

Remarks

High- 125˚C/5.5 V — — — — 1946 1.08×1060 8.52×10–7 *1

temperature

operation 125˚C/7 V 652 6.52×1050 1.41×10–6 1096 6.78×1051*1 2.98×10–6 Foreign ×

Moisture

endurance 85˚C/85%

RH 7 V 391 3.91×1050 2.35×10–6 287 4.14×1050 2.22×10–6 *2

Leak × 1

Pressure

cooker 121˚C/100%

RH 115 2.30×10404×10–5 150 3.90×1040 2.36×10–5

Note: Confidence level 60%

Reliability of Hitachi IC Memories

2.2.2 Reliability Test Data on EPROM

There are two types of EPROM: the conventional EPROM with a transparent window over the active device area;

and the one-time-program-mable ROM (OTPROM) packaged in plastic. Table 8 shows the reliability test data on

the 1-Mbit EPROM (HN27C101A, HN27C301A) and 4-Mbit EPROM (HN27C4096).

The high temperature failures shown in Table 8 are due to data dissipation in the memory cells. By absorbing

thermal energy, the electrons in the floating gates are activated and dissipated. In actual usage, however, this is not a

significant problem since this phenomenon is highly dependent on temperature (about 1.0 eV of activated energy)

that should not appear during normal operation.

The moisture resistance of the OTPROM is satisfactory.

Table 9 shows an example of PROM derating. The primary derating parameter is generally temperature since other

operating parameters are specified. The maintaining of low junction temperature during device mounting is

especially important for a stable application operation (relative to access time, refresh time, and other

characteristics).

Table 8 Reliability Data on 1-Mbit and 4-Mbit MOS EPROMs

HN27C101A/HN27C301A

(Cerdip/Plastic) HN27C4096 (Cerdip)

Test Item Test

Condition Sam-

ples Total

Test

Time

Fail-

ures Failure

RateNote

(1/h)

Sam-

ples Total

Test

Time

Fail-

ures Failure

RateNote

(1/h)

Remarks

High- 125˚C/5.5 V 240 4.52×1050 2.03×10–6 220 4.18×1050 2.20×10–6 *

temperature

operation 125˚C/7 V 570 9.55×1050 0.96×10–6 445 8.45×1050 1.09×10–6 Data dis-

sipation

High- 175˚C 290 5.51×1050 1.67×10–6 180 3.60×1050 2.56×10–6 ×43

temperature 200˚C 260 4.02×1050* 2.29×10–6 130 2.60×1051* 7.77×10–6

bake 250˚C 200 2.09×1052* 1.48×10–5 110 1.10×10540* 3.64×10–4

Moisture

endurance 85˚C/85%

RH 5.5 V 300 5.42×1050 1.70×10–6 — — — — Data of

Pressure

cooker 121˚C/100%

RH 50 0.10×1050 9.20×10–5 — — — — OTPROM

Note: Confidence level 60%

Reliability of Hitachi IC Memories

Table 9 Example of HN27C101/HN27C301 Derating

Factor Temperature

Failure criteria Electrical characteristics,

function test

Failure mechanism Increase of leakage

current, and others

Results:

The result of high temperature baking of the

PROM is shown in the figure at right.

10 1.5 2.0

103

104

MTTF (h)

2.5 3.0 3.5

10 /Tj (°K )

3–1

100°C

70°C

25°C

125°C

150°C

200°C

250°C

300°C

Note: As shown in the figure, decreasing junction temperature will improve reliability. The junction temperature can

be calculated by the formula: Tj = Ta + qja · Pd where qja is about 100°C/W with no air flow and about 60° to

70°C/W with 2.5 m/s air flow.

2.2.3 Reliability Test Data of EEPROM/Flash Memory

Table 10 shows the Reliability test data for the 256-kbit EEPROM (HN58C256P) and 1-Mbit Flash memory

(HN28F101T).

EEPROM has a function to program or erase the data electrically.

Reliability of Hitachi IC Memories

Table 10 Reliability Data on 256-kbit EEPROM and 1-Mbit Flash Memory

HN58C256P (NMOS) HN28F101T (Flash Memory)

Test Item Test

Condition Sam-

ples Total

Test

Time

Fail-

ures Failure

RateNote

(1/h)

Sam-

ples Total

Test

Time

Fail-

ures Failure

RateNote

(1/h)

Remarks

High- 125°C/5.5 V 120 1.2×1050 7.7×10–6 280 2.8×1050 3.3×10–6 *

temperature

operation 125°C/7 V 390 3.9×1050 2.4×10–6 170 1.7×1050 5.4×10–6 Data dis-

sipation

High- 150°C 340 3.4×1050 2.7×10–6 150 1.5×1050 6.1×10–6 ×16

temperature 200°C 80 8.0×10416 2.2×10480 8×1040 1.2×10–5

bake 250°C———— 20

(DILC) 2×1040 4.6×10–5

Moisture

endurance 85°C 85%

RH 5.5 V 240 2.4×1050 3.8×10–6 240 2.4×1050 3.8×10–6

Pressure

cooker 121°C/100%

RH 85 1.7×1040 5.4×10–5 220 4.4×1040 2.1×10–5

Note: Confidence level 60%

2.2.4 Reliability Test Data on MASK ROM

Table 11 shows the reliability test data for the 16-Mbit and 8-Mbit MASK ROMs. The MASK ROM is patterned in

the manufacturing process, so data dissipation is not generated during high temperature operations, unlike EPROM

and EEPROM devices.

Table 11 Reliability Data on 16-Mbit and 8-Mbit MASK ROMs

HN624016P (Plastic) HN62408P (Plastic)

Test Item Test

Condition Sam-

ples Total

Test

Time

Fail-

ures Failure

RateNote

(1/h)

Sam-

ples Total

Test

Time

Fail-

ures Failure

RateNote

(1/h)

Remarks

High- 125˚C/5.5 V 140 1.4×1050 6.6×10–6 200 4.0×1050 2.3×10–6

temperature

operation 125˚C/7 V 100 1.0×1050 9.2×10–6 130 1.3×1050 7.1×10–6

Moisture

endurance 85˚C/85%

RH 5.5 V 100 1.0×1050 9.2×10–6 150 1.5×1050 6.1×10–6

Pressure

cooker 121˚C/100%

RH 60 3.0×1040 3.1×10–5 90 4.5×1040 2.0×10–5

Note: Confidence level 60%

Reliability of Hitachi IC Memories

2.2.5 Reliability Test Data on MOS Memory (environmental testing)

Tables 12 and 13 list MOS memory environmental test data, showing excellent results without any failures, even in

severe environments.

In MOS transistor operations, VTH is a basic process parameter. While in use, MOS memory exhibits almost no

change in VTH, largely due to designed-in surface stabilization technology and extremely clean production processes.

Figure 1 shows examples of time dependent degradation for minimum VCC and access time tRAC for 4-Mbit DRAM

under high temperature operation test conditions.

Table 12 Reliability Data on MOS Memory (1)

HM628128FP (SOP) EPROM (Cerdip)

Test Item Test Condition Samples Failures Samples Failures

Temperature cycling –55˚ to 150˚C

10 cycles 1215 0 2850 0

Temperature cycling –55˚ to 150˚C

500 cycles 210 0 520 0

Thermal shock –65˚ to 150˚C

15 cycles 77 0 100 0

Soldering heat 260˚C, 10 sec 35 0 22 0

Mechanical shock 1500 G, 0.5 ms — — 38 0

Variable frequency vibration 100 to 2000 Hz

20 G — — 38 0

Constant acceleration 6000 G — — 38 0

Table 13 Reliability Data on MOS Memory (2)

HM514400A

S (SOJ) HM514400A

Z (ZIP) HM514400A

T (TSOP) HM5116400

J (SOJ) HM5116400

TT (TSOP) HN624016P

(DIP) HN62408P

(DIP)

Test Item Test

Condition Sam-

ples Fail-

ures Sam-

ples Fail-

ures Sam-

ples Fail-

ures Sam-

ples Fail-

ures Sam-

ples Fail-

ures Sam-

ples Fail-

ures Sam-

ples Fail-

ures

Tempera-

ture cycling –55˚ to 150˚C

10 cycles 949 0 1000 0 900 0 1438 0 350 0 330 0 370 0

Tempera-

ture cycling –55˚ to 150˚C

500 cycles 200 0 200 0 100 0 141 0 129 0 70 0 12 0

Thermal

shock –65˚ to 150˚C

15 cycles 22 0 22 0 22 0 32 0 22 0 22 0 22 0

Soldering

heat 260˚C,

10 sec 22 0 600 0 22 0 22 0 22 0 22 0 22 0

Reliability of Hitachi IC Memories

2.3 Change of Electrical Characteristics on IC Memories

The degradation of ICBO and hFE are the main factors of performance degradation for inner cell transistors in bipolar

memory. The actual element design, however, specifies the operation in a range at which no degradation occurs. In

this normal situation, no changes in the operating character-istics, including access time, will arise. Time

dependencies in the access time for the HM514400AS are shown in Figures 1.

Example Example of Time Dependent Degradation in VCC min and

tRAC for MOS Memory

Device name HM514400AS

Test condition Ta = 125˚C, VCC = 7 V

all bit scanning

Failure criteria ∆VCC = 1.0 V, ∆tRAC = 6 ns

Failure mechanism Surface degradation

Results:

VCC margin and access time (tAA) are stabilized

and are within the failure criteria.

Note: Test accuracy is 0.2 V, 2 ns.

0 168 500 1,000 2,000

Test Condition

Marching Pattren

Ta = 25°C

N = 100

Maximum

Average

Minimum

Time (hr)

V min (V)

0 168 500 1,000 2,000

Test Condition

Same as Above

Time (hr)

t (ns)

RAC

Figure 1 Time Dependent Degradation in Minimum VCC and tRAC for MOS Memory

2.4 Failure Mode Rate

Figures 2 and 3 show examples of failure modes identified in user applications. Since IC memories require the finest

pattern process technology, the percentage of failures due to factors such as pinholes, photoresist defects, and foreign

materials tends to increase along with product complexity. Hitachi has continued to improve its fabrication process

technology, and performs 100% high temperature “burn-in” screening as a standard part of manufacturing.

Hitachi collects and analyzes customer usage data as part of a program designed to achieve higher product reliability.

This analysis is a very useful feature of the program.

Reliability of Hitachi IC Memories

Foreign

Material

21%

Defective

Oxide Film

20%

Marginal

Destruction

15%

Non-detected

Failure

24%

Others

Defective

Photolithography

Statistics

for 1992–1994

10–100 FIT

Figure 2 Failure Mode Rates for Hi-BiCMOSMemory

Destruction

Others

13.8%

5.5%

Non-

reapparing

Failures

44.2%

Oxide

Film Failures

11.5%

10.1%

Foregin

Material

9.8%

Marginal

Statistics

for 1992–1995

10–100 FIT

Figure 3 Failure Mode Rates for MOS Memory

Reliability of Hitachi IC Memories

3. Reliability of Semiconductor Devices

3.1 Reliability Characteristics for Semiconductor Devices

Hitachi semiconductor devices are designed, manufactured, and inspected to achieve a high level of reliability.

System reliability is improved by combining highly reliable components with the proper environmental conditions.

This section describes the reliability characteristics, failure types, and their mechanisms in terms of devices. First,

the semiconductor device characteristics are examined in light of their reliability.

1. Semiconductor devices are essentially structure sensitive as seen in surface phenomena. Fabricating devices

requires precise control of a large number of process steps.

2. Device reliability is partly governed by electrode materials and package materials, as well as by the coordination

of these materials with the device materials.

3. Devices employ thin-film and fine-processing techniques for metallization and bonding. Fine materials and thin-

film surfaces sometimes exhibit different physical characteristics from the bulk quantities of identical materials.

4. Semiconductor device technology advances very quickly, and therefore many new devices have been developed

using new processes over a short period of time. Hence, conventional device reliability data cannot always be

used for comparisons.

5. Semiconductor devices are characterized by volume production. Therefore, manufacturing variation is an

important consideration.

6. Initial and accidental failures are only considered to be semiconductor device failures based on the fact that

semiconductor devices are essentially semipermanently operable. However, failures caused by worn or aged

materials and migration should also be reviewed when electrode and package materials are not suited for

particular environmental conditions.

7. Component reliability may depend on the device mounting, conditions used, and environment. Device reliability

is affected by such factors as voltage, electric field strength, current density, temperature, humidity, gas, dust,

mechanical stress, vibration, mechanical shock, and radiation magnetic field strength.

Device reliability is generally represented by a failure rate. “Failure” implies that a device has lost its function,

and includes intermittent degradation or complete destruction.

Generally, the failure rate of electrical components and equipment is represented by the “bathtub” curve as shown

in Figure 4. For semiconductor devices, the configuration parameter of the Weibull distribution is smaller than 1,

which indicates an initial failure type. Such devices ensure a long lifetime unless extreme environmental stress is

applied. Therefore, initial and accidental failures can become a problem for semiconductor devices.

Semiconductor device reliability can be represented physically as well as statistically. Both failure aspects have

been thoroughly analyzed to establish a high level of reliability.

3.2 Failure Types and Their Mechanisms

3.2.1 Failure Physics

Failure physics is, in a broad sense, a basic technology of “physics + engineering.” It is used to examine the physical

mechanism of failures, in terms of atoms and molecules, to improve device reliability. This physical approach was

introduced to the reliability field to answer the demand for minimized developmental cost and time. These

Reliability of Hitachi IC Memories

conditions were derived from the development of solid-state physics (semiconductor physics) since the 1940’s and

from other associated device development. Failure physics has been employed to do the following:

1. Detect failed devices as soon as possible.

2. Establish models and equations used for failure prediction.

3. Evaluate the reliability in short time periods by accelerated life testing.

The purpose of the failure physics approach is to contribute to reliability related fields such as product design,

prediction, test, storage, and usage, by including physics as a basic technology to conventional experimental and

statistical approaches.

3.2.2 Failure Types and Their Mechanisms

The physical aspects of device failures are covered in this section. Semiconductor device failures are basically

categorized as open, short circuit, deterioration, and miscellaneous failures. These failures and their causes are

summarized in Table 14. Typical failure mechanisms are as follows:

1. Surface deterioration

The pn junction has a charge density of 1014 to 1020 cm-3. If charges exceeding the above density are accumulated

on the pn junction surface, the electrical characteristics of the junction will tend to vary. Although the surface of

such devices as planar transistors is generally covered with a SiO2 film and is in an inactive state, the possibility

of deterioration caused by the surface channels still exists. Surface deterioration depends heavily on the applied

temperature and voltage and is often handled by the reaction model.

An example of a recent failure is the surface deterioration caused by hot carriers. Hot carriers are generated when

such devices as MOS dynamic RAMs are operated at a voltage near the minimum breakdown voltage BVDS,

thus raising the internal voltage and establishing a strong electric field near the drain of the MOS device. This

may be a result from reduced device geometry (from 2 mm to 0.8 mm) as technological advances have occurred

in production methods. Generated hot carriers may affect the surface boundary characteristics on a section of the

gate oxide film, resulting in the degradation of the threshold voltage (VTH) and counter conductance (gm).

Hitachi devices have consistently employed improved designs and process techniques to prevent these problems.

However, as processes become even finer, surface deterioration may become a serious problem.

Initial failure region

: Declining failure rates (m < 1)

Wearout failure region

: Rising failure rates (m > 1)

Useful longevity

Speicfied failure rate

Failure rate (t)

Random failure region

: Constant failure rates (m = 1)

Reduced failure rate

by maintenance

Time (t)

m: Weibull distribution

form parameter

Figure 4 Typical Failure Rate Curve

Reliability of Hitachi IC Memories

2. Electrode-related failures

The concern for electrode-related failures has increased as multilayer metallization has become more complex.

Noticeable failures include electromigration and Al metallization corrosion in plastic sealed packages.

a. Electromigration

This phenomenon takes place when metal atoms are moved by a large current of about 106 A/cm2 that is

supplied to the metal. When ionized atoms collide with the current of electrons, an “electron wind” is

produced. This wind moves the metal atoms in the opposite direction from the current flow, which generates

voids at a negative electrode, and hillock and whiskers at the opposite side. The generated voids increase

wiring resistance and cause excessive currents to flow in some areas, leading to disconnection. The generated

whiskers may cause short circuits in multimetal lines.

b. Multimetal line related failures

Major failures associated with multimetal lines include increased leakage currents, short circuits caused by a

failed dielectric interlayer, and increased contact metal resistance and disconnection between metal wirings.

c. Al line corrosion and disconnection

When plastic encapsulated devices are subjected to high temperatures, high humidity, or a bias-applied

condition, the Al electrodes in the devices can cause corrosion or disconnection (Figure 5). Under high

temperature and high humidity, corrosion is randomly generated over the element surface.

However, after an extended period of time, such corrosion does not significantly increase. This type of

failure is possibly due to initial failures associated with manufacturing variances. It is also known that such

failures can be generated when the adhesion surface between an element and resin is separated or when

foreign materials are attached to the element with human saliva. Under a bias-applied, high temperature,

high humidity condition, on the other hand, pit corrosion is generated in higher potential areas while in lower

potential areas, intergranular corrosion occurs. Once this failure occurs in part of a device, the device can

become worn out in a relatively short time. This failure proves to depend on the hydroscopic volume

resistivity of sealed resin. The Al line corrosion mechanism described above is summarized in Figure 6.

Reliability of Hitachi IC Memories

Moiture resistance test

High temp and

high himidity

and bias

Random Lower potential

area

Pit corrosions Intergranular

corrosions

Higher potential

area

Pit corrosions

High temp and

high humidity

Figure 5 Categorized Al Corrosions

Moisture

penetration

Moisture penetrates

resin bulk

Adhesion surface

sepated

Melting

corrosive impurity

Impurity in resin

Chip & lead

contamination

Passivation film

Mold

releasing Bonding pad

Chip-resin

boundary stress

Chip-resin boundray

separated Al electrode exposed

Mechanism

Moisture

penetration

Melting corrosive

impurity in moisture

chip-resin

separated

Corrosive

water film

Bias type

Al corrosion Storage type

Al corrosion

Passivation

defect

Al electrode exposed

Al electrode

Figure 6 Plastic Package Cross Section and Al Corrosion Mechanism

Reliability of Hitachi IC Memories

3. Bonding related failures

a. Degradation caused by intermetallic formation

Bonding strength degradation and contact resistance increase are caused by compounds formed in the

connections between Au wire and Al film or between Au film and Al wire. These are the most serious

problems in terms of reliability. The compounds are formed rapidly during bonding and are increased

through thermal treatment. Consequently, Hitachi products are subjected to a lower-temperature, shorter-

period bonding whenever possible.

b. Wire creep

Wire creep is wire neck destruction in an Au ball along an intergranular system occurring when a plastic

sealed device is subjected to a long-term thermal cycling test. This failure results from increased crystal

grains due to heat application when forming a ball at the top of an Au wire, or from an impurity introduced to

the intergranular system. Bonding under usual conditions with no abnormal loop configuration failures does

not cause this failure, unless a severe long-term thermal cycling test is applied. Accordingly, wire creep is

not a problem in actual usage.

c. Chip crack

With the increase in chip size associated with the increased number of incorporated functions, more problems

have been occurring during assembly, such as chip cracks during bonding. Bonding methods include Au-

silicon eutectic, soldering and Ag-paste. Soldering and Ag-paste exhibit few chip crack problems. For Au-

silicon eutectic, in contrast, large stress is applied to a pellet due to its strength and high temperature

resistance for attachment, which may result in critical chip defects.

Today, the chip destruction limit can be determined by finite-element method and by distortion measurement

using a fine accuracy gauge. Ideally, Au-silicon eutectic should be evenly applied over the entire surface.

Therefore, specifications for Au-silicon eutectic have been established based on stress analysis and thermal

cycling test results.

d. Reduced maximum power dissipation

For power devices, heat fatigue due to thermal expansion coefficient mismatches among different materials

deteriorates thermal resistance. This results in decreased maximum power dissipation.

Reliability of Hitachi IC Memories

0.1

1.0

Cumulative Failure (%)

102103104105

Test Time (hrs)

138°C

127°C 110°C

85°C

Condition

Vcc = 5.5 V

RH = 85 %

Figure 7 An Example of Moisture Resistance by High Temperature, High Humidity, and High Bias

3.53.02.52.0

138°C

Time to 1% failure (hrs)

Temperature 1/ T (10 / °C)

127°C

110°C

85°C

30°C

Figure 8 Relationship Between Temperature and Time to 1% Failure (RH = 85%)

4. Sealing related failures

Hermetic sealing packages, including metal, glass, ceramic, and all other types, have the possibility of the

following failures.

 Al line corrosion on the chip surface due to slight moisture and reactions between different ionized

materials.

Reliability of Hitachi IC Memories

 Intermittent moving foreign metals causing short circuiting.

 Al line corrosion due to extraneous H20 caused by hermetic failure.

Moving foreign matter, even if it is a non-active solid, can be charged up within a cavity during movement,

thereby inducing parasitic effects and metal shorts. The foreign matter detection method is specified by the MIL-

STD-883C, PIND (particle impact noise detection) test. The PIND test consists of filtering a particle impact

waveform (ultrasonic waveform), detecting it with a microphone, and then amplifying it.

5. Disturbance

a. Electrostatic discharge destruction

Destruction caused by electrostatic discharge is a problem common to semiconductor devices. A recent

report introduced three modes of this failure: the human body model, a charged device model, and a field

induced model.

The human body is easily charged. A person just walking across a carpet can be charged up to 15,000 V.

This voltage is high enough to destroy a device. An equivalent circuit of the human body model is shown in

Figure 9. The human body’s capacitance Cb and resistance Rb are 100 to 200 pF and 1000 to 2000 W,

respectively. Assuming a body is charged with 2000 V, the dissipated energy is obtained as follows: With a

time constant of 10-7s, the dissipated energy is 2 kW, which is enough to destroy a small area of a chip.

In the charged device model, charges are accumulated in a device, not a human body, and discharged through

contact resistance during a short time. The equivalent circuit of this model is shown in Figure 10. Device

size and device position relative to ground are important parameters in this model since the model depends on

device capacity.

In the field induced model a device is left under a strong electric field or is affected by nearby high voltage.

Since the capacitors or leads of a device act like antennas, the following cases will possibly cause its

destruction.

 device is incorporated into a high electric field such as a CRT.

 A device is left under a high-frequency electric field.

 A device is moved within a container charged at high voltage, such as a tube.

Cb Rb Rd Rc

Human body capacity

Human body resistance

Device resistance

Resistance between device and ground

E = CbV = 0.2 10 J

2–3

Figure 9 Equivalent Circuit of the Human Body Model

Reliability of Hitachi IC Memories

Figure 10 Equivalent Circuit of a Charged Model

b. Latch-up

Latch-up is a problem unique to CMOS devices. This problem is a thyristor phenomenon caused by a

parasitic PNP or NPN transistor formed in the CMOS configuration.latch up occurs when an accidental surge

voltage exceeding a maximum rating, a power supply ripple, an unregulated power supply, or noise is

applied, or when a device is operated from two sources having different setup voltages. These cases can

cause input or output current to flow in the opposite direction from the usual flow, which triggers parasitic

thyristors. This results in an excessive current flowing between a power supply and ground. This

phenomenon continues until the power is removed or the current flow is reduced to a certain level. Once

latch-up occurs in an operating device, the device will be destroyed.

Much effort should be made in designing circuits to prevent latch-up. Input or output currents that trigger

latch-up start to flow under the following conditions.

Vin > VCC or Vin < GND for input level

Vout > VCC or Vout < GND for input level

Circuits should be designed so that no forward current flows through the input protection diodes or output

parasitic diodes.

c. Soft errors

When a-particles are generated from uranium or thorium on or near the silicon

surface of an LSI chip and bombard the Si substrate, electron-hole pairs are formed. They act as noise to

memory cell nodes and data lines, which results in data errors. This type of error occurs temporarily and is

called a soft error. This phenomenon is shown in Figure 11. Only electrons from among the electron-hole

pairs are collected into a memory cell. As a result, the cell changes from a state of 1 to 0, which is a soft

error.

Hitachi devices have been subjected to simulation and irradiation tests to prevent soft errors. In some cases,

an organic material, PIQ, is applied to the surface of the device.

6. Fine Geometry Related Problems

LSI circuit geometry has been reduced down to 0.8 mm, and further reductions are expected.

However, while transmission line dimensions have undergone this substantial reduction in size, power supplies

have not been correspondingly adjusted for 5 V use. Problems associated with finer geometries are shown in

Table 15.

Reliability of Hitachi IC Memories

+ –

– +

+ –

– +

+ –

– +

+ –

– +

+ –

– +

+ –

++++

–

Figure 11 Soft Errors Caused by α-Particles in Dynamic Memory

Reliability of Hitachi IC Memories

Table 14 Failure Causes and Mechanisms

Failure Related Causes Failure Mechanisms Failure Modes

Passivation Surface oxide film,

insulating film between

metallizations

Pin hole, crack, uneven

thickness, contamination,

surface inversion, hot carrier

injected

Degradation of breakdown

voltage, short, leak current

increased, hFE degraded,

threshold voltage variation,

noise

Metallization Interconnection, contact,

through hole Flaw, void, mechanical damage,

break due to uneven surface,

non-ohmic contact, insufficient

adhesion strength, improper

thickness, electromigration,

corrosion

Open, short, resistance

increased

Connection Wire bonding, ball

bonding Bonding runout, compounds

between metals, bonding

position mismatch, bonding

damaged

Open, short resistance

increased

Wire lead Internal connection Disconnection, sagging, short Open, short

Diffusion, junction Junction diffusion,

isolation Crystal defect, crystallized

impurity, photo resist

mismatching

Degradation of breakdown

voltage, short

Die bonding Connection between die

and package Peeling chip, crack Open, short, unstable

operation, thermal

resistance increased

Package sealing Package, hermetic seal,

lead plating, hermetic

package and plastic

package, filler gas

Integrity, moisture ingress,

impurity gas, high temperature,

surface contamination, lead

rust, lead bend, break

Short, leakage current

increased, open, corrosion

soldering failure

Foreign matter Foreign matter in

package Dirt, conducting foreign

matter,organic carbide Short, leakage current

increased

Input/output pin Electrostatistics,

excessive voltage, surge Human body charged device Short, open, fusing

Disturbance α particle Electron hole generated Soft error

High electric field Surface inversion Leakage current increased

Reliability of Hitachi IC Memories

Table 15 Finer Geometry Related Problems

Item Problems Countermeasure

5 V single supply

voltage • Breakdown voltage of gate oxide films

• SiO2 defects

Oxide film formation process improved

• Cleaning

• Gettering

• Screening

Horizontal dimension

reduction • Soft errors by α particles

• Al reliability

• CMOS latch up

• Mask alignment margin

• Hot carriers

Surface passivation film improved

• Metallization improved

• Design/layout improved

• Process improved

Vertical and horizontal

dimension reduction • Higher breakdown voltage not permitted

• Electrostatic discharge resistance

reduced

Use of low voltage examined

• Configuration improved

• Protection circuits enhanced